Built-in self-test system and method for crystal oscillator amplifier

Abstract

The invention relates to a BIST system and method for a crystal oscillator amplifier. The BIST system comprises current mirror circuitry, ADC, DAC and test control circuitry. The amplifier includes a current source, a base transistor, and a feedback resistor. The ADC converts a self-bias voltage on the input node to a digital bias code during a normal mode when the current source is coupled to the base transistor. During the phase of the test mode, the base transistor is instead coupled to mirror circuitry that mirrors the current through the base transistor into the test resistor. The digital bias code is converted into an upper digital bias code and a lower digital bias code using the difference value, the upper digital bias code and the lower digital bias code being converted by the DAC to corresponding bias voltages driven onto the input nodes during respective phases of the test mode. The ADC converts a corresponding test voltage on the test resistor into a test code used to estimate amplifier transconductance.

Description

Technical Field

[0001] The present disclosure generally relates to crystal oscillator amplifiers, and more particularly, to a built-in self-test (BIST) configuration for testing the transconductance of a crystal oscillator amplifier. Background Art

[0002] Integrated crystal oscillator amplifiers undergo various levels of characterization and testing to ensure proper functionality. In operation, a crystal oscillator amplifier applies a negative resistance to an external crystal to establish oscillation, where the level of the applied negative resistance varies with the transconductance (gm) of the amplifier. The transconductance should be at least a minimum level or within a predetermined range to ensure successful oscillation. Thus, the transconductance of a crystal oscillator amplifier is typically tested during production testing to identify faulty amplifiers.

[0003] Conventional methods for measuring the transconductance of a crystal oscillator amplifier include at least three measurement steps using hardware instruments including a voltmeter, an ammeter, and a source meter. Such conventional testing performed during a production process has drawbacks as it is expensive and time-consuming and tends to increase the time to market of the final product. Summary of the Invention

[0004] The present invention discloses a built-in self-test system for a crystal oscillator amplifier, characterized in that the crystal oscillator amplifier includes a bias current source that generates current from a supply voltage, a base transistor having a current terminal coupled between an output node and a supply reference node and having a control terminal coupled to an input node, and a feedback resistor coupled between the input node and the output node. The built-in self-test system includes: a current mirror circuit system capable of mirroring the current through the current terminal of the base transistor into a test resistor coupled to a test node during a first stage and a second stage of a test mode; a test control circuit system including a test switch controlled by a test mode signal to couple the output node to the bias current source during a normal mode and to couple the output node to the current mirror circuit system during the test mode; an analog-to-digital converter capable of converting a self-bias voltage formed on the input node during the normal mode into a digital bias code, capable of converting a first test voltage on the test node into a first test code during the first stage of the test mode, and capable of converting a second test voltage on the test node into a second test code during the second stage of the test mode; the test control circuit system further includes a test controller capable of providing the test mode signal to switch between the normal mode and the test mode, and capable of incrementing and decrementing a difference value of the digital bias code during the first stage and the second stage of the test mode respectively to provide an upper digital bias code and a lower digital bias code; and a digital-to-analog converter capable of converting the upper digital bias code into a first bias voltage driven onto the input node during the first stage of the test mode, and capable of converting the lower digital bias code into a second bias voltage driven onto the input node during the second stage of the test mode.

[0005] In one or more embodiments, the current mirror circuit system includes: a first transistor, which is a replica of the base transistor, the first transistor having a current terminal coupled between a mirror node and the supply reference node and having a control terminal coupled to the input node; a second transistor having a current terminal coupled between the supply voltage and the mirror node and having a control terminal coupled to the mirror node; a third transistor having a current terminal coupled between the supply voltage and the test switch and having a control input coupled to the mirror node; and a fourth transistor having a current terminal coupled between the supply voltage and the test node and having a control input coupled to the mirror node.

[0006] In one or more embodiments, the test control circuitry further includes a selection circuitry that is controlled by the test mode signal to select the input node during the normal mode and to select the test node during the test mode to provide an analog input voltage; and wherein the analog-to-digital converter includes: a comparator configured to compare the analog input voltage with a tap voltage to provide a comparison value; a counter configured to adjust a digital count value based on the comparison value; a decoder configured to decode the digital count value into a decimal value; a converter configured to convert the decimal value into the tap voltage; and a buffer configured to store the digital count value when the comparison value indicates that the tap voltage is equal to the analog input voltage.

[0007] In one or more embodiments, the converter includes: a resistor array serially coupled between a pair of reference voltage nodes and forming a plurality of intermediate nodes; and a plurality of tap switches each having a switching end coupled between a corresponding one of the plurality of intermediate nodes and a common node forming the tap voltage, wherein each of the plurality of tap switches has a control end controlled by a corresponding bit of the decimal value.

[0008] In one or more embodiments, the test controller is configured to prompt the analog-to-digital converter to convert the input voltage into the digital bias code during the normal mode, to prompt the analog-to-digital converter to convert the first test voltage into the first test code during the first phase of the test mode, and to prompt the analog-to-digital converter to convert the second test voltage into the second test code during the second phase of the test mode.

[0009] In one or more embodiments, the test control circuitry includes a switch that is controlled by the test mode signal to the output of the digital-to-analog converter to the input node during the test mode; and wherein the test controller is configured to prompt the digital-to-analog converter to convert the upper digital bias code into the first bias voltage during the first phase of the test mode, and to prompt the digital-to-analog converter to convert the lower digital bias code into the second bias voltage during the second phase of the test mode.

[0010] In one or more embodiments, the digital-to-analog converter includes: a decoder configured to decode a selected one of the upper digital bias code and the lower digital bias code into a decimal value; a converter configured to convert the decimal value into a converted voltage; and a buffer configured to buffer the converted voltage as a selected one of the first bias voltage and the second bias voltage.

[0011] In one or more embodiments, the converter includes: a resistor array that is serially coupled between a pair of reference voltage nodes and forms a plurality of intermediate nodes; and a plurality of tap switches, each having a switching terminal coupled between a corresponding one of the plurality of intermediate nodes and a common node that forms the converted voltage, wherein each of the plurality of tap switches has a control terminal controlled by a corresponding bit of the decimal value.

[0012] In one or more embodiments, the test control circuitry is configured to estimate a transconductance of the crystal oscillator amplifier based on a difference between the first test code and the second test code.

[0013] In one or more embodiments, the test control circuitry is configured to evaluate the determined estimate of the transconductance of the crystal oscillator amplifier and provide one of a pass notification and a fail notification.

[0014] The present invention also discloses a method for performing built-in self-test on a crystal oscillator amplifier, the crystal oscillator amplifier including a bias current source that sources a bias current from a supply voltage, a base transistor having a current terminal coupled between an output node and a supply reference node and having a control terminal coupled to an input node, and a feedback resistor coupled between the input node and the output node, the method including: coupling the output node to the bias current source during a normal mode to source the bias current through the current terminal of the base transistor and converting a self-bias voltage formed on the input node during the normal mode into a digital bias code; coupling the output node to a mirror circuitry during a test mode and mirroring a current through the current terminal of the base transistor into a test resistor coupled to a test node during the test mode; incrementing the digital bias code by an increment value during a first stage of the test mode to provide an upper digital bias code, converting the upper digital bias code into a first bias voltage, and driving the first bias voltage to the input node; decrementing the digital bias code by the increment value during a second stage of the test mode to provide a lower digital bias code, converting the lower digital bias code into a second bias voltage, and driving the second bias voltage to the input node; and converting a first test voltage on the test node into a first test code during the first stage of the test mode and converting a second test voltage on the test node into a second test code during the second stage of the test mode.

[0015] In one or more embodiments, coupling the output node to a mirror circuit system and mirroring a current during the test mode includes: providing a replica transistor of the base transistor, the replica transistor having a current terminal coupled between the mirror circuit system and the supply reference node and having a control terminal coupled to the input node; and using the replica transistor by the mirror circuit system during the test mode to mirror the current through the current terminal of the base transistor into the test resistor.

[0016] In one or more embodiments, converting the self - bias voltage into a digital bias code during the normal mode, converting a first test voltage into a first test code during the first stage of the test mode, and converting a second test voltage into a second test code during the second stage of the test mode includes: selecting the input node during the normal mode and selecting the test node during the test mode to provide an analog input voltage; comparing the analog input voltage with a converted voltage to provide a comparison value; adjusting a digital count value based on the comparison value; decoding the digital count value into a decimal value; converting the decimal value into the converted voltage; and storing the digital count value when the comparison value indicates that the converted voltage is equal to the analog input voltage.

[0017] In one or more embodiments, the conversion includes: serially coupling a resistor array between a pair of reference voltage nodes and forming a plurality of intermediate nodes; coupling a plurality of tap switches at a switching end between a corresponding one of the plurality of intermediate nodes and a common node forming the converted voltage; and controlling the plurality of tap switches by corresponding bits of the decimal value.

[0018] In one or more embodiments, the method further includes: prompting an analog - to - digital converter to convert the self - bias voltage formed at the input node during the normal mode into the digital bias code; prompting the analog - to - digital converter to convert the first test voltage into the first test code during the first stage of the test mode; and prompting the analog - to - digital converter to convert the second test voltage into the second test code during the second stage of the test mode.

[0019] In one or more embodiments, the method further includes: prompting a digital-to-analog converter to convert the upper digital bias code into the first bias voltage during the first phase of the test mode; driving the first bias voltage onto the input node during the first phase of the test mode; prompting the digital-to-analog converter to convert the lower digital bias code into the second bias voltage during the second phase of the test mode; and driving the first bias voltage onto the input node during the first phase of the test mode.

[0020] In one or more embodiments, each of driving the upper digital bias code into the first bias voltage and driving the first bias voltage onto the input node during the first phase of the test mode and driving the lower digital bias code into the second bias voltage and driving the second bias voltage onto the input node during the second phase of the test mode includes: decoding a selected one of the upper digital bias code and the lower digital bias code into a decimal value; converting the decimal value into a converted voltage; and buffering the converted voltage as a selected one of the first bias voltage and the second bias voltage.

[0021] In one or more embodiments, the conversion includes: serially coupling a resistor array between a pair of reference voltage nodes and forming a plurality of intermediate nodes; coupling a plurality of tap switches of a switching terminal between a corresponding one of the plurality of intermediate nodes and a common node forming the converted voltage; and controlling the plurality of tap switches by corresponding bits of the decimal value.

[0022] In one or more embodiments, the method further includes estimating a transconductance of the crystal oscillator amplifier based on a difference between the first test code and the second test code.

[0023] In one or more embodiments, the method further includes evaluating the determined estimate of the transconductance of the crystal oscillator amplifier and providing one of a pass notification and a fail notification. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present invention are illustrated by way of example and are not limited by the drawings. Like reference numerals in the figures may indicate like elements. Elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale.

[0025] Figure 1 is a simplified schematic diagram and block diagram of a crystal oscillator amplifier, the crystal oscillator amplifier being coupled to an built-in self-test (BIST) circuit implemented according to one embodiment for testing a transconductance (gm) of the crystal oscillator amplifier.

[0026] Figure 2 is Figure 1 a simplified schematic diagram and block diagram of a crystal oscillator amplifier, which shows additional details of a current mirror circuit implemented according to one embodiment.

[0027] Figure 3 is implemented according to one embodiment Figure 1 of the ADC's simplified block diagram.

[0028] Figure 4 is implemented according to one embodiment Figure 1 of the DAC's simplified block diagram.

[0029] Figure 5 is a schematic diagram of a tapped resistor array circuit according to one embodiment, which can be used to implement Figure 3 and Figure 4 the first and second tapped resistor arrays of

[0030] Figure 6 is a flowchart showing the operation of the BIST circuit of Figure 1 according to one embodiment. DETAILED DESCRIPTION

[0031] The crystal oscillator amplifier includes a bias current source, a base transistor, and a feedback resistor. During normal operation, the bias current source supplies a bias current from the supply voltage to the base transistor at the output node, where the transistor has a control terminal coupled to the input node. The feedback resistor is coupled between the input node and the output node. The crystal oscillator amplifier generates a negative resistance for an externally coupled crystal, where the negative resistance varies with the transconductance of the crystal oscillator amplifier. The built-in self-test system (BIST) described herein includes: a current mirror circuit system that mirrors the current flowing through the base transistor into a test resistor that forms a test voltage at the test node; a test switch that switches between the bias current source in the normal mode and the current mirror circuit system in the test mode; an analog-to-digital converter (ADC); a digital-to-analog converter (DAC); and a test control circuit system.

[0032] The test control circuit system places the crystal oscillator amplifier in the normal mode and prompts the ADC to convert the self - bias voltage formed at the input node into a digital bias code BC. The test control circuit system increments and decrements the digital bias code by a differential value to form an upper digital bias code BC1 and a lower digital bias code BC0. The test control circuit system then places the crystal oscillator amplifier in the test mode and prompts the DAC to convert BC1 into a first bias voltage, which is driven onto the input node. The current flowing through the base transistor is mirrored by the current mirror circuit system into the test resistor to form a first test voltage VT1, which is converted by the ADC into a first test code TC1. The test control circuit system then prompts the DAC to convert BC0 into a second bias voltage, which is driven onto the input node. The current flowing through the base transistor is mirrored by the current mirror circuit system into the test resistor to form a second test voltage VT0, which is converted by the ADC into a second test code TC0. The test control circuit system estimates the transconductance gm of the crystal oscillator amplifier based on the difference between the first test code and the second test code. Additionally, the test control circuit system can compare the estimated gm value with a transconductance specification value or range to determine whether the crystal oscillator amplifier passes or fails the test.

[0033] Figure 1 FIG. 4 is a simplified schematic diagram and block diagram of a crystal oscillator amplifier 100 that is coupled to a built - in self - test (BIST) circuit 120 implemented in accordance with one embodiment for testing the transconductance (gm) of the crystal oscillator amplifier 100. The BIST circuit 120 includes a single - pole, double - throw (SPDT) switch S0 that has a common terminal labeled "C" and a pair of switching terminals labeled "N" and "T". The switch S0 is controlled by a signal gm_TEST that is "0" in the normal mode where the N terminal is connected to the C terminal and "1" in the test mode where the T terminal is connected to the C terminal. The BIST circuit 120 also includes a single - pole, single - throw (SPST) switch S1 that is open in the normal mode (when gm_TEST = 0) and closed in the test mode (when gm_TEST = 1). The crystal oscillator amplifier 100 includes a bias current source 102, a base transistor M0 configured as an N - type or N - channel MOS (NMOS) transistor or NFET, and a feedback resistor 104 having a resistance RF. Different types of transistors can be used, each including current terminals (e.g., drain and source, emitter and collector) and a control terminal (e.g., gate or base). M0 is shown with an internal body connection coupled to its source terminal.

[0034] The bias current source 102 has an input coupled to the supply voltage VDD and an output that provides a bias current IB to the N terminal of the switch S0. The C terminal of the switch S0 is coupled to an output node 106 that forms the output signal XTAL. M0 has a drain terminal coupled to the output node 106, a source terminal coupled to a supply reference node such as VSS (which can be any suitable voltage level, including ground), and a gate terminal coupled to an input node 108 that forms the input signal EXTAL. The resistor 104 is coupled between the input node 108 and the output node 106.

[0035] During normal operation mode when the gm_TEST signal = 0, the crystal oscillator amplifier 100 is powered to provide a negative resistance to an external crystal (not shown) coupled between EXTAL and XTAL via a corresponding input / output (I / O) pin or pad (not shown), thereby causing oscillation. The negative resistance of the crystal oscillator amplifier 100 varies with its transconductance (gm). A BIST circuit 120 is provided to test the transconductance gm of the crystal oscillator amplifier 100, as further described herein, which is performed without connecting an external crystal.

[0036] The BIST circuit 120 includes another N-type or N-channel MOS (NMOS) or NFET transistor M1, which is a replica or copy transistor of M0 having substantially the same size and the same type or structure. M1 is also shown having an internal body connection coupled to its source terminal. M1 has a source terminal coupled to VSS, a gate terminal coupled to the input node 108, and a drain terminal coupled to a mirror node 122. The BIST circuit 120 includes a current mirror circuit 124 coupled to VDD, where the current mirror circuit 124 has a first terminal coupled to the T terminal of the switch S0, a second terminal coupled to the mirror node 122, and a third terminal coupled to a test node 126 that forms a test voltage VT. A test resistor 128 having a resistance RT is coupled between the test node 126 and VSS.

[0037] The BIST circuit 120 further includes an analog-to-digital converter (ADC) 130 and a digital-to-analog converter (DAC) 132, both of which refer to the same reference voltage VREF, and a selection circuit system in the form of a 2-input multiplexer (MUX) 133. The MUX 133 has a logic "0" input coupled to the input node 108 for receiving the EXTAL voltage, a logic "1" input coupled to the test node 126 for receiving the test voltage VT, and an output for providing an analog input signal AIN. The ADC 130 has an input for receiving AIN and an output for providing a digital code value, which is provided to an input of the test controller 134. The test controller 134 has an output coupled to an input of the DAC 132. The DAC 132 has an output for providing an analog output (AOUT) signal to one switching terminal of the switch S1, and the other switching terminal of the switch is coupled to the output node 108.

[0038] The test controller 134 provides a gm_TEST signal to control the switching between the normal mode and the test mode. The test controller 134 provides a reset signal ARST to reset the ADC 130, and provides another reset signal DRST to reset the DAC 132. It should be noted that each of the reset signals ARST and DRST can be asserted to put the corresponding converter (ADC 130 and DAC 132) in reset, or de-asserted (or negated) to release and prompt the converter to perform a conversion. Each of the reset signals ARST and DRST can be pulsed (e.g., from negated to asserted and back to negated) to prompt the corresponding converter to perform a new conversion. The switches S0 and S1, the MUX 133, and the test controller 134 together form the test control circuit system of the BIST circuit 120. As further described herein, the test controller 134 receives and stores a first test code TC1 and a second test code TC0 during a test operation, estimates the transconductance gm of the crystal oscillator amplifier 100 based on the difference between the test codes TC1 and TC0, evaluates the estimated transconductance gm by comparison with a specification or the like, for example, and provides a pass or fail notification based on the result of the evaluation.

[0039] Now briefly describe the operation of the BIST circuit 120 for estimating the transconductance gm of the crystal oscillator amplifier 100. The test controller 134 first places the BIST circuit 120 in the normal mode by asserting the gm_TEST signal to 0. The switch S0 selects its N terminal, the MUX 133 selects the input node 108, and S1 is open. The bias current IB provided by the bias current source 102 flows through the current terminal of M0, and a self-bias voltage is formed on the input node 108. The input of the ADC 130 receives the analog bias voltage formed on the input node 108 as the input analog voltage AIN. The digital controller 134 prompts the ADC 130 to convert AIN into a digital value CODE, for example, by pulsing the ARST signal, and the digital value is received by the test controller 134 as the digital bias code (BC). The test controller 134 increments and decrements the BC by an incremental digital difference value to provide the upper digital bias code BC1 and the lower digital bias code BC0, respectively. The incremental digital values added to and subtracted from the BC to provide BC1 and BC0 can be expressed in terms of the least significant bit (LSB) of the ADC 130 and the DAC 132. Generally, the incremental digital value can be 1 or 2 LSBs, such that the BC is increased to BC1 and decreased to BC0 to provide two separate digital bias codes on both sides of the BC.

[0040] The test controller 134 then asserts the gm_TEST signal to 1 to place the BIST circuit 120 in the test mode. In the test mode, the switch S0 selects its T terminal, such that M0 is disconnected from the bias current source 102 and instead is coupled to the current mirror circuit 124 via the output node 106, the MUX 133 selects the test node 126 to provide VT as AIN, and the switch S1 is closed to couple the output of the DAC 132 to the input node 108. The test controller 134 then initiates the first stage of the test mode by providing the upper digital bias code BC1 to the DAC 132, and prompts the DAC 132 to convert BC1 into the corresponding first bias voltage VB1, for example, by pulsing the DRST. The DAC 132 thus applies AOUT as VB1 to the input node 108 via the switch S1. In the first stage of the test mode, the corresponding first test current IT1 flowing through M0 is sensed by the current mirror circuit 124 via M1 and mirrored into the test resistor 128 as the first test current IT1, such that the first test voltage VT1 is formed on the test node 126. The test controller 134 prompts the ADC 130 to convert VT1 into the first test code TC1, for example, by pulsing the ARST, and the first test code is received and stored by the test controller 134.

[0041] The test controller 134 then initiates the second phase of the test mode by providing the lower digital bias code BC0 to the DAC 132 and prompts the DAC 132 to convert BC0 into the corresponding second bias voltage VB0, e.g., by pulsing DRST again. The DAC 132 thus applies AOUT as VB0 to the input node 108 via the switch S1. During the second phase of the test mode, the corresponding second test current IT0 flowing through M0 is sensed by the current mirror circuit 124 via M1 and mirrored into the test resistor 128 as the second test current IT0, such that a second test voltage VT0 is formed at the test node 126. The test controller 134 then prompts the ADC 130 to convert VT0 into a second test code TC0, e.g., by pulsing ARST again, and the second test code is received and stored by the test controller 134.

[0042] The test controller 134 can estimate the transconductance gm according to the following equation (1):

[0043]

[0044] where VSTEP is the incremental analog voltage conversion of 1 LSB for the ADC 130 and the DAC 132, and VSTEP is proportional to the reference voltage VREF. Since VSTEP is eliminated from the equation for estimating gm, VREF can be driven from the supply voltages (VDD, VSS). The test controller 134 can evaluate the estimated transconductance gm by comparing it with a minimum specification value or determining whether the estimated transconductance gm falls within a specified transconductance range. Based on the result of the evaluation, the test controller 134 can provide either a pass or a fail notification.

[0045] Figure 2 is a simplified schematic and block diagram of the crystal oscillator amplifier 100, which shows additional details of the current mirror circuit 124 of the BIST circuit 120 implemented according to one embodiment. The crystal oscillator amplifier 100 includes in the same manner as Figure 1A bias current source 102, a base transistor M0, and a feedback resistor 104 are coupled in substantially the same manner as shown. The bias current source 102 is coupled in the same manner between VDD and the N terminal of the switch S0, where the C terminal of the switch S0 is coupled to the output node 106 (XTAL). The current mirror circuit 124 includes a replica N-type transistor M1 and additional mirror transistors M2, M3, and M4 that can be configured as P-type MOS transistors or PFETs or the like. The gate terminal of M1 is coupled to the input node 108, its source terminal is coupled to VSS, and its drain terminal is coupled to the mirror node 122. M2, M3, and M4 each have a source terminal coupled to VDD and a gate terminal coupled to the mirror node 122. M2 is diode-biased, with its drain terminal and gate terminal coupled together at the mirror node 122. The drain terminal of M3 is coupled to the T terminal of the switch S0. The drain terminal of M4 is coupled to the test node 126. The test resistor 128 is shown coupled between the test node 126 and VSS in the same manner. The DAC 132 and the switch S1 are replicated to show the application of the bias voltages VB1 and VB0 during the test mode.

[0046] During normal mode as previously described, the switch S0 transfers the bias current IB from the bias current source 102 through M0, thereby forming an initial self-bias voltage on the input node 108 (EXTAL), which is converted into a digital bias code BC and used to provide an upper digital bias code BC1 and a lower digital bias code BC0. During the first stage of the test mode, BC1 is converted and applied as a first analog bias voltage VB1, causing M3 to generate a first test current IT1 through M0, which is mirrored by M4 to flow through the test resistor 128 that forms a first test voltage VT1 on the test node 126. VT1 is converted into TC1 as previously described. During the second stage of the test mode, BC0 is converted and applied as a second analog bias voltage VB2 to the input node 108, causing M3 to generate a second test current IT0 through M0, which is mirrored by M4 to flow through the test resistor 128 that forms a second test voltage VT0 on the test node 126. VT0 is converted into TC0 as previously described.

[0047] In one embodiment, the ratio of the size of M3 to M4 is 4, the resistance RT of the test transistor 128 is 1 kiloohm (K), and for a total difference of 4 LSBs, the increment and decrement are 2 LSBs. In this way, the transconductance can be estimated as gm = (TC1 - TC0) milliamperes per volt (mA / V).

[0048] Figure 3Is a simplified block diagram of an ADC 130 implemented according to an embodiment. The illustrated ADC circuit 130 includes a comparator 304, a counter 306, a decoder 308, an ADC controller 310, a buffer 312, and a first tapped resistor array 314. AIN is provided to the positive (non-inverting) input of the comparator 304, which receives an analog voltage V_TAP1 at its negative (inverting) input and provides a COMP_OUT signal at its output. COMP_OUT is provided to the input of the counter 306, which outputs a count value to the input of the decoder 308 and the input of the buffer 312. The decoder 308 outputs a decoded decimal value DEC_1 to the input of the tapped resistor array 314, which outputs the V_TAP1 voltage as a converted voltage representing the value of DEC_1. When sampled, the buffer 312 stores the count value as an output code value.

[0049] In one embodiment, the counter 306 is an 8-bit up / down counter that receives a clock signal CLK and provides a count as an 8-bit count value COUNT<0:7>. When ARST is asserted, the counter 306 sets or holds COUNT<0:7> to zero. The decoder 308 converts COUNT<0:7> into a 256-bit decoded decimal value DEC_1<0:255>, where only 1 bit is set to 1 at the time indicating the binary value of COUNT<0:7>. The tapped resistor array 314 converts the decimal value of DEC_1<0:255> into a corresponding voltage V_TAP1 based on VREF. The ADC controller 310 receives CLK, COMP_OUT, and gm_TEST, and provides a signal sample to the buffer 312 to store the current value of COUNT<0:7> as a corresponding 8-bit CODE<0:7> provided to the test controller 134. The code is provided as a digital bias code BC during normal mode (gm_TEST = 0), where the test controller 134 uses BC to generate an upper digital bias code BC1 and a lower digital bias code BC0. The code is provided as a first test code TC1 during the first phase of the test mode and as a second test code TC0 during the second phase of the test mode. After determining TC1 and TC0, the test controller 134 estimates the transconductance gm of the crystal oscillator amplifier 100 as previously described.

[0050] In the operation of the ADC circuit 130, the test controller 134 asserts gm_TEST as 0 for the normal mode and prompts the ADC controller 310 to initiate a measurement, for example, by pulsing ARST to reset the counter 306 to set the count to zero. When the count is zero, the decoded decimal value DEC_1 causes the tap resistor array 314 to assert V_TAP1 at or near zero. The comparator 304 compares AIN with V_TAP1 to generate COMP_OUT. Initially, when V_TAP1 is zero, COMP_OUT is asserted high (to a logic 1 value), causing the counter 306 to increment the count such that the count increments in each of successive CLK cycles. The decoder 308 converts the count value to the decoded decimal value DEC_1, which causes the tap resistor array 314 to incrementally increase the voltage of V_TAP1 in successive cycles of CLK. When V_TAP1 reaches (or otherwise exceeds) AIN, which is the voltage of EXTAL during the normal mode, the controller 310 toggles the sample, causing the buffer 312 to store the count as the output code value. The code is provided to the test controller 134 as BC as previously described.

[0051] During the first and second phases of the test mode, the operation is substantially the same. The test controller 134 asserts gm_TEST as 1 for the test mode and provides BC1 during the first phase as previously described. In the first phase, the test node 126 forms a corresponding first test voltage VT1, which is provided to the ADC 130 as AIN. The test controller 134 prompts the ADC 132, for example, by pulsing ARST, such that the ADC 132 converts VT1 to a corresponding code value, which is provided to the test controller 134 as TC1. The test controller 134 provides BC0 in the second phase, where the test node 126 forms a corresponding second test voltage VT0, which is provided to the ADC 130 as AIN. The test controller 134 prompts the ADC 132, for example, by pulsing ARST, such that the ADC 132 converts VT0 to a corresponding code value, which is provided to the test controller 134 as TC0.

[0052] Figure 4Is a simplified block diagram of the DAC 132 implemented according to an embodiment. The illustrated DAC circuit 132 includes a decoder 402, a second tapped resistor array 404, and an amplifier 406. The decoder 402 operates in substantially the same manner as the decoder 308, except that it receives DRST provided by the test controller 134. The digital bias codes BC1 and BC0 values can each be provided as 8-bit values (each derived from the count value as previously described), where the decoder 402 converts each 8-bit value into a 256-bit decoded decimal value DEC_2<0:255>, where only 1 bit is set to 1 at the time of the decimal value indicating the corresponding digital bias code. The second tapped resistor array 404 is configured in substantially the same manner as the first tapped resistor array 314, each referencing VREF. The tapped resistor array 404 converts the decoded decimal value of BC1 or BC0 (via DEC_2) into a corresponding voltage V_TAP2 based on VREF, where V_TAP2 is the converted voltage representing the value of DEC_2. V_TAP2 is provided to the positive (non-inverting) input of the amplifier 406, the negative (inverting) input of which is coupled to its output, which provides the output analog signal AOUT. The amplifier 406 is configured as a unity gain buffer to drive the voltage level of V_TAP2 as AOUT to the input node 108 during the first and second phases of the test mode.

[0053] In operation, the test controller 134 provides the upper digital bias code BC1 to the DAC circuit 132 during the first phase of the test mode. The test controller 134 pulses the DRST signal, and the decoder 402 and the tapped resistor array 404 convert BC1 into an analog bias voltage VB1. VB1 is driven to the input node 108 by the amplifier 406. The ADC circuit 130 converts VT1 into TC1 as previously described. Subsequently, the test controller 134 provides the lower digital bias code BC0 to the DAC circuit 132 for the second phase of the test mode, and cues the DAC 132 by pulsing DRST. The decoder 402 and the tapped resistor array 404 convert BC0 into an analog bias voltage VB0, which is driven to the input node 108 by the amplifier 406. The ADC circuit 130 converts VT0 into TC0 as previously described.

[0054] Figure 5FIG. 0 is a schematic diagram of a tapped resistor array circuit 500 according to an embodiment, which can be used to implement a first tapped resistor array 314 and a second tapped resistor array 404. The tapped resistor array circuit 500 includes an amplifier 502 having a negative (inverting) input receiving VREF and an output coupled to the gate terminal of another P-type transistor M5. M5 has a source terminal coupled to VDD and a drain terminal coupled to an upper node 504. The first tapped resistor array 314 includes a first array of substantially equal resistors (e.g., each having approximately the same resistance), the resistors being coupled in series between the upper node 504 and VSS to form a corresponding first array of intermediate nodes. The first tapped resistor array 314 further includes a corresponding first array of SPST switches, each of the SPST switches having a first end coupled to a first common node 506 forming a voltage V_TAP1 and a second end coupled to a corresponding one of the first intermediate node array of the first resistor array. Each of the first array of SPST switches has a control terminal receiving a corresponding bit of the decoded decimal value DEC_1. The center node 508 of the first resistor array is coupled to the positive (non-inverting) input of the amplifier 502, with half of the resistors coupled in series between the center node 508 and VSS and the other half coupled in series between nodes 504 and 506. Thus, the amplifier 502 drives the voltage of the center node 508 to VREF, such that the upper node 504 forms a voltage twice that of 2VREF. In this way, the first resistor array divides the voltage 2VREF by substantially equal increments based on the number of resistors.

[0055] The second tapped resistor array 404 is configured in a similar manner to the first tapped resistor array 314. The second tapped resistor array 404 includes a second array of substantially equal resistors (e.g., each having the same resistance), the resistors being coupled in series between the upper node 504 and VSS to form a corresponding second array of intermediate nodes. The second tapped resistor array 404 further includes a corresponding second array of SPST switches, each of the SPST switches having a first end coupled to a second common node 510 forming a voltage V_TAP2 and a second end coupled to a corresponding one of the second intermediate node array of the second resistor array. Each of the second array of SPST switches has a control terminal receiving a corresponding bit of the decoded decimal value DEC_2. Since the second resistor array is coupled between the node 504 and VSS, the second resistor array also divides the voltage 2VREF by substantially equal increments based on the number of resistors.

[0056] The resistance of each resistor in the first resistor array and the second resistor array is substantially equal, such that the first tapped resistor array 314 and the second tapped resistor array 404 are substantially equivalent based on the reference voltage VREF. Reference Figure 3 and Figure 5 , the counter 306 adjusts the count value corresponding to the value converted to DEC_1 by the decoder 308, and the corresponding value selects a corresponding one of the first intermediate nodes of the first tapped resistor array 314 to provide a corresponding voltage of V_TAP1 until V_TAP1 is substantially equal to AIN. In this way, the count value is a digital representation of AIN, which is the voltage of EXTAL in the normal mode or the voltage VT1 or VT0 during the first or second stage of the test mode. Reference Figure 4 and Figure 5 , the upper digital bias code BC1 and the lower digital bias code BC0 are converted by the decoder 402 into corresponding values of DEC_2, and the corresponding values select a corresponding one of the second intermediate nodes of the second tapped resistor array 404 to provide a corresponding one of the bias voltages VB1 and VB0, which are used to generate the test voltages VT1 and VT0 respectively during the first and second stages of the test mode as previously described. The test voltages VT1 and VT0 are converted into the first test code TC1 and the second test code TC0 using the first tapped resistor array 314 as previously described.

[0057] In one embodiment, the first resistor array includes 256 resistors R1<0:255>, forming 256 intermediate nodes, each of which is coupled to a corresponding one of the first array of 256 SPST switches, and each switch is controlled by a corresponding bit of DEC_1<0:255>. In this way, 2VREF is divided into 256 substantially equal voltage increments selected by DEC_1<0:255>. Also, the second resistor array includes 256 resistors R2<0:255>, forming 256 intermediate nodes, each of which is coupled to a corresponding one of the second array of 256 SPST switches, and each switch is controlled by a corresponding bit of DEC_2<0:255>. In this way, 2VREF is also divided into 256 substantially equal voltage increments selected by DEC_2<0:255>.

[0058] Figure 6is a flowchart showing the operation of the BIST circuit 120 according to one embodiment. The test controller 134 generally controls the test operation mode by controlling the gm_TEST signal, by prompting the ADC 130 and the DAC 132 via the ARST and DRST signals respectively, and by performing various calculations. At the first block 602, the test controller 134 of the BIST circuit 120 places the crystal oscillator amplifier 100 in the normal mode, for example, by asserting gm_TEST to 0. At the next block 604, the BIST circuit 120 converts the self-biased voltage formed on the input node 108 into a digital bias code BC. At the next block 606, BC is incremented by a digital difference value to determine an upper digital bias code BC1, and BC is also decremented by the digital difference value to determine a lower digital bias code BC0. In one embodiment, the test controller 134 is configured to derive BC1 and BC0 based on BC. At the next block 608, the test controller 134 of the BIST circuit 120 places the crystal oscillator amplifier 100 in the test mode, for example, by asserting gm_TEST to 1. In the test mode, the current flowing through the base transistor M0 of the crystal oscillator amplifier 100 is mirrored into the test resistor 128, thereby forming a corresponding test voltage VT on the test node 126.

[0059] The next block 610 starts the first stage of the test mode. At block 610, the test controller 134 prompts the DAC 132 to convert BC1 into a first analog bias voltage VB1, which is applied to the input node 108 of the crystal oscillator amplifier 100 via the switch S1. At the next block 612, the test controller 134 prompts the ADC 130 to convert the test voltage VT1 formed on the test node 126 into a digital equivalent test code TC1, which is received and stored by the test controller 134. The next block 614 starts the second stage of the test mode. At the next block 614, the test controller 134 prompts the DAC 132 to convert BC0 into a second analog bias voltage VB0, which is applied to the input node 108 of the crystal oscillator amplifier 100 via the switch S1. At the next block 616, the test controller 134 prompts the ADC 130 to convert the test voltage VT0 formed on the test node 126 into a digital equivalent test code TC0, which is received and stored by the test controller 134. At the next block 618, the test controller 134 calculates the estimated transconductance gm using the test codes TC1 and TC0 as previously described, where the transconductance gm can subsequently be evaluated by the test controller 134. In one embodiment, this evaluation is a comparison with the gm specification, such as whether gm is at least a minimum value or falls within a predetermined acceptable range of gm values. At the next block 620, it is queried whether the gm value falls within the required specification, such as the range of acceptable gm values. If so, the operation proceeds to block 622, where a pass notification is provided by the test controller 134. If not, the operation proceeds to block 624, where a fail notification is provided by the test controller 134. Additional remedial steps may be taken if required. From block 622 or 624, the operation proceeds to block 626 to query whether another test will be performed. If not, the operation is complete. Otherwise, the operation loops back to block 602, where the entire process is repeated.

[0060] Although the invention has been described in connection with several embodiments, it is not intended that the invention be limited to the specific forms set forth herein. Rather, it is intended to cover such alternatives, modifications, and equivalents as may reasonably be included within the scope of the invention as defined by the appended claims. For example, in various embodiments in which the invention is not limited to a particular circuit system polarity, device type, or voltage or error levels, etc., variations of positive or negative circuit systems may be used. For example, circuit system states such as circuit system low level and circuit system high level may be reversed depending on whether the pin or signal is implemented in a positive or negative circuit system, etc. In some cases, the circuit system state may be programmable, where the circuit system state can be reversed for a given circuit system function.

[0061] As used herein, the term "a" is defined as one or more than one. Additionally, the use of leading phrases such as "at least one" and "one or more" in the claims should not be construed to imply that another claim element preceded by the indefinite article "a" limits any particular claim containing such a claimed element to an invention having only one such element, even when the same claim includes the leading phrase "one or more" or "at least one" and an indefinite article such as "a". The foregoing applies to the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used arbitrarily to distinguish the elements so described. Thus, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.

Claims

1. A built-in self-test system for a crystal oscillator amplifier, characterized in that: The crystal oscillator amplifier includes a bias current source sourcing current from a supply voltage, a base transistor having a current terminal coupled between an output node and a supply reference node and having a control terminal coupled to an input node, and a feedback resistor coupled between the input node and the output node, the built-in self-test system comprising: current mirror circuitry capable of mirroring a current through the current terminal of the base transistor into a test resistor coupled to a test node during a first phase and a second phase of a test mode; test control circuitry including a test switch controlled by a test mode signal to couple the output node to the bias current source during a normal mode and to couple the output node to the current mirror circuitry during the test mode; an analog-to-digital converter capable of converting a self-bias voltage formed on the input node during the normal mode into a digital bias code, capable of converting a first test voltage on the test node into a first test code during the first stage of the test mode, and capable of converting a second test voltage on the test node into a second test code during the second stage of the test mode; The test control circuitry further includes a test controller capable of providing the test mode signal to switch between the normal mode and the test mode, and capable of incrementing and decrementing the digital bias code by a differential value to provide an upper digital bias code and a lower digital bias code during the first stage and the second stage of the test mode, respectively; and a digital-to-analog converter capable of converting the upper digital bias code into a first bias voltage driven onto the input node during the first phase of the test mode and capable of converting the lower digital bias code into a second bias voltage driven onto the input node during the second phase of the test mode.

2. The built-in self-test system according to claim 1, characterized in that: The current mirror circuit system comprises: a first transistor that is a replica of the base transistor, the first transistor having a current terminal coupled between a mirror node and the supply reference node and having a control terminal coupled to the input node; a second transistor having a current terminal coupled between the supply voltage and the mirror node and having a control terminal coupled to the mirror node; a third transistor having a current terminal coupled between the supply voltage and the test switch and having a control input coupled to the mirror node; and A fourth transistor has a current terminal coupled between the supply voltage and the test node and has a control input coupled to the mirror node.

3. The built-in self-test system according to claim 1, wherein: The test control circuitry further includes selection circuitry controlled by the test mode signal to select the input node during the normal mode and to select the test node to provide an analog input voltage during the test mode; and The analog-to-digital converter comprises: a comparator configured to compare the analog input voltage with a tap voltage to provide a comparison value; a counter configured to adjust a digital count value based on the comparison value; a decoder configured to decode the digital count value into a decimal value; a converter configured to convert the decimal value into the tap voltage; and A buffer stores the digital count value when the comparison value indicates that the tap voltage is equal to the analog input voltage.

4. The built-in self-test system according to claim 3, characterized in that: The converter comprises: a resistor array coupled in series between a pair of reference voltage nodes and forming a plurality of intermediate nodes; and A plurality of tap switches each having a switching terminal coupled between a corresponding one of the plurality of intermediate nodes and a common node forming the tap voltage, wherein each of the plurality of tap switches has a control terminal controlled by a corresponding bit of the decimal value.

5. The built-in self-test system according to claim 1, characterized in that: The test controller is configured to prompt the analog-to-digital converter to convert the input voltage into the digital bias code during the normal mode, to prompt the analog-to-digital converter to convert the first test voltage into the first test code during the first phase of the test mode, and to prompt the analog-to-digital converter to convert the second test voltage into the second test code during the second phase of the test mode.

6. The built-in self-test system according to claim 1, characterized in that: The test control circuitry includes a switch controlled by the test mode signal to the output of the digital-to-analog converter to the input node during the test mode; and wherein the test controller is configured to prompt the digital-to-analog converter to convert the upper digital bias code to the first bias voltage during the first phase of the test mode, and to prompt the digital-to-analog converter to convert the lower digital bias code to the second bias voltage during the second phase of the test mode.

7. The built-in self-test system according to claim 1, characterized in that: The digital-to-analog converter comprises: a decoder configured to decode a selected one of the upper digital offset code and the lower digital offset code into a decimal value; a converter configured to convert the decimal value into a converted voltage; and A buffer is configured to buffer the converted voltage as a selected one of the first bias voltage and the second bias voltage.

8. The built-in self-test system according to claim 7, characterized in that: The converter comprises: a resistor array coupled in series between a pair of reference voltage nodes and forming a plurality of intermediate nodes; and A plurality of tap switches each having a switching terminal coupled between a corresponding one of the plurality of intermediate nodes and a common node forming the converted voltage, wherein each of the plurality of tap switches has a control terminal controlled by a corresponding bit of the decimal value.

9. The built-in self-test system according to claim 1, characterized in that: The test control circuitry is configured to estimate a transconductance of the crystal oscillator amplifier based on a difference between the first test code and the second test code.

10. A method for performing built-in self-test on a crystal oscillator amplifier, characterized in that: The crystal oscillator amplifier includes a bias current source sourcing a bias current from a supply voltage, a base transistor having a current terminal coupled between an output node and a supply reference node and having a control terminal coupled to an input node, and a feedback resistor coupled between the input node and the output node, the method comprising: coupling the output node to the bias current source to source the bias current through the current terminal of the base transistor during a normal mode and converting a self-bias voltage formed on the input node during the normal mode into a digital bias code; coupling the output node to mirror circuitry during a test mode and mirroring a current through the current terminal of the base transistor into a test resistor coupled to a test node during the test mode; incrementing the digital bias code by a differential value to provide an upper digital bias code during a first phase of the test mode, converting the upper digital bias code to a first bias voltage, and driving the first bias voltage to the input node; decrementing the digital bias code by the delta value to provide a lower digital bias code during a second phase of the test mode, converting the lower digital bias code to a second bias voltage, and driving the second bias voltage to the input node; and A first test voltage on the test node is converted into a first test code during the first phase of the test mode, and a second test voltage on the test node is converted into a second test code during the second phase of the test mode.

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