A method for measuring semiconductor nonlinear output junction capacitance based on fitting iteration

Abstract

This invention relates to the field of semiconductor device measurement technology, and proposes a method for measuring the nonlinear output junction capacitance of semiconductors based on fitting iteration. This method first constructs a junction capacitance extraction circuit, and then acquires the turn-off transient waveform of the device under test through a test platform. Finally, it uses Fast Fourier Transform to extract the oscillation frequency f. exp Based on the relationship between the oscillation frequency, junction capacitance, and parasitic parameters, the initial junction capacitance C is deduced. oss Subsequently, a hyperbolic tangent function was used for fitting, and the fitting parameters were optimized using the least squares method to obtain the preliminary junction capacitance C under different voltage levels. oss - Test voltage u dc Based on the relationship curve, a simulation circuit for the oscillation frequency was further constructed to obtain the simulation frequency f. m and f m with f exp The fitting curve is compared, and if a deviation exists, the fitting curve is adjusted and iteratively optimized until the error between two adjacent fitting results is lower than the set error threshold, thus obtaining the final accurate junction capacitance C. oss - Test voltage u dc Relationship curve.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device measurement, and particularly relates to a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration. BACKGROUND

[0002] The nonlinear change of the output junction capacitance of a high-voltage semiconductor device with voltage brings a series of challenges to the design and application of the power device. This change trend makes it more difficult to accurately measure and model the output junction capacitance under high-voltage conditions, and the traditional low-voltage measurement method may not cover the capacitance change range under high-voltage conditions. At the same time, in high-voltage high-frequency applications, the nonlinear change of the output junction capacitance may cause unstable switching speed and energy loss in the soft switching process, thereby affecting the efficiency and reliability of the power device. Therefore, accurately extracting the output junction capacitance of the high-voltage semiconductor device under the corresponding working condition is crucial for optimizing the performance of the power device and improving the system efficiency.

[0003] At present, the output junction capacitance extraction methods of semiconductor devices mainly include instrument methods and simulation methods. The instrument methods usually use special instruments such as high-frequency Q tables, small-capacitance measuring instruments, and impedance analyzers for measurement.

[0004] The measurement results of the first two instruments are reliable, but are limited by the low measurement voltage range, and cannot accurately extract the output junction capacitance value in the high-voltage range. Although the impedance analyzer can measure the output capacitance under high-voltage conditions, its use and maintenance cost is high. The simulation method usually needs to use commercial simulation software such as TCAD and Multiphysics to model the device structure accurately to simulate the junction capacitance behavior mode under high-voltage and high-frequency conditions. Since there are many types of high-voltage semiconductor devices, it is impossible to model and accurately simulate each type of device in practice, and there is a great limitation in universality. SUMMARY

[0005] The purpose of the present application is to solve the problems of the prior art, and to provide a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration, which realizes high-precision modeling of the nonlinear characteristics of the output junction capacitance through semiconductor model fitting and multiple frequency matching iterations, can effectively reduce the measurement error in the strong nonlinear region, and is suitable for wide-voltage-range junction capacitance testing of various high-voltage semiconductor devices.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme:

[0007] A semiconductor nonlinear output junction capacitance measurement method based on fitting iteration, comprising the following steps:

[0008] Step 1, build a semiconductor device junction capacitance extraction circuit;

[0009] Step 2, connect the device under test to the junction capacitance extraction circuit, obtain the turn-off transient waveform of the device under test through the test platform, and obtain the oscillation frequency f using fast Fourier transform exp ; use the relationship between the oscillation frequency f exp , the junction capacitance and the platform parasitic parameters to back-calculate the initial junction capacitance C oss of the device under test, and generate the initial junction capacitance C dc -voltage u oss data set in combination with the actual test voltage u dc ;

[0010] Step 3, fit the initial junction capacitance C oss -voltage u dc data set generated in step 2 using the hyperbolic tangent function, optimize the fitting parameters using the least squares method, and obtain the preliminary junction capacitance C oss -voltage u dc relationship curve;

[0011] Step 4, build an oscillation frequency simulation circuit to simulate the dynamic behavior of the output junction capacitance C oss , obtain the simulation frequency f m , and compare f m with f exp to determine the accuracy of the fitting curve;

[0012] Step 5, if there is a deviation between f m and f exp , fine-tune the C oss values corresponding to each voltage point in the fitting curve, update the junction capacitance C oss -voltage u dc data set, and re-fit using the hyperbolic tangent function;

[0013] Step 6, repeat the iteration process of steps 4 and 5 until the error of the adjacent two rounds of fitting results meets the preset convergence condition, thereby obtaining the final accurate output junction capacitance C oss -voltage u dc relationship curve.

[0014] Preferably, the semiconductor device junction capacitance test platform in step 1 comprises: a direct current power supply unit u dc , a DUT port, a diode D, and a load inductance L load connected in series; the DUT port is connected in parallel with a power device S, and the power device S, the diode and the direct current power supply unit form a turn-off transient oscillation loop; when the test voltage is high, the power device S can be in the form of multiple devices connected in series for voltage division.

[0015] Preferably, the step 2 is characterized in that the device to be tested is connected to the extraction circuit under different test voltages u dc The off transient oscillation is excited under the condition, the time-domain waveform is collected, and the measured oscillation frequency is calculated by the following formula:

[0016]

[0017] Wherein, L loop is the platform parasitic inductance, C serial is the equivalent capacitance of the power device, C oss is the output junction capacitance of the device to be tested.

[0018] Preferably, the specific expression of the step 3 is fitted by the hyperbolic tangent function:

[0019] C oss =C0+A·tanh(B·u dc );

[0020] Wherein, C0, A and B are fitting parameters to be determined by the least square method.

[0021] Preferably, the step 4 simulates the transient behavior of the device to be tested under different test voltages by the following formula:

[0022]

[0023] Wherein, i oss (t) is the transient current, C oss (u ds (t)) is the junction capacitance corresponding to the voltage u ds (t), u ds (t) is the drain-source voltage in the off transient oscillation process, i load (t) is the load current.

[0024] Preferably, the step 6 is characterized in that when the relative error between the C oss values obtained by the adjacent two rounds of fitting is less than the set error threshold, the iteration process is terminated, and the final accurate output junction capacitance C oss is output. -Test voltage u dc relationship curve.

[0025] The application discloses a semiconductor nonlinear output junction capacitance measurement method based on fitting iteration, which has the following beneficial effects.

[0026] The application can effectively improve the measurement accuracy, avoid the error caused by ignoring the nonlinear characteristics of the junction capacitance in the traditional method, extract the oscillation frequency through fast Fourier transform (FFT), and combine the hyperbolic tangent function fitting and the least square method optimization to obtain more accurate junction capacitance C oss -test voltage udc The relationship curve is fitted by using an iterative optimization strategy, dynamic comparison of the simulation frequency and the measured data, continuous optimization of the fitting result, guarantee of the accuracy and convergence of the measurement, elimination of the influence of the parasitic parameters of the test platform on the measurement result, and improvement of the stability and universality of the measurement. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The semiconductor device junction capacitance test platform of the application.

[0028] Figure 2 The measurement time domain waveform diagram when the test voltage is set to 200V in the embodiment of the application.

[0029] Figure 3 The simulation frequency iterative model of the application.

[0030] Figure 4 The multiple iteration curve and output result in the embodiment of the application and the curve in the data manual.

[0031] Figure 5 The semiconductor nonlinear output junction capacitance measurement method flowchart based on fitting iteration of the application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application.

[0033] In this document, the term "embodiment" refers to a specific feature, structure, or characteristic described in connection with an embodiment. The appearance of the term "embodiment" in various places in the specification is not necessarily referring to the same embodiment, nor is it necessarily referring to a particular embodiment at all. In principle, any feature described in relation to any one embodiment can be combined with features of any other embodiment, unless technically incompatible, to form a further embodiment.

[0034] Unless otherwise defined, the technical terms used in this document have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the use of related terms in this document is only for the purpose of describing specific embodiments, and is not intended to limit the application.

[0035] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.

[0036] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0037] Example

[0038] In this embodiment, a MOSFET module with a rated withstand voltage of 3.3kV is used as the device under test. Please refer to [reference needed]. Figures 1 to 5 A method for measuring the nonlinear output junction capacitance of a semiconductor based on fitting iteration includes the following steps:

[0039] Step 1, set up as follows Figure 1 The circuit shown is for extracting the junction capacitance of a semiconductor device.

[0040] Specifically, the semiconductor device junction capacitance test platform in step 1 includes: DC power supply units u connected in series. dc DUT port, diode D, load inductor L load A power device S is connected in parallel across the two ends of the DUT port. The power device S, together with the diode and the DC power supply unit, forms a turn-off transient oscillation circuit. When the test voltage is high, the power device S can be used in series to divide the voltage.

[0041] Step 2: Connect the device under test (DUT) to the junction capacitance extraction circuit, acquire the turn-off transient waveform of the DUT through the test platform, and obtain the oscillation frequency f using Fast Fourier Transform. exp ; using the oscillation frequency f exp From the relationship between junction capacitance and plateau parasitic parameters, the initial junction capacitance C of the device under test can be derived. oss Value, generating the initial junction capacitance C oss -Test voltage u dc Dataset;

[0042] Specifically, in step 2, the device under test is connected to the extraction circuit, and different test voltages u are applied. dcUnder certain conditions, transient oscillations during turn-off are excited, and time-domain waveforms are acquired. The turn-off transient time-domain waveforms of the semiconductor device under different test voltages are measured, such as... Figure 2 As shown, the measured oscillation frequency is calculated using the following formula:

[0043]

[0044] Among them, L loop For the platform's parasitic inductance, C serial C is the equivalent capacitance of the power device. oss L is the output junction capacitance of the device under test; in this embodiment, L loop C serial Pre-measurement is required, and the measurement steps are as follows:

[0045] The experimental platform was short-circuited beforehand to obtain the transient oscillation frequency f0 of the switch. A known capacitance C was connected in parallel with the switch. add The capacitor is used to obtain the transient oscillation frequency f of the switch. add .

[0046] in L can be calculated from the measured frequency. loop C serial .

[0047] Step 3: Apply the hyperbolic tangent function to the initial junction capacitance C generated in Step 2. oss -Test voltage u dc The dataset was fitted, and the least squares method was used to optimize the fitting parameters to obtain the preliminary junction capacitance C. oss -Test voltage u dc Relationship curve;

[0048] Specifically, the specific expression for fitting the hyperbolic tangent function in step 3 is as follows:

[0049] C oss =C0+A·tanh(B·u) dc );

[0050] Where C0, A, and B are the parameters to be fitted, determined by the least squares method; in this embodiment, the steps for obtaining the fitted parameters are as follows:

[0051] 1. Set the fitting model as the hyperbolic tangent function shown in the above formula.

[0052] 2. The dataset consists of voltage u. dc Initial capacitance value C oss .

[0053] 3. Set the initial values ​​of parameters C0, A, and B to 35000, 35000, and -0.001, respectively.

[0054] 4. The optimal fitting result was obtained by the least squares method. C0 is 24508.6625, and A and B are 19344.8979 and -0.0043888, respectively.

[0055] Step 4, build as follows Figure 3 The simulation circuit for the oscillation frequency shown simulates the output junction capacitance C. oss The dynamic behavior of the simulation frequency f is obtained. m and f m with f exp Compare the fitted curves to determine their accuracy;

[0056] Specifically, step 4 simulates the transient behavior of the device under test under different test voltages using the following formula:

[0057]

[0058] Among them, i oss (t) is the transient current, C oss (u ds (t) represents the voltage u ds The junction capacitance corresponding to (t), u ds (t) represents the drain-source voltage during the turn-off transient oscillation process, i load (t) represents the load current;

[0059] It should be noted that for C, which forms the oscillating waveform oss In terms of u ds Changes will cause C oss The value of C changes, therefore, in practice, C at each moment... oss It is based on the voltage taken from the voltage-capacitance curve obtained in the previous round of fitting, the specific process is as follows: Figure 3 As shown.

[0060] Functional module 1: Based on the fitted junction capacitance C oss -Test voltage u dc Determine C under different voltages during the oscillation process from the relationship curve. oss value.

[0061] Functional Module 2: Used to simulate voltage changes during the turn-off transient oscillation process. C during the turn-off transient process. oss With load current i load u ds The relationship can be expressed by equation (1), therefore functional module 2 can be obtained through C at each time step. oss u ds with i load The calculated voltage value at the next moment is shown in equation (2). The calculation result is output to the drain-source voltage u. dsThis completes the transient simulation of the oscillation process. The resulting u... ds The simulated oscillation frequency f can be obtained by performing a Fast Fourier Transform on the transient time-domain waveform. m .

[0062] Step 5, if f m with f exp If there is a deviation, then the C corresponding to each voltage point in the fitted curve... oss The value is fine-tuned, and the junction capacitance C is updated. oss -Test voltage u dc The dataset is refitted using the hyperbolic tangent function. In this embodiment, the maximum test error between the adjusted capacitance value and the previous capacitance value is 5.5%. If the maximum error between the adjusted capacitance value and the previous capacitance value does not meet the convergence condition, fitting and iteration continue. In this embodiment, the maximum error is 5.5%, so iterative optimization is required, necessitating further fitting and iteration. The fitted parameters C0 are 24566.2855, and A and B are 19708.2705 and -0.0043313, respectively.

[0063] Step 6: Repeat the iterative process of steps 4 and 5 until the error of the fitting results of two adjacent rounds meets the preset convergence condition, at which point the iterative process terminates. More specifically, in this embodiment, the error convergence threshold is set to 2%, and the error convergence threshold is set at C obtained from two adjacent rounds of fitting. oss When the relative error between the values ​​is less than 2%, the iteration process terminates. The maximum test error between the capacitance value after the second fitting adjustment and the capacitance value in the previous round is 1.9%, which satisfies the condition for iteration convergence, and the result is as follows: Figure 4 The output junction capacitance C shown is the result of each round of iterative optimization. oss -Test voltage u dc The relationship curve is used to obtain the final accurate output junction capacitance C. oss -Test voltage u dc Relationship curve; such as Figure 4 As shown, to verify the measurement accuracy of the method, the output junction capacitance measurement curve of the working interval in the embodiment was compared with the corresponding datasheet. The maximum measurement error did not exceed 0.1%, proving the measurement accuracy of the present invention. Based on the analysis of turn-off transient oscillations, the present invention significantly reduces the oscillation frequency deviation caused by junction capacitance nonlinearity through multiple rounds of fitting iterations, thus improving measurement accuracy. Combining experimental data and theoretical fitting, it can dynamically correct the measurement error at different voltage points, especially showing superior performance in the strongly nonlinear region. This method can be applied to the measurement of nonlinear characteristics of different types of semiconductor devices (such as MOSFETs, IGBTs, etc.) and has shown good measurement results on discrete semiconductor devices or modules at the 3.3kV level.

[0064] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Substitutions may include replacements of some structures, devices, or method steps, or may be complete technical solutions. Equivalent substitutions or modifications made to the technical solutions and inventive concepts of the present invention should all be covered within the scope of protection of the present invention.

Claims

1. A method for measuring the output junction capacitance of a semiconductor device based on fitting iterations, the method comprising: The method comprises the following steps: Step 1, building a semiconductor device junction capacitance extraction circuit; Step 2, initial data acquisition; the device under test is connected to the junction capacitance extraction circuit, the off-state transient waveform of the device under test is obtained through the test platform, the oscillation frequency f is obtained by using fast Fourier transform exp ; the initial junction capacitance C oss of the device under test is inversely deduced by using the relationship between the oscillation frequency f exp and the junction capacitance and the platform parasitic parameters, combined with the actual test voltage u dc , to generate the initial junction capacitance C oss -test voltage u dc data set; Step 3, preliminary fitting; the initial junction capacitance C generated in step 2 is fitted with a hyperbolic tangent function oss - test voltage u dc The data set is fitted, the fitting parameters are optimized with the least squares method, and the preliminary junction capacitance C is obtained oss - test voltage u dc Relationship curve; Step 4, simulation frequency matching; build the simulation circuit of oscillation frequency, simulate the dynamic behavior of output junction capacitance C oss , obtain the simulation frequency f m , and compare f m with f exp to determine the accuracy of the fitting curve; Step 5, iterative optimization of the curve fitting; if f m deviation exists between f exp , then the C oss value corresponding to each voltage point in the fitting curve is fine-tuned, and the junction capacitance C oss is updated - test the voltage u dc data set, and re-adopt the hyperbolic tangent function fitting; Step 6, obtain final accurate output junction capacitance C oss - test voltage u dc relationship curve; The iterative process of steps 4 and 5 is repeated until the error of the fitting results of two adjacent rounds meets a preset convergence condition, so as to obtain a final accurate output conclusion capacitor C oss - test voltage u dc Relationship curve.

2. The method of claim 1, wherein the fitting iteration based semiconductor non-linear output junction capacitance measurement method is characterized by, The semiconductor device junction capacitance test platform in step 1 comprises: a direct current power supply unit u dc , a DUT port, a diode D, and a load inductor L load ; the DUT port is connected in parallel with a power device S, and the power device S, the diode, and the direct current power supply unit constitute an off transient oscillation loop; when the test voltage is high, the power device S can adopt a multi-device series connection form for voltage division.

3. The method of claim 1, wherein the method is based on fitting iterations for semiconductor nonlinear output junction capacitance measurement, and wherein the method further comprises: determining a first set of parameters for a first iteration of the fitting iterations; determining a second set of parameters for a second iteration of the fitting iterations; and determining a third set of parameters for a third iteration of the fitting iterations. The step 2 connects the device under test into the extraction circuit, and the different test voltages u dc The step 2 connects the device under test into the extraction circuit, and the different test voltages u dc The step 2 connects the device under test into the extraction circuit, and the different test voltages u dc The step 2 connects the device under test into the extraction circuit, and the different test voltages u dc The step 2 connects the device under test into the extraction circuit, and the where L loop is the platform parasitic inductance, C serial is the equivalent capacitance of the power device, C oss is the output junction capacitance of the device under test.

4. The method of claim 1, wherein the fitting iteration based semiconductor non-linear output junction capacitance measurement method is characterized by, The specific expression of the hyperbolic tangent function fitting in the step 3 is as follows: C oss = C0+ A · tanh(B · u dc ); Wherein, C0, A and B are to-be-fitted parameters, and are determined by the least square method.

5. The method of claim 1, wherein the fitting iteration based semiconductor non-linear output junction capacitance measurement method is characterized by, The step 4 simulates the transient behavior of the device to be tested under different test voltages by the following formula: where i oss (t) is the transient current, C oss (u ds (t) is the voltage u ds (t) is the corresponding junction capacitance, u ds (t) is the drain-source voltage during the turn-off transient oscillation, i load (t) is the load current.

6. The method of claim 1, wherein the fitting iteration based semiconductor non-linear output junction capacitance measurement method further comprises: The relative error between the C oss The iteration process is terminated when the relative error between the C oss - test voltage u dc relationship curve.

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