Chip testing device and method

Abstract

The invention discloses a chip testing device and method, and relates to the field of chip testing, the chip testing device comprises a main control module and a signal path switching module, and the main control module is connected with a tested chip through the signal path switching module; the main control module is used for controlling the signal path switching module to conduct a first channel of the tested chip based on a pin number of the tested chip required by a target task in the target configuration file, so as to process the target task through the first channel, and under the condition that the target task is switched, the tested chip is switched; and based on the pin number of the tested chip required by the switched target task in the target configuration file, controlling the signal path switching module to conduct a second channel of the tested chip so as to process the switched target task through the second channel. The chip testing efficiency can be improved.

Description

Technical Field

[0001] This application relates to the technical field of chip testing applications, and in particular, to a chip testing device and method. Background Art

[0002] When chip users replace microcontrollers, for the testing of chips with different cores, packages, and manufacturers, the chips can only be selected for product application research after going through processes such as principle design, PCB (Printed Circuit Board) design, board making and trial production, and debugging. However, this process takes a long time and the chip testing efficiency is low. Therefore, it is very necessary to perform chip suitability testing for different types of chips to reduce the difficulty of testing operations and improve the chip testing efficiency. Summary of the Invention

[0003] In view of the above problems, this application provides a chip testing device and method, which can improve the chip testing efficiency. The specific solutions are as follows:

[0004] In the first aspect of this application, a chip testing device is provided, including:

[0005] A main control module and a signal path switching module;

[0006] The main control module is connected to the chip under test through the signal path switching module;

[0007] The main control module is configured to control the signal path switching module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel. In the case of switching the target task, based on the pin numbers of the chip under test required for the switched target task in the target configuration file, the signal path switching module is controlled to conduct the second channel of the chip under test, so as to process the switched target task through the second channel.

[0008] In a possible implementation, the signal path switching module includes:

[0009] A power control array;

[0010] The power control array is respectively connected to the main control module, the chip under test, and the power supply device;

[0011] The main control module is configured to control the power control array to conduct the power supply channel of the chip under test based on the power supply pin numbers of the chip under test in the target configuration file, so that the power supply device provides the required voltage for the chip under test through the power supply channel.

[0012] In a possible implementation, the signal path switching module further includes:

[0013] A switch array module;

[0014] The switch array module is respectively connected to the main control module, the chip under test, and the test equipment;

[0015] The main control module is used to control the switch array module to conduct the channel connecting the terminal to the download pin of the chip under test based on the download pin number of the chip under test in the target configuration file, so that the terminal downloads the test program to the chip under test;

[0016] The main control module is further used to control the switch array module to conduct the channel connecting the main control module to the pin to be tested of the chip under test and / or control the switch array module to conduct the channel connecting the pin to be tested of the chip under test to the test equipment based on the pin number to be tested of the chip under test required for the test task in the target configuration file, so that the chip under test running the test program executes the test task.

[0017] In a possible implementation, the switch array module includes:

[0018] A first switch array and a second switch array;

[0019] The first switch array is respectively connected to the main control module, the chip under test, and the second switch array;

[0020] The second switch array is connected to the main control module and the test equipment;

[0021] The main control module is used to control the first switch array to conduct the channel connecting the pin to be tested of the chip under test to the second switch array based on the pin number to be tested of the chip under test, and control the second switch array to conduct the channels connecting the main control module to the test equipment and the chip under test, so that the main control module receives the test data transmitted by the chip under test and / or the test equipment.

[0022] In a possible implementation,

[0023] The second switch array is connected to a clock device and / or the second switch array is connected to peripheral components;

[0024] The main control module is used to control the second switch array to conduct the clock channel of the chip under test based on the clock pin number of the chip under test in the target configuration file, so that the clock device provides the required clock signal for the chip under test through the clock channel;

[0025] The master control module is used to control the second switch array to conduct the connection channel between the chip under test and the peripheral components based on the function pin numbers of the chip under test in the target configuration file, so as to perform the reset operation and / or mode selection operation of the chip under test.

[0026] The second aspect of this application provides a chip testing method, which is applied to the chip testing device in the first aspect or any implementation manner of the first aspect. The method includes:

[0027] The master control module obtains a target configuration file;

[0028] The master control module controls the signal path switching module connected to the master control module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel;

[0029] If the current operation step is not the last operation step in the chip testing process and in the case of target task switching, the master control module controls the signal path switching module to conduct the second channel of the chip under test based on the pin numbers of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel.

[0030] In a possible implementation, the master control module controls the signal path switching module connected to the master control module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel, including:

[0031] The master control module controls the power control array of the signal path switching module to conduct the power supply channel of the chip under test based on the power supply pin numbers of the chip under test required for the power supply task in the target configuration file, so that the power supply device provides the required voltage for the chip under test through the power supply channel;

[0032] The master control module controls the signal path switching module to conduct the second channel of the chip under test based on the pin numbers of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel, including:

[0033] The master control module controls the switch array module of the signal path switching module to conduct the clock channel of the chip under test based on the clock pin numbers of the chip under test required for the clock task in the target configuration file, so that the clock device provides the required clock signal for the chip under test through the clock channel.

[0034] In a possible implementation, the main control module controls the signal path switching module connected to the main control module to turn on the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel, including:

[0035] The main control module controls the switch array module of the signal path switching module to turn on the channel connecting the terminal to the download pin of the chip under test based on the download pin numbers of the chip under test required for the download task in the target configuration file, so that the terminal downloads the target program to the chip under test; wherein, the target program includes a test program;

[0036] The main control module controls the signal path switching module to turn on the second channel of the chip under test based on the pin numbers of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel, including:

[0037] The main control module controls the switch array module to turn on the channel connecting the main control module to the pins to be tested of the chip under test and / or controls the switch array module to turn on the channel connecting the pins to be tested of the chip under test to the test equipment based on the pin numbers of the chip under test required for the test task in the target configuration file, so that the chip under test runs the test program to perform a test operation.

[0038] In a possible implementation, the test equipment includes a working condition test device and a measuring device;

[0039] The main control module controls the switch array module to turn on the channel connecting the pins to be tested of the chip under test to the test equipment based on the pin numbers of the chip under test required for the test task in the target configuration file, so that the chip under test runs the test program to perform a test operation, including:

[0040] The main control module determines the pin numbers of the chip under test required for the test task and the test working condition conditions required for the chip under test to execute the test task from the target configuration file;

[0041] The main control module controls the switch array module to turn on the channel connecting the pins to be tested of the chip under test to the working condition test device, so that the working condition test device provides the test working condition conditions to the chip under test;

[0042] The main control module controls the switch array module to turn on the test channel connecting the pins to be tested of the chip under test to the measuring device, so as to collect test data during the process of the chip under test running the test program through the test channel.

[0043] In a possible implementation, it further includes:

[0044] In the case of replacing the chip under test, the main control module obtains an updated target configuration file, and based on the pin numbers of the chip under test required for the download task in the updated target configuration file, controls the switch array module to conduct the channel connecting the terminal to the download pins of the chip under test, so that the terminal downloads the updated target program to the replaced chip under test, enables the test module required for executing the test task by the chip under test based on the updated driver program, and makes the chip under test run the test program to perform a test operation; wherein, the updated target program includes the test program and the updated driver program.

[0045] The third aspect of the present application provides a computer program product, including computer-readable instructions, which when running on an electronic device, enable the electronic device to implement the chip testing method of the second aspect or any implementation manner of the second aspect.

[0046] The fourth aspect of the present application provides an electronic device, including at least one processor and a memory connected to the processor, wherein:

[0047] The memory is used to store a computer program;

[0048] The processor is used to execute the computer program, so that the electronic device can implement the chip testing method of the second aspect or any implementation manner of the second aspect.

[0049] The fifth aspect of the present application provides a computer storage medium, which carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, can enable the electronic device to implement the chip testing method of the second aspect or any implementation manner of the second aspect.

[0050] By means of the above technical solution, for the chip testing device and method provided by the present application, the main control module controls the signal path switching module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel. In the case of switching the target task, based on the pin numbers of the chip under test required for the switched target task in the target configuration file, the signal path switching module is controlled to conduct the second channel of the chip under test, so as to process the switched target task through the second channel. The present application can separately test different types of chips, and by determining the pins required by the chip under test during the chip testing process and conducting corresponding channels to perform each operation step during the chip testing process, the chip automated testing efficiency is improved. Description of the Drawings

[0051] In conjunction with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0052] Figure 1 Structural diagram of a chip testing device provided by this application;

[0053] Figure 2 Another structural diagram of a chip testing device provided by this application;

[0054] Figure 3 Another structural diagram of a chip testing device provided by this application;

[0055] Figure 4 Flowchart of a chip testing method provided by this application;

[0056] Figure 5 Schematic diagram of hardware decoupling of a chip under test provided by this application;

[0057] Figure 6 Structural diagram of an electronic device provided by this application. Specific embodiments

[0058] The following describes the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. The terms used in the embodiments part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0059] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0060] The terms "first", "second", etc. in the specification, claims, and above-mentioned drawings of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing when describing objects with the same attributes in the embodiments of the present application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product, or device comprising a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products, or devices.

[0061] The embodiments of the present application provide a chip testing device. The following describes the chip testing device of the embodiments of the present application in detail with reference to the accompanying drawings.

[0062] Reference Figure 1 , Figure 1 is a structural diagram of a chip testing device provided by an embodiment of the present application. As Figure 1 shown, a chip testing device 10 provided by an embodiment of the present application may include:

[0063] A main control module 1 and a signal path switching module 2.

[0064] The main control module 1 is connected to the chip under test 3 through the signal path switching module 2.

[0065] The main control module is used to control the signal path switching module to turn on the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to perform target task processing through the first channel. In the case of target task switching, based on the pin numbers of the chip under test required for the switched target task in the target configuration file, the signal path switching module is controlled to turn on the second channel of the chip under test, so as to perform the switched target task processing through the second channel.

[0066] The main control module may be a main control chip. The input end of the signal path switching module is connected to the main control chip, and the output end of the signal path switching module is connected to the chip under test. The output end of the signal path switching module is connected to multiple pins of the chip under test through multiple wires. The chip under test may be a chip under test MCU (Microcontroller Unit).

[0067] The signal path switching module may include multiple switches. Each switch connects a pin of the chip under test and the main control chip. The main control chip may control one of the multiple switches of the signal path switching module to open and the other switches to close. The pin of the chip under test connected to the opened switch is connected to the main control chip, that is, the channel connecting the main control chip and a certain pin of the chip under test is turned on.

[0068] The target configuration file may include a chip pin configuration file, in which information such as the pin numbers of the signals under test and the pin functions can be recorded. The target configuration file may also include a test task file, which contains the test tasks of the chip under test, the task types of each test task, the pins used for each test task, the operating frequency, the number of test times, etc. The test tasks of the chip under test may include, but are not limited to, reset, internal high- and low-speed oscillator accuracy, TIMER (timer) accuracy, PWM (Pulse Width Modulation), GPIO (General Purpose Input / Output), UART (Universal Asynchronous Receiver / Transmitter), IIC (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), etc. Of course, the target configuration file may also include a debug interface configuration file for the chip under test, in which the chip debug pin numbers and corresponding functions can be recorded. The chip pin configuration file, the test task file, and the debug interface configuration file of the target configuration file can be generated according to the specification of the chip under test. Specifically, they can be quickly written through a terminal such as the EXCEL software of the host computer or similar software, and an xml file is generated and sent to the main control module. The main control module receives the xml file from the host computer, obtains the pin configuration, debug interface configuration, test task configuration, etc. of the chip under test from the xml file, and conducts chip testing by turning on the corresponding channels through the signal path switching module.

[0069] The chip testing process may include a test preparation stage and a functional test stage, and may also include a test result reporting stage. After determining the target task, the main control module can determine the pin numbers of the chip under test required for the target task according to the target configuration file, and control the signal path switching module to conduct the first channel of the chip under test, so as to process the target task through the first channel. The target task may be a power supply task, a clock task, a reset task, a download task, a debugging task, or a test task. The power supply task is a task of enabling the power supply device to provide the voltage required by the chip under test to the chip under test. The clock task is a task of enabling the clock device to provide a clock signal to the chip under test. The reset task is a task of enabling the chip under test to implement the reset function. The download task is a task of enabling the terminal to download the test program to the chip under test. The debugging task is a task of debugging the chip under test. The test task is a task of testing the chip under test. The first channel can connect the corresponding pins of the chip under test to the main control module, or can connect the corresponding pins of the chip under test to the test equipment, and can also connect the corresponding pins of the chip under test to the power supply device, the clock device, peripheral components, etc. Among them, the test equipment may include a working condition testing device, such as one or more of defrost heating, a fan, and a damper. The test equipment may also include a measuring device, such as one or more of an analog-to-digital converter, an ammeter, and a voltage source. The peripheral components may include capacitors and resistors to implement external reset, mode selection, etc.

[0070] In the case of target task switching, the main control module can determine the pin numbers of the chip under test required for the switched target task according to the target configuration file, and control the signal path switching module to conduct the second channel of the chip under test. The second test channel can also connect the corresponding pins of the chip under test to the main control module, or can connect the corresponding pins of the chip under test to the test equipment, and can also connect the corresponding pins of the chip under test to the power supply device, the clock device, peripheral components, etc., so as to process the switched target task through the second channel. Among them, the second channel can be a channel different from the first channel.

[0071] In a possible implementation, as Figure 2 shown, the signal path switching module includes:

[0072] A power control array 21.

[0073] The power control array 21 is respectively connected to the main control module 1, the chip under test 3, and the power supply device 4.

[0074] The main control module is used to control the power control array to conduct the power supply channel of the chip under test based on the pin number of the power supply pin of the chip under test in the target configuration file, so that the power supply device provides the voltage required by the chip under test to the chip under test through the power supply channel.

[0075] The main control module controls the power control array to turn on the power supply channel of the device under test, so that the power supply pins of the device under test are connected to the power supply device. The power supply device can be an adjustable power supply or a programmable precision power supply. According to the specific power supply conditions of different devices under test, the adjustable power supply is configured by the main control module to output the corresponding voltage to supply power to the device under test.

[0076] The power supply pins and ground pins of different devices under test are different. Through the power control array, the main control module can flexibly configure the connection channels between the power supply pins of different devices under test and the power supply, and the main control module can also flexibly configure the connection channels between the ground pins of different devices under test and the ground.

[0077] Optionally, the power control array may include one or more third switch arrays. The third switch array includes multiple switches. The input end of the third switch array is connected to the main control module, the power supply end of the third switch array is connected to the power supply device, and the output end of the third switch array is connected to the power supply pins of the device under test. The third switch array can be an analog switch array, a relay switch array, a triode array, etc.

[0078] Optionally, the power control array may further include a control unit. The input end of the control unit is connected to the main control module, and the output end of the control unit is connected to the third switch array. The control unit can be an MCU. The main control module can control the third switch array by controlling the control unit to enable the power supply channel required by the device under test. If the third switch array is an analog switch array, and the analog switch array can be a MOS transistor (field effect transistor) switch array, the main control module can control the corresponding MOS transistors to enable the power supply channel required by the device under test through the bus to control the control unit. The control unit can also be one or more. If there are multiple control units, each control unit can be connected to the third switch array in a one-to-one correspondence, and the number of control units can be the same as the number of third switch arrays. In practical applications, if the pins of the device under test are 144, four third switch arrays can be set, and correspondingly four control units can also be set. Each third switch array is connected to the control unit in a one-to-one correspondence. Of course, if the number of pins of the device under test is other, the number of third switch arrays and control units can be set according to actual needs.

[0079] In a possible implementation, as Figure 2 shown, the signal path switching module further includes:

[0080] Switch array module 22.

[0081] The switch array module 22 is respectively connected to the main control module 1, the device under test 3, and the test equipment 6.

[0082] The main control module is used to control the switch array module to turn on the channel connecting the terminal and the download pin of the chip under test based on the download pin number of the chip under test in the target configuration file, so that the terminal can download the test program to the chip under test.

[0083] The main control module is also used to control the switch array module to turn on the channel connecting the main control module and the pins to be tested of the chip under test required by the test task in the target configuration file, and / or control the switch array module to turn on the channel connecting the pins to be tested of the chip under test and the test equipment, so that the chip under test running the test program can execute the test task.

[0084] The switch array module can include one switch array or multiple switch arrays. One switch array can include multiple switches. One switch connects one pin of the chip under test and the main control module, or one switch connects one test equipment and the main control module. The switch array module can connect the chip under test to test equipment with different functions, clock devices, and peripheral components. The main control module controls the switch array module according to the chip pin configuration file and the test task file, and can realize the "plug and play" of different chips under test with different packages, cores, and manufacturers.

[0085] Before testing the chip under test, the test program can be downloaded to the chip under test. At this time, the main control module can control the switch array module to turn on the switch connecting to the download pin of the chip under test, so as to turn on the channel connecting the terminal and the download pin of the chip under test, and thus the terminal can download the test program to the chip under test. Optionally, the terminal can be an upper computer, and the upper computer can be an industrial control computer or a computer, and can run operating systems such as Windows 7 and above.

[0086] Of course, before testing the chip under test, the main control module can also control the switch array module to turn on the switch connecting to the debug pin of the chip under test, so as to turn on the debug channel of the chip under test for debugging operations on the chip under test. In practical applications, the debug pin of the chip under test can be connected to the download debugger through the switch array module.

[0087] According to the specific test tasks, the main control module can select and connect the pins of the chip under test and the test ports of the functional test equipment through the switch array module. Specifically, the main control module can control the switch array module to conduct the channel connecting the main control module and the pins to be tested of the chip under test. The main control module can send corresponding test instructions to the chip under test, such as SPI, UART, IIC tests, etc. After receiving the test instructions, the chip under test runs the test program to execute the test tasks. Since the functional pins of different chips under test are different, the connection between the pins to be tested of the chip under test and the corresponding functional interfaces of the main control module can be flexibly configured through the switch array module. In addition, the main control module can also control the switch array module to conduct the channel connecting the pins to be tested of the chip under test and the test equipment. The test equipment includes a measuring device and a working condition test device. The measuring device, such as a high-precision analog-to-digital converter or digital-to-analog converter, a bidirectional high-precision ammeter, a high-precision reference voltage source, etc., can provide test conditions for the pins to be tested of the chip under test. The working condition test equipment, such as defrost heating, a fan, a damper, etc., can provide working condition test conditions for the chip under test, so that the chip under test running the test program can execute the test tasks. The test equipment can be flexibly added according to specific test requirements.

[0088] In a possible implementation, as Figure 3 shown, the switch array module includes:

[0089] The first switch array 221 and the second switch array 222.

[0090] The first switch array 221 is respectively connected to the main control module 1, the chip under test 3, and the second switch array 222.

[0091] The second switch array 222 is connected to the main control module 1 and the test equipment 6.

[0092] The first switch array 221 and the second switch array 222 are connected through a bus.

[0093] The first switch array and the second switch array can be an analog switch array, a relay switch array, a triode array, etc.

[0094] The main control module is used to control the first switch array to conduct the channel connecting the pins to be tested of the chip under test and the second switch array based on the pin numbers to be tested of the chip under test, and control the second switch array to conduct the channels connecting the main control module with the test equipment and the chip under test, so that the main control module can receive the test data transmitted by the chip under test and / or the test equipment.

[0095] The main control module is used to control the first switch array to conduct the channel connecting the pins to be tested of the chip under test with the second switch array, and control the second switch array to conduct the channels connecting the main control module with the test equipment and the channels connecting the main control module with the chip under test, so that the main control module can receive the test data transmitted by the chip under test and / or the test equipment. The test equipment includes a measuring device.

[0096] The test results can be obtained through two channels. One channel is directly obtained through the chip under test, that is, the chip under test obtains through the channels connecting the first switch array, the second switch array with the main control module. For example, in UART testing, the test results of the chip under test are directly transmitted back to the main control module. The other channel is obtained through the measuring device, that is, the measuring device obtains through the channels connecting the second switch array with the main control module. For example, to obtain VOH (Output High Voltage, the minimum voltage value when the output pin is at logic 1 (high level)), VOL (Output Low Voltage, the maximum voltage value when the output pin is at logic 0 (low level)), IOH (Input Output High, the current at high input / output level), IOL (Input Output Low, the current at low input / output level), analog signals, digital signals, etc. of the ports of the chip under test.

[0097] In a possible implementation, as Figure 3 shown, the second switch array is connected to the clock device 7, and / or the second switch array is connected to the peripheral component 8.

[0098] The main control module is used to control the second switch array to conduct the clock channel of the chip under test based on the clock pin number of the chip under test in the target configuration file, so that the clock device can provide the required clock signal for the chip under test through the clock channel.

[0099] The main control module is used to control the second switch array to conduct the connection channels between the chip under test and the peripheral components based on the function pin numbers of the chip under test in the target configuration file, so as to perform the reset operation and / or mode selection operation of the chip under test.

[0100] Some chips under test need an external clock to work. The second switch array is connected to the clock device. The main control module determines the clock pin number of the chip under test based on the target configuration file, and conducts the connection channels between the chip under test and the clock device, that is, the clock channel, through the second switch array, so that the clock device can provide the clock signal for the chip under test through the clock channel.

[0101] The tests for some chips under test include reset, mode selection, etc. The second switch array is connected to the peripheral components, which mainly include capacitors and resistors. The main control module determines the functional pin numbers of the chips under test, such as the reset pin and the mode selection pin, based on the target configuration file, and controls the second switch array to conduct the connection channels between the chips under test and the peripheral components to perform the reset operation and / or mode selection operation on the chips under test.

[0102] Referring to Figure 4 , Figure 4 is a schematic flowchart of a chip testing method provided by an embodiment of the present application. As Figure 1 shown, a chip testing method provided by an embodiment of the present application is applied to a chip testing device as Figures 1 to 3 shown. The chip testing method may include step 401 to step 403, and the following will describe these steps in detail.

[0103] Step 401: The main control module obtains the target configuration file.

[0104] Step 402: The main control module controls the signal path switching module connected to the main control module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel.

[0105] Step 403: In the case of target task switching, the main control module controls the signal path switching module to conduct the second channel of the chip under test based on the pin numbers of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel.

[0106] In a possible implementation, the main control module controls the signal path switching module connected to the main control module to conduct the first channel of the chip under test based on the pin numbers of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel, including:

[0107] The main control module controls the power control array of the signal path switching module to conduct the power supply channel of the chip under test based on the power supply pin numbers of the chip under test required for the power supply task in the target configuration file, so that the power supply device provides the required voltage for the chip under test through the power supply channel.

[0108] The main control module controls the signal path switching module to conduct the second channel of the chip under test based on the pin numbers of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel, including:

[0109] Based on the clock pin numbers of the device under test (DUT) required for the clock task in the target configuration file, the main control module controls the switch array module of the signal path switching module to turn on the clock channel of the DUT, so that the clock device provides the clock signal required by the DUT to the DUT through the clock channel.

[0110] If the DUT needs an external clock to work, before chip testing, after the DUT is powered on, the terminal such as the host computer generates a target configuration file according to the specification of the DUT. The target configuration file includes a chip pin configuration file, which can be an EXCEL table, including the pin numbers of the DUT, all functions corresponding to the pin numbers, such as GPIO, serial port, SPI, power supply, clock, etc. The host computer converts the EXCEL target configuration file into XML format and downloads it to the main control module. The main control module obtains information such as the power supply pins, ground pins, and clock pins of the DUT in the pin configuration file. The main control module programs the power supply device such as an adjustable precision power supply to output a voltage value that meets the power supply requirements of the DUT. The main control module controls the power control array to enable the chip power supply channel, and the main control module controls the switch array module to enable the clock channel, so that the chip reaches the operating conditions.

[0111] In a possible implementation, based on the pin numbers of the DUT required for the target task in the target configuration file, the main control module controls the signal path switching module connected to the main control module to turn on the first channel of the DUT to process the target task through the first channel, including:

[0112] Based on the download pin numbers of the DUT required for the download task in the target configuration file, the main control module controls the switch array module of the signal path switching module to turn on the channel connecting the terminal to the download pins of the DUT, so that the terminal downloads the target program to the DUT; among them, the target program includes a test program.

[0113] The target configuration file also includes a debug interface configuration file. The debug interface configuration file includes the debugger pin numbers and their corresponding debugger pin functions (such as SWD_Data, SWD_CLK, etc.). Based on the debug interface configuration file, the main control module controls the switch array module to enable the channel between the download debugger and the debug interface of the DUT to prepare for downloading the embedded test program of the DUT. The main control module turns on the channel connecting the terminal to the download pins of the DUT, and the terminal such as the host computer uses the embedded test program after hardware abstraction decoupling to download it to the DUT through the download debugger.

[0114] In addition to the test program, the target program also includes a driver program. The test program and the driver program are downloaded to the DUT through the channel connecting the terminal to the download pins of the DUT.

[0115] Based on the pin numbers of the device under test (DUT) chips required for the switched target task in the target configuration file, the main control module controls the signal path switching module to turn on the second channel of the DUT chips, so as to process the switched target task through the second channel, including:

[0116] Based on the pin numbers of the DUT chips to be tested required for the test task in the target configuration file, the main control module controls the switch array module to turn on the channel connecting the main control module and the pins to be tested of the DUT chips, and / or controls the switch array module to turn on the channel connecting the pins to be tested of the DUT chips and the test equipment, so that the DUT chips run the test program to perform test operations.

[0117] The target configuration file further includes a test task file, which includes test types, such as different tasks like reset, internal high and low speed oscillator accuracy, TIMER accuracy, PWM, GPIO, UART, IIC, SPI, etc., and also includes task parameters, such as task type, used pins, operating frequency, number of tests, etc.

[0118] The test equipment includes a measuring device and / or a working condition test device.

[0119] In a possible implementation, based on the pin numbers of the DUT chips to be tested required for the test task in the target configuration file, the main control module controls the switch array module to turn on the channel connecting the pins to be tested of the DUT chips and the test equipment, so that the DUT chips run the test program to perform test operations, including:

[0120] The main control module determines the pin numbers of the DUT chips to be tested required for the test task and the test working condition conditions required for the DUT chips to execute the test task from the target configuration file;

[0121] The main control module controls the switch array module to turn on the channel connecting the pins to be tested of the DUT chips and the working condition test device, so that the working condition test device provides the test working condition conditions for the DUT chips;

[0122] The main control module controls the switch array module to turn on the test channel connecting the pins to be tested of the DUT chips and the measuring device, so as to collect test data during the process of the DUT chips running the test program through the test channel.

[0123] The main control module parses the test task file, completes each test task one by one. For each test type, the main control module enables the corresponding test channel through the switch array module and the bus. If it is a communication interface test such as UART or SPI, the main control module can directly control the switch array module to enable the channel between the chip under test and the main control module, that is, control the switch array module to conduct the channel connecting the pins to be tested of the main control module and the chip under test; if it is a port voltage or ADC function test, the main control module can enable the channel between the pins of the chip under test and the port of the measuring device through the switch array module; if it is a function test under working conditions, such as a fan or a damper, the main control module controls the switch array module to enable the channel between the chip under test and the corresponding working condition test device.

[0124] When performing chip testing, after the main control module configures the corresponding channels according to the specific requirements of each test, it issues the corresponding test instructions to the chip under test, such as serial port testing, SPI testing, etc. After receiving the specific test instructions, the chip under test makes test configurations for itself according to the test instruction type and pin-related parameters, and synchronizes with the main control module to start the specific test through the handshake protocol.

[0125] When testing each task, the test results are mainly obtained through two channels. For one channel, the main control module directly obtains the results from the chip under test. For example, in UART testing, the obtained results are directly returned to the main control module; for the other channel, the main control module obtains the VOH, VOL, IOH, IOL of the ports of the chip under test through the measuring device, or the main control module obtains the analog-to-digital signal through the analog-to-digital converter.

[0126] The main control module collects and analyzes the results from the chip under test or the measuring device, and reports the test results to the upper computer. The upper computer can display the detection results, such as waveform display, and can also display the test results in the form of a test report for users' reference.

[0127] In a possible implementation, the chip testing method provided by this application further includes:

[0128] In the case of replacing the chip under test, the main control module obtains the updated target configuration file. Based on the pin numbers of the chip under test required for the download task in the updated target configuration file, the main control module controls the switch array module to conduct the channel connecting the terminal to the download pins of the chip under test, so that the terminal downloads the updated target program to the replaced chip under test, enables the test modules required for the test task based on the updated driver program of the chip under test, and enables the chip under test to run the test program for test operations; where the updated target program includes the test program and the updated driver program.

[0129] When testing by replacing different test chips, since the pins of different test chips are different, the chip pin files generated by the terminal are also different. The main control module receives the updated target configuration file sent by the terminal, specifically, it can be the updated chip pin file. Based on the updated chip pin file, the download pins of the chip under test connect the channels between the terminal and the download pins of the chip under test, so that the terminal downloads the test program and the updated driver program to the replaced chip under test. Among them, the test program can be the same as before, and the driver program can be different. The terminal modifies the register-level driver program of the chip under test according to the chip specification of the chip under test without rewriting the test program.

[0130] To achieve the rapid automated testing of the chip under test, the HAL (Hardware Abstraction Layer) method is used to decouple the test tasks from the specific hardware drivers. As Figure 5 shown, the function scheduling layer schedules the specific test function modules in the chip under test according to the specific test instructions of the main control module, such as the reset function test module, PWM test module, GPIO test module, UART test module, on-chip Flash (flash memory) test module, etc. The implementation of specific test tasks is modularly implemented in the classification function modules. The HAL hardware abstraction layer provides virtual interfaces to decouple the test functions from the hardware drivers. In this way, for each chip under test, as long as the register configuration information of the MCU hardware driver part is modified and the driver program is recompiled and downloaded, there is no need to rewrite the main body of the embedded test software, such as scheduling, function modules, etc. In this way, the embedded program deployment of the chip under test can be quickly realized, greatly improving the efficiency of the function and performance testing of the chip under test.

[0131] The chip testing method provided by this application can realize the configurable connection path between the chip under test, the measuring device, and the working condition testing device, and can achieve the "plug and play" and "one-key testing" of the chip under test across kernels, packages, and manufacturers, improving the chip testing efficiency. There is no need for traditional steps such as principle design, PCB design, prototyping, and board-level debugging, greatly reducing the human and material costs of product R & D and shortening the R & D cycle.

[0132] An electronic device is also provided in an embodiment of this application. Referring to Figure 6 shown, it shows a schematic structural diagram suitable for implementing the electronic device in the embodiment of this application. The electronic device in the embodiment of this application may include but is not limited to fixed terminals such as mobile phones, laptop computers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), desktop computers, and the like. Figure 6 The electronic device shown is only an example and should not bring any limitations to the functions and usage ranges of the embodiments of this application.

[0133] As Figure 6As shown, the electronic device may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 601, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage device 608 into the random access memory (RAM) 603. When the electronic device is powered on, various programs and data required for the operation of the electronic device are also stored in the RAM 603. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

[0134] Generally, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 608 including, for example, a memory card, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 6 an electronic device with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had.

[0135] In an embodiment of the present application, there is also provided a computer program product including computer-readable instructions. When the computer-readable instructions run on an electronic device, the electronic device is enabled to implement any one of the chip testing methods provided in the embodiments of the present application.

[0136] In an embodiment of the present application, there is also provided a computer-readable storage medium. The storage medium carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can be enabled to implement any one of the chip testing methods provided in the embodiments of the present application.

[0137] In addition, it should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided in the present application, the connection relationship between the modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines.

[0138] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be diverse, such as analog circuits, digital circuits or dedicated circuits, etc. However, for the present application, in more cases, software program implementation is a better implementation manner. Based on such an understanding, the technical solution of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disc of a computer, etc., and includes several instructions for causing a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods of various embodiments of the present application.

[0139] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0140] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A chip testing device, characterized in that: include: Main control module and signal path switching module; The main control module is connected to the chip under test through the signal path switching module; The main control module is used to control the signal path switching module to turn on the first channel of the chip under test based on the pin number of the chip under test required for the target task in the target configuration file, so as to process the target task through the first channel; in the case of switching of the target task, based on the pin number of the chip under test required for the switched target task in the target configuration file, the signal path switching module is controlled to turn on the second channel of the chip under test, so as to process the switched target task through the second channel.

2. The chip testing device according to claim 1, characterized in that: The signal path switching module comprises: Power control array; The power control array is connected to the main control module, the chip under test and the power supply device respectively; The main control module is used to control the power control array to turn on the power supply channel of the chip under test based on the power supply pin number of the chip under test in the target configuration file, so that the power supply device provides the voltage required by the chip under test to the chip under test through the power supply channel.

3. The chip testing device according to claim 1, characterized in that: The signal path switching module further includes: Switch array module; The switch array module is respectively connected to the main control module, the chip under test and the test equipment; The main control module is used to control the switch array module to conduct the channel connecting the terminal with the download pin of the chip under test based on the download pin number of the chip under test in the target configuration file, so that the terminal downloads the test program to the chip under test; The main control module is also used to control the switch array module to turn on the channel connecting the main control module with the pin to be tested of the chip under test based on the pin number to be tested of the chip under test required by the test task in the target configuration file, and / or to control the switch array module to turn on the channel connecting the pin to be tested of the chip under test and the test equipment, so that the chip under test running the test program performs the test task.

4. The chip testing device according to claim 3, characterized in that: The switch array module comprises: a first switch array and a second switch array; The first switch array is connected to the main control module, the chip under test and the second switch array respectively; The second switch array is connected to the main control module and the test equipment; The main control module is used to control the first switch array to turn on the channel connecting the pin to be tested of the chip under test and the second switch array based on the pin number to be tested of the chip under test, and control the second switch array to turn on the channel connecting the main control module with the test equipment and the chip under test, so that the main control module receives the test data transmitted by the chip under test and / or the test equipment.

5. The chip testing device according to claim 4, characterized in that: The second switch array is connected to a clock device, and / or the second switch array is connected to a peripheral element; The main control module is used to control the second switch array to turn on the clock channel of the chip under test based on the clock pin number of the chip under test in the target configuration file, so that the clock device provides the chip under test with the clock signal required by the chip under test through the clock channel; The main control module is used to control the second switch array to turn on the connection channel between the chip under test and the peripheral component based on the functional pin number of the chip under test in the target configuration file, so as to perform a reset operation and / or a mode selection operation on the chip under test.

6. A chip testing method, characterized in that: Applied to the chip testing device according to any one of claims 1 to 5, the method comprises: The main control module obtains the target configuration file; The main control module controls the signal path switching module connected to the main control module to turn on the first channel of the chip under test based on the pin number of the chip under test required by the target task in the target configuration file, so as to process the target task through the first channel; In the case of switching the target task, the main control module controls the signal path switching module to turn on the second channel of the chip under test based on the pin number of the chip under test required for the switched target task in the target configuration file, so as to process the switched target task through the second channel.

7. The chip testing method according to claim 6, characterized in that: The main control module controls the signal path switching module connected to the main control module to turn on the first channel of the chip under test based on the pin number of the chip under test required by the target task in the target configuration file, so as to perform the target task processing through the first channel, including: The main control module controls the power control array of the signal path switching module to turn on the power supply channel of the chip under test based on the power supply pin number of the chip under test required for the power supply task in the target configuration file, so that the power supply device provides the voltage required by the chip under test to the chip under test through the power supply channel; The main control module controls the signal path switching module to turn on the second channel of the chip under test based on the pin number of the chip under test required by the switched target task in the target configuration file, so as to process the switched target task through the second channel, including: The main control module controls the switch array module of the signal path switching module to turn on the clock channel of the chip under test based on the clock pin number of the chip under test required for the clock task in the target configuration file, so that the clock device provides the clock signal required by the chip under test to the chip under test through the clock channel.

8. The chip testing method according to claim 6, characterized in that: The main control module controls the signal path switching module connected to the main control module to turn on the first channel of the chip under test based on the pin number of the chip under test required by the target task in the target configuration file, so as to perform the target task processing through the first channel, including: The main control module controls the switch array module of the signal path switching module to conduct the channel connecting the terminal with the download pin of the chip under test based on the download pin number of the chip under test required for the download task in the target configuration file, so that the terminal downloads the target program to the chip under test; wherein the target program includes a test program; The main control module controls the signal path switching module to turn on the second channel of the chip under test based on the pin number of the chip under test required by the switched target task in the target configuration file, so as to process the switched target task through the second channel, including: The main control module controls the switch array module to conduct the channel connecting the main control module with the pin to be tested of the chip under test based on the pin number to be tested of the chip under test required by the test task in the target configuration file, and / or controls the switch array module to conduct the channel connecting the pin to be tested of the chip under test with the test equipment, so that the chip under test runs the test program to perform the test operation.

9. The chip testing method according to claim 8, characterized in that: The test equipment includes a working condition test device and a measuring device; The main control module controls the switch array module to conduct a channel connecting the pin to be tested of the chip under test and the test equipment based on the pin number to be tested of the chip under test required by the test task in the target configuration file, so that the chip under test runs the test program to perform a test operation, including: The main control module determines the pin number of the chip under test required for the test task and the test working condition required for the chip under test to execute the test task from the target configuration file; The main control module controls the switch array module to conduct the channel connecting the pin to be tested of the chip under test and the working condition test device, so that the working condition test device provides the test working condition to the chip under test; The main control module controls the switch array module to conduct the test channel connecting the pin to be tested of the chip under test with the measuring device, so as to collect test data of the chip under test during the process of running the test program through the test channel.

10. The chip testing method according to claim 8, characterized in that: Also includes: In the case of replacing the chip under test, the main control module obtains an updated target configuration file, and based on the download pin number of the chip under test required for the download task in the updated target configuration file, controls the switch array module to turn on the channel connecting the terminal with the download pin of the chip under test, so that the terminal downloads the updated target program to the replaced chip under test, enables the chip under test to enable the test module required for executing the test task based on the updated driver, and enables the chip under test to run the test program to perform the test operation; wherein, the updated target program includes the test program and the updated driver.

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