Chip Performance Testing Method and System Based on Automated Equipment

Abstract

This invention provides a chip performance testing method and system based on automated equipment. The method includes: connecting the chip under test (DUT) to a test channel via a probe card; sampling multiple voltage sensor nodes in the power distribution layer of the probe card to obtain power rail voltage distribution data; calculating predicted power rail voltage drop data based on the power rail voltage distribution data and test vector sequence using a preset neural network model; performing compensation control on a multi-level parallel capacitor array on the test board based on the predicted data, and performing chip testing under this control to obtain test results and compensation control data; and correcting the test results using the compensation control data and voltage distribution data to obtain corrected chip performance parameters. This invention achieves accurate monitoring, prediction, active compensation, and correction of power rail transient voltage drop, significantly improving the accuracy and consistency of chip performance testing.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip performance testing method and system based on automated equipment. Background Technology

[0002] In the field of integrated circuit testing, chip performance testing is a crucial step in ensuring chip functionality and performance. Existing chip performance testing methods based on automated equipment typically employ fixed test vector sequences to verify chip functionality and performance. However, during the testing of high-performance integrated circuits, especially transient response testing, high-speed switching testing, or analog mixed-signal circuit testing, the chip's power consumption exhibits drastic fluctuations. These power consumption fluctuations cause transient voltage drops on the power rails of the test equipment, affecting the stability of the test voltage. This is particularly true when the chip experiences sudden high current demands, resulting in significant transient voltage drops on the power rails and causing voltage fluctuations. Because existing test systems typically only perform single-point voltage monitoring at the power supply end, they cannot capture voltage changes at different locations in the power distribution network. Furthermore, the use of a single large-capacity decoupling capacitor for power stabilization is insufficient to handle distributed, high-frequency voltage fluctuations. Therefore, the accuracy and reliability of test results are severely affected, especially for timing-sensitive circuits and chips operating in low-voltage regions. Summary of the Invention

[0003] The main objective of this invention is to solve the technical problem of deviation in test results caused by transient voltage drop of the power rail during existing chip performance testing.

[0004] The first aspect of this invention provides a chip performance testing method based on automated equipment, wherein the automated equipment includes a test board, a probe card, and test channels, and the chip performance testing method based on the automated equipment includes:

[0005] The chip under test is placed on the test board and connected to the test channel through the probe card. Multiple voltage sensor nodes set in the power distribution layer of the probe card are sampled and controlled to obtain power rail voltage distribution data.

[0006] The test vector sequence of the chip under test is obtained, and the power rail voltage drop prediction data is calculated based on the power rail voltage distribution data and the test vector sequence using a preset neural network model.

[0007] Based on the power rail voltage drop prediction data, the multi-level parallel capacitor array on the test board is compensated and controlled, and the chip test corresponding to the test vector sequence is executed under the compensation control to obtain the chip test results and power rail compensation control data.

[0008] Based on the power rail compensation control data and the power rail voltage distribution data, the chip test results are corrected to obtain the corrected chip performance parameters.

[0009] Optionally, in a first implementation of the first aspect of the present invention, the step of placing the chip under test on the test board, connecting it to the test channel via the probe card, and sampling and controlling multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data includes:

[0010] The chip under test is placed on the test board and connected to the test channel through the probe card. Current density analysis is performed on the power distribution layer of the probe card to determine the key monitoring location of voltage fluctuation.

[0011] The power distribution layer of the probe card is divided into multiple sampling areas according to the key monitoring locations, and a voltage sensor node is set in each sampling area.

[0012] The voltage sensor nodes in each sampling area are initialized and sampled to obtain the main frequency component and harmonic component of the voltage fluctuation. The bandwidth range of power consumption change is calculated by Fourier transform based on the main frequency component and harmonic component.

[0013] According to the bandwidth range, the voltage sensor nodes of each sampling area are configured with sampling timing control parameters, and the sampling data is transmitted to the sensor control unit through a low-latency data bus to obtain the power rail voltage distribution data.

[0014] Optionally, in a second implementation of the first aspect of the present invention, the step of obtaining the test vector sequence of the chip under test and calculating the predicted power rail voltage drop data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model includes:

[0015] Obtain the test vector sequence of the chip under test, and call the corresponding pre-trained neural network model according to the identification code of the chip under test;

[0016] The test vector sequence is segmented according to the execution time sequence, the signal flip data of each segment of the test vector is calculated, and a test vector feature matrix is ​​constructed.

[0017] The power rail voltage distribution data is decomposed in the time domain to extract the amplitude, frequency, and phase characteristics of voltage fluctuations, and a voltage feature matrix is ​​generated.

[0018] The test vector feature matrix and voltage feature matrix are input into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features;

[0019] The decoder of the pre-trained neural network model predicts voltage changes based on the time-series correlation features to obtain the power rail voltage drop prediction data.

[0020] Optionally, in a third implementation of the first aspect of the present invention, the step of inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features includes:

[0021] The test vector feature matrix is ​​bidirectionally segmented. The forward temporal features of the test vector feature matrix are input into the forward channel of the bidirectional encoder, and the reverse temporal features of the test vector feature matrix are input into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the test vector.

[0022] The voltage feature matrix is ​​bidirectionally segmented, and the forward timing features of the voltage feature matrix are input into the forward channel of the bidirectional encoder, while the reverse timing features of the voltage feature matrix are input into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the voltage features.

[0023] Bidirectional cross-attention weights are calculated based on the bidirectional hidden features of the test vector and the bidirectional hidden features of the voltage features, and a weight matrix of positive and negative features is generated.

[0024] The time-series correlation features are obtained by weighting and combining the bidirectional hidden features of the test vector and the bidirectional hidden features of the voltage feature according to the weight matrix.

[0025] Optionally, in a fourth implementation of the first aspect of the present invention, the step of performing compensation control on the multi-level parallel capacitor array on the test board based on the power rail voltage drop prediction data, and performing chip testing corresponding to the test vector sequence under the compensation control to obtain chip test results and power rail compensation control data includes:

[0026] The response speed of the predicted power rail voltage drop is analyzed to calculate the voltage drop compensation requirements at different time scales.

[0027] Based on the voltage drop compensation requirements at different time scales, the magnitude of the compensation current and the injection timing of each capacitor unit in the multi-level parallel capacitor array are calculated.

[0028] The charging and discharging control of the capacitor units in the multi-level parallel capacitor array is performed by a multi-channel PWM controller to obtain power rail compensation control data, and the test vector sequence is executed under the charging and discharging control to obtain the chip test results.

[0029] Optionally, in a fifth implementation of the first aspect of the present invention, calculating the compensation current magnitude and injection timing of each capacitor unit in the multi-stage parallel capacitor array according to the voltage drop compensation requirements at different time scales includes:

[0030] Wavelet transform decomposition is performed on the voltage drop compensation requirements according to the different time scales to decompose the compensation signal into different frequency sub-bands, and the energy distribution characteristics and phase characteristics of each frequency sub-band are calculated.

[0031] Based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-level parallel capacitor array, a dynamic impedance model is constructed, and the compensation capability of each capacitor unit at different frequencies is calculated through state equations.

[0032] The compensation tasks for each frequency sub-band are optimized and allocated based on the genetic algorithm. An objective function for the compensation efficiency and timing of the capacitor unit is established, and a candidate set of compensation strategies is generated.

[0033] The candidate set of compensation strategies is iteratively optimized using the particle swarm optimization algorithm to calculate the magnitude of the compensation current and the injection timing of each capacitor unit.

[0034] Optionally, in a sixth implementation of the first aspect of the present invention, the step of correcting the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain corrected chip performance parameters includes:

[0035] The power rail compensation control data and power rail voltage distribution data are aligned according to the time series to obtain the actual working voltage data.

[0036] Based on the difference between the nominal operating voltage and the actual operating voltage of the chip under test, calculate the operating voltage deviation curve of each functional module of the chip under test.

[0037] The performance parameters in the chip test results are correlated with the operating voltage deviation curve according to the test sequence to obtain parameter-voltage relationship data;

[0038] The chip test results are nonlinearly corrected based on the parameter-voltage relationship data to obtain the corrected chip performance parameters.

[0039] A second aspect of the present invention provides a chip performance testing system based on automated equipment, the automated equipment including a test board, probe cards, and test channels, the chip performance testing system based on automated equipment comprising:

[0040] The voltage acquisition module is used to place the chip under test on the test board, connect it to the test channel through the probe card, and sample and control multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data.

[0041] The voltage drop prediction module is used to acquire the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model.

[0042] The dynamic compensation module is used to compensate and control the multi-level parallel capacitor array on the test board according to the power rail voltage drop prediction data, and to perform chip testing corresponding to the test vector sequence under the compensation control to obtain chip test results and power rail compensation control data.

[0043] The result correction module is used to correct the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

[0044] The aforementioned chip performance testing method and system based on automated equipment connects the chip under test (DUT) to a test channel via a probe card. Multiple voltage sensor nodes in the power distribution layer of the probe card are sampled to obtain power rail voltage distribution data. A preset neural network model calculates predicted power rail voltage drop data based on the power rail voltage distribution data and test vector sequences. Compensation control is applied to a multi-level parallel capacitor array on the test board based on the predicted data, and chip testing is performed under this control to obtain test results and compensation control data. The test results are then corrected using the compensation control data and voltage distribution data to obtain the corrected chip performance parameters. This invention achieves accurate monitoring, prediction, active compensation, and correction of power rail transient voltage drop, significantly improving the accuracy and consistency of chip performance testing.

[0045] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the first embodiment of the chip performance testing method based on automated equipment in this invention.

[0048] Figure 2This is a schematic diagram of an embodiment of a chip performance testing system based on automated equipment according to the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0051] To facilitate understanding of this embodiment, a chip performance testing method based on automated equipment disclosed in this embodiment of the invention will first be described in detail. The automated equipment includes a test board, probe cards, and test channels. For example... Figure 1 As shown, this method includes the following steps:

[0052] 101. Place the chip under test on the test board, connect it to the test channel through the probe card, and sample and control the multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain the power rail voltage distribution data.

[0053] In one embodiment of the present invention, the step of placing the chip under test on the test board, connecting it to the test channel via the probe card, and sampling and controlling multiple voltage sensor nodes in the power distribution layer of the probe card to obtain power rail voltage distribution data includes: placing the chip under test on the test board, connecting it to the test channel via the probe card, performing current density analysis on the power distribution layer of the probe card to determine key monitoring locations for voltage fluctuations; dividing the power distribution layer of the probe card into multiple sampling areas according to the key monitoring locations, and setting voltage sensor nodes in each sampling area; initializing sampling of the voltage sensor nodes in each sampling area to obtain the main frequency component and harmonic components of the voltage fluctuations, and calculating the bandwidth range of power consumption changes based on the main frequency component and harmonic components using Fourier transform; configuring sampling timing control parameters for the voltage sensor nodes in each sampling area according to the bandwidth range, and transmitting the sampled data to the sensor control unit via a low-latency data bus to obtain the power rail voltage distribution data.

[0054] Specifically, in this embodiment, the chip under test (DUT) is first placed on a test board and connected to the test channels via a probe card, thereby establishing an electrical connection from the test equipment to the functional units of the chip. During operation, a vacuum suction head is used to precisely position the DUT in the chip fixing area of ​​the test board. Positioning pins and an optical alignment system ensure precise alignment between the chip pins and the test board contacts, with alignment errors controlled within ±5μm. Then, an automatic pressure-lowering system is activated, applying uniform pressure (typically 0.5-0.8 kg / cm²) to establish stable contact between the miniature elastic probes on the probe card and the test pads on the chip surface. The system then performs a contact impedance test, measuring the contact impedance of each probe using a four-wire measurement method to ensure that the resistance value of all contact points is less than 100mΩ and the dispersion does not exceed ±10%. Next, current density analysis is performed on the power distribution layer of the probe card, and a precise electrical model of the probe card is constructed using dedicated power integrity analysis tools (such as Cadence Sigrity or Ansys PowerSI). The analysis tool combines the chip's SPICE model with the probe card's power network model to perform transient power analysis on key state transition points in the test vector. The system calculates current density heatmaps for each node in the power network under different test states, identifying areas with current densities exceeding 50 A / cm² or voltage fluctuations exceeding 5% of the nominal value as key monitoring locations.

[0055] Specifically, based on the identified key monitoring locations, the system implements a zoned monitoring strategy. First, the K-means clustering algorithm is used to spatially cluster these key locations, grouping points with similar electrical characteristics and close physical locations together to initially form monitoring areas. Then, the Voronoi diagram algorithm is applied to optimize the area boundaries, ensuring that the monitoring areas consider both spatial distribution and electrical connectivity. Typically, the entire probe card is divided into 10-12 areas, each with an area between 5mm² and 15mm². After determining the areas, the system uses precise positioning technology to install voltage sensor nodes in each area. These sensor nodes are designed using a dedicated ASIC, measuring 120μm × 85μm, and integrate a 12-bit ADC, a precision reference source, and digital interface circuitry. During installation, micro-soldering equipment is used to directly solder the sensor nodes to specific locations on the probe card's power layer, with solder joint spacing controlled at 75μm to ensure reliable electrical connections while minimizing interference with the existing power network. The system configures the registers for each sensor node, setting sampling accuracy, trigger thresholds, and operating modes to ensure that the sensor nodes can effectively capture voltage fluctuation information in the target area.

[0056] Specifically, after sensor deployment is complete, the system performs sensor node calibration and initial sampling. During calibration, a high-precision power supply (stability ±0.01%) provides 2-3 standard voltage points (e.g., 0.9V, 1.0V, 1.1V), records the output value of each sensor, and calculates the sensor's gain and bias correction coefficients. Before initial sampling begins, the system places the chip in typical operating conditions and runs a specially designed power transient test vector (including workloads such as high-speed switching, block memory access, and multi-core parallel computing). All sensors start synchronously, with the sampling frequency set to 12.8 GS / s. Each sensor continuously acquires voltage data for 250 μs, achieving a sampling depth of 3,200,000 points. After processing the sampled data through a pre-filter (bandwidth limit of 4 GHz), the system segments the time-domain data of each sensor into data blocks of 8,192 points each, performing a 512-point overlapping FFT operation on each data block at a resolution of 1.56 MHz. The system implements a specific spectrum analysis algorithm: First, the frequency point with the most concentrated energy is identified by amplitude sorting as the dominant frequency component, and its power percentage in the total power is calculated; then, the frequency axis is scanned point by point, and when the energy of a certain frequency point exceeds 10% of the energy of the dominant frequency component, it is marked as a harmonic component, and its frequency and phase information are recorded; a refined analysis is performed on each harmonic component, calculating its multiple relationship with the dominant frequency and its phase difference, and distinguishing between true harmonics generated by nonlinear loads and pseudo-harmonics caused by system noise; finally, all harmonics are sorted according to their energy contribution, and the top 5 harmonics are retained as characteristic harmonic components.

[0057] Specifically, based on the acquired main frequency and harmonic data, the system executes a bandwidth determination algorithm. First, a spectral energy accumulation distribution function is established, calculating the energy accumulation percentage starting from low frequencies to determine the upper frequency limit containing 98% of the signal energy as the actual bandwidth boundary. Typically, the bandwidth range of chip power supply fluctuations is between 100MHz and 2.5GHz. Based on the determined bandwidth data, the system customizes sampling parameters for each sampling region. For example, for the digital core region with a high power switching frequency, the sampling rate is set to 5GS / s; while for the analog peripheral region with slower fluctuations, the sampling rate is set to 1.2GS / s. Simultaneously, the system configures adaptive trigger thresholds for sensor nodes based on the characteristic frequencies of each region, typically setting the trigger sensitivity to ±1.5% of the nominal voltage. Sampling timing control employs a time-division multiplexing strategy, dividing all sensors into 3-4 groups. Sensors within each group sample at off-peak times, and sampling times between groups are staggered by 10-15ns to prevent power supply interference caused by simultaneous sampling. The system uses a custom-designed low-latency data bus to collect sampled data. This bus is based on a high-speed serial interface design, with each channel having a bandwidth of 3.2Gbps. A 7-bit checksum and a 16-bit timestamp are appended to each sampled data point. The data is transmitted via the bus to the central sensor control unit, which performs real-time data verification and reconstruction, reconstructing the data from different regions into a complete power rail voltage distribution dataset in chronological order. This dataset is stored using a three-dimensional data structure, containing spatial coordinates, time coordinates, and voltage values. Test vectors are also appended to indicate the execution status, forming a complete dynamic mapping of the power rail voltage distribution.

[0058] 102. Obtain the test vector sequence of the chip under test, and calculate the predicted power rail voltage drop data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model;

[0059] In one embodiment of the present invention, the step of acquiring the test vector sequence of the chip under test and calculating the power rail voltage drop prediction data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model includes: acquiring the test vector sequence of the chip under test and calling the corresponding pre-trained neural network model according to the identification code of the chip under test; segmenting the test vector sequence according to the execution time sequence, calculating the signal flip data of each segment of the test vector, and constructing a test vector feature matrix; performing time-domain decomposition on the power rail voltage distribution data, extracting the amplitude, frequency, and phase features of voltage fluctuations, and generating a voltage feature matrix; inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features; and using the decoder of the pre-trained neural network model to predict voltage changes based on the time-series correlation features to obtain the power rail voltage drop prediction data.

[0060] Specifically, in this embodiment, the test vector sequence of the chip under test is first obtained from the test plan library of the test system. The test vector sequence is typically stored in a standard test vector format (STIL or WGL format), containing input stimulus signals, expected output responses, and timing control information. The system identifies the specific model and version information of the chip by reading the electronic identification code (usually a 64-bit binary code containing manufacturer information, chip series model, process version, etc.) on the chip package or wafer. The identification code is obtained using a dedicated read instruction, employing a 3.3V TTL level signal and completed via serial data communication. After obtaining the identification code, the system queries the model library index table, which contains the mapping relationship between different chip models and corresponding pre-trained neural network models. For a specific chip under test, such as an ARM Cortex-A78 architecture processor using a 14nm process, the system will call a pre-trained model specifically trained for that chip series. These models are stored in the system's model library, saved in standard HDF5 format, and include network weights, neuron biases, model hyperparameters, and normalized parameters. The model invocation process is implemented through a high-speed cache loading mechanism, which loads the model parameters into the GPU or dedicated TPU computing unit, initializes the runtime environment, and prepares to start prediction calculations.

[0061] Specifically, after acquiring the test vector sequence, the system performs time-division segmentation. First, based on the test clock signal, the test vector sequence is divided into fixed-length segments according to the execution timing, each typically containing 1000-2000 consecutive test vectors. The segment length is determined based on the chip's clock frequency and the power network's discharge time constant, ensuring continuous correlation of power states within each segment. For each test vector segment, the system calculates signal flip data, including the state changes of each signal line. In the specific calculation process, the system first represents each test vector as a binary signal state vector, and then calculates the Hamming distance (i.e., the number of bits involved in the state flip) between adjacent test vectors. For a chip with 256 input pins, the system constructs a 256-dimensional flip vector, where each dimension represents the number of flips of the corresponding pin between adjacent test cycles. Furthermore, the system also calculates weighted flip data, considering the differences in load capacitance among different pins. For example, pins connected to large-area buses consume more current during flips due to their larger load capacitance, thus receiving a higher weight. The system assigns a weighting factor (typically ranging from 0.5 to 2.5) to each pin based on the load parameters in the chip design file, multiplies it by the original flip data, and obtains weighted flip data. Finally, the system integrates the weighted flip data of each test vector segment into a test vector feature matrix. The matrix dimension is the number of segments × feature dimension, where the feature dimension includes multi-dimensional features such as total flip count, maximum consecutive flip count, and pin group flip mode.

[0062] Specifically, the system simultaneously performs time-domain decomposition and feature extraction on the acquired power rail voltage distribution data. First, the Empirical Mode Decomposition (EMD) algorithm is applied to decompose the voltage waveform into multiple Intrinsic Mode Functions (IMFs), each IMF representing a characteristic oscillation mode in the voltage fluctuation. Typically, the system extracts 5-7 IMF components, covering the complete spectrum from high-frequency transient response to low-frequency voltage drift. For each IMF component, the system calculates the instantaneous amplitude and instantaneous phase using Hilbert transform to obtain the dynamic characteristics of the voltage fluctuation at different time scales. During feature extraction, the system calculates the main characteristic parameters of each IMF, including the mean amplitude, maximum amplitude, amplitude standard deviation, dominant frequency component, and phase change rate. Furthermore, the system extracts statistical features of the voltage waveform, such as skewness, kurtosis, and average crossover rate, to capture the non-Gaussian nature of the voltage distribution. For spatially distributed voltage data, the system uses Principal Component Analysis (PCA) to reduce dimensionality, retaining the principal components that explain 95% of the variance, thus reducing data redundancy. Finally, the system combines these time-domain features, frequency-domain features, and statistical features into a voltage feature matrix. The matrix contains two dimensions: the number of time windows and the feature dimension. The feature dimension is usually 30-50, which includes a multi-faceted description of voltage fluctuations.

[0063] Specifically, after constructing the test vector feature matrix and voltage feature matrix, the system inputs them into the bidirectional encoder of the pre-trained neural network model for processing. The bidirectional encoder adopts a BiLSTM (Bidirectional Long Short-Term Memory) structure, consisting of forward recursive units and backward recursive units. The forward recursive units start from the beginning of the time series and process the data sequentially; the backward recursive units start from the end of the sequence and process the data in reverse time. The network's input layer receives the concatenated vector of the test vector feature matrix and voltage feature matrix, which is then transformed into a unified feature representation through a 128-unit embedding layer. The BiLSTM layer contains 64 LSTM units in each direction, and each LSTM unit contains an input gate, a forget gate, an output gate, and a memory unit. The flow of information is determined by controlling the opening and closing states of these gates. The forward LSTM captures the causal relationship between the test vector and voltage fluctuations, while the backward LSTM captures the global constraints of voltage distribution. Together, they establish a complete temporal dependency model. Following the BiLSTM layer is an attention mechanism layer, which calculates the importance weights for each time step, enabling the model to focus on the most critical time points for voltage prediction. Ultimately, the bidirectional encoder generates temporal correlation features containing rich contextual information, which encode the underlying patterns of voltage fluctuations during test vector execution.

[0064] Specifically, after the temporal correlation features are generated, they are passed to the decoder part of the pre-trained neural network model for voltage change prediction. The decoder adopts a multi-layer Transformer structure, containing four decoder blocks, each containing a multi-head self-attention layer and a feedforward neural network layer. The self-attention mechanism allows the model to associate each position in the input sequence with all other positions, effectively modeling long-distance dependencies. In the specific implementation, eight attention heads are used, each with a dimension of 64, allowing the model to focus on different aspects of the input sequence simultaneously. The decoding process adopts an autoregressive approach, that is, the model first predicts the voltage change at the next time step, and then uses the prediction result as a new input to continue predicting further time steps. To improve prediction accuracy, the system uses a beam search algorithm to maintain multiple candidate prediction paths and selects the optimal path as the final prediction result based on the cumulative probability. The decoder output is converted into the expected voltage change value through a fully connected layer, covering voltage fluctuations within the next 100-500 test vector execution cycles. Ultimately, the system combines the predicted voltage changes with the nominal voltage value to construct complete power rail voltage drop prediction data. The data includes three dimensions: time, spatial location, and predicted voltage value, forming an accurate prediction map of the future state of the power network.

[0065] Furthermore, the step of inputting the test vector feature matrix and voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate temporal correlation features includes: bidirectionally segmenting the test vector feature matrix, inputting the forward temporal features of the test vector feature matrix into the forward channel of the bidirectional encoder, and inputting the reverse temporal features of the test vector feature matrix into the reverse channel of the bidirectional encoder to obtain bidirectional hidden layer features of the test vector; bidirectionally segmenting the voltage feature matrix, inputting the forward temporal features of the voltage feature matrix into the forward channel of the bidirectional encoder, and inputting the reverse temporal features of the voltage feature matrix into the reverse channel of the bidirectional encoder to obtain bidirectional hidden layer features of the voltage features; calculating bidirectional cross-attention weights based on the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage features to generate a weight matrix of forward and reverse features; and weighting and combining the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage features based on the weight matrix to obtain the temporal correlation features.

[0066] Specifically, the test vector feature matrix is ​​first bidirectionally segmented to fully utilize the bidirectional information of the test vectors over time. In practice, the system first divides the original test vector feature matrix (with dimensions N×F, where N is the time step and F is the feature dimension) along the time axis into multiple overlapping windows of length L, with an overlap rate of 50% between adjacent windows. For each window's data, the system constructs two representations: forward temporal features and reverse temporal features. The forward temporal features maintain the original time order, from t0 to tL-1; the reverse temporal features reverse the time order, from tL-1 to t0. This bidirectional segmentation strategy allows the model to simultaneously consider causal relationships (forward propagation) and constraints (backward propagation). Subsequently, the system inputs the forward temporal features into the forward channel of the bidirectional encoder, which consists of three stacked GRUs (Gated Recurrent Units), each containing 128 neurons. The forward channel processes data starting from the beginning of the sequence, progressively updating the hidden states in chronological order. Simultaneously, the system inputs the reverse temporal features into the reverse channel of the bidirectional encoder. This channel also consists of three stacked GRU layers, but the processing direction is opposite to that of the forward channel. The reverse channel updates the hidden states in reverse chronological order, starting from the end of the sequence. After the two channels process the data independently, the system extracts all time-step outputs of the last GRU layer in each channel and combines them to form the bidirectional hidden layer features of the test vector, represented as a tensor of dimension N×(2×128) Ht, where the first 128 dimensions represent the forward channel features and the last 128 dimensions represent the reverse channel features.

[0067] Specifically, the same processing flow is applied to the voltage feature matrix to capture the bidirectional temporal characteristics of voltage changes. The voltage feature matrix (with dimensions N×E, where E is the voltage feature dimension) is first constructed into forward and reverse temporal representations using the same windowing method. The voltage feature processing employs a bidirectional encoder with the same architecture as the test vector features, but uses independent weight parameters to optimize specifically for the temporal patterns of the voltage features. In the implementation, the forward channel uses a residual connection structure, adding skip connections after each GRU layer to mitigate the gradient vanishing problem; the reverse channel uses layer normalization techniques to improve training stability. The forward channel processes the forward temporal data of the voltage features, capturing the gradual trend of voltage changes; the reverse channel processes the reverse temporal data, identifying abrupt changes and bounce patterns in voltage fluctuations. After processing, the system also extracts all time-step outputs of the last GRU layer in both channels to form the bidirectional hidden layer feature Hv of the voltage features, a tensor with dimensions N×(2×128). Bidirectional processing enables the model to understand the behavior of voltage fluctuations at different time scales, including fast transient response and slow accumulation effect, which greatly improves the ability to model complex voltage changes.

[0068] Specifically, after obtaining the bidirectional hidden features of the test vector and voltage features, the system calculates bidirectional cross-attention weights to establish the correlation between the two features. First, the system maps the bidirectional hidden features Ht of the test vector to a query matrix Q (N×64 dimension) through a linear transformation; it then maps the bidirectional hidden features Hv of the voltage features to a key matrix K (N×64 dimension) and a value matrix V (N×64 dimension) through different linear transformations. The linear transformations employ a weight-sharing mechanism to reduce the number of parameters while maintaining the model's expressive power. Next, the system calculates the dot product of the query matrix and the key matrix, divides it by a scaling factor of 8 (i.e., the square root of the feature dimension), and then applies a softmax function to normalize it to obtain the attention weight matrix A (N×N dimension). Each element Aij of the attention weight matrix represents the degree of attention the test vector features at time step i pay to the voltage features at time step j. To enhance the model's ability to model long-term dependencies, the system also implements a multi-head attention mechanism, projecting the hidden features in parallel to eight subspaces, calculating the attention weights for each subspace, and then merging the results. Furthermore, the system introduces relative position encoding, considering the relative distance between the test vector and voltage features in the time dimension, enabling the model to capture temporal local and global dependencies. The final generated weight matrix includes weights for four types of cross-relationships: positive feature versus positive feature, positive feature versus negative feature, negative feature versus positive feature, and negative feature versus negative feature.

[0069] Specifically, based on the calculated weight matrix, the system weights and combines the bidirectional hidden features of the test vector and the bidirectional hidden features of the voltage feature to generate time-series correlated features. First, the system multiplies the weight matrix with the value matrix to obtain a weighted voltage feature representation. Then, a gated fusion mechanism combines the weighted voltage features with the original test vector hidden features. In the implementation, the system uses a two-layer feedforward neural network to calculate the fusion gate, with the gate value ranging from 0 to 1, controlling the fusion ratio of the original features and the weighted features. The calculation of the fusion gate considers the local contextual information of the features, assigning different weights to noisy features and strongly correlated features. The fused features undergo layer normalization and residual connections to form preliminary correlated features. Next, the system uses a two-layer position-aware feedforward network to further transform the features and extract a more abstract representation. The feedforward network has a hidden layer dimension of 512 and uses the GELU activation function, exhibiting good nonlinear modeling capabilities. Finally, the system applies a feature enhancement module, extracting global statistical features through global average pooling and max pooling operations, and combining them with local features to form the final time-series correlated features. The obtained temporal correlation feature is a tensor with a dimension of N×256. Each row represents a comprehensive feature representation of a time step, which contains the deep interaction information between the test vector and voltage features in the time series. It can effectively express the influence pattern of the test vector on voltage changes and the feedback effect of voltage state on subsequent test execution.

[0070] 103. Based on the predicted power rail voltage drop data, perform compensation control on the multi-level parallel capacitor array on the test board, and execute chip tests corresponding to the test vector sequence under compensation control to obtain chip test results and power rail compensation control data.

[0071] In one embodiment of the present invention, the step of performing compensation control on the multi-level parallel capacitor array on the test board based on the power rail voltage drop prediction data, and executing the chip test corresponding to the test vector sequence under the compensation control to obtain the chip test results and power rail compensation control data includes: performing response speed analysis on the power rail voltage drop prediction data to calculate the voltage drop compensation requirements at different time scales; calculating the compensation current magnitude and injection timing of each capacitor unit in the multi-level parallel capacitor array based on the voltage drop compensation requirements at different time scales; performing charge and discharge control on the capacitor units in the multi-level parallel capacitor array through a multi-channel PWM controller to obtain power rail compensation control data, and executing the test vector sequence under the charge and discharge control to obtain the chip test results.

[0072] Specifically, the system first performs response speed analysis on the power rail voltage drop prediction data to determine the voltage drop compensation requirements at different time scales. The system uses multi-resolution wavelet analysis to decompose the power rail voltage drop prediction data in the time-frequency domain, employing the db4 wavelet basis function for a 5-level decomposition, breaking down the original prediction data into components of different frequency bands. The decomposed data includes high-frequency detail component D1 (corresponding to a frequency range of 1-2 GHz), mid-high frequency detail component D2 (500 MHz-1 GHz), mid-frequency detail component D3 (250-500 MHz), mid-low frequency detail component D4 (125-250 MHz), low-frequency detail component D5 (62.5-125 MHz), and low-frequency approximate component A5 (0-62.5 MHz). For each frequency band component, the system calculates its energy distribution and time response characteristics, including parameters such as peak amplitude, energy percentage, rise time rate, and duration. High-frequency components typically reflect voltage spikes caused by rapid chip core switching and clock edge triggering; mid-frequency components reflect fluctuations caused by data bus transmission and memory access; while low-frequency components represent temperature effects and cumulative voltage drops resulting from prolonged operation. The system combines these analysis results to construct a three-dimensional feature map of time, frequency, and amplitude, mapping it to a voltage drop compensation requirement matrix at different time scales. Each element in the matrix contains information in three dimensions: time point, frequency band, and required compensation current value.

[0073] Specifically, based on the voltage drop compensation requirements at different time scales, the system calculates the compensation current magnitude and injection timing of each capacitor unit in the multi-stage parallel capacitor array. The multi-stage parallel capacitor array on the test board consists of three types of capacitor units: large-capacity electrolytic capacitors (330μF-470μF, ESR approximately 10-15mΩ), medium-capacity ceramic capacitors (4.7μF-10μF, ESR approximately 5-8mΩ), and small-capacity film capacitors (0.01μF-0.1μF, ESR approximately 2-3mΩ). The system first establishes an accurate equivalent circuit model of the capacitor array, including the capacitance value, equivalent series resistance, equivalent series inductance, and interconnection impedance between units for each capacitor unit. Then, the system uses the state-space method to solve for the optimal charging and discharging control strategy. In the specific implementation, the system constructs an objective function, taking the mean square error between the predicted voltage and the desired voltage as the main optimization objective, while also considering switching losses and stability constraints. The optimization process adopts a model predictive control framework, progressively solving for the optimal control sequence within a sliding time window. For high-frequency voltage drop compensation, the system primarily utilizes small-capacity thin-film capacitors with charge / discharge cycles set within the range of 5-20 ns. For mid-frequency voltage drops, medium-capacity ceramic capacitors are used, with charge / discharge cycles set within the range of 50-200 ns. For low-frequency voltage drops, large-capacity electrolytic capacitors are employed, with charge / discharge cycles ranging from 500 ns to 2 μs. The system also considers the location distribution of the capacitor units, prioritizing those closer to the voltage drop hotspots to reduce transmission delay. Ultimately, the system generates a complete capacitor unit control strategy, including the activation time, conduction duration, and compensation current magnitude for each capacitor unit.

[0074] Specifically, after calculating the control strategy, the system uses a multi-channel PWM controller to precisely control the charging and discharging of the capacitor units in the multi-level parallel capacitor array. The multi-channel PWM controller is implemented using a dedicated FPGA and has 128 independent control channels. Each channel is equipped with a high-speed MOSFET driver circuit, achieving a drive capability of 2A and a rise time of less than 3ns. The controller's clock frequency is set to 500MHz, and the PWM resolution is 10 bits, enabling a minimum pulse width modulation accuracy of 1ns. The system converts the capacitor unit control strategy calculated in the previous step into specific PWM parameters, including PWM frequency, duty cycle, and phase. For high-frequency compensation requiring precise control, the system employs multi-interleaved PWM technology, superimposing multiple PWM signals with staggered phases to achieve an equivalent resolution improvement. The controller also integrates an adaptive dead-time control function, dynamically adjusting the dead time (typically 2-5ns) according to the MOSFET switching characteristics to prevent through-current. The PWM signal, through an isolation buffer and driver amplifier, controls the on and off of the MOSFET switches, thereby realizing the charging and discharging process of the capacitor units. The actual compensation current of each capacitor unit is monitored in real time by an integrated current sensor, forming a closed-loop control system. The system records all control parameters and monitoring data as power rail compensation control data, including the PWM parameters, switching status, compensation current value and actual power supply voltage value of each capacitor unit at each time point, for subsequent test result correction.

[0075] Specifically, after establishing a complete compensation control system, the system executes chip tests corresponding to the test vector sequence under dynamic compensation conditions. The test execution process employs a synchronous control strategy; the test vector generator and PWM controller maintain timing consistency through a precise clock synchronization mechanism, with deviations controlled within 100ps. The system first enters a warm-up phase, running a set of standard test vectors (lasting approximately 100μs) to bring the capacitor array to a stable operating state. Then, the system begins the formal testing process. The test vector generator applies input excitation to the chip according to a predetermined timing sequence, while the PWM controller adjusts the compensation state of the capacitor array in real time according to a pre-calculated control strategy. During the test, the system continuously monitors the chip's output response and power supply voltage status, forming a closed-loop regulation mechanism. If the actual voltage deviates from the predicted value by more than a preset threshold (typically ±3% of the nominal voltage), the system triggers emergency compensation adjustment logic, temporarily increasing the compensation intensity. The test data acquisition system records all output signals and power supply status information of the chip, with a sampling rate set to 5GS / s and a precision of 12 bits. After the test, the system performs preliminary processing on the acquired raw data, including digitization, noise reduction, and time alignment, generating a structured chip test result dataset. This dataset contains information such as test vector ID, timestamp, input status, output response, expected output, and power supply voltage value.

[0076] Furthermore, the step of calculating the compensation current magnitude and injection timing of each capacitor unit in the multi-stage parallel capacitor array according to the voltage drop compensation requirements at different time scales includes: performing wavelet transform decomposition on the voltage drop compensation requirements at different time scales, decomposing the compensation signal into different frequency sub-bands, and calculating the energy distribution characteristics and phase characteristics of each frequency sub-band; constructing a dynamic impedance model based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-stage parallel capacitor array, and calculating the compensation capability of each capacitor unit at different frequencies through state equations; optimizing the allocation of compensation tasks for each frequency sub-band based on a genetic algorithm, establishing an objective function for capacitor unit compensation efficiency and compensation timing, and generating a candidate set of compensation strategies; iteratively optimizing the candidate set of compensation strategies using a particle swarm optimization algorithm, and calculating the compensation current magnitude and injection timing of each capacitor unit.

[0077] Specifically, the system first performs wavelet transform decomposition on the voltage drop compensation requirements at different time scales to accurately distinguish the compensation characteristics of different frequency components. The system employs Biorthogonal Wavelet Transform (DWPT) technology, selecting the Daubechies 8 (db8) wavelet basis function for decomposition. This function has good time-frequency localization characteristics and smoothness, making it suitable for handling spikes and oscillating components in power supply waveforms. During the decomposition process, the system decomposes the original compensation requirement signal into 7 levels according to a binary tree structure, generating a total of 128 frequency sub-bands covering the complete spectrum from 5MHz to 2.5GHz. For each frequency sub-band, the system calculates four sets of key characteristic parameters: energy density (energy distribution per unit time), peak factor (ratio of maximum amplitude to root mean square), frequency center within the sub-band (energy-weighted average frequency), and phase continuity (phase change rate between adjacent time windows). These parameters reflect the distribution characteristics of different frequency components in the time and amplitude dimensions. Especially for high-frequency transient voltage drops, the system additionally calculates the rise time and duration to accurately characterize its time-domain characteristics. After processing, the system organizes these features into a structured spectrum, which includes four dimensions: time, frequency, energy, and phase. This spectrum describes the complete characteristics of voltage drop compensation requirements in different frequency sub-bands, providing a data foundation for subsequent compensation resource allocation.

[0078] Specifically, the system constructs an accurate dynamic impedance model based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-level parallel capacitor array. The capacitor array on the test board contains three types of capacitor units: large-capacity electrolytic capacitors (330μF, ESR=12mΩ, ESL=15nH), medium-capacity ceramic capacitors (10μF, ESR=6mΩ, ESL=5nH), and small-capacity film capacitors (0.1μF, ESR=3mΩ, ESL=1nH), corresponding to low-frequency, mid-frequency, and high-frequency compensation requirements, respectively. The system first measures the impedance characteristics of each type of capacitor unit at different frequencies (from 100kHz to 3GHz) using a vector network analyzer, generating impedance curves at 25 frequency points. Then, the system uses a Foster equivalent circuit model to represent each capacitor unit, which includes RLC parallel branches and series impedance, and determines the model parameters through a curve fitting algorithm. To account for the effects of temperature, parametric models were established at three key temperature points (25℃, 55℃, and 85℃), and piecewise linear interpolation was used to calculate the parameter values ​​at the intermediate temperatures. The positional effect of the capacitor cells was also incorporated into the model. By establishing a planar electromagnetic field distribution map based on measured data, the electrical coupling coefficient of the capacitor cells at different locations was calculated. Finally, all parameters were integrated into the state-space equations, which used differential-algebraic equations (DAE) to describe the dynamic characteristics of the system. The transient response of each capacitor cell under different operating conditions was solved by numerical integration to obtain a complete evaluation index of the compensation capability, including response delay, peak compensation current, energy efficiency, and stable operating region.

[0079] Specifically, based on the spectral features and dynamic model of the capacitor cells obtained in the first two steps, the system applies a genetic algorithm to optimize the allocation of compensation tasks for each frequency sub-band. The genetic algorithm uses a 128-bit binary code to represent a compensation strategy, with each gene representing whether a frequency sub-band is allocated to a specific type of capacitor cell. The initial population contains 500 randomly generated strategies to ensure a sufficiently large solution space. The fitness function design comprehensively considers three factors: compensation accuracy (mean square error between predicted and target voltages), energy efficiency (energy consumption during compensation), and switching loss (number of capacitor cell switching operations). Fitness calculation uses a weighted summation method to comprehensively evaluate performance under different test scenarios. Genetic operations include elite selection, single-point crossover, and uniform mutation, with a crossover probability of 0.85 and a mutation probability of 0.05. To accelerate convergence, the algorithm uses adaptive genetic parameters, dynamically adjusting the operation probabilities based on population diversity. After 200 iterations, the algorithm generates a Pareto non-dominated solution set, representing the optimal trade-off between different compensation strategies. For each candidate strategy, the system calculates in detail the allocation schemes of 128 frequency sub-bands among the three types of capacitor units, as well as the preliminary compensation timing for each capacitor unit. From these non-dominated solutions, the system selects 50 representative solutions to form a candidate set of compensation strategies, which serves as the starting point for the next optimization step.

[0080] Specifically, the system uses a particle swarm optimization (PSO) algorithm to perform fine-grained iterative optimization on the candidate set of compensation strategies, calculating the precise compensation current magnitude and injection timing for each capacitor unit. The PSO algorithm uses 50 particles, corresponding to 50 candidate strategies generated by a genetic algorithm. Each particle contains three sets of parameters: capacitor unit activation time sequence, current amplitude modulation coefficient, and phase adjustment factor. The particle's position represents a specific compensation control scheme, and its velocity represents the search direction and step size. The objective function design employs a weighted synthesis method, combining the three objectives of minimizing voltage error, minimizing power consumption, and minimizing response time into a single score. The inertia weight is set to a linear decreasing strategy, decreasing from 0.9 to 0.4, giving the algorithm strong global search capabilities in the early stages and fine-grained local optimization capabilities in the later stages. The individual optimal position and the global optimal position record the historical best solutions for each particle and the entire swarm, respectively, guiding the particle's motion direction. To improve search efficiency, the algorithm introduces a dynamic topology structure, adaptively adjusting the information sharing range based on the Euclidean distance between particles. After 150 iterations, the algorithm converges to a stable solution, generating a complete compensation control strategy. The final output includes precise compensation parameters for each capacitor unit (56 in total): activation time (accuracy of 1ns), current amplitude modulation curve (10-point piecewise linear representation), duration of action, and cooling time. These parameters constitute a complete control scheme for the multi-level parallel capacitor array, ensuring accurate power rail voltage drop compensation at different frequency sub-bands.

[0081] 104. Based on the power rail compensation control data and power rail voltage distribution data, the chip test results are corrected to obtain the corrected chip performance parameters.

[0082] In one embodiment of the present invention, the step of correcting the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain corrected chip performance parameters includes: aligning the power rail compensation control data and the power rail voltage distribution data according to a time series to obtain actual operating voltage data; calculating the operating voltage deviation curves of each functional module of the chip under test based on the difference between the nominal operating voltage of the chip under test and the actual operating voltage data; correlating the performance parameters in the chip test results with the operating voltage deviation curves according to the test sequence to obtain parameter-voltage relationship data; and performing nonlinear correction calculations on the chip test results based on the parameter-voltage relationship data to obtain corrected chip performance parameters.

[0083] Specifically, the system first performs time series alignment processing on the power rail compensation control data and power rail voltage distribution data to obtain complete actual operating voltage data. The system employs a timestamp-based multi-source data synchronization algorithm to process two sets of time series data: power rail compensation control data (including PWM control parameters, switching states, and compensation current values) and power rail voltage distribution data (including voltage measurements at each sampling point). The alignment process first establishes a unified time baseline, using the test vector clock as the primary reference, with a time resolution of 100 ps. Then, the system maps the two sets of data onto the reference time axis according to their respective timestamps. For regions with inconsistent sampling points, cubic spline interpolation is used to calculate the values ​​at intermediate moments. During the alignment process, the system also addresses the sampling delay issue from different data sources, calculating the relative delay between each data stream through cross-correlation analysis. Typical delay values ​​are 3-15 ns, and time offset compensation is performed accordingly. After data alignment, the system combines the compensation current and voltage distribution data from the compensation control data and uses a distributed circuit model to calculate the actual operating voltage of each functional area of ​​the chip. The calculations took into account the impedance characteristics of the power distribution network, the spatial distribution effect of the compensation current, and the voltage drop difference between the voltage measurement point and the actual chip power supply point. The final generated actual operating voltage data is a three-dimensional data structure containing three coordinate axes: time dimension (test cycle), spatial dimension (chip functional area), and voltage value, which fully records the actual power supply status of each area of ​​the chip during the test.

[0084] Based on the acquired actual operating voltage data, the system calculates the operating voltage deviation curves for each functional module of the chip under test. First, the system extracts nominal operating voltage data from the chip design database. This data includes the design voltage values ​​and allowable fluctuation ranges for different functional modules of the chip (such as core logic, I / O interfaces, analog circuits, and memory cells). During nominal voltage extraction, the system considers the configuration information of different power domains; for example, the nominal voltage for the core logic region is 0.9V, for the I / O region it is 1.8V, and for the analog circuit region it is 2.5V. Then, the system compares the actual operating voltage data with the nominal voltage and calculates the voltage deviation value ΔV = V_actual - V_nominal. To accurately characterize the voltage state of each functional module, the system divides the chip's planar layout into regions. Based on the layout data, the chip is divided into 16 main functional blocks, and corresponding voltage monitoring points are assigned to each block. For areas with insufficient voltage monitoring points, the system constructs a voltage distribution interpolation model based on the power network topology and equipotential surface characteristics to estimate the voltage values ​​in areas not directly monitored. The calculation of the operating voltage deviation also considers the temperature effect. Using readings from a temperature sensor integrated on the chip, combined with a voltage-temperature sensitivity coefficient (typically -1.5mV / °C to -2.2mV / °C), voltage offsets caused by temperature fluctuations are corrected. The resulting operating voltage deviation curve contains two dimensions: a time dimension (the execution process of the test vector sequence) and a spatial dimension (the 16 functional blocks of the chip), recording the dynamic changes in voltage deviation throughout the entire test process.

[0085] Next, the system performs correlation analysis between the performance parameters and the operating voltage deviation curve in the chip test results to establish parameter-voltage relationship data. First, the system extracts key performance parameters from the raw test results, including digital circuit parameters (such as logic gate delay, flip-flop setup time, clock skew, etc.), analog circuit parameters (such as amplifier gain, bandwidth, signal-to-noise ratio, etc.), and mixed-signal parameters (such as ADC / DAC linearity, effective bits, etc.). The parameter extraction process is based on a specific test vector sequence and the corresponding output response. For example, logic gate delay is calculated by measuring the time interval between input and output changes; amplifier gain is determined by the input-output voltage ratio. Then, the system establishes a mapping relationship between performance parameters and test timing, determining the precise measurement time point for each parameter in the test vector sequence. This mapping is obtained through the test program flowchart and vector annotation information; each performance parameter is assigned one or more timestamps indicating the time when its measurement occurred. Subsequently, the system aligns these time points with the previously calculated operating voltage deviation curve to find the actual operating voltage value corresponding to the measurement time of each parameter. For parameters whose measurement process spans multiple test cycles, the system calculates the voltage statistical characteristics within that time window, including the average value, maximum deviation, and standard deviation. The final generated parameter-voltage relationship data is a correlation table. Each row contains a performance parameter, its measured value, normal range, measurement time period, and corresponding voltage deviation characteristics, comprehensively describing the impact of voltage changes on the test results.

[0086] Based on the established parameter-voltage relationship data, the system performs nonlinear correction calculations on the chip test results to obtain the corrected chip performance parameters. The correction process first extracts the sensitivity coefficient of each parameter to voltage changes from a pre-built parameter sensitivity library. These sensitivity coefficients are obtained through offline characterization experiments. During the experiments, parameters of standard chip samples are measured under different voltage conditions to establish parameter-voltage response curves. For example, logic gate delay parameters typically exhibit a relationship proportional to the reciprocal of the voltage, and their sensitivity curves are described using a piecewise polynomial model; while analog parameters such as the gain of operational amplifiers often exhibit nonlinear response characteristics, represented by higher-order polynomials or lookup tables. For each measured parameter, the system extracts the corresponding correction model from the sensitivity library and calculates the parameter correction value based on the actual voltage deviation. The calculation process employs an adaptive correction algorithm, applying different correction strategies to different degrees of voltage deviation: linear correction is used for small deviations (<3%), second-order polynomial correction is used for medium deviations (3%-8%), and lookup table interpolation is used for large deviations (>8%). The calibration calculation also considers the mutual influence between parameters, describing the multi-parameter coupling effect through a sensitivity matrix. Particularly for related parameters sharing the same power domain, a joint calibration strategy is employed to improve accuracy. Ultimately, the system generates a complete set of calibrated chip performance parameters, each containing four parts: the original measured value, the calibrated value, the calibration confidence level, and the reference range. The calibrated performance parameters reflect the chip's true performance characteristics under standard voltage conditions, eliminating measurement bias introduced by power rail voltage drop, and providing an accurate and reliable basis for chip performance evaluation and classification.

[0087] In this embodiment, the chip under test (DUT) is connected to the test channel via a probe card. Multiple voltage sensor nodes in the power distribution layer of the probe card are sampled to obtain power rail voltage distribution data. A preset neural network model is used to calculate predicted power rail voltage drop data based on the power rail voltage distribution data and the test vector sequence. Compensation control is applied to the multi-level parallel capacitor array on the test board based on the predicted data, and chip testing is performed under this control to obtain test results and compensation control data. The test results are then corrected using the compensation control data and voltage distribution data to obtain the corrected chip performance parameters. This invention achieves accurate monitoring, prediction, active compensation, and correction of power rail transient voltage drop, significantly improving the accuracy and consistency of chip performance testing.

[0088] The chip performance testing method based on automated equipment in the embodiments of the present invention has been described above. The chip performance testing system based on automated equipment in the embodiments of the present invention will be described below. Please refer to [link / reference]. Figure 2 One embodiment of the chip performance testing system based on automated equipment in this invention includes:

[0089] The voltage acquisition module 201 is used to place the chip under test on the test board, connect to the test channel through the probe card, and sample and control multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data.

[0090] The voltage drop prediction module 202 is used to acquire the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model;

[0091] The dynamic compensation module 203 is used to perform compensation control on the multi-level parallel capacitor array on the test board according to the power rail voltage drop prediction data, and to perform chip testing corresponding to the test vector sequence under the compensation control to obtain chip test results and power rail compensation control data.

[0092] The result correction module 204 is used to correct the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

[0093] In this embodiment of the invention, the chip performance testing system based on automated equipment runs the aforementioned chip performance testing method based on automated equipment. The system connects the chip under test to the test channel via a probe card, samples multiple voltage sensor nodes in the power distribution layer of the probe card to obtain power rail voltage distribution data, calculates predicted power rail voltage drop data based on the power rail voltage distribution data and test vector sequence using a preset neural network model, performs compensation control on the multi-level parallel capacitor array on the test board based on the predicted data, and executes chip testing under this control to obtain test results and compensation control data, and corrects the test results using the compensation control data and voltage distribution data to obtain corrected chip performance parameters. This invention achieves accurate monitoring, prediction, active compensation, and correction of power rail transient voltage drop, significantly improving the accuracy and consistency of chip performance testing.

[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system, device, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0095] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0096] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip performance testing method based on automated equipment, characterized in that, The automated equipment includes a test board, probe cards, and test channels. The chip performance testing method based on the automated equipment includes: The chip under test is placed on the test board and connected to the test channel through the probe card. Multiple voltage sensor nodes set in the power distribution layer of the probe card are sampled and controlled to obtain power rail voltage distribution data. The test vector sequence of the chip under test is obtained, and the power rail voltage drop prediction data is calculated based on the power rail voltage distribution data and the test vector sequence using a preset neural network model. The response speed of the predicted power rail voltage drop is analyzed to calculate the voltage drop compensation requirements at different time scales. Wavelet transform decomposition is performed on the voltage drop compensation requirements at different time scales to decompose the compensation signal into different frequency sub-bands, and the energy distribution characteristics and phase characteristics of each frequency sub-band are calculated. Based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-level parallel capacitor array on the test board, a dynamic impedance model is constructed, and the compensation capability of each capacitor unit at different frequencies is calculated using state equations. The compensation tasks for each frequency sub-band are optimized and allocated using a genetic algorithm, establishing objective functions for capacitor unit compensation efficiency and compensation timing, and generating a candidate set of compensation strategies. The candidate set of compensation strategies is iteratively optimized using a particle swarm optimization algorithm to calculate the compensation current magnitude and injection timing of each capacitor unit. A multi-channel PWM controller is used to control the charging and discharging of the capacitor units in the multi-level parallel capacitor array to obtain power rail compensation control data, and the test vector sequence is executed under the charging and discharging control to obtain the chip test results. Based on the power rail compensation control data and the power rail voltage distribution data, the chip test results are corrected to obtain the corrected chip performance parameters.

2. The chip performance testing method based on automated equipment according to claim 1, characterized in that, The step of placing the chip under test on the test board, connecting it to the test channel via the probe card, and sampling and controlling multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data includes: The chip under test is placed on the test board and connected to the test channel through the probe card. Current density analysis is performed on the power distribution layer of the probe card to determine the key monitoring location of voltage fluctuation. The power distribution layer of the probe card is divided into multiple sampling areas according to the key monitoring locations, and a voltage sensor node is set in each sampling area. The voltage sensor nodes in each sampling area are initialized and sampled to obtain the main frequency component and harmonic component of the voltage fluctuation. The bandwidth range of power consumption change is calculated by Fourier transform based on the main frequency component and harmonic component. According to the bandwidth range, the voltage sensor nodes of each sampling area are configured with sampling timing control parameters, and the sampling data is transmitted to the sensor control unit through a low-latency data bus to obtain the power rail voltage distribution data.

3. The chip performance testing method based on automated equipment according to claim 1, characterized in that, The step of obtaining the test vector sequence of the chip under test and calculating the predicted power rail voltage drop data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model includes: Obtain the test vector sequence of the chip under test, and call the corresponding pre-trained neural network model according to the identification code of the chip under test; The test vector sequence is segmented according to the execution time sequence, the signal flip data of each segment of the test vector is calculated, and a test vector feature matrix is ​​constructed. The power rail voltage distribution data is decomposed in the time domain to extract the amplitude, frequency, and phase characteristics of voltage fluctuations, and a voltage feature matrix is ​​generated. The test vector feature matrix and voltage feature matrix are input into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features; The decoder of the pre-trained neural network model predicts voltage changes based on the time-series correlation features to obtain the power rail voltage drop prediction data.

4. The chip performance testing method based on automated equipment according to claim 3, characterized in that, The step of inputting the test vector feature matrix and voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features includes: The test vector feature matrix is ​​bidirectionally segmented. The forward temporal features of the test vector feature matrix are input into the forward channel of the bidirectional encoder, and the reverse temporal features of the test vector feature matrix are input into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the test vector. The voltage feature matrix is ​​bidirectionally segmented, and the forward timing features of the voltage feature matrix are input into the forward channel of the bidirectional encoder, while the reverse timing features of the voltage feature matrix are input into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the voltage features. Bidirectional cross-attention weights are calculated based on the bidirectional hidden features of the test vector and the bidirectional hidden features of the voltage features, and a weight matrix of positive and negative features is generated. The time-series correlation features are obtained by weighting and combining the bidirectional hidden features of the test vector and the bidirectional hidden features of the voltage feature according to the weight matrix.

5. The chip performance testing method based on automated equipment according to claim 1, characterized in that, The step of correcting the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters includes: The power rail compensation control data and power rail voltage distribution data are aligned according to the time series to obtain the actual working voltage data. Based on the difference between the nominal operating voltage and the actual operating voltage of the chip under test, calculate the operating voltage deviation curve of each functional module of the chip under test. The performance parameters in the chip test results are correlated with the operating voltage deviation curve according to the test sequence to obtain parameter-voltage relationship data; The chip test results are nonlinearly corrected based on the parameter-voltage relationship data to obtain the corrected chip performance parameters.

6. A chip performance testing system based on automated equipment, characterized in that, The automated equipment includes a test board, probe cards, and test channels. The chip performance testing system based on the automated equipment includes: The voltage acquisition module is used to place the chip under test on the test board, connect it to the test channel through the probe card, and sample and control multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data. The voltage drop prediction module is used to acquire the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data based on the power rail voltage distribution data and the test vector sequence using a preset neural network model. The dynamic compensation module is used to analyze the response speed of the predicted power rail voltage drop data and calculate the voltage drop compensation requirements at different time scales; it performs wavelet transform decomposition on the voltage drop compensation requirements at different time scales, decomposes the compensation signal into different frequency sub-bands, and calculates the energy distribution characteristics and phase characteristics of each frequency sub-band; it constructs a dynamic impedance model based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-level parallel capacitor array on the test board, and calculates the compensation capability of each capacitor unit at different frequencies through state equations; it optimizes the allocation of compensation tasks for each frequency sub-band based on a genetic algorithm, establishes the objective function of capacitor unit compensation efficiency and compensation timing, and generates a candidate set of compensation strategies; it iteratively optimizes the candidate set of compensation strategies using a particle swarm optimization algorithm, calculates the compensation current magnitude and injection timing of each capacitor unit; it controls the charging and discharging of the capacitor units in the multi-level parallel capacitor array using a multi-channel PWM controller to obtain power rail compensation control data, and executes the test vector sequence under the charging and discharging control to obtain chip test results; The result correction module is used to correct the chip test results based on the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

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