A 3DIC iJTAG test interconnection structure

Abstract

The present application provides an iJTAG test interconnect structure for 3DIC, which relates to the field of chip testing technology, including: a plurality of chip dies stacked vertically; each chip die includes a test access port controller; each test access port controller forms a test control path in series to coordinate test tasks, and the test tasks include testing multiple chip dies and testing a single chip die; the bottom chip die is configured with a test data input port and a test data output port; the test data input port receives test data and transmits it to the test access port controller of the chip die to be tested; a TDOMUX module is set in some chip dies, and the selection end of the module is controlled by the test access port controller of the chip die to which it belongs. The present application can significantly reduce the consumption of test ports and chip area resources, efficiently complete single chip testing or multi-chip joint testing, and improve the flexibility and efficiency of overall testing.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an iJTAG test interconnection structure for 3DIC. Background Art

[0002] With the slowdown of Moore's Law, integrated circuits have entered the post-Moore era, with the continuous emergence of new processes, new materials, and new architectures driving the development of integrated circuits. Against this backdrop, the technological development trends in the integrated circuit industry emphasize multi-path innovation in advanced processing, advanced packaging, and architectural innovation.

[0003] In terms of advanced packaging, 3DIC (three-dimensional integrated circuit) technology offers an alternative solution, optimizing performance, power consumption, and size by vertically stacking chips into a single packaged device. This technology allows developers to utilize multiple different manufacturing processes, technology nodes, and even fundamental technologies, providing greater flexibility in chip design. It also allows for the reuse of existing chips without redesign, reducing costs and increasing yields. By shortening interconnect lengths and increasing communication density, it achieves faster data transmission rates and lower latency while reducing power consumption. The development of 3DIC technology is driving integrated circuit technology into a new era, making electronic devices more compact and intelligent.

[0004] Based on architectural innovations, we continuously optimize the communication standards for testing and debugging within integrated circuit chips, introducing iJTAG (internal Joint Test Group) technology. This technology, an extension of the traditional JTAG (Joint Test Group) standard, is designed to improve chip reliability and production efficiency. This technology complies with the IEEE 1687 standard and consists of three main components: a flexible serial TDR (Test Data Register) link, the iJTAG Network Connection Language (ICL), and the iJTAG Program Description Language (PDL). iJTAG's interoperability is crucial for chip developers, ensuring greater reuse of IP developed for verifying or testing chip designs within circuit board designs, effectively reducing chip design costs. Furthermore, the bidirectional feedback loop between chip and board tools enables advanced diagnostic capabilities throughout the tool flow, effectively isolating chip or board design issues. This technology is now widely adopted as an efficient, standardized solution for IC testing and debugging.

[0005] In existing technology, multiplexing logic between independent test chips and biased through-silicon vias (TSVs) is used to switch paths during chip testing after stacking. The test data input (TDI) on the top chip is used to input test data to the corresponding layer before bonding. Test data is then transferred from the bottom chip to the top chip after bonding.

[0006] Each individual chip can embed various DFT (Design for Testability) logic, controlled by its own TAP (Test Access Port) controller and associated test data registers (TDRs). The solution's DFT architecture requires that all stacked chips be equipped with a JTAG interface (TDI (Test Data In), TDO (Test Data Out), TMS (Test Mode Select), TCK (Test Clock), and optional TRST (Test Reset)) as a test access mechanism to build a 3D DFT chain, and a TAP controller to build the IEEE 1687 circuit around it: segment insertion bits and associated TDRs.

[0007] Existing architectures introduce multiple data transmission ports per chip. To accommodate TDI data exchange and parallel transmission between chips, this leads to excessive port usage. Existing interconnect structures require the addition of multiplexers (MUXs) to select data paths. These MUXs can be configured using additional configuration registers as outlined in IEEE 1838 or optimized using automatic chip detection mechanisms, but are controlled by statically cascaded TAP serial chains.

[0008] by Figure 1 Taking the TMSMUX in the DIE1 chip as an example, the input signal TMS completes the control of the TAP state machine. The TAPcontroller also has control over the TMSMUX selection end. The transmission and control of interface protocol data and enable signals do not have an accurate priority order. For different test requirements (a specific chip, several chips or all chips), the selection and configuration of the multiplexing logic data path in the test phase is more restrictive and difficult to implement. Summary of the Invention

[0009] In response to the problems in the prior art, the embodiments of the present application provide an iJTAG test interconnect structure for 3DIC, which can solve the problem of how to build an efficient testability design circuit and IEEE 1687 interface protocol network structure in the 3DIC package to reduce test port consumption, chip area overhead and test configuration complexity, while improving the flexibility and efficiency of chip testing.

[0010] In a first aspect, the present application provides an iJTAG test interconnect structure for a 3DIC, comprising: a plurality of chip dies stacked vertically;

[0011] Each of the chip dies includes a test access port controller; the test access port controllers of each chip die are connected in series to form a test control path to coordinate test tasks of the multiple chip dies, wherein the test tasks include testing the multiple chip dies and testing a single chip die;

[0012] The bottom layer of the chip bare die is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip bare die to be tested for processing;

[0013] A TDOMUX module is provided in some of the chip dies, and a selection end of the TDOMUX module is controlled by a test access port controller of the chip dies to which it belongs, so as to control an output path of test data.

[0014] Furthermore, the test access port controller includes a state machine, and the state machine is used to switch the test mode according to an input control signal.

[0015] Furthermore, when the plurality of chip dies are tested, the test access port controller of each chip die is switched to INTEST mode through a state machine to control its corresponding embedded instrument.

[0016] Furthermore, when testing a single chip die, the test access port controller in the chip die below the chip die to be tested is switched to BYPASS mode through a state machine, so that test data is transferred to the chip die to be tested.

[0017] Furthermore, the chip die further comprises: segment insertion bytes and embedded instruments;

[0018] The segment insertion byte is used to control the access status of the embedded instrument during the test process.

[0019] Furthermore, the chip die further comprises: a test data register;

[0020] The test data register is arranged between the segment insertion byte and the embedded instrument, and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

[0021] Furthermore, each of the chip bare die further comprises: a local reset module;

[0022] The local reset module is used to perform a reset operation on the corresponding test data register before the test operation to clear the previously configured data state.

[0023] Furthermore, each of the chip dies further comprises: a local enabling module;

[0024] The local enable module is used to output an enable signal during the test process to control the corresponding test data register to perform data shifting and updating operations.

[0025] Furthermore, the test access port controller complies with the IEEE 1687 standard.

[0026] Furthermore, each core functional module in the chip die is correspondingly provided with an embedded instrument.

[0027] The present application provides an iJTAG test interconnect structure for 3DIC, comprising: a plurality of chip dies stacked vertically; each of the chip dies includes a test access port controller; the test access port controllers of each chip die form a test control path in a series manner to coordinate the test tasks of the plurality of chip dies, wherein the test tasks include testing the plurality of chip dies and testing a single chip die; the bottom layer of chip dies is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing; a TDOMUX module is provided in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs to control the output path of the test data. The present application realizes flexible access and test configuration of embedded instruments in multiple chips while significantly reducing the consumption of test ports and chip area resources, and efficiently completes the individual test of the target chip or the multi-chip joint test, thereby improving the flexibility and efficiency of the overall test.

[0028] Among them, vertical stacking is used to improve chip integration, shorten interconnection paths, reduce power consumption and latency, and at the same time improve the computing performance and compactness of the overall system; each chip die includes a test access port controller, segment insertion bytes, test data registers and embedded instruments, which can realize accurate testing and debugging of each chip functional module, and improve the flexibility and coverage of the test through embedded instruments. The programmable structure of segment insertion bytes and test data registers improves the configurability and module reusability of the network; the bottom chip die is configured with test data input ports and test data output ports, which can simplify the connection between external test equipment and 3DIC chip system, reduce the number of test ports, and reduce packaging complexity and manufacturing cost; the test access port controllers of each chip die form a test control path in series, which can avoid the traditional parallel The system reduces the area consumption and configuration complexity introduced by multiple input multiplexing logic (MUX) in the test access port (TAP) structure, improves the uniformity and controllability of test path configuration, and effectively supports multi-chip joint testing or selective chip testing; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing, which can improve the continuity and transmission efficiency of the test data flow, realize cross-chip test chain configuration and operation, and support flexible switching of the test range of the target chip; a TDOMUX module is set in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs, which can realize the isolation or bypass of the test data of a specific chip, and effectively improve the flexibility of test data path selection and the accuracy of test operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 It is a schematic diagram of the structure of a chip bare die in the prior art;

[0031] Figure 2 3DIC iJTAG test interconnect structure according to an embodiment of the present application;

[0032] Figure 3 3DIC iJTAG test interconnect structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clearly understood, the embodiments of the present application are further described in detail below with reference to the accompanying drawings. The illustrative embodiments of the present application and their descriptions are used to explain the present application but are not intended to limit the present application. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application may be combined with each other in any manner.

[0034] Three-dimensional integrated circuits (3DICs) are integrated circuit technologies that improve performance, reduce power consumption, and increase integration by vertically stacking die and using advanced packaging techniques such as through-silicon vias (TSVs). TSVs are an integrated circuit packaging technology that drills holes in silicon chips and fills them with conductive material to create vertical electrical connections within or between chips, thereby increasing integration, reducing power consumption, and latency. The Internal Joint Test Action Group (iJTAG) is an integrated circuit testing technology that complies with the IEEE 1687 standard and allows for flexible testing and debugging within the chip. It inserts a single-bit segment insertion bit (SIB) into the JTAG link, enabling flexible configuration of the test network and streamlining chip verification and testing. The SIB is a core component of iJTAG technology, allowing for arbitrary hierarchical structures within the iJTAG network by inserting a single-bit test data register (TDR), thus enabling flexible configuration of the iJTAG network. The Test Access Port Controller (TAPController) is the core component of the JTAG interface. It is a finite state machine responsible for controlling the sequence of JTAG test operations, including state transitions and data transfers.

[0035] Figure 2 FIG. 1 is a schematic diagram of the iJTAG test interconnect structure of a 3DIC provided in one embodiment of the present application. Figure 2 As shown, the iJTAG test interconnect structure of the 3DIC provided by the present application includes: a plurality of chip dies (Die) stacked vertically;

[0036] Each chip die includes a test access port controller (TAP Controller); the TAP controllers of each chip die are connected in series to form a test control path to coordinate test tasks of the multiple chip dies, wherein the test tasks include testing the multiple chip dies and testing a single chip die;

[0037] The bottom-level chip die is configured with a test data input port (TDI) and a test data output port (TDO); the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing;

[0038] A TDOMUX module is provided in some of the chip dies, and a selection end of the TDOMUX module is controlled by a test access port controller of the chip dies to which it belongs, so as to control an output path of test data.

[0039] Specifically, Figure 2 The bold black solid lines in the figure represent the iJTAG interconnect network paths, while the dashed lines represent the control relationships between different modules. These represent functional associations only, not actual circuit connections. To meet the testing requirements of different chips, the 1687 interface protocol IP is configured through a series of multi-TAP controllers.

[0040] To simplify external test interface wiring, the test data input (TDI) and test data output (TDO) ports are located on the bottom-level chip die, serving as unified entry and exit points for test data for the entire system. Test data is input through the TDI ports, and the TAP controller selectively enables, configures, or bypasses embedded instruments based on the control instructions or status configuration information contained in the data, enabling full-chip or single-chip targeted testing.

[0041] To support flexible data output path configuration, a TDOMUX module is set in the chips except the top chip die ( Figure 2 (represented by a ladder symbol in the figure). This module serves as the test data output multiplexing logic. Its selection end is controlled by the TAP controller of the chip to which it belongs. It determines whether the current test data is output from this chip or continues to be passed to the upper-layer chip. This structural design enables dynamic selection and responsive output of test data paths without interrupting the test link.

[0042] Through the above structure, multiple chip dies realize unified management of test control through serial test access paths. It can not only jointly test all chip dies, but also flexibly select specific chip dies for independent testing, with good scalability, reusability and resource efficiency.

[0043] In one embodiment, Figure 2 The SIB, TDR, and other modules (1687 IP) that comply with the IEEE 1687 interface protocol shown in the figure mainly represent their functional roles. In specific implementation, the appropriate 1687 IP structure will be selected for expansion based on the number of integrated functional modules.

[0044] In one embodiment, the test access port controller includes a state machine, and the state machine is configured to switch the test mode according to an input control signal.

[0045] Specifically, to support efficient management and state scheduling of iJTAG test links across multiple die, a state machine is implemented within each die's test access port controller. This state machine responds to control fields from TMS signals or test data, switching and managing test modes according to the IEEE 1687 standard. The state machine supports modes such as INTEST and BYPASS, enabling full-die testing or individual testing of target die.

[0046] In one embodiment, when the plurality of chip dies are tested, the test access port controller of each chip die is switched to INTEST mode through a state machine to control its corresponding embedded instrument.

[0047] Specifically, in a multi-die joint test scenario, the state machine of each die's test access port controller switches to INTEST mode, allowing test data to be applied to the embedded instruments within that chip. When the TAP is in INTEST mode, the segment insertion bytes and test data registers it controls are activated to write test parameters and sample data to the selected embedded instruments, achieving complete coverage testing of the entire chip system.

[0048] In one embodiment, when testing a single chip die, the test access port controller in the chip die below the chip die to be tested is switched to BYPASS mode through a state machine to enable test data to be transferred to the chip die to be tested.

[0049] Specifically, when performing directed testing on a target die, to avoid unnecessary mid-chip testing and improve link efficiency, the TAP controller state machine on the chip below the target chip is controlled to switch to BYPASS mode. In this mode, test data is transparently transmitted within the chip through a single 1-bit bypass register, bypassing the chip's TDR structure and passing it directly to the TDI interface of the upper-level chip. This approach effectively reduces the amount of data shifted, improves link response speed, and isolates the impact of test logic on the link from non-target chips.

[0050] In one embodiment, the chip die further comprises: a segment insertion byte and (SIB) embedded instrument;

[0051] The segment insertion byte is used to control the access status of the embedded instrument during the test process.

[0052] Specifically, to enhance the control and selectivity of embedded instruments, the Segment Insertion Byte (SIB) structure selectively enables target embedded instruments as needed during testing, controlling their access status. Through the SIB's control logic, the test chain can flexibly decide whether to activate a specific embedded instrument, thereby forming a tree-structured test network and improving the overall test structure's configurability and resource utilization.

[0053] In one embodiment, the chip die further comprises: a test data register (TDR);

[0054] The test data register is arranged between the segment insertion byte and the embedded instrument, and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

[0055] Specifically, the test data register (TDR), used in conjunction with the segment insertion byte, corresponds one-to-one with each embedded instrument. It configures test parameters and transmits data to the corresponding embedded instrument when it is enabled. The TDR structure supports serial shifting in and parallel loading of multi-bit data and exchanges signals with the target embedded instrument to perform tasks such as writing initialization parameters, collecting operating status, or outputting fault information. It is a key component for achieving highly controllable test interaction.

[0056] In one embodiment, the SIB and TDR maintain consistent configuration modes for different embedded instruments, and have good versatility and consistency.

[0057] In one embodiment, each of the chip dies further comprises: a local reset module (LR);

[0058] The local reset module is used to perform a reset operation on the corresponding test data register before the test operation to clear the previously configured data state.

[0059] In one embodiment, each of the chip dies further comprises: a local enabling block (NIB);

[0060] The local enable module is used to output an enable signal during the test process to control the corresponding test data register to perform data shifting and updating operations.

[0061] Specifically, if Figure 2As shown in the figure, the local reset module LR A is responsible for locally resetting the test data configured for TDR A. The local enable module NIB A is used to control the local enable signals of TDR B and TDR C, and works in conjunction with the global enable signal output by the TAP 0 controller to complete operations such as shifting, updating, and capturing the relevant TDRs.

[0062] In one embodiment, the test access port controller complies with the IEEE 1687 standard.

[0063] In one embodiment, each core functional module in the chip die is correspondingly provided with an embedded instrument.

[0064] Specifically, embedded instruments are used to monitor the operational status, perform structural testing, or verify the functionality of the chip's functional modules (such as the processing unit, storage interface, or other key modules). Each chip die contains at least one embedded instrument, and each core functional module (such as the NPU, DDR, etc.) within the die has an embedded instrument to enable module-level testing and debugging.

[0065] In one embodiment, if Figure 2 As shown in the figure, during the complete multi-chip test flow, test data is input from Die0's TDI terminal, and the TAP 0 controller operates in INTEST mode. In this mode, the embedded instrument A included in the test is selected using the enable segment insertion byte SIB A. The test data register TDR A is used to configure the test parameters of embedded instrument A.

[0066] After completing the configuration and testing of the embedded instrument, test data passes through NIB A and is then output by the TAP 0 controller to the TDIS interface of Die 0 and the first input port of the test data output multiplexing logic TDOMUX. Since this is a complete multi-chip test process, a control signal in the TDI test data stream must be set to 0 by the TAP 0 controller to control the TDOMUX select pin to ensure that the data does not originate from the TAP 0 controller, thus ensuring a continuous multi-chip test chain. The TAP 1 controller receives test data from Die 0 via Die 1's TDI port, aligning with Die 0. After its internal 1687 IP completes the configuration of the target embedded instrument, the data is transmitted to the subsequent die. During this process, the TDOMUX select pins of all chips are set to 0 by their corresponding TAP controllers, ensuring that the final test data is fully output at Die 0's TDO port, completing the traversal test of all chips.

[0067] In one embodiment, if Figure 3 As shown in the figure, compared to full multi-chip joint testing, testing Die1 individually requires not only setting Die1's TDOMUX select pin but also enabling BYPASS mode on its predecessor, Die0. This process uses the TMS port to control the TAP controller's state machine to switch modes. When the TAP controller operates in BYPASS mode, a single 1-bit bypass register is inserted between TDI and TDO, allowing shift operations to be performed solely through this register rather than through the entire boundary-scan register (BSR). This approach effectively isolates Die0, improving Die1 testing efficiency.

[0068] It's important to note that the bypass register is implemented internally by the TAP controller. In this test flow, after TDI test data enters Die0, it is directly transmitted to the TDI port of Die1 via the bypass register. After Die1 completes embedded instrument configuration and test operations, its TAP controller sets the TDOMUX select pin to 1, allowing the test response data to be output directly to the system's TDO port.

[0069] The BYPASS operation of the front chip (such as Die0) is implemented through its TAP controller, while the data bypass of the back chip is completed through the TDOMUX control of the chip under test (such as Die1). This test structure supports flexible configuration and can efficiently implement targeted test operations on any target chip.

[0070] Targeting 3DIC packaging technology, this application utilizes a serial multi-TAP controller structure to configure the IEEE 1687 interface protocol network comprised of multiple chips. Analysis of the design for testability process indicates that the time required to configure TDI data in a serial multi-TAP structure is minimal compared to the time required for a complete scan test (load / unload). Therefore, in this application, TDI and TDO ports are only implemented on the bottom-level chip, and unified TDI data configuration is accomplished via serial input, effectively reducing port resource usage.

[0071] In addition, this application only introduces the TDOMUX module, replacing the multiple interface protocol MUXs configured for each chip in the traditional structure (such as test data input multiplexing logic TDIMUX, test clock signal multiplexing logic TCKMUX, test reset signal multiplexing logic TRSTnMUX, and test mode selection signal multiplexing logic TMSMUX). In conjunction with the state machine control of the TAP controller inside each chip, this application significantly reduces area overhead and configuration complexity while ensuring test flexibility. During the test process, the input test data of any chip can directly act on its TAP controller. The state machine of the multi-TAP controller selects test operations or bypasses for different logic modules, thereby realizing individual testing of the target chip or joint testing of multiple chips.

[0072] The present application provides an iJTAG test interconnect structure for 3DIC, comprising: a plurality of chip dies stacked vertically; each of the chip dies includes a test access port controller; the test access port controllers of each chip die form a test control path in a series manner to coordinate the test tasks of the plurality of chip dies, wherein the test tasks include testing the plurality of chip dies and testing a single chip die; the bottom layer of chip dies is configured with a test data input port and a test data output port; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing; a TDOMUX module is provided in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs to control the output path of the test data. The present application realizes flexible access and test configuration of embedded instruments in multiple chips while significantly reducing the consumption of test ports and chip area resources, and efficiently completes the individual test of the target chip or the multi-chip joint test, thereby improving the flexibility and efficiency of the overall test.

[0073] Among them, vertical stacking is used to improve chip integration, shorten interconnection paths, reduce power consumption and latency, and at the same time improve the computing performance and compactness of the overall system; each chip die includes a test access port controller, segment insertion bytes, test data registers and embedded instruments, which can realize accurate testing and debugging of each chip functional module, and improve the flexibility and coverage of the test through embedded instruments. The programmable structure of segment insertion bytes and test data registers improves the configurability and module reusability of the network; the bottom chip die is configured with test data input ports and test data output ports, which can simplify the connection between external test equipment and 3DIC chip system, reduce the number of test ports, and reduce packaging complexity and manufacturing cost; the test access port controllers of each chip die form a test control path in series, which can avoid the traditional parallel The system reduces the area consumption and configuration complexity introduced by multiple input multiplexing logic (MUX) in the test access port (TAP) structure, improves the uniformity and controllability of test path configuration, and effectively supports multi-chip joint testing or selective chip testing; the test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing, which can improve the continuity and transmission efficiency of the test data flow, realize cross-chip test chain configuration and operation, and support flexible switching of the test range of the target chip; a TDOMUX module is set in some of the chip dies, and the selection end of the TDOMUX module is controlled by the test access port controller of the chip die to which it belongs, which can realize the isolation or bypass of the test data of a specific chip, and effectively improve the flexibility of test data path selection and the accuracy of test operation.

[0074] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more.

[0075] The descriptions with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. The order of steps involved in each embodiment is used to schematically illustrate the implementation of the present application, and the order of steps therein is not limited and can be appropriately adjusted as needed.

[0076] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0077] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An iJTAG test interconnect structure for 3DIC, characterized in that: include: Multiple chip dies stacked vertically; Each of the chip dies includes a test access port controller; the test access port controllers of each chip die are connected in series to form a test control path to coordinate test tasks of the multiple chip dies, wherein the test tasks include testing the multiple chip dies and testing a single chip die; The bottom-level chip die is configured with a test data input port and a test data output port; The test data input port receives test data and transmits the test data to the test access port controller of the chip die to be tested for processing; A TDOMUX module is provided in some of the chip dies, and a selection end of the TDOMUX module is controlled by a test access port controller of the chip dies to which it belongs, so as to control an output path of test data; The test access port controller includes a state machine, and the state machine is used to switch the test mode according to the input control signal; When testing the plurality of chip dies, the test access port controller of each chip die switches to INTEST mode through a state machine to control its corresponding embedded instrument; When testing a single chip die, the test access port controller in the chip die below the chip die to be tested is switched to the BYPASS mode through a state machine, so that test data is transferred to the chip die to be tested.

2. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The chip die further includes: segment insertion bytes and embedded instruments; The segment insertion byte is used to control the access status of the embedded instrument during the test process.

3. The iJTAG test interconnect structure of 3DIC according to claim 2, characterized in that: The chip die further includes: a test data register; The test data register is arranged between the segment insertion byte and the embedded instrument, and corresponds to the embedded instrument one by one, and is used to configure the test parameters of the corresponding embedded instrument and transmit test data when the corresponding embedded instrument is enabled.

4. The iJTAG test interconnect structure of 3DIC according to claim 1, characterized in that: The chip die further includes: a local reset module; The local reset module is used to perform a reset operation on the corresponding test data register before the test operation to clear the previously configured data state.

5. The iJTAG test interconnect structure of 3DIC according to claim 1, wherein: Each of the chip dies further comprises: a local enabling module; The local enable module is used to output an enable signal during the test process to control the corresponding test data register to perform data shifting and updating operations.

6. The iJTAG test interconnect structure of 3DIC according to claim 1, wherein: The test access port controller complies with the IEEE 1687 standard.

7. The iJTAG test interconnect structure of 3DIC according to claim 3, characterized in that: Each core functional module in the chip die is correspondingly provided with an embedded instrument.

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