Hybrid Orthogonal Receiving Array
By using multiple real receiver channels in phased array receivers and combining phase offsets, the problems of low performance and high cost in the prior art are solved, and the effect of similar performance to all IQ receivers but close to that of real phased array receivers is achieved.
Patent Information
- Application Number
- CN202411736896.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-11-29
- Publication Date
- 2025-05-30
AI Technical Summary
Existing phased array receivers have lower performance in distinguishing positive and negative frequencies, and the full IQ receiver topology is costly and consumes more area and current.
The performance similar to that of all IQ receivers is achieved by using multiple real receiver channels in phased array receivers and distinguishing positive and negative frequencies through appropriate phase offset and combination techniques, but with a cost close to that of real phased array receivers.
Reduces the cost of phased array receivers, improves performance for small arrival directions for interference sources, and is the same as all IQ receivers in terms of zero arrival directions for interference sources.
Smart Images

Figure CN120065130A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to receivers for radar applications. Background Art
[0002] Generally, a phased array receiver includes a plurality of receiver circuits coupled to a plurality of antennas. Each receiver circuit provides information about the angle of arrival of a signal relative to the antenna elements. Generally, each individual receiver circuit is coupled to an antenna in a phased array of the same antenna and is implemented using a real receiver topology or a full IQ receiver topology. The real receiver topology is relatively low cost, but compared to the full IQ receiver topology, the performance is reduced because the real receiver cannot distinguish between positive and negative frequencies. The full IQ receiver allows for the distinction between positive and negative frequencies, enabling more functions and higher performance than the real receiver topology. However, the full IQ receiver topology is more costly than the real receiver topology because the full IQ receiver topology includes additional circuitry (e.g., additional mixers, additional filters, additional analog-to-digital converters, phase shift circuits, etc.). Therefore, the full IQ receiver consumes more area and more current than the real receiver. Accordingly, improved techniques for receiving wireless signals using a phased array receiver are desired. Summary of the Invention
[0003] In an embodiment, a method for receiving a radio frequency signal using a phased array receiver includes generating a first digital receive signal based on a first signal received from a first antenna and a local clock signal. The method includes generating a second digital receive signal based on a second signal received from a second antenna and the local clock signal. The method includes combining the first digital receive signal and the second digital receive signal to generate a first complex receive signal. The second antenna is spaced apart from the first antenna by a predetermined distance.
[0004] In an embodiment of the method, the first antenna and the second antenna are configured for a small angle of arrival of the received signal.
[0005] In an embodiment of the method, the predetermined distance is λ / 2, where λ = c / f, c is the speed of light, and f is a predetermined frequency of the carrier signal.
[0006] In an embodiment, the method further includes delaying the first signal received from the first antenna to generate a delayed signal. The delayed signal is ninety degrees out of phase with the first signal received from the first antenna. The first digital receive signal is generated using the delayed signal.
[0007] In an embodiment, the method further includes generating a first clock signal based on the local clock signal. In an embodiment, the method further includes generating a second clock signal based on the local clock signal. In an embodiment of the method, the second clock signal is out of phase with the first clock signal by ninety degrees. In an embodiment of the method, the first clock signal is used to generate the first digital received signal, and the second clock signal is used to generate the second digital received signal.
[0008] In an embodiment, the method further includes generating a third digital received signal based on a third signal received from a third antenna and the local clock signal. In an embodiment, the method further includes generating a fourth digital received signal based on a fourth signal received from a fourth antenna and the local clock signal. In an embodiment, the method further includes combining the third digital received signal and the fourth digital received signal to generate a second complex received signal. In an embodiment, the third antenna is spaced apart from the second antenna by the predetermined distance, and the fourth antenna is spaced apart from the third antenna by the predetermined distance.
[0009] In an embodiment, the method further includes delaying a first signal received from the first antenna to generate a delayed signal. The delayed signal is out of phase with the first signal received from the first antenna by ninety degrees. In an embodiment, the method further includes delaying a fourth signal received from the fourth antenna to generate a second delayed signal. The second delayed signal is out of phase with the fourth signal received from the fourth antenna by ninety degrees. In an embodiment, the first digital received signal is generated using the delayed signal and the local clock signal, and the fourth digital received signal is generated using the second delayed signal and the local clock signal.
[0010] In an embodiment, the method further includes generating a first clock signal based on the local clock signal. In an embodiment, the method further includes generating a second clock signal based on the local clock signal. In an embodiment, the method further includes generating a third clock signal based on the local clock signal, and generating a fourth clock signal based on the local clock signal. In an embodiment, the second clock signal and the third clock signal are out of phase with the first clock signal and the fourth clock signal by ninety degrees.
[0011] In an embodiment of the method, the first antenna, the second antenna, the third antenna, and the fourth antenna are configured for small angles of arrival of received signals. In an embodiment, the predetermined distance is λ / 2, where λ = c / f, c is the speed of light, and f is a predetermined frequency of the carrier signal.
[0012] In an embodiment, a phased array receiver includes a first receiver path configured to generate a first digital receive signal based on a first signal received from a first antenna and a local clock signal. The phased array receiver includes a second receiver path configured to generate a second digital receive signal based on a second signal received from a second antenna and the local clock signal. The phased array receiver includes circuitry configured to combine the first digital receive signal and the second digital receive signal to generate a first complex receive signal. The second antenna is spaced apart from the first antenna by a predetermined distance.
[0013] In an embodiment, the phased array receiver further includes the first antenna and the second antenna. In an embodiment of the phased array receiver, the first antenna and the second antenna are configured for a small angle of arrival of received signals.
[0014] In an embodiment of the phased array receiver, the predetermined distance is λ / 2, where λ = c / f, c is the speed of light, and f is a predetermined frequency of a carrier signal.
[0015] In an embodiment of the phased array receiver, the first receiver path includes a delay element coupled between the first antenna and the circuitry.
[0016] In an embodiment of the phased array receiver, the predetermined distance is λ / 2, where λ = c / f, c is the speed of light, f is a predetermined frequency of a carrier signal, and the delay element is a conductive trace on a printed circuit board having a length of λ / 4.
[0017] In an embodiment, the phased array receiver further includes a second circuit configured to provide a first clock signal based on the local clock signal and configured to provide a second clock signal based on the local clock signal. The second clock signal is out of phase with the first clock signal by ninety degrees. In an embodiment of the phased array receiver, the first receiver path includes a first mixer circuit responsive to the first clock signal, and the second receiver path includes a second mixer circuit responsive to the second clock signal.
[0018] In an embodiment, the phased array receiver further includes a third receiver path configured to generate a third digital received signal based on a third signal received from a third antenna and the local clock signal. In an embodiment, the phased array receiver further includes a fourth receiver path configured to generate a fourth digital received signal based on a fourth signal received from a fourth antenna and the local clock signal. In an embodiment of the phased array receiver, the circuit is further configured to combine the third digital received signal and the fourth digital received signal to generate a second complex received signal. In an embodiment of the phased array receiver, the third antenna is spaced from the second antenna by the predetermined distance, and the fourth antenna is spaced from the third antenna by the predetermined distance.
[0019] In an embodiment of the phased array receiver, the first receiver path includes a delay element coupled between the first antenna and the circuit. In an embodiment of the phased array receiver, the fourth receiver path includes a second delay element coupled between the fourth antenna and the circuit.
[0020] In an embodiment, the phased array receiver further includes a second circuit configured to provide a first clock signal based on the local clock signal and configured to provide a second clock signal based on the local clock signal. The second clock signal is out of phase with the first clock signal by ninety degrees. In an embodiment, the phased array receiver further includes a third circuit configured to provide a third clock signal based on the local clock signal and configured to provide a fourth clock signal based on the local clock signal. The fourth clock signal is out of phase with the third clock signal by ninety degrees. In an embodiment of the phased array receiver, the first receiver path includes a first mixer circuit responsive to the first clock signal, the second receiver path includes a second mixer circuit responsive to the second clock signal, the third receiver path includes a third mixer circuit responsive to the third clock signal, and the fourth receiver path includes a fourth mixer circuit responsive to the fourth clock signal.
[0021] In an embodiment, the phased array receiver further includes the first antenna, the second antenna, the third antenna, and the fourth antenna. In an embodiment of the phased array receiver, the first antenna and the second antenna are configured for small angles of arrival of received signals. In an embodiment of the phased array receiver, the predetermined distance is λ / 2, where λ = c / f, c is the speed of light, and f is a predetermined frequency of the carrier signal.
[0022] In an embodiment, a device includes:
[0023] A component for generating a first digital receive signal based on a first signal received from a first antenna and a local clock signal;
[0024] A component for generating a second digital receive signal based on a second signal received from a second antenna and the local clock signal; and
[0025] A component for combining the first digital receive signal and the second digital receive signal to generate a first complex receive signal,
[0026] wherein the second antenna is spaced apart from the first antenna by a predetermined distance.
[0027] Thus, the hybrid beamforming technique reduces the cost of the phased array receiver. Compared with the real phased array receiver, the hybrid phased array receiver topology has improved performance for small arrival directions of interference sources and the same performance as the full IQ phased array receiver for a zero-degree arrival direction of interference sources. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The present invention is illustrated by way of example and is not limited by the drawings, in which like reference numerals indicate like elements. For simplicity and clarity, the elements in the figures are shown, and these elements are not necessarily drawn to scale.
[0029] Figure 1 A functional block diagram showing a conventional IQ phased array receiver having two antennas.
[0030] Figure 2 A functional block diagram showing a conventional real receiver having two antennas.
[0031] Figure 3 A functional block diagram showing a hybrid IQ phased array receiver according to at least one embodiment of the present invention.
[0032] Figure 4 A functional block diagram showing an alternative embodiment of a hybrid IQ phased array receiver according to at least one embodiment of the present invention.
[0033] Figure 5 For use Figure 1 Amplitude waveforms varying with the arrival direction are shown for the positive and negative frequencies of the signal received by the receiver.
[0034] Figure 6 Amplitude waveforms varying with the arrival direction are shown for the positive and negative frequencies of the signal received by using a hybrid IQ phased array receiver according to at least one embodiment of the present invention.
[0035] Figure 7Waveforms of signal-to-interference ratio (SIR) versus frequency are shown for a conventional IQ phased array receiver, a real receiver, and a hybrid IQ phased array receiver.
[0036] Figure 8 Waveforms of signal-to-interference-plus-noise ratio (SINR) versus the direction of arrival at the antenna array of a target signal are shown for a conventional IQ phased array receiver, a real phased array receiver, a hybrid IQ phased array receiver, and a full IQ single antenna receiver in the presence of an interference source fixed at zero degrees.
[0037] Figure 9 Waveforms of signal-to-interference-plus-noise ratio (SINR) versus the direction of arrival at the antenna array of an interference source are shown for a conventional IQ phased array receiver, a real phased array receiver, a hybrid IQ phased array receiver, and a full IQ single antenna receiver in the presence of a target signal fixed at zero degrees.
[0038] Like or identical items are designated by like reference numerals in the different figures. DETAILED DESCRIPTION
[0039] A hybrid phased array receiver includes N real receiver channels coupled to N corresponding antennas. Each of the N real receiver channels of the hybrid phased array receiver has a phase offset from another corresponding real receiver channel of the hybrid phased array receiver. By appropriately combining the received signals, positive and negative frequencies can be distinguished, thereby providing advantages similar to those of a phased array of N full IQ receiver channels, but at a cost approximately the same as that of N real receiver channels, which is less than the cost of N full IQ receiver channels. The hybrid phased array receiver has a higher signal-to-interference ratio against broadband interference compared to a real phased array receiver whose cost is lower than that of a full IQ phased array receiver that provides a complex received signal for each full IQ receiver channel.
[0040] REFERENCE Figure 1, the full IQ phased array receiver 100 includes two full IQ receiver channels (i.e., N = 2) in a beamforming receiver. Antenna 106 and antenna 108 are respectively coupled to full IQ receiver channel 102 and full IQ receiver channel 104. Generally, beamforming antennas are spaced apart by a distance that provides a useful constructive and destructive interference pattern (e.g., λ / 2) that reduces or minimizes the mutual coupling of the antennas. A larger spacing can produce higher grating lobes (i.e., unwanted beams). Antenna 106 is spaced λ / 2 from antenna 108 (where λ is the wavelength of the radio frequency carrier signal), which is consistent with conventional beamforming techniques for estimating the direction of arrival of one or more signals received by the full IQ phased array receiver 100 at the antenna array. In an embodiment of the full IQ phased array receiver 100, full IQ receiver channel 102 and full IQ receiver channel 104 are included in integrated circuit 101. Each full IQ receiver channel n (where 0 ≤ n ≤ N - 1) includes a low noise amplifier coupled to the corresponding antenna, an IQ clock generator configured to generate quadrature clock signals, and provides in-phase received digital signal I to digital signal processor 122 n and quadrature received digital signal Q n of the quadrature receiver path. For example, full IQ receiver channel 102 includes quadrature clock generator 118, which generates two clock signals that are 90 degrees out of phase with each other based on local oscillator signal LO. Quadrature clock generator 118 provides one of these clock signals (e.g., the 0° clock signal) to mixer 110 for reducing the received signal frequency to an intermediate frequency or baseband frequency to generate in-phase received digital signal I 0 . Quadrature clock generator 118 provides the other clock signal (e.g., the 90° clock signal) to mixer 112 for reducing the received signal frequency to an intermediate frequency or baseband frequency to generate quadrature received digital signal Q 0 . Similarly, full IQ receiver channel 104 includes quadrature clock generator 120, which generates two clock signals that are 90 degrees out of phase with each other based on local oscillator signal LO. Quadrature clock generator 120 provides one of these clock signals (e.g., the 90° clock signal) to mixer 114 for generating quadrature received digital signal Q 1 , and provides the other clock signal (e.g., the 0° clock signal) to mixer 116 for generating in-phase received digital signal I 1 .
[0041] Full IQ receiver channel 102 provides in-phase received digital signal I to digital signal processor 122 0 and quadrature received digital signal Q 0and the full IQ receiver channel 104 provides the in-phase received digital signal I to the digital signal processor 122 1 and the quadrature received digital signal Q 1 . The digital signal processor 122 combines the in-phase component and the quadrature component of each receiver channel to generate a complex received digital signal (e.g., I 0 +jQ 0 and I 1 +jQ 1 ), and the complex received digital signal can be further processed according to conventional beamforming techniques. The two full IQ receiver channels of the full IQ phased array receiver 100 consume a large area of the integrated circuit 101 and consume a large amount of current during operation.
[0042] In an alternative phased array receiver topology of a beamforming receiver, the phased array receiver topology includes N real receiver channels, and the N real receiver channels generate only real signals for each channel and antenna, that is, each channel and antenna uses only one phase of the local oscillator clock signal and one antenna, rather than generating an in-phase received digital signal and a quadrature digital signal for each receiver channel and antenna. Referring Figure 2 , the real phased array receiver 200 includes two antennas (i.e., N = 2) and two real receiver channels in the beamforming receiver. Antenna 206 and antenna 208 are respectively coupled to real receiver channel 202 and real receiver channel 204. Antenna 206 is spaced λ / 2 from antenna 208, which is consistent with the conventional beamforming technique for estimating the direction of arrival of the signal received by the real receiver array 200 at the phased array of antennas. In an embodiment, the real receiver channel 202 and the real receiver channel 204 are included in the integrated circuit 201. Each real receiver channel n includes a low-noise amplifier coupled to the corresponding antenna and a corresponding receiver path that provides the real received digital signal I n to the digital signal processor 222.
[0043] For example, the real receiver channel 202 and the real receiver channel 204 each include a low-noise amplifier, a frequency mixer for converting the corresponding RF signal into an intermediate frequency signal using a local oscillator signal, an intermediate frequency filtering and gain stage, and an analog-to-digital converter for respectively providing the output digital real received signal I 0 and the output digital real received signal I 1 . The digital signal processor 122 combines the real signals provided by each channel according to the conventional beamforming technique to generate a received digital signal (e.g., I 0 +I 1)。Compared with the full IQ receiver topology, the real topology significantly reduces the integrated circuit area and significantly reduces the current consumed by the phased array receiver during operation. However, the signals generated by the real topology cannot distinguish between positive and negative frequencies. Therefore, the real topology reduces the SNR of the phased array receiver system by approximately 6 dB, thus significantly degrading the system performance.
[0044] A hybrid phased array receiver in a beamforming receiver system includes N real receiver channels coupled to N corresponding antennas. Each of the N real receiver channels has a phase offset from another corresponding real receiver channel among the N receiver channels. The digital received signals generated by the N real receiver channels are combined to generate N / 2 complex received signals. The hybrid phased array receiver reduces power consumption during operation and consumes less integrated circuit area compared to the full IQ phased array receiver topology described above, and has improved performance compared to the real phased array receiver topology described above. Each antenna of the hybrid phased array receiver 300 is coupled to a real receiver channel, and the real receiver channel includes a low noise amplifier, a frequency mixer for converting an RF signal into an intermediate frequency signal, an intermediate frequency filtering and gain stage, and an analog-to-digital converter for providing an output digital signal, which is the in-phase received digital signal I n or the quadrature received digital signal Q n+1 , where n is the antenna index and 0 ≤ n ≤ N - 1. Each hybrid receiver channel includes two antennas coupled to a corresponding real receiver path, and the real receiver path generates the in-phase received digital signal I n and the quadrature received digital signal Q n+1 . The corresponding real receiver path provides a 90-degree phase shift between the in-phase received digital signal I n and the quadrature received digital signal Q n+1 .
[0045] Refer to Figure 3 , the hybrid phased array receiver 300 in the beamforming receiver includes two hybrid receiver channels formed by four real receiver channels (i.e., N = 4) coupled to four corresponding antennas. Antenna 306 and antenna 308 are coupled to hybrid receiver channel 302. Antenna 310 and antenna 312 are coupled to hybrid receiver channel 304. Antenna 306 is spaced λ / 2 from antenna 308, and antenna 308 is spaced λ / 2 from antenna 310. Antenna 310 is spaced λ / 2 from antenna 312. In an embodiment, the hybrid receiver channel 302 and the hybrid receiver channel 304 are included in the integrated circuit 301.
[0046] In an embodiment, the hybrid receiver channel 302 includes an orthogonal clock generator 326 that generates two clock signals that are 90 degrees out of phase with each other based on a local oscillator signal LO. The orthogonal clock generator 326 provides one of these clock signals (e.g., the 0° clock signal) to the mixer 318 for generating an in-phase received signal I 0 , and provides another clock signal (e.g., the 90° clock signal) to the mixer 320 for generating a quadrature received digital signal Q 1 . Similarly, the hybrid receiver channel 304 includes an orthogonal clock generator 328 that generates two clock signals that are 90 degrees out of phase with each other based on a local oscillator signal LO. The orthogonal clock generator 328 provides one of these clock signals (e.g., the 90° clock signal) to the mixer 322 for generating a quadrature received digital signal Q 3 , and provides another clock signal (e.g., the 0° clock signal) to the mixer 324 for generating an in-phase received digital signal I 3 .
[0047] The hybrid receiver channel 302 provides an in-phase received digital signal I corresponding to the real receiver channel coupled to the antenna 306 to the digital signal processor 330 0 and a quadrature received digital signal Q corresponding to the real receiver channel coupled to the antenna 308 1 . The hybrid receiver channel 304 provides a quadrature received digital signal Q corresponding to the real receiver channel coupled to the antenna 310 to the digital signal processor 330 2 and an in-phase received digital signal I corresponding to the real receiver channel coupled to the antenna 312 3 . The digital signal processor 330 combines the in-phase received digital signal and the quadrature received digital signal provided by each hybrid channel to generate a complex received signal (e.g., I 0 +jQ 1 and I 3 +jQ 2 ), and the complex received signal can be further processed according to conventional beamforming techniques. Although two hybrid receiver channels including four real receiver channels and four corresponding antennas are shown, other numbers N / 2 of hybrid receiver channels corresponding to N real receiver channels and N antennas can be used to generate N / 2 received complex digital signals.
[0048] In another embodiment of the hybrid phased array receiver, instead of using an orthogonal clock generator to generate the phase shift for the alternating receiver paths, the phase shift is generated by delaying the received signal between the antenna and the mixer of one of the pair of real receiver paths. In at least one embodiment, an integrated circuit delay element (e.g., a conductive trace of length λ / 4 for antennas spaced λ / 2 apart) is used to implement the delay. In at least one embodiment, a delay element formed on a printed circuit board (e.g., a conductive trace of length λ / 4 for antennas spaced λ / 2 apart) is used to implement the delay. In at least one embodiment, the delay is implemented in the antenna (e.g., increasing the length of the antenna in the antenna pair coupled to the hybrid receiver path by λ / 4).
[0049] Reference Figure 4 , the hybrid phase array receiver 400 includes, in a beamforming receiver, four (i.e., N = 4) real receiver channels coupled to four corresponding antennas and configured as two (i.e., N / 2 = 2) hybrid receiver channels. Antenna 406 and antenna 408 are coupled to the corresponding real receiver channels of hybrid receiver channel 402. Antenna 410 and antenna 412 are coupled to the corresponding real receiver channels of hybrid receiver channel 404. Antenna 406 is spaced λ / 2 from antenna 408, and said antenna 408 is spaced λ / 2 from antenna 410. Antenna 410 is spaced λ / 2 from antenna 412. In an embodiment, hybrid receiver channel 402 and hybrid receiver channel 404 are included in integrated circuit 401. Each antenna is coupled to a real receiver channel, which includes a low-noise amplifier, a frequency mixer for converting the RF signal to an intermediate frequency signal, an intermediate frequency filtering and gain stage, and an analog-to-digital converter for providing the in-phase received digital signal I n or the quadrature received digital signal Q n+1 , where n is the antenna index and 0 ≤ n ≤ N - 1.
[0050] Each hybrid receiver channel includes two antennas coupled to the corresponding real receiver paths, which generate an in-phase received signal or a quadrature received signal. The receiver path coupled to antenna 406 and the receiver path coupled to antenna 412 include delay elements 414 and 416, respectively. Hybrid receiver channel 402 provides the in-phase received digital signal I 0 and the quadrature received digital signal Q 1 to digital signal processor 426, and hybrid receiver channel 404 provides the in-phase received digital signal I 3 and the quadrature received digital signal Q 2 . Digital signal processor 426 combines the in-phase and quadrature received digital signals generated by each hybrid receiver channel to generate the corresponding complex received signal (e.g., I0 +jQ 1 and I 3 +jQ 2 ), and the complex received signal can be further processed according to conventional beamforming techniques.
[0051] In at least one embodiment of a beamforming communication system, the predetermined frequency of the RF carrier signal is 80 GHz, and for antennas spaced λ / 2 apart, λ / 4 is approximately 1 mm. Generally, it is less expensive to implement the delay using conductive traces on a printed circuit board than on an integrated circuit. A conventional printed circuit board physical design includes several centimeters of conductive traces coupled to corresponding antennas. Thus, including an additional millimeter of conductive material on the printed circuit board to implement the phase delay of a hybrid phased array receiver topology will not substantially affect the cost of the printed circuit board. In contrast, integrated circuit dies are typically measured in millimeters, so an additional millimeter of conductive material consumes a large amount of the area of the integrated circuit die.
[0052] Reference Figure 1 and 5 , in an embodiment of a full IQ phased array receiver 100 including two antennas spaced λ / 2 apart, the gain (AMP) is the sum of the amplitude of the signal received by the first antenna (i.e., A1) and the amplitude of the signal received by the second antenna (i.e., A2):
[0053]
[0054] where φ A = πsin(θ) is the phase related to the angle of arrival, and φ IF = 2πft is the beat frequency phase. Thus, the gain of the full IQ phased array receiver 100 is as follows:
[0055]
[0056] Reference Figure 3 and 6 , an embodiment of a hybrid phased array receiver (e.g., hybrid receiver channel 302) including two antennas spaced λ / 2 apart has the following gain:
[0057]
[0058] Beamforming is the result of combining the in-phase received digital signal I and the quadrature received digital signal Q. The suppression of negative frequencies depends on the direction of arrival of the received signal at the antenna array. The positive frequency sideband gain of a hybrid phased array receiver with N antennas is the same as that of a full IQ phased array receiver with N antennas. When the direction of arrival is zero degrees (i.e., θ = 0), the amplitude of the positive frequency sideband of the received signal reaches a peak. However, the negative frequency sideband gain of the hybrid phased array receiver is different from that of the full IQ phased array receiver. In the negative frequency sideband, for a zero-degree direction of arrival, the hybrid phased array receiver completely suppresses the negative frequencies of the received signal. However, as the absolute value of the direction of arrival of the received signal increases from zero, the suppression of negative frequencies decreases. Generally, the beamforming of the hybrid phased array receiver is beneficial for small directions of arrival of interference signals. For example, for a λ / 2 antenna spacing, |DOA| < 30 degrees.
[0059] In typical radar applications (e.g., frequency-modulated continuous-wave radar), interference sources often appear as broadband baseband chirps. Such interference sources increase the background noise of the received signal. Figure 7 Shows a portion of the frequency response (waveform 702) of a dual-antenna full IQ phased array receiver, the response (waveform 704) of a dual-antenna real phased array receiver, and the response (waveform 706) of a dual-antenna hybrid phased array receiver for a broadband baseband chirp interference source. The SIR is normalized to the value of a single antenna, the direction of arrival of the target signal is 15 degrees, and the direction of arrival of the interference source is zero degrees. The real receiver signal spectrum is comb-shaped. The quadrature signal component will also have a comb-shaped spectrum, but the peaks and zeros are swapped compared to the in-phase component (i.e., the quadrature signal component will have frequency orthogonal ripples compared to the in-phase signal component). Therefore, the full IQ interference source (see waveform 702) has a flat spectrum, which is the sum of the in-phase received digital signal spectrum (see waveform 704) and the quadrature received digital signal spectrum. The in-phase received digital signal spectrum and the quadrature received digital signal spectrum each have a comb-shaped spectrum, which makes the complex signal I + jQ have the same spectral peak envelope as the single-phase received digital signal spectrum and the quadrature received digital signal spectrum (e.g., -74.8 dBV 2 / Hz).
[0060] The SNR of the dual-antenna hybrid phased array receiver and the dual-antenna full IQ phased array receiver at the beat signal frequency (e.g., -5 MHz) is approximately 50.4 dB, and it attenuates by approximately 6 dB in the dual-antenna real phased array receiver. The dual-antenna full IQ phased array receiver completely suppresses the sideband signal image at 5 MHz. The dual-antenna real phased array receiver attenuates the image by 6 dB at 5 MHz, and the dual-antenna hybrid beamformer system further suppresses the image by another 3 dB, for example. The dual-antenna full IQ phased array receiver response (i.e., I 0+jQ 0 +I 1 +jQ 1 ) and the dual - antenna hybrid beamformer (i.e., I 0 +jQ 1 ) has a beamforming signal response that is approximately 6 dB higher than the response of the dual - antenna real - phase - controlled array receiver (i.e., I 0 +I 1 ). Additionally, for these four configurations of the interfering source at an arrival direction of approximately zero degrees, the peak envelope of the interfering source is the same. Thus, both the dual - antenna full - IQ phase - controlled array receiver configuration and the dual - antenna hybrid phase - controlled array receiver configuration benefit from a maximum 6 dB SNR advantage.
[0061] Figure 8 and 9 The SINR ( Figure 8 , where the interfering source is at zero degrees and the target signal is swept in the arrival direction) and the SINR ( Figure 9 , where the target signal is fixed at zero degrees and the interfering source is swept in the arrival direction) are shown as a function of the arrival direction of the target signal for a dual - antenna full - IQ phase - controlled array receiver, a dual - antenna real - phase - controlled array receiver, a dual - antenna hybrid phase - controlled array receiver, and a single - antenna full - IQ receiver channel using antenna elements with a half - power beamwidth of + / - 35°. Assuming that the thermal noise is constant, the SINR is defined by the power received from one or more antennas. Compared to the waveform 802 corresponding to the single - antenna full - IQ receiver channel, beamforming causes the energy to be concentrated in the coherent combination around zero degrees corresponding to the waveform 806 of the dual - antenna real - phase - controlled array receiver and the waveforms 804 of the dual - antenna full - IQ phase - controlled array receiver or the dual - antenna hybrid phase - controlled array receiver.
[0062] When sweeping the direction of arrival of the target signal, compared to a single-antenna full-IQ receiver configuration, the phased array receiver configuration has an array factor power loss. The dual-antenna hybrid phased array receiver configuration and the dual-antenna full-IQ phased array receiver configuration have an SNR that is 6 dB greater than that of the dual-antenna real phased array receiver configuration. When sweeping the direction of arrival of the interfering source, the dual-antenna full-IQ phased array receiver configuration (waveform 902) maintains a 6 dB SNR advantage compared to the dual-antenna real phased array receiver configuration (waveform 904), while for the direction of arrival of interfering sources with an absolute value less than thirty degrees (i.e., |DOA| < 30°), the dual-antenna hybrid phased array receiver configuration (waveform 908) is a compromise between the dual-antenna real phased array receiver configuration (waveform 904) and the single-antenna full-IQ phased array receiver configuration (waveform 906). When the absolute value of the direction of arrival of the interfering source exceeds thirty degrees (i.e., |DOA| > 30°), the performance improvement of the dual-antenna hybrid phased array receiver configuration is less compared to the dual-antenna real phased array receiver configuration. Refer to Figure 7 , 8 and the relationships described in 9 are specific to antennas spaced λ / 2 apart, where the inter-element phase delay At the direction of arrival θ = 30°, the in-phase received digital signal I 0 of the dual-antenna hybrid phased array receiver 1 and the quadrature received digital signal Q
[0063] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the invention as set forth in the appended claims. For example, although the embodiments are described as including a carrier signal having a predetermined frequency of 80 GHz and λ / 4 being approximately 1 mm, in other embodiments, other predetermined frequencies and other delays are used. Additionally, although the embodiments are described as including an antenna array spaced λ / 2 apart, where λ is the wavelength of the carrier signal, in other embodiments, the antennas are spaced different ratios of the wavelength of the carrier signal. Furthermore, although the embodiments are described in the context of radar applications, the above techniques are applicable to other beamforming applications. Accordingly, the specification and figures should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention. It is not intended that any of the benefits, advantages, or solutions to problems described herein with respect to specific embodiments be construed as critical, required, or essential features or elements of any or all of the claims.
[0064] Unless otherwise stated, terms such as "first" and "second" are used arbitrarily to distinguish such terms from the elements they describe. Therefore, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.
Claims
1. A method for receiving radio frequency signals using a phased array receiver, characterized in that: The method comprises: generating a first digital received signal based on a first signal received from a first antenna and a local clock signal; generating a second digital reception signal based on a second signal received from a second antenna and the local clock signal; and combining the first digital received signal and the second digital received signal to generate a first complex received signal, The second antenna is spaced apart from the first antenna by a predetermined distance.
2. The method according to claim 1, characterized in that Also includes: generating a first clock signal based on the local clock signal, generating a second clock signal based on the local clock signal, wherein the second clock signal is ninety degrees out of phase with the first clock signal, wherein generating the first digital receive signal uses the first clock signal, and The second digital receiving signal is generated using the second clock signal.
3. The method according to claim 1, characterized in that: Also includes: generating a third digital received signal based on a third signal received from a third antenna and the local clock signal; generating a fourth digital received signal based on a fourth signal received from a fourth antenna and the local clock signal; as well as combining the third digital received signal and the fourth digital received signal to generate a second complex received signal, The third antenna is spaced apart from the second antenna by the predetermined distance, and the fourth antenna is spaced apart from the third antenna by the predetermined distance.
4. The method according to claim 3, characterized in that Also includes: delaying the first signal received from the first antenna to generate a delayed signal, the delayed signal being ninety degrees out of phase with the first signal received from the first antenna; as well as delaying the fourth signal received from the fourth antenna to generate a second delayed signal, the second delayed signal being ninety degrees out of phase with the fourth signal received from the fourth antenna, wherein the first digital received signal is generated using the delayed signal and the local clock signal, and The fourth digital received signal is generated using the second delayed signal and the local clock signal.
5. A phased array receiver, characterized in that: include: a first receiver path configured to generate a first digital receive signal based on a first signal received from a first antenna and a local clock signal; a second receiver path configured to generate a second digital receive signal based on a second signal received from the second antenna and the local clock signal; as well as circuit configured to combine the first digital received signal and the second digital received signal to generate a first complex received signal, The second antenna is spaced apart from the first antenna by a predetermined distance.
6. The phased array receiver according to claim 5, characterized in that: Also includes: a second circuit configured to provide a first clock signal based on the local clock signal and configured to provide a second clock signal based on the local clock signal, the second clock signal being ninety degrees out of phase with the first clock signal, wherein the first receiver path includes a first mixer circuit responsive to the first clock signal, and Wherein the second receiver path includes a second mixer circuit responsive to the second clock signal.
7. The phased array receiver according to claim 5, characterized in that: Also includes: a third receiver path configured to generate a third digital receive signal based on a third signal received from a third antenna and the local clock signal; as well as a fourth receiver path configured to generate a fourth digital received signal based on a fourth signal received from a fourth antenna and the local clock signal, wherein the circuit is further configured to combine the third digital received signal and the fourth digital received signal to generate a second complex received signal, The third antenna is spaced apart from the second antenna by the predetermined distance, and the fourth antenna is spaced apart from the third antenna by the predetermined distance.
8. The phased array receiver according to claim 7, characterized in that: The first receiver path includes a delay element coupled between the first antenna and the circuit, and The fourth receiver path includes a second delay element coupled between the fourth antenna and the circuit.
9. The phased array receiver according to claim 7, characterized in that: Also includes: a second circuit configured to provide a first clock signal based on the local clock signal and configured to provide a second clock signal based on the local clock signal, the second clock signal being ninety degrees out of phase with the first clock signal; as well as a third circuit configured to provide a third clock signal based on the local clock signal and configured to provide a fourth clock signal based on the local clock signal, the fourth clock signal being ninety degrees out of phase with the third clock signal, wherein the first receiver path includes a first mixer circuit responsive to the first clock signal, wherein the second receiver path includes a second mixer circuit responsive to the second clock signal, wherein the third receiver path includes a third mixer circuit responsive to the third clock signal, and Wherein the fourth receiver path includes a fourth mixer circuit responsive to the fourth clock signal.
10. A device, characterized in that: include: means for generating a first digital received signal based on a first signal received from a first antenna and a local clock signal; means for generating a second digital received signal based on a second signal received from a second antenna and the local clock signal; as well as means for combining the first digital received signal and the second digital received signal to generate a first complex received signal, The second antenna is spaced apart from the first antenna by a predetermined distance.