Reset control method and control unit

Abstract

The invention discloses a reset control method and a control unit. The reset control method is applied to a control unit, and the control unit comprises a first processor and a second processor. The reset control method comprises the steps that the first processor obtains the running state of the second processor; and when the running state of the second processor is abnormal, the first processor controls the second processor to reset. According to the embodiment of the invention, the running state of the second processor is obtained through the first processor in the control unit, the reset of the second processor is controlled, the monitoring and reset control of the second processor can be realized without arranging an additional hardware structure, and the design complexity and the production and manufacturing cost of the control unit can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of controllers, and particularly to a reset control method and a control unit. Background Art

[0002] With the wide application of the Internet of Things and intelligent devices, electronic devices have higher and higher requirements for low power consumption and high performance. Traditional single-core microcontroller units have difficulty meeting these requirements, and multi-core microcontroller units have gradually become the mainstream. In particular, heterogeneous multi-core processors with a big-little core architecture can achieve dynamic balance between low power consumption and high performance. However, with the increase in system complexity, ensuring the stability of the big core during long-term operation has become crucial.

[0003] In the prior art, the control unit relies on a hardware watchdog for reset operations to ensure its stable operation. During normal operation, the big core of the control unit clears the count register of the hardware watchdog at a certain period. When the big core of the control unit is abnormal, it cannot clear the counter of the hardware watchdog in time, resulting in the counter continuing to count. Once the counter of the hardware watchdog overflows, a reset signal will be generated to reset the big core.

[0004] However, the introduction of the hardware watchdog increases the design complexity and production cost of the control unit. Summary of the Invention

[0005] The present invention provides a reset control method and a control unit to reduce the design complexity and production cost of the control unit.

[0006] According to one aspect of the present invention, a reset control method is provided, which is applied to a control unit. The control unit includes a first processor and a second processor. The reset control method includes:

[0007] The first processor obtains the operating state of the second processor;

[0008] When the operating state of the second processor is abnormal, the first processor controls the second processor to reset.

[0009] Optionally, the specific method for the first processor to obtain the operating state of the second processor includes:

[0010] Obtaining at least one of the following three types of data: a plurality of operating data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor during external communication in continuous time;

[0011] Determine whether the second processor is abnormal based on at least one of the following three types of data: a plurality of operation data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor during external communication in continuous time.

[0012] Optionally, the specific method for determining whether the second processor is abnormal based on at least one of the following three types of data: a plurality of operation data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor during external communication in continuous time includes:

[0013] Compare whether the data of a plurality of operation data generated by the second processor in continuous time is the same;

[0014] If the plurality of operation data generated by the second processor in continuous time is the same, the operation state of the second processor is abnormal;

[0015] If the plurality of operation data generated by the second processor in continuous time is different, the operation state of the second processor is normal.

[0016] Optionally, the specific method for determining whether the second processor is abnormal based on at least one of the following three types of data: a plurality of operation data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor during external communication in continuous time includes:

[0017] Compare whether the plurality of communication voltages generated by the second processor during external communication in continuous time is the same;

[0018] If the plurality of communication voltages generated by the second processor during external communication in continuous time is the same, the operation state of the second processor is abnormal;

[0019] If the plurality of communication voltages generated by the second processor during external communication in continuous time is different, the operation state of the second processor is normal.

[0020] Optionally, the specific method for determining whether the second processor is abnormal based on at least one of the following three types of data: a plurality of operation data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor during external communication in continuous time includes:

[0021] Calculate the average core temperature of the second processor in continuous time according to the plurality of core temperatures of the second processor in continuous time;

[0022] If the average core temperature of the second processor in continuous time is higher than the average temperature threshold, the operating state of the second processor is abnormal;

[0023] If the average core temperature of the second processor in continuous time is lower than or equal to the average temperature threshold, the operating state of the second processor is normal.

[0024] Optionally, the specific method for determining whether the second processor is abnormal based on at least one of the following three types of data: multiple operating data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor during external communication in continuous time, includes:

[0025] Calculate the core temperature variance of the second processor in continuous time based on the multiple core temperatures of the second processor in continuous time;

[0026] If the core temperature variance of the second processor in continuous time is greater than the temperature variance threshold, the operating state of the second processor is abnormal;

[0027] If the core temperature variance of the second processor in continuous time is less than or equal to the temperature variance threshold, the operating state of the second processor is normal.

[0028] Optionally, the specific method for determining whether the second processor is abnormal based on at least one of the following three types of data: multiple operating data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor during external communication in continuous time, includes:

[0029] Compare whether the multiple communication voltages generated by the second processor during external communication in continuous time are the same;

[0030] Calculate the average core temperature of the second processor in continuous time based on the multiple core temperatures of the second processor in continuous time;

[0031] If the multiple communication voltages generated by the second processor during external communication in continuous time are the same and the average core temperature of the second processor in continuous time is higher than the average temperature threshold, the operating state of the second processor is abnormal;

[0032] If the multiple communication voltages generated by the second processor during external communication in continuous time are different or the average core temperature of the second processor in continuous time is lower than or equal to the average temperature threshold, the operating state of the second processor is normal.

[0033] Optionally, the specific method for determining whether the second processor is abnormal according to at least one of the following three types of data: multiple operating data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor during external communication in continuous time includes:

[0034] Compare whether the multiple communication voltages generated by the second processor during external communication in continuous time are the same;

[0035] Calculate the core temperature variance of the second processor in continuous time based on the multiple core temperatures of the second processor in continuous time;

[0036] If the multiple communication voltages generated by the second processor during external communication in continuous time are the same and the core temperature variance of the second processor in continuous time is greater than the temperature variance threshold, then the operating state of the second processor is abnormal;

[0037] If the multiple communication voltages generated by the second processor during external communication in continuous time are different or the core temperature variance of the second processor in continuous time is less than or equal to the temperature variance threshold, then the operating state of the second processor is normal.

[0038] According to another aspect of the present invention, there is also provided a control unit, which includes: a first processor, a second processor, and a storage medium;

[0039] Both the second processor and the first processor are connected to the storage medium, the second processor is also connected to an external device, and the first processor is also connected to the second processor;

[0040] The second processor is used for calculation; the first processor is used to execute the reset control method described in any one of the above embodiments.

[0041] Optionally, the control unit further includes: an enable pin and at least one general-purpose pin;

[0042] The enable pin is connected to the second processor, and the first processor is connected to the enable pin through the general-purpose pin.

[0043] Optionally, the storage medium includes: a random access memory or a Flash memory, wherein the storage medium is used to record the operating data of the second processor.

[0044] In the embodiment of the present invention, the control unit monitors the operating state of the second processor through the first processor, and the first processor controls the second processor to reset when the operating state of the second processor is abnormal. In the embodiment of the present invention, the first processor in the control unit obtains the operating state of the second processor and controls the reset of the second processor, so that the monitoring and reset control of the second processor can be realized without setting additional hardware structures, which is beneficial to reducing the design complexity and manufacturing cost of the control unit.

[0045] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 It is a flowchart of a reset control method provided by an embodiment of the present invention;

[0048] Figure 2 It is a flowchart of another reset control method provided by an embodiment of the present invention;

[0049] Figure 3 It is a schematic diagram of a control unit provided by an embodiment of the present invention;

[0050] Figure 4 It is a schematic diagram of another control unit provided by an embodiment of the present invention. Detailed Embodiments

[0051] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0053] An embodiment of the present invention provides a reset control method. The reset control method is applied to a control unit, and the control unit includes a first processor and a second processor. In this embodiment, the first processor in the control unit obtains the operating state of the second processor to control the reset of the second processor, and the monitoring and reset control of the second processor can be realized without setting additional hardware structures, which is beneficial to reducing the design complexity and production cost of the control unit. Figure 1 It is a flowchart of a reset control method provided by an embodiment of the present invention. Refer to Figure 1 , the reset control method includes:

[0054] S110. The first processor obtains the operating state of the second processor.

[0055] Exemplarily, the first processor may be a slave processor in the control unit, and the second processor may be a master processor in the control unit. Specifically, when the control unit is running, the second processor responds to the computing requirements of the external devices connected to the control unit, that is, the second processor calculates the data sent by the external devices. The first processor monitors at least one of the three types of data of the operating data, core temperature, and external communication of the second processor, so as to judge the operating state of the second processor.

[0056] Limited by the working environment and requirements of the control unit, during the operation of the control unit, the operating data, core temperature, and external communication of the second processor in the control unit may occasionally have short-term abnormalities. Nevertheless, the short-term abnormalities will not affect the normal operating state of the second processor, nor will they affect the overall operation of the control unit.

[0057] However, if at least one of the three types of data of the operating data of the second processor, the core temperature of the second processor, and the external communication of the second processor has a long-term abnormality, the second processor is in an abnormal operating state. At this time, the second processor cannot work properly, and the control unit cannot respond to the computing requirements of the external devices.

[0058] S120. Determine whether the operating state of the second processor is abnormal; if so, execute S130; if not, continue to execute S110.

[0059] Specifically, when the first processor detects that the second processor is in an abnormal operating state, the first processor controls the second processor to be reset so that the second processor resumes its normal operating state; when the first processor detects that the second processor is in a normal operating state, the first processor re-obtains the operating state of the second processor.

[0060] S130. The first processor controls the second processor to be reset.

[0061] Exemplarily, the first processor controls the second processor to be reset can be achieved by controlling the reset pin of the control unit. When the first processor detects that the second processor is in an abnormal operating state, the first processor generates a reset signal and sends it to the reset pin of the control unit through the general-purpose pin of the control unit. When the second processor receives the reset signal through the reset pin, the second processor is reset.

[0062] In the embodiment of the present invention, the control unit monitors the operating state of the second processor through the first processor, and the first processor controls the second processor to be reset when the operating state of the second processor is abnormal. In the embodiment of the present invention, the first processor in the control unit obtains the operating state of the second processor and controls the reset of the second processor, and it is possible to monitor and reset the second processor without setting an additional hardware structure, which is beneficial to reducing the design complexity and production cost of the control unit.

[0063] Figure 2 It is a flowchart of another reset control method provided by an embodiment of the present invention. On the basis of the above embodiment, optionally, referring to Figure 2 , the specific method for the first processor to obtain the operating state of the second processor includes:

[0064] S111. Obtain at least one of the following three types of data: a plurality of operating data generated by the second processor in continuous time, a plurality of core temperatures of the second processor in continuous time, and a plurality of communication voltages generated by the second processor for external communication in continuous time.

[0065] Among them, the continuous time can be a set value confirmed in engineering practice, such as 1 minute, 10 minutes, etc., and the present invention does not limit it. The "multiple operation data", "multiple core temperatures", and "multiple communication voltages" all refer to at least two. In a specific embodiment, in order to prevent the first processor from misjudging the state of the second processor due to too few samples, 10 operation data, 10 core temperatures, and 10 communication voltages can be selected for acquisition. It should be clear that the length of the "continuous time" and the quantities of the "multiple operation data", "multiple core temperatures", and "multiple communication voltages" do not limit the scope of protection of the present invention.

[0066] In a specific implementation, the operation data can be self-increasing data controlled by the second processor. In some embodiments, the length of the self-increasing data can be 8 bits and is stored in a certain area of the storage medium inside the control unit. When the second processor is running normally, it regularly reads the operation data from this area, increments it, and then rewrites the updated operation data back to this area. Both the first processor and the second processor have access rights to this area. Therefore, the first processor can regularly read the operation data in this area to monitor the running state of the second processor. The storage medium inside the control unit can be a random access memory or a Flash memory.

[0067] The core temperature of the second processor can be detected by a temperature sensor, and the first processor obtains the core temperature of the second processor by acquiring the data of the temperature sensor. The second processor communicates with external devices through general-purpose pins. Therefore, the communication voltage of the second processor for external communication can be obtained by detecting the voltage of the general-purpose pins used for connecting the second processor and external devices. In this step, the first processor acquires at least one of the following three types of data: multiple operation data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor for external communication in continuous time.

[0068] S112. Determine whether the second processor is abnormal according to at least one of the following three types of data: multiple operation data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor for external communication in continuous time.

[0069] Specifically, the long-term abnormality of the operation data of the second processor can be determined by multiple pieces of operation data generated by the second processor in continuous time, and the data of multiple pieces of operation data generated by the second processor in continuous time are compared. When the data of multiple pieces of operation data generated by the second processor in continuous time are the same, it indicates that the operation data of the second processor is abnormally long-term, and it is determined that the operation state of the second processor is abnormal; when the data of multiple pieces of operation data generated by the second processor in continuous time are different, it is determined that the operation state of the second processor is normal.

[0070] Among them, whether the second processor is in an abnormal state can be judged by the operation data. The operation data can be self-increasing data controlled by the second processor. In some embodiments, the length of the self-increasing data can be 8 bits and is stored in a certain area of the storage medium inside the control unit. When the second processor is operating normally, it regularly reads the operation data from this area, increments it, and then rewrites the updated operation data back to this area. Both the first processor and the second processor have the right to access this area. The first processor accesses this area at a preset frequency and reads the operation data. When the multiple pieces of operation data read by the first processor in continuous time are the same, it indicates that the second processor does not control the self-increase of the operation data, and it is determined that the operation state of the second processor is abnormal; when the multiple pieces of operation data read by the first processor in continuous time are different, it is determined that the operation state of the second processor is normal.

[0071] The long-term abnormality of the core temperature of the second processor can be determined by multiple core temperatures of the second processor in continuous time. The first processor can calculate the average core temperature of the second processor in continuous time through multiple core temperatures of the second processor in continuous time. When the average core temperature of the second processor in continuous time is higher than the average temperature threshold, it can indicate that the second processor has been in a high-temperature state for a long time, and it is determined that the operation state of the second processor is abnormal; when the average core temperature of the second processor in continuous time is lower than or equal to the average temperature threshold, it is determined that the operation state of the second processor is normal.

[0072] In addition, the first processor can also calculate the core temperature variance of the second processor in continuous time through the core temperatures of multiple cores of the second processor in continuous time. When the core temperature variance of the second processor in continuous time is greater than the temperature variance threshold, the core temperature of the second processor is abnormally high for a long time, and the operating state of the second processor is abnormal; when the core temperature variance of the second processor in continuous time is less than or equal to the temperature variance threshold, the core temperature of the second processor is normal, and the operating state of the second processor is normal. It should be noted that the average temperature threshold is the highest average core temperature of the second processor set in advance, and the temperature variance threshold is the maximum temperature variance of the second processor set in advance. In practical applications, the average temperature threshold and the temperature variance threshold can be set according to actual needs, and this embodiment does not limit this. Among them, when determining the operating state of the second processor based on the core temperatures of the second processor generated in continuous time, the first processor can store the core temperatures of the second processor in a sliding window queue and calculate the average core temperature or the core temperature variance of the second processor at preset time intervals. In practical applications, the preset time interval can be set according to actual needs, and this embodiment does not limit this.

[0073] The long-term abnormality of the external communication of the second processor can be determined through multiple communication voltages generated by the second processor in continuous time. The first processor compares the multiple communication voltages generated by the second processor during external communication in continuous time. When the multiple communication voltages generated by the second processor during external communication in continuous time are the same, the external communication of the second processor is abnormally long, and the operating state of the second processor is abnormal; when the multiple communication voltages generated by the second processor during external communication in continuous time are different, the external communication of the second processor is normal, and the operating state of the second processor is normal. It should be noted that the method of determining whether the external communication of the second processor is abnormally long through multiple communication voltages generated by the second processor in continuous time is applicable to scenarios that need to communicate frequently with external devices, such as a home central control screen that needs to maintain constants; this method is not used for scenarios with a low communication frequency with external devices, such as Internet of Things sensors for data collection. Because when the communication frequency between the second processor and external devices is low, it is normal for the communication voltage to be the same for a long time.

[0074] It is obvious to those skilled in the art that the running data can directly reflect the working state of the second processor, and it can be determined whether the second processor is in an abnormal running state only through the running data. The core temperature and the communication voltage indirectly reflect the working state of the second processor, and it can be inferred whether the second processor is in an abnormal state through the core temperature and the communication voltage. In some embodiments, whether the running state of the second processor is abnormal can be determined separately through the running data, core temperature or communication voltage of the second processor; in some embodiments, in order to improve the accuracy of monitoring, the two types of indirect data of the core temperature and the communication voltage can be combined to determine the working state of the second processor. Exemplarily, the first processor can also determine the running state of the second processor through multiple communication voltages generated by the second processor during external communication in continuous time and multiple core temperatures of the second processor in continuous time. The first processor compares multiple communication voltages generated by the second processor during external communication in continuous time, and calculates the average core temperature of the second processor in continuous time through multiple core temperatures of the second processor in continuous time. When multiple communication voltages generated by the second processor during external communication in continuous time are the same, and the average core temperature of the second processor in continuous time is higher than the average temperature threshold, the running state of the second processor is abnormal; when multiple communication voltages generated by the second processor during external communication in continuous time are different or the average core temperature of the second processor in continuous time is lower than or equal to the average temperature threshold, the running state of the second processor is normal.

[0075] The embodiment of the present invention also provides a control unit. Figure 3 is a schematic diagram of a control unit provided by an embodiment of the present invention. Refer to Figure 3 As shown in the figure, the control unit 10 includes: a first processor 110, a second processor 120, and a storage medium 130.

[0076] Both the second processor 120 and the first processor 110 are connected to the storage medium 130, the second processor 120 is also connected to an external device 20, and the first processor 110 is also connected to the second processor 120; the second processor 120 is used for calculation; the first processor 110 is used to execute the reset control method provided in any of the above embodiments. It should be noted that the storage medium 130 is used to record the running data of the second processor 120. Among them, the storage medium 130 can be a random access memory or a Flash memory.

[0077] It should be noted that the control unit 10 provided in this embodiment has the beneficial effects of the reset control method provided in any of the above embodiments, and will not be elaborated here.

[0078] Figure 4It is a schematic diagram of another control unit provided by an embodiment of the present invention. On the basis of the above embodiment, optionally, referring to Figure 4 , the control unit 10 further includes: an enable pin EN and at least one general-purpose pin GPIO;

[0079] The enable pin EN is connected to the second processor 120, and the first processor 110 is connected to the enable pin EN through the general-purpose pin GPIO.

[0080] In addition, the control unit 10 is further provided with a temperature sensor 140, a communication pin DATA, and an analog-to-digital pin ADC. The temperature sensor 140 is connected to the first processor 110. The second processor 120 is connected to the external device 20 through the communication pin DATA, and the first processor 110 is connected to the communication pin DATA through the analog-to-digital pin ADC. The first processor 110 monitors the communication voltage of the second processor 120 through the analog-to-digital pin ADC, and the first processor 110 monitors the core temperature of the second processor 120 through the temperature sensor 140.

[0081] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and this is not limited herein.

[0082] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made to the specific embodiments according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A reset control method, characterized in that: Applied in a control unit, the control unit includes a first processor and a second processor; the reset control method includes: The first processor obtains the running status of the second processor; When the operating state of the second processor is abnormal, the first processor controls the second processor to reset.

2. The reset control method according to claim 1, characterized in that: The specific method for the first processor to obtain the running status of the second processor includes: Acquire at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication; Determine whether the second processor is abnormal based on at least one of three types of data: multiple operating data generated by the second processor in continuous time, multiple core temperatures of the second processor in continuous time, and multiple communication voltages generated by the second processor for external communication in continuous time.

3. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: comparing whether the plurality of operation data generated by the second processor in successive times are the same; If the plurality of operation data generated by the second processor in consecutive time are the same, the operation state of the second processor is abnormal; If the plurality of operating data generated by the second processor in consecutive time periods are different, the operating state of the second processor is normal.

4. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: comparing whether a plurality of communication voltages generated by the second processor in continuous time for external communication are the same; If the plurality of communication voltages generated by the second processor for external communication in a continuous period of time are the same, then the operation state of the second processor is abnormal; If the plurality of communication voltages generated by the second processor for external communication in a continuous period of time are different, the operation state of the second processor is normal.

5. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: calculating an average core temperature of the second processor in a continuous time according to a plurality of core temperatures of the second processor in a continuous time; If the average core temperature of the second processor in a continuous period of time is higher than the average temperature threshold, the operation state of the second processor is abnormal; If the average core temperature of the second processor in a continuous period of time is lower than or equal to the average temperature threshold, the operation status of the second processor is normal.

6. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: Calculating a core temperature variance of the second processor in a continuous time according to a plurality of core temperatures of the second processor in a continuous time; If the core temperature variance of the second processor in the continuous time is greater than the temperature variance threshold, the operation state of the second processor is abnormal; If the core temperature variance of the second processor in continuous time is less than or equal to the temperature variance threshold, the operating state of the second processor is normal.

7. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: comparing whether a plurality of communication voltages generated by the second processor in continuous time for external communication are the same; calculating an average core temperature of the second processor in a continuous time according to a plurality of core temperatures of the second processor in a continuous time; If the plurality of communication voltages generated by the second processor for external communication in a continuous time are the same and the average core temperature of the second processor in a continuous time is higher than the average temperature threshold, the operation state of the second processor is abnormal; If the plurality of communication voltages generated by the second processor for external communication in a continuous time are different or the average core temperature of the second processor in a continuous time is lower than or equal to the average temperature threshold, the operation status of the second processor is normal.

8. The reset control method according to claim 2, characterized in that: The specific method of determining whether the second processor is abnormal based on at least one of three types of data: a plurality of operation data generated by the second processor in a continuous time, a plurality of core temperatures of the second processor in a continuous time, and a plurality of communication voltages generated by the second processor in a continuous time for external communication includes: comparing whether a plurality of communication voltages generated by the second processor in continuous time for external communication are the same; Calculating a core temperature variance of the second processor in a continuous time according to a plurality of core temperatures of the second processor in a continuous time; If the plurality of communication voltages generated by the second processor for external communication in a continuous time are the same and the core temperature variance of the second processor in a continuous time is greater than a temperature variance threshold, then the operation state of the second processor is abnormal; If the plurality of communication voltages generated by the second processor for external communication in continuous time are different or the core temperature variance of the second processor in continuous time is less than or equal to the temperature variance threshold, the operation state of the second processor is normal.

9. A control unit, characterized in that: include: A first processor, a second processor, and a storage medium; The second processor and the first processor are both connected to the storage medium, the second processor is also connected to an external device, and the first processor is also connected to the second processor; The second processor is used for performing calculations; and the first processor is used for executing the reset control method according to any one of claims 1 to 8.

10. The control unit according to claim 9, characterized in that The control unit further comprises: an enable pin and at least one general pin; The enable pin is connected to the second processor, and the first processor is connected to the enable pin via the general pin.

11. The control unit according to claim 9, characterized in that: The storage medium includes: a random access memory or a Flash memory, wherein the storage medium is used to record the operation data of the second processor.

Images