Systems, methods, and apparatus for memory allocation for storage devices

Abstract

In some aspects, a method may include receiving, at a memory interface of a device configured as a memory, a request using a memory access protocol to make regions of the memory assignable; and processing the request to make the region of the memory allocable. Processing the request may include making at least a portion of a storage medium of the device corresponding to a region of memory assignable and / or assigning a value to at least a portion of the storage medium corresponding to the region of memory. A device may be configured to track allocated addresses on the device, and the method may further include modifying at least one circuit such that addresses corresponding to a region of the memory may be allocated. The method may also include modifying the device to indicate that the region of memory is free, and adding the region of memory to a list of allocable memory locations.

Description

Technical Field

[0001] The present disclosure generally relates to storage devices, and more particularly to systems, methods, and apparatuses for memory allocation in storage devices. Background Art

[0002] Garbage collection is a background process commonly found in not-AND (NAND)-based storage devices that reorganizes valid data and reclaims space from invalid data on blocks of the storage device for future writes. Garbage collection can involve internal data movement on the storage device, which can affect the performance of the device.

[0003] The above information disclosed in this background section is only for enhancing the understanding of the background of the present invention, and thus may include information that does not constitute the prior art. Summary of the Invention

[0004] In some aspects, the techniques described herein relate to a method that includes: receiving, at a memory interface of a device configured as a memory, a request to make a region of the memory allocable using a memory access protocol; and processing the request to make the region of the memory allocable. In some aspects, processing the request includes making at least a portion of a storage medium of the device corresponding to the region of the memory allocable. In some aspects, processing the request includes assigning a value to at least a portion of the storage medium of the device corresponding to the region of the memory. In some aspects, the device includes at least one circuit configured to track addresses allocated on the device, and the method further includes modifying the at least one circuit to make the addresses corresponding to the region of the memory allocable. In some aspects, the method further includes: modifying the device to indicate that the region of the memory is allocable; and adding the region of the memory to a list of allocable memory locations. In some aspects, the device includes at least one circuit configured to perform one or more operations on the region of the memory, and processing the request includes sending a command to the at least one circuit to make the region of the memory allocable based on receiving the request. In some aspects, the request to make a region of the memory allocable includes an indication of a memory range and an operation. In some aspects, the indication of the operation includes at least one of a trim operation, an initialization operation, a deallocation operation, a flush operation, a retention operation, a prefetch operation, an eviction operation, an encryption operation, a compression operation, and a deduplication operation. In some aspects, the indication of the operation includes a command to perform at least one of: assigning a value to at least a portion of the storage medium of the device corresponding to the memory range; and making at least a portion of the storage medium corresponding to the memory range allocable. In some aspects, the method further includes sending a completion message that includes at least one of an indicator that the memory range has been assigned and an indicator that the memory range is allocable.

[0005] In some aspects, the techniques described herein relate to an apparatus that includes: at least one circuit; a storage medium; and a storage device; wherein the at least one circuit is configured to perform one or more operations, the one or more operations including: receiving, using a memory access protocol, a request to make an area of a memory allocable; and making an area of the memory allocable. In some aspects, the at least one circuit is configured to track the addresses of the allocated areas of the memory on the apparatus; and the at least one circuit is further configured to perform one or more operations, the one or more operations including modifying the at least one circuit to make available at least one address corresponding to an area of the memory. In some aspects, the apparatus includes a storage device that includes the storage medium, and the at least one circuit is further configured to perform one or more operations, the one or more operations including: sending to the storage medium a command to make an area of the memory allocable; wherein the storage medium is configured to make an area of the memory allocable based on the command. In some aspects, the storage medium is further configured to perform one or more operations, including: receiving from the at least one circuit a command to make an area of the memory on the storage medium allocable; and making an area of the memory on the storage medium allocable. In some aspects, the storage medium is configured to perform one or more operations including making an area of the memory on the storage medium allocable. In some aspects, the at least one circuit is further configured to perform one or more operations, including sending an indication that an area of the memory is allocable on the apparatus.

[0006] In some aspects, the techniques described herein relate to a system that includes: a host device; and a storage device that includes at least one circuit, a storage medium, and a storage device; wherein the storage device includes a persistent storage device; and wherein the at least one circuit is configured to perform one or more operations, including: receiving, using a memory access protocol, from the host device a request to make a portion of the storage device allocable; converting the portion of the storage device into one or more addresses; and modifying the at least one circuit to make the one or more addresses available. In some aspects, the at least one circuit includes a flash translation layer, and wherein the at least one circuit is further configured to perform one or more operations, including modifying the flash translation layer to make available an address corresponding to the one or more addresses. In some aspects, the at least one circuit is further configured to perform one or more operations, including: sending to the storage device a request to make one or more areas of the storage device corresponding to the one or more addresses allocable; wherein the storage device is configured to perform one or more operations, including making one or more areas of the storage device allocable. In some aspects, the system further includes a storage medium; and the at least one circuit is further configured to perform one or more operations, including making one or more areas of the storage medium corresponding to the one or more addresses allocable. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are not necessarily to scale, and in all the drawings, for illustrative purposes, elements of similar structure or function are generally represented by the same reference numeral or a portion thereof. The drawings are only intended to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming cluttered, not all components, connections, etc. may be shown, and not all components may have reference numerals. However, the pattern of the component configuration can be readily apparent from the drawings. The drawings, together with the description, illustrate example embodiments of the present disclosure and are used together with the description to explain the principles of the present disclosure.

[0008] Figure 1 Shows an embodiment of a storage device scheme according to an example embodiment of the present disclosure.

[0009] Figure 2a Shows additional embodiments of a storage device scheme according to an embodiment of the present disclosure.

[0010] Figure 2b Shows additional embodiments of a storage device scheme according to an embodiment of the present disclosure.

[0011] Figure 3 Shows a flowchart of a method for making a memory allocable according to an embodiment of the present disclosure.

[0012] Figure 4 Shows an example embodiment of a command and status register according to an embodiment of the present disclosure.

[0013] Figure 5 Shows an example embodiment of a region of a memory according to an embodiment of the present disclosure.

[0014] Figure 6 Shows an example operating environment according to an embodiment of the present disclosure.

[0015] Figure 7 Shows another example operating environment according to an embodiment of the present disclosure.

[0016] Figure 8 Shows a flowchart of a memory deallocation process according to an embodiment of the present disclosure. Detailed Description

[0017] A storage device may make a region of the memory allocable (e.g., deallocate and / or initialize the region of the memory) before writing data to the region of the memory. In some embodiments, the storage device may also use a background garbage collection process to perform one or more operations to make a region of the memory allocable. Thus, in some embodiments, garbage collection may improve the efficiency of the storage device by making regions of the memory allocable in the background, such that when the storage device writes data, the host may not have to wait for a region of the memory to be allocable for the write operation.

[0018] Generally, the host may not control when garbage collection is performed. In other words, the storage device may determine when to perform garbage collection. For example, the storage device may wait until the storage device is not being used for running garbage collection operations. However, since attempts to perform garbage collection operations may conflict with other operations, the performance (e.g., latency) of the storage device may be improved if the host may also control when some garbage collection operations are being run. Thus, in some embodiments, providing components for host control of some garbage collection related operations may improve the overall performance of the storage device.

[0019] According to embodiments of the present disclosure, using a memory access protocol, the host may communicate with the storage device to proactively perform some garbage collection related operations (e.g., operations to make the memory allocable). In some embodiments, the storage device may receive a request to make a region of the memory allocable using the memory access protocol. In some embodiments, the storage device may perform one or more operations to make a region of the memory allocable, such that the region may be freed / available for future write operations.

[0020] Figure 1 Embodiments showing a storage device scheme according to example embodiments of the present disclosure are presented. Figure 1 The illustrated embodiments may include one or more host devices 100 and one or more storage devices 150 configured to communicate using one or more communication connections 110.

[0021] In some embodiments, the host device 100 may be implemented with any component or combination of components that may utilize one or more features of the storage device 150. For example, the host may be implemented with one or more of a server, a storage node, a compute node, a central processing unit (CPU), a workstation, a personal computer, a tablet computer, a smart phone, etc., or a combination thereof.

[0022] In some embodiments, the storage device 150 may include a communication interface 130, a memory 180 (some or all of which may be referred to as device memory), one or more computing resources 170 (which may also be referred to as computing resources), a device controller 160, and / or device functional circuitry 190. In some embodiments, the device controller 160 may control the overall operation of the storage device 150, including any of the operations, features, and / or the like described herein. For example, in some embodiments, the device controller 160 may parse, process, invoke, etc., commands received from the host device 100.

[0023] In some embodiments, the device functional circuitry 190 may include any hardware for implementing the primary functions of the storage device 150. For example, the device functional circuitry 190 may include storage media, such as magnetic media (e.g., if the storage device 150 is implemented as a hard disk drive (HDD) or a tape drive), solid-state media (e.g., one or more flash memory devices), optical media, etc. For example, in some embodiments, the storage device may be at least partially implemented as a NAND flash-based solid-state drive (SSD), persistent memory (PMEM) (such as cross-grid non-volatile memory), memory with variable bulk resistance, phase change memory (PCM), or any combination thereof. In some embodiments, the device controller 160 may include a media conversion layer, such as a flash translation layer (FTL) for interfacing with one or more flash memory devices. In some embodiments, the storage device 150 may be implemented as a compute storage drive, a compute storage processor (CSP), and / or a compute storage array (CSA).

[0024] As another example, if the storage device 150 is implemented as an accelerator, the device functional circuitry 190 may include one or more accelerator circuits, memory circuits, etc.

[0025] The computing resource 170 can be implemented with any component or combination of components that can perform operations on data that can be received, stored, and / or generated at the storage device 150. Examples of computing engines can include combinational logic, sequential logic, timers, counters, registers, state machines, complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), embedded processors, microcontrollers, central processing units (CPUs), such as complex instruction set computer (CISC) processors (e.g., x86 processors), and / or reduced instruction set computer (RISC) processors, such as ARM processors, graphics processing units (GPUs), data processing units (DPUs), neural processing units (NPUs), tensor processing units (TPUs), etc., which can execute instructions stored in any type of memory and / or implement any type of execution environment, such as containers, virtual machines, operating systems (such as Linux), extended Berkeley packet filters (eBPF) environments, etc., or combinations thereof.

[0026] In some embodiments, the memory 180 can be used, for example, by one or more of the computing resources 170 to store input data, output data (e.g., computation results), intermediate data, transitional data, etc. The memory 180 can be implemented, for example, with volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and any other type of memory (such as non-volatile memory).

[0027] In some embodiments, the memory 180 and / or the computing resources 170 may include software, instructions, programs, code, etc. that may be executed, run, etc. using one or more computing resources (e.g., hardware (HW) resources). Examples may include software implemented in any language such as assembly language, C, C++, binary code, FPGA code, one or more operating systems, kernels, environments such as eBPF, etc. The software, instructions, programs, code, and / or the like may be stored in a repository in, for example, the memory 180 and / or the computing resources 170. In some embodiments, the software, instructions, programs, code, etc. may be downloaded, uploaded, sideloaded, pre-installed, built-in, etc. into the memory 180 and / or the computing resources 170. In some embodiments, the storage device 150 may receive one or more instructions, commands, and / or the like to select, enable, activate, execute the software, instructions, programs, code, and / or the like and / or the like. Examples of computing operations, functions, etc. that may be implemented by the memory 180, computing resources 170, software, instructions, programs, code, etc. may include any type of algorithms, data movement, data management, data selection, filtering, encryption and / or decryption, compression and / or decompression, checksum calculation, hash value calculation, cyclic redundancy check (CRC), weight calculation, activation function calculation, training, inference, classification, regression, etc. for artificial intelligence (AI), machine learning (ML), neural networks, etc.

[0028] In some embodiments, the communication interface 120 at the host device 100, the communication interface 130 at the storage device 150, and / or the communication link 110 may implement one or more interconnects, one or more networks, a network of networks (e.g., the Internet), and / or the like or combinations thereof, and / or be implemented via one or more interconnects, one or more networks, a network of networks (e.g., the Internet), and / or the like or combinations thereof, using any type of interface, protocol, and / or the like. For example, one or more of the communication link 110 and / or interface 120 and / or 130 may implement and / or utilize any type of wired and / or wireless communication medium, interface, network, interconnect, protocol, etc., including Peripheral Component Interconnect Express (PCIe), NVMe, NVMe over Fabric (NVMe-oF), Compute Express Link (CXL), and / or coherent protocols such as CXL.mem, CXL.cache, CXL.io, and / or the like, Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc., Advanced eXtensible Interface (AXI), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Advanced Message Queuing Protocol (AMQP), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, any generation of wireless network including 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc., or any combination thereof. In some embodiments, the communication link 110 may include one or more switches, hubs, nodes, routers, etc.

[0029] In some embodiments, the storage device 150 may be implemented in any physical form factor. Examples of form factors may include 3.5 inches, 2.5 inches, 1.8 inches, etc., storage device (e.g., storage drive) form factors, M.2 device form factors, enterprise and data center standard form factors (EDSFF) (which may include, for example, E1.S, E1.L, E3.S, E3.L, E3.S 2T, E3.L 2T, etc.), add-in card (AIC) (e.g., PCIe card (e.g., PCIe expansion card) form factors, including half-height (HH), half-length (HL), half-height, half-length (HHHL), etc.), next generation small form factor (NGSFF), NF1 form factor, compact flash (CF) form factor, secure digital (SD) card form factor, personal computer memory card international association (PCMCIA) device form factor, etc., or combinations thereof. Any computing device disclosed herein may be connected to the system using one or more connectors, such as SATA connectors, SCSI connectors, SAS connectors, M.2 connectors, EDSFF connectors (e.g., 1C, 2C, 4C, 4C+, etc.), U.2 connectors (which may also be referred to as SSD form factor (SSF) SFF-8639 connectors), U.3 connectors, PCIe connectors (e.g., card edge connectors), etc.

[0030] Any storage device disclosed herein may be used in combination with one or more personal computers, smart phones, tablet computers, servers, server chassis, server racks, data areas, data centers, edge data centers, mobile edge data centers, and / or any combination thereof.

[0031] In some embodiments, the storage device 150 may be implemented with any device that may include or may access memory, storage media, etc., to store data that may be processed by one or more computing resources 170. Examples may include memory expansion and / or buffer devices, such as CXL type 2 and / or CXL type 3 devices, and CXL type 1 devices that may include memory, storage media, etc.

[0032] Figure 2a Another example embodiment of a storage device solution according to an embodiment of the present disclosure is shown. Figure 2a A host device 210 and a storage device 220 are shown. The host device 210 and the storage device 220 may be similar to Figure 1The host device 100 and the storage device 150 therein. In some embodiments, the storage device 220 may include: an interface 230, which may include a device-side cache (e.g., device cache 238); and a storage device 240, which may be used as additional memory for the device cache 238. In some embodiments, the interface 230 may be implemented on an ASIC, FPGA, or system-on-chip (SOC). In some embodiments, the storage device 240 may be implemented on an SSD. In some embodiments, the interface 230 may include endpoints (EPs) 232, host interface (I / F) logic (HIL) 234, and storage device I / F logic (NIL) 236. In some embodiments, the NIL 236 may be NVMe host I / F logic and may communicate with the storage device 240 using the NVMe protocol. In some embodiments, the EPs 232, HIL 234, and NIL 236 may be implemented on one or more circuits of the interface 230. In some embodiments, the device cache 238 may be implemented as DRAM or static random access memory (SRAM). In some embodiments, the storage device 240 may include a controller 242, a storage medium 244, and a storage medium 246. In some embodiments, the controller 242 may include HIL 248, a flash translation layer (FTL) 250, and a flash channel 252. In some embodiments, the HIL 234, FTL 250, and flash channel 252 may be implemented on one or more circuits of the storage device 240. In some embodiments, the storage medium 244 may be implemented on DRAM, and the storage medium 246 may be implemented on NAND flash memory. In some embodiments, the storage medium 244 and the storage medium 246 may be implemented on other types of media. For example, the storage medium 244 may be implemented on a memory characterized as a relatively fast memory, and the storage medium 246 may be implemented on a memory characterized as having a relatively large capacity.

[0033] In some embodiments, the host device 210 may communicate with the storage device 220 using a memory access protocol (e.g., sending commands to the storage device 220). For example, the storage device 220 may be a CXL-compatible device that uses the CXL.mem, CXL.IO, and CXL.cache protocols to communicate with the host device 210.

[0034] In some embodiments, the EP 232 may receive commands from the host device 210 and send commands to the HIL 234. In some embodiments, the interface 230 may receive a host physical address (HPA) from the host device 210 and convert the HPA to a device physical address (DPA) to be used by the HIL 234. In some embodiments, when transmitted back to the host device 210, the DPA may be converted to an HPA for use by the host device 210.

[0035] In some embodiments, when the HIL 234 receives a command (e.g., a read request), the HIL 234 may check whether the data requested by the host device 210 is found in the device cache 238 and return the data from the device cache 238. In some embodiments, if the data is not found in the device cache 238, the HIL 234 may send a request to the NIL 236 to retrieve the data from the storage device 240.

[0036] In some embodiments, when the host device 210 writes data to the storage device 220 (e.g., a write request), if there is space available for the write operation, the HIL 234 may write the data to the device cache 238. In some embodiments, if there is not enough free space, the HIL 234 may send a request to the NIL 236 to move some data pages in the device cache 238 to the storage device 240 to make room for new data in the device cache 238. In some embodiments, the NIL 236 may use, for example, the NVMe protocol to fetch (e.g., NVMe read) and flush or evict (e.g., NVMe write) to / from the storage device 240.

[0037] In some embodiments, NIL 236 and HIL 248 may communicate using a protocol such as the NVMe protocol. For example, in some embodiments, NIL 236 may send a request (e.g., an NVMe read request) to HIL 248. In some embodiments, the host device 210 and the storage device 220 may communicate using methods other than the communication between NIL 236 and HIL 248. Additionally, the communication between NIL 236 and HIL 248 may use any protocol that allows communication between the host device 210 and the storage device 220. It is within the scope of the present invention for the host device 210 and the storage device 220 to communicate using any protocol and any interface that allows communication between the host device and the storage device. For example, any type of interface and / or protocol may be used to connect one or more storage devices, including Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe-over-fabric (NVMe oF), Advanced eXtensible Interface (AXI), UltraPath Interconnect (UPI), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, etc. or any combination thereof.

[0038] In some embodiments, the controller 242 may manage read / write operations to the storage medium 244 and the storage media 246. For example, in some embodiments, the controller 242 may be used to determine where data resides on the storage media 246. In some embodiments, the FTL 250 may receive an address from the storage device 220 and convert the address into a physical address on the storage medium 244 and the storage media 246. In other words, in some embodiments, the FTL 250 may include logical-to-physical address translation and keep track of valid written data on the storage device 240. In some embodiments, the controller 242 may use the flash channel 252 to communicate with the storage media 246.

[0039] In some embodiments, in addition to reading / writing data to / from the storage medium 244 and the storage medium 246, the controller 242 may also perform various functions, such as garbage collection on the storage device 240. In some embodiments, garbage collection may be performed in the background (e.g., using a background process or thread). In some embodiments, the background process may conflict with data read / write operations (e.g., the garbage collection operation and the read / write operation may be attempted to be executed simultaneously), resulting in a higher latency for the host device 210 (e.g., the host may wait for the garbage collection operation to be executed before performing a read / write operation). Some examples of garbage collection operations include wear leveling, recycling, recovery, and retention.

[0040] In some embodiments, the storage device 220 may be a hierarchical memory expansion device that allows additional RAM and flash memory accessible by the host device 210 to be used as memory. In some embodiments, the storage device 220 may be used as a replacement for the DRAM on the host device 210 to expand the memory capacity, as the storage device may be more reasonably priced than DRAM, thus helping to reduce the overall total cost of ownership. In other words, the storage device 220 may be used by the host device 210 as an extended memory. In some embodiments, although the storage device may provide a lower-cost solution for memory expansion, compared to the DRAM on the host device, the storage device may have higher and more unpredictable latency results. In some embodiments, this may lead to performance fluctuations and affect the execution of system tasks on the host device 210. In some embodiments, a contributor to the latency of the storage device may be the garbage collection process. For example, since garbage collection involves internal data movement, when it is active (e.g., the garbage collection is in the process of being executed), it may affect the performance of the storage device as seen by the host (e.g., the host may wait for the garbage collection operation before performing an operation on the storage device).

[0041] Figure 2b Another exemplary embodiment of a storage device scheme according to an embodiment of the present disclosure is shown. Figure 2b The elements shown in Figure 2a may be elements similar to those shown in Figure 2a wherein similar elements may be indicated by reference numerals that end with the same numbers, letters, and / or analogs and / or include the same numbers, letters, and / or analogs. Figure 2b The differences between Figure 2b include that, as shown in Figure 2a the storage device 220 may directly use the storage medium 246 (e.g., NAND flash memory) instead of being connected to the storage device 240, as shown in Figure 2bThe storage device 220 can be referred to as an integrated hierarchical memory expander device. Any of the disclosed embodiments can be applied to Figure 2a the storage device 220 (e.g., a hierarchical memory expander device) in Figure 2b or the storage device 220 (e.g., an integrated hierarchical memory expander device) in Figure 2b For the storage device 220 in Figure 2a the NIL 236 shown in may not be required, and optimizations (e.g., NAND media management optimizations) can be performed on the storage medium 246.

[0042] Figure 3 A flowchart showing a method for making memory allocatable according to an embodiment of the present disclosure is shown. The following description can be applied to Figure 2a and 2b the storage device 220 in. In the case of differences, the description will identify which figure the description applies to.

[0043] At 310, a request can be received at the memory interface of a device configured as a memory using a memory access protocol to make a region of the memory allocatable. In some embodiments, a command set for communication between the storage device and the host can be defined for the memory access protocol. For example, the storage device can provide one or more commands that the host can use to communicate with control and status registers (CSRs) on the storage device. In some embodiments, the CSR can include an indication of a memory region—e.g., a memory address range—and an opcode—e.g., an operation that the host can request to be performed on the storage device. In some embodiments, the operations can include operations such as deallocating memory, initializing memory, flushing memory, persisting memory, prefetching memory, evicting memory, encrypting memory, compressing memory, and deduplicating memory.

[0044] In some embodiments, a host may send a request to a storage device to make an (one or more) address region allocable. In other words, in some embodiments, the host may identify when data is no longer used by the host and request the storage device to deallocate the memory (e.g., using a deallocate memory opcode). For example, when the host no longer uses the data, the reference to the data may be removed on the host. However, the data may be retained on the storage device until the host communicates to the storage device that the region of the memory containing the data may be allocable. In some embodiments, the data may continue to reside on the storage medium of the storage device. Thus, in some embodiments, the host may update one or more circuits (e.g., CSR) on the storage device to indicate that the region of the memory may be allocable. In some embodiments, the host may not use the CSR and may, for example, send a different request to make the region of the memory allocable. For example, a memory access protocol may provide one or more commands to make the region of the memory allocable.

[0045] As described above, the storage device may deallocate a region of the memory to make the memory allocable. It should be understood that making the memory allocable may include other operations. For example, in some embodiments, the address of the region of the memory may be included in a free memory pool to allocate the memory for future memory requests. In some embodiments, a pointer to the region of the memory may be removed. Additionally, in some embodiments, the storage device may write zeros to the memory locations in the region of the memory.

[0046] At 320, the storage device may process a request to make a region of the memory allocable. For example, the storage device may send an NVMe Data Set Management (NVMe DSM) deallocate command to the storage medium (such as Figure 2a the storage medium 246 therein) to make the associated Logical Block Addressing (LBA) region with the deallocated memory range allocable. In some embodiments, the storage device may use an interface (such as Figure 2b the interface 230 therein) to convey a request to make the memory region allocable to the storage medium.

[0047] Typically, a storage device can wait until it receives a write request (e.g., an LBA write request) to make a region of the memory allocable (e.g., de - allocable). For example, the storage device can receive a write request and check to see if the region of the memory is allocable. If the region of the memory is allocable, the storage device can write to that region of the memory. If data exists in that region of the memory, the storage device can move the valid data to another region of the memory and make that region of the memory allocable for the write request. In some embodiments, if moving the valid data to another region of the memory and making that region allocable is performed separately from the write operation, the host can perform a write operation on the storage device without waiting for the memory to be allocable.

[0048] In some embodiments, a storage device can be partitioned into blocks, and the blocks can be partitioned into pages. Data can be read and written at the page level (e.g., the size of a read or write can be a page), but data can be erased at the block level (e.g., the size of an erase can be a block). In some embodiments, when data is written to the storage device, the data can be written to an empty page. However, in some embodiments, the block in which the page is located may contain data (e.g., valid and / or invalid data). In some embodiments, if a block contains valid data (e.g., data that is still in use), the data can be moved to another block before making the block allocable. In other words, in some embodiments, before a write operation on a first block, the valid data can be moved from the first block to a second block, and the first block can be erased before writing the data corresponding to the write operation to the first block. Thus, in some embodiments, a block can be made allocable before data is written.

[0049] In some embodiments, the FTL can be updated to free the LBAs corresponding to an allocable memory address range (e.g., a region of the memory). In some embodiments, requests from the host (e.g., de - allocation commands) can be used to mark unused pages instead of at the next write request (e.g., an LBA write request). In some embodiments, this can prevent the garbage collection process from copying unused pages (e.g., if the data in a region of the memory has not been de - allocated and the storage device moves data from the region of the memory before a write request), and thus, reduce the garbage collection load and the garbage collection time, which helps to improve the overall latency.

[0050] In some embodiments, data initialization (e.g., zeroing pages) can be offloaded to the device. In some embodiments, for data initialization, regions of the memory can be assigned values such as zeros. In some embodiments, instead of the memory manager on the host initializing the data on the device, the storage device can perform its own initialization (e.g., using CSRs to perform the initialization). In some embodiments, operations such as encryption / decryption, compression, deduplication, pattern search, regular expressions, etc. to a specified address range can also be offloaded to the device. In some embodiments, data privacy / security protection with lower overhead can be provided by actively removing unused blocks from the storage device. In other words, data can be actively removed from the storage device such that the data is not retained on the physical media of the device.

[0051] In some embodiments, when it is determined that the memory can be made allocable by the operating system (OS), system software, or an application, the OS can use a system call to make a specified address range allocable. For example, the OS can issue a request to remove the mapping of pages that include at least a portion of the address range (e.g., munmap()) to make the pages of the memory allocable. In some embodiments, the request can initiate a new process to invalidate the associated address range in the storage device in the background. In some embodiments, the OS can add the address range to the free memory pool for future allocation requests. It should be understood that any operation and / or combination of operations that make an address range allocable can be used. In some embodiments, multiple processes can be used to support multiple deallocation tasks simultaneously. In some embodiments, using multiple processes can be orthogonal to using a request to remove the mapping of pages that include at least a portion of the address range to spawn new processes for deallocating different address ranges. For example, in some embodiments, using the munmap() command, munmap() can remove the mapping of pages that include any portion of the address space of a process that starts at a first address and extends for the length of the address range. In some embodiments, the munmap() call may not be used, and another system call that makes an address range allocable can be used. Using any system call to deallocate a portion of the memory is within the scope of the present disclosure.

[0052] In some embodiments, one or more commands can be sent to the storage device to discard a specified memory region or invalidate a specified memory region. In some embodiments, when the storage device receives the command, the storage device can form an SSD command, such as a DSM deallocation command using the NVMe protocol, to complete the invalidation task and respond to the OS once completed.

[0053] In some embodiments, the storage device may be notified before a page is added back to the free list (e.g., a list of allocatable pages). In some embodiments, the device may update the FTL to mark the LBA as free.

[0054] In some embodiments, a command such as an NVMe DataSet management trim command may be sent to the storage medium, or the FTL may be updated directly to make a region of the memory allocatable (e.g., deallocate a memory range). In some embodiments, a communication indicating that the memory is allocatable may be sent to the host. For example, the communication may be performed via CSR polling, interrupt, or message response.

[0055] In some embodiments, in the case of an integrated hierarchical memory expander device having a NAND memory directly interfaced with the HIL, the equivalent NAND management function may unmap the LBA range corresponding to the deallocated memory region.

[0056] In some embodiments, the CSR may be polled by the host to convey deallocation completion. In some embodiments, an interrupt may be used to convey deallocation completion, such as a legacy interrupt (e.g., INTx), message-signaled interrupt (e.g., MSI, MSI-X), etc. In some embodiments, when a response is received from the device, the OS may complete the unmap task and add the free page to the linked list of blocks that are free and ready for new allocation.

[0057] In some embodiments, if the storage device is an integrated hierarchical memory expander device, as Figure 2b shown, the NVMe DSM deallocation command may not be sent to the storage medium and may be processed by the integrated hierarchical memory expander device. In some embodiments, a region of the memory may be made allocatable while the data in the block remains until a garbage collection operation is performed.

[0058] Figure 4An example embodiment of a control and status register according to an embodiment of the present disclosure is shown. In some embodiments, CSR commands for communication between a host and a hierarchical storage device may be provided. In some embodiments, the device may provide CSRs for address range deallocation tasks and completions. In some embodiments, CSR 400 may include a start memory address range (e.g., task_mem_start_addr 402), an end memory address range (e.g., task_mem_end_addr 404), a task_completion status 408, a task_completion interrupt vector 410, and a task command opcode (e.g., task_command 406). In some embodiments, examples of task_command 406 opcodes may include deallocation, initialization, flush, persist, prefetch, evict, encrypt, compress, and deduplicate memory, etc. In some embodiments, the CSR may not include all of the foregoing fields, and may include only some fields, and may additionally include other fields. For example, the CSR may not include task_completion_status 408, and may use an interrupt, for example, to convey the completion status. In some embodiments, task_command 406 may include code for trimming regions of memory and / or allocating regions of memory to zero. For example, code may be provided for setting only the trim command, setting only the initialize to zero command, and setting both the trim and initialize to zero commands. In some embodiments, code for task_completion_status 408 and / or task_completion_interrupt_vector 410 may be provided. For example, code may be provided indicating that a trim operation has been completed or that memory has been initialized to zero.

[0059] In some embodiments, the lengths of task_mem_strt_addr 402 and task_mem_end_addr 404 may be 64 bits. In some embodiments, task_command 406 may be an 8-bit value.

[0060] In some embodiments, multiple sets of CSRs may be used to facilitate multiple outstanding memory address range deallocations. In some embodiments, a mechanism based on a looped command submission / completion queue with appropriate flow control characteristics may be used for communication between the host device and the storage device. In some embodiments, the CSR may be exposed to the host as an input / output (I / O) mapped register set utilizing an I / O block protocol and / or a PCIe / cache coherent memory configuration space. In some embodiments, the request may be an out-of-band message.

[0061] In some embodiments, the CSRs can be exposed to the host system software using a memory-mapped set of addresses. For example, the exposed CSRs can be part of one or more memory address ranges advertised by the storage device. In some embodiments, the memory address locations of the CSRs can be fixed or programmable by the system software.

[0062] In some embodiments, when the storage device receives a request to deallocate memory from the host, the device can issue one or more trim commands (e.g., DSM deallocation commands in the case of NVMe) to the storage medium (e.g., the backend SSD). In some embodiments, the device can scan the device-side cache for any pages that fall within the deallocated address range. In some embodiments, device cache pages that fall within the deallocated range can be marked as free / invalid.

[0063] In some embodiments, the NVMe DSM deallocation command can mark the NAND pages associated with the LBA as invalid. In some embodiments, the FTL can merge the valid data into fewer blocks and erase the blocks with invalid data. In some embodiments, the FTL can be able to track which physical blocks are no longer needed to be reclaimed. In some embodiments, by reducing the unnecessary data movement of invalid blocks caused by garbage collection and wear leveling, write amplification can be reduced, the durability of the flash memory can be improved, and the overall performance can be improved.

[0064] In some embodiments, for an integrated hierarchical memory expander device, the FTL table can be updated directly without using NVMe commands.

[0065] In some embodiments, to protect data privacy and security, the storage pages can be initialized (e.g., zeroed) before they are allocated by a new process. In some embodiments, the same policy can be applied to SSD-backed hierarchical storage devices.

[0066] In some embodiments, a storage device may receive a memory request from an OS on a host to zero out an allocated region before it is accessed by a new process. In some embodiments, if the size of the memory request is 64 bytes, in order to free a page of size 4K, the OS may need 64 memory requests to fully zero out the entire page. In some embodiments, the memory ranges on the storage device may be initialized, resulting in an improvement in overall initialization performance. In some embodiments, the OS may use a CSR to send a command to initialize the memory region on the storage device. In some embodiments, upon receiving the command, a controller on the storage device may issue a zeroing command to initialize the LBAs associated with the memory address range. In some embodiments, the storage device may invalidate the corresponding data blocks in the device cache to make room for future data. In some embodiments, the initialization step may be offloaded to the storage device and performed with higher performance and with minimal communication between the host and the storage device, thus reducing the burden on the host's processor. In some embodiments, to minimize communication between the host and the storage device, the deallocation (e.g., making the memory allocatable) and initialization mechanisms may be combined and performed using a single command. In other words, when the memory regions on the storage device are deallocated, they may be initialized to zero. Thus, data privacy protection can be ensured (e.g., because data is removed when the regions of the memory are initialized), and no further initialization steps may be required when the page is allocated by another process.

[0067] In some embodiments, the host-device communication method may also be used to perform a large number of operations on a specified address range. Some examples of operations include encryption of data, compression of data, deduplication, pattern search, prefetching and eviction into the device cache, flushing and persisting to NAND media, etc.

[0068] In some embodiments, initialization and deallocation may be managed by host system software such as a hypervisor or other applications.

[0069] Figure 5 Shows a region of memory according to an embodiment of the present disclosure. Figure 5Regions 0 510, region 1 520, and region n 530 are shown. However, regions 0 510, region 1 520, and region n 530 are shown for illustrative purposes, and there may be more regions (e.g., n + 1 regions). In some embodiments, the memory on the storage device may be organized into regions. For example, in some embodiments, the size of a region may be 100 MB. In other embodiments, a region may be any size. For example, a region may be the size of a page, a block, a part of a block, or multiple blocks. In some embodiments, a region may be any size that a host can use to issue commands. For example, in some embodiments, a region may be the minimum size of a region for the storage device to deallocate memory.

[0070] Figure 6 An operating environment according to an embodiment of the present disclosure is shown. Figure 6 The elements shown in Figure 2a and 2b may be elements similar to those shown in Figure 6 wherein similar elements may be indicated by reference numerals that end with and / or include the same numbers, letters, and / or analogs. In some embodiments, the storage device 220 may include at least one CSR 610, an execution block 630, a controller 640, a storage medium 650, and a storage medium 660. In some embodiments, the storage medium 650 may include a memory range 652, and the storage medium 660 may include a memory range 662. Although Figure 6 a plurality of CSRs are shown for illustrative purposes, at least one CSR 610 may be the same CSR. In some embodiments, the CSR 610 may include a start address 612, an end address 614, a command 616, a completion status 618, and a completion interrupt 620. In some embodiments, the start address 612, the end address 614, the command 616, the completion status 618, and the completion interrupt 620 may be similar to Figure 4 the task_mem_start_addr 402, task_mem_end_addr 404, task_command 406, task_completion_status 408, and task_completion_interrupt_vector 410 in

[0071] In some embodiments, the host device 210 may send commands to the storage device 220. In some embodiments, the commands may be requests to make regions of the memory allocable or to zero out memory regions. In some embodiments, based on the requests, the storage device 220 may send commands (e.g., trim or initialize zeroing commands) to the execution blocks. For example, a trim command may indicate which blocks are no longer in use and may be erased. In some embodiments, an initialize zeroing command may zero out regions of the memory (e.g., remove data located on the physical media of the device). In some embodiments, the data structures on the FTL of the storage device may be updated (e.g., regions of the memory may be indicated as free). In some embodiments, if the region of the memory on which the command is executed (e.g., memory range 662) is on the storage medium 660, the pages in the memory range 662 may be invalidated (e.g., the addresses may be indicated as free for future write operations). In some embodiments, if the region of the memory on which the command is executed (e.g., memory range 652) is on the storage medium 650, the storage device 220 may use the controller 640 to execute the command on the storage medium 650. For example, the command may be transmitted to the storage medium 650 to make regions of the memory allocable or to initialize regions of the memory to zero.

[0072] In some embodiments, a completion message may be transmitted to the host device 210. For example, in some embodiments, the CSR 610 (e.g., completion status 618 and / or completion interrupt 620) may be modified, and for example, the host device 210 may poll the CSR to determine the status of the operation or may handle the interrupt. In some embodiments, a message indicating the completion status may be sent to the host device 210.

[0073] Figure 7 FIG. illustrates a storage device according to an embodiment of the present disclosure. Figure 7 The elements shown in Figure 2a and Figure 2b may be elements similar to those shown in

[0074] In some embodiments, when the storage device 220 receives a request, the storage device 220 may determine an operation to be performed on the storage device 220. For example, if the storage device 220 receives a request to make a region of the memory allocable, one or more circuits 710 may receive the request, process the request, and send a command to the storage medium 720 to make the region of the memory allocable. In some embodiments, the request may use a memory access protocol. For example, using the memory access protocol, the CSR on the storage device 220 may be updated with an address range and an indication of the operation to be performed on the storage device 220. In some embodiments, one or more circuits 710 may determine where the region of the memory to be made allocable is located. For example, when a region of data is on the storage medium 720, one or more circuits 710 may send a command to initialize at least a portion of the storage medium 720 corresponding to the memory range and / or make at least a portion of the storage medium 720 corresponding to the memory range allocable.

[0075] In some embodiments, the storage medium 720 may receive a command and perform a corresponding operation on the storage medium 720. For example, in some embodiments, the storage medium 720 may receive a command to make a region of the memory allocable. In some embodiments, based on the command, the storage medium 720 may make the region of the memory allocable.

[0076] Figure 8 A flowchart showing a garbage collection process according to an embodiment of the present disclosure is presented. At 810, the storage device may receive a request to make a region of the memory allocable. For example, the host may update the CSR on the storage device using a memory access protocol, indicating that the region of the memory may be allocable. In some embodiments, the CSR may be updated with an opcode to perform an operation corresponding to the opcode. For example, the storage device may receive a CSR with an opcode to reserve a region of the memory. In some embodiments, the CSR may include an indication of the region of the memory on which the operation is to be performed (e.g., start address and end address).

[0077] At 820, the request to make a region of the memory allocable may be processed. For example, the storage device may make the region of the memory allocable. In some embodiments, the FTL may be updated with free LBA regions of the memory, indicating that they are available. In some embodiments, the regions corresponding to the LBA on the storage medium may be made allocable. For example, the regions on the storage medium may be deallocated. In some embodiments, the storage device may communicate with the backend SSD using a command to make the memory allocable or initialize the memory on the SSD. In some embodiments, the pages in the region of the memory may be made allocable.

[0078] At 830, a completion message can be sent. For example, the storage device can receive communication that a region of the memory is allocable from the backend SSD. In some embodiments, the storage device can send the completion to the host based on the communication from the backend SSD. In some embodiments, the completion communication may not be from the backend SSD and can be generated by the storage device. For example, in the case of an integrated tiered memory expander device, the storage device can make a region of the memory allocable and send the completion to the host.

[0079] In some embodiments, the host can send a command (e.g., a forced garbage collection command) to the storage device. The host may not send the forced garbage collection command, and the storage device can perform the garbage collection operation on its own. For example, the storage device can use artificial intelligence to determine when to perform the garbage collection operation based on the deallocated data on the storage device. In some embodiments, the storage device can forward the forced garbage collection command to the storage medium. This can allow the storage device to start garbage collection at a determined time. For example, the storage device can forward the forced garbage collection command whenever it receives a garbage collection command from the host. In some embodiments, the storage device can determine whether to forward the forced garbage collection command based on the logic on the storage device.

[0080] In some embodiments, the storage device can zero out the deallocated pages (e.g., remove the charge on the transistors). In some embodiments, the storage device can alternatively initialize the memory range indicated by the host without deallocating.

[0081] In some embodiments, making the memory allocable can be performed more frequently because the system does not have to wait for a write operation to make the memory allocable. In some embodiments, the OS, application, and / or system software can make the memory allocable. In some embodiments, a virtual machine (VM) and / or container can release the memory after use. In some embodiments, making the memory allocable can be applied to both volatile and non-volatile memory address ranges.

[0082] In some embodiments, the OS and / or system software can initialize the memory before allocating the memory to a VM, container, and / or application. In some embodiments, initializing the memory may consume CPU cycles and may add an additional CPU burden. In some embodiments, before removing data from the storage device, it can be retained (e.g., the data may need to be explicitly deleted). In some embodiments, this may add an additional burden to the storage device controller, for example, for garbage collection, recycling, retention, etc. Therefore, by controlling the operations to make the memory allocable, the burden on the storage device can be reduced.

[0083] This disclosure encompasses many aspects related to devices having memory and storage configurations. The aspects disclosed herein can have independent utilities and can be embodied individually, and not every embodiment can utilize every aspect. Additionally, these aspects can also be embodied in various combinations, some of which can amplify some of the benefits of the individual aspects in a synergistic manner.

[0084] For the purpose of illustrating the inventive principles of this disclosure, some example embodiments may be described in the context of specific implementation details, such as a processing system that can implement a NUMA architecture, a storage device and / or pool that can be connected to the processing system using an interconnect interface and / or the Compute Express Link (CXL) protocol, etc. However, the principles are not limited to these example details, and can be implemented using any other type of system architecture, interface, protocol, etc.

[0085] In some embodiments, the latency of a storage device may refer to the delay between accessing the storage device in memory and the processor. Additionally, the latency can include delays caused by hardware, such as the read / write speed of accessing the storage device, and / or the structure of an arrayed storage device that generates individual delays when reaching the respective elements of the array. For example, a first storage device in the form of DRAM may have a faster read / write speed than a second storage device in the form of a NAND device. Additionally, the latency of a storage device can change over time based on conditions (e.g., relative network load) and the performance of the storage device over time and environmental factors (e.g., changing temperature that affects the delay on the signal path).

[0086] While some example embodiments may be described in the context of specific implementation details, such as a processing system that may implement a NUMA architecture, storage devices and / or pools that may be connected to the processing system using an interconnect interface and / or protocol such as CXL, etc., the principles are not limited to these example details and may be implemented using any other type of system architecture, interface, protocol, etc. For example, in some embodiments, any type of interface and / or protocol may be used to connect one or more storage devices, including Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe-over-fabric (NVMeoF), Advanced eXtensible Interface (AXI), UltraPath Interconnect (UPI), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, etc. or any combination thereof. In some embodiments, the interconnect interface may be implemented using one or more memory semantics and / or memory coherence interfaces and / or protocols, the one or more memory semantics and / or memory coherence interfaces and / or protocols including one or more CXL protocols, such as CXL.mem, CXL.io, and / or CXL.cache, Gen-Z, Cache Coherent Interconnect for Accelerators (CAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc. or any combination thereof. Any storage device may be implemented using one or more of any type of storage device interface, including DDR, DDR2, DDR3, DDR4, DDR5, LPDDRX, Open Memory Interface (OMI), NVLink, High Bandwidth Memory (HBM), HBM2, HBM3, etc.

[0087] In some embodiments, any one or its components of a storage device, memory pool, host, and / or the like can be implemented in any physical and / or electrical configuration and / or form factor, such as a stand-alone device, an add-in card such as a PCIe adapter or expansion card, a plug-in device such as a connector and / or slot (e.g., a connector on the backplane and / or midplane of a server or other device) that can be inserted into a server chassis, and / or the like. In some embodiments, any one or its components of a storage device, memory pool, host, etc. can be implemented using any connector configuration for an interconnect interface (such as a SATA connector, SCSI connector, SAS connector, M.2 connector, U.2 connector, U.3 connector, etc.) for a form factor of the storage device (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, enterprise and data center SSD form factor (EDSFF), NF1, etc.). Any device disclosed herein can be implemented in whole or in part using a server chassis, server rack, dataroom, data center, edge data center, mobile edge data center, and / or any combination thereof, and / or used in combination with a server chassis, server rack, data center, data center, edge data center, mobile edge data center, and / or any combination thereof. In some embodiments, any one or its components of a storage device, memory pool, host, etc. can be implemented as a CXL Type 1 device, CXL Type 2 device, CXL Type 3 device, etc.

[0088] In some embodiments, any functionality described herein (including, for example, any logic for implementing tiering, device selection, etc.) can be implemented in hardware, software, or a combination thereof, including combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more complex programmable logic devices (CPLDs), FPGAs, ASICs, central processing units (CPUs), such as complex instruction set computers (CISC) processors (such as x86 processors) and / or reduced instruction set computers (RISC) processors (such as ARM processors), graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), etc., executing instructions stored in any type of memory or any combination thereof. In some embodiments, one or more components can be implemented as an SOC.

[0089] In this disclosure, numerous specific details are set forth in order to provide a thorough understanding of the disclosure, but the disclosed aspects can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0090] References to "an embodiment" or "embodiments" in the present specification mean that the particular features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment disclosed herein. Thus, the phrases "in an embodiment" or "in embodiments" or "in accordance with an embodiment" (or other phrases with similar meanings) that appear in various places throughout this specification may not necessarily all refer to the same embodiment. Additionally, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily being preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Further, depending on the context discussed herein, singular terms can include the corresponding plural forms, and plural terms can include the corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.) can occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two dimensional", "predetermined", "pixel specific", etc.), and capitalized entries (e.g., "Counter Clock", "Row Select", "Pixout", etc.) can be used interchangeably with their corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeable use should not be regarded as inconsistent with each other.

[0091] Further, depending on the context discussed herein, singular terms can include the corresponding plural forms, and plural terms can include the corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. Additionally, if deemed appropriate, reference numerals are repeated in the figures to indicate corresponding and / or similar elements.

[0092] The terms used herein are for the purpose of describing only some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. When used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0093] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. The same reference numerals always refer to the same elements. As used herein, the term "and / or" can include any and all combinations of one or more of the associated listed items.

[0094] As used herein, the terms "first," "second," etc. are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Additionally, the same reference numerals may be used across two or more figures to refer to components, assemblies, blocks, circuits, units, or modules having the same or similar functionality. However, this usage is merely for the sake of simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the example embodiments disclosed herein.

[0095] The term "module" can refer to any combination of software, firmware, and / or hardware that is configured to provide the functionality described herein in connection with the module. For example, software can be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any of the embodiments described herein can include, for example, components, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry, either individually or in any combination. A module can be embodied, jointly or separately, as circuitry that forms part of a larger system, such as, by way of example and not limitation, an integrated circuit (IC), a system on a chip (SoC), a component, and the like. Embodiments of the subject matter and the operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, e.g., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, a data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to a suitable receiver apparatus for execution by the data processing apparatus. A computer storage medium can be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. Moreover, although a computer storage medium is not a propagated signal, a computer storage medium can be the source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium can also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0096] Although this specification may contain many specific implementation details, the implementation details should not be construed as limiting the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of separate embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although the features may be described as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination can in some cases be deleted from the combination, and the claimed combination can be directed to a sub-combination or variations of the sub-combination.

[0097] Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or sequentially, or that all of the illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0098] Accordingly, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the acts recited in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking and parallel processing may be advantageous.

[0099] Although certain exemplary embodiments have been described and shown in the figures, it should be understood that such embodiments are merely illustrative, and the scope of the present disclosure is not limited to the embodiments described or shown herein. The present invention can be modified in arrangement and detail without departing from the inventive concept, and such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method comprising: At a memory interface of a device configured as a memory, receiving a request to make a region of memory allocatable using a memory access protocol; as well as A request is processed to make a region of memory allocatable.

2. The method according to claim 1, wherein: Processing requests includes: At least a portion of a storage medium of the device corresponding to the area of ​​the memory is made allocatable.

3. The method according to claim 1, wherein: Processing requests includes: A value is assigned to at least a portion of a storage medium of the device corresponding to the area of ​​the memory.

4. The method according to claim 1, wherein: The device comprises at least one circuit configured to track assigned addresses on the device, wherein the method further comprises: At least one circuit is modified to make addresses corresponding to the region of the memory allocatable.

5. The method according to claim 1, further comprising: modifying a device to indicate that the region of memory is allocatable; as well as The region of memory is added to a list of allocatable memory locations.

6. The method according to claim 1, wherein: The apparatus comprises at least one circuit configured to perform one or more operations on the region of the memory, and wherein processing the request comprises: Based on receiving the request, a command is sent to at least one circuit to make the region of the memory allocatable.

7. The method according to claim 1, wherein: The request to make a region of memory allocatable comprises: Indication of memory ranges and operations.

8. The method according to claim 7, wherein: The indication of the operation includes at least one of the following: trim operations, initialize operations, deallocate operations, flush operations, persist operations, prefetch operations, evict operations, encrypt operations, compress operations, and de-duplicate operations.

9. The method according to claim 7, wherein: The instructions for the operations include commands for performing at least one of the following: A value is assigned to at least a portion of a storage medium of a device corresponding to the memory range, and at least a portion of the storage medium corresponding to the memory range is made allocatable.

10. The method according to claim 1, further comprising: Send a completion message that includes at least one of the following: An indicator that the memory range is assigned and an indicator that the memory range is allocatable.

11. A device comprising: at least one circuit; Storage media; as well as Storage medium; Wherein, at least one circuit is configured to perform one or more operations including: receiving a request to make a memory region allocatable using a memory access protocol; and Makes a region of memory allocatable.

12. The device according to claim 11, wherein At least one circuit is configured to track addresses of allocated regions of memory on a device; and wherein the at least one circuit is further configured to perform one or more operations including: At least one circuit is modified to make available at least one address corresponding to the region of the memory.

13. The device according to claim 11, wherein: The device includes a storage device, wherein the storage device includes the storage medium, wherein at least one circuit is further configured to perform one or more operations including: A command to make the region of the memory allocatable is sent to a storage medium; wherein the storage medium is configured to make the region of the memory allocatable based on the command.

14. The device according to claim 11, wherein: The storage medium is further configured to perform one or more operations including: receiving from at least one circuit a command to make a region of the memory on the storage medium allocatable; and An area of ​​the memory on the storage medium is made allocatable.

15. The apparatus according to claim 11, wherein: The storage medium is configured to perform one or more operations including: A region of the memory on the storage medium is made allocatable.

16. The apparatus according to claim 11, wherein: The at least one circuit is further configured to perform one or more operations including: An indication is sent that the region of memory is allocatable on the device.

17. A system comprising: Host device; as well as Storage devices, including: at least one circuit; storage media; and Storage medium; wherein the storage medium comprises a persistent storage device; and Wherein, at least one circuit is configured to perform one or more operations including: receiving a request from a host device to make a portion of a storage medium allocatable using a memory access protocol; converting the portion of the storage medium into one or more addresses; and At least one circuit is modified to make the one or more addresses available.

18. The system of claim 17, wherein: The at least one circuit includes a flash translation layer, and wherein the at least one circuit is further configured to perform one or more operations including: The flash translation layer is modified to make available addresses corresponding to the one or more addresses.

19. The system of claim 17, wherein: The at least one circuit is further configured to perform one or more operations including: Sending a request to a storage medium to make one or more areas of the storage medium corresponding to the one or more addresses allocatable; wherein the storage medium is configured to perform one or more operations, including: The one or more regions of the storage medium are made dispensable.

20. The system of claim 17, further comprising a storage medium; in, The at least one circuit is further configured to perform one or more operations including: One or more areas of the storage medium corresponding to the one or more addresses are made allocatable.

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