Flash memory controller and memory block read count recording method

Abstract

A controller for flash memory and a method for recording read counts of memory blocks are disclosed. The controller includes a first storage unit for persistently storing a total read count table, which records not only the read counts of each memory block within each logical group but also the maximum read count for each logical group. A hardware circuit unit is used to receive feedback from the flash memory chips regarding read commands, increase the read count of the target memory block determined by the feedback, and update the maximum read count of the logical group containing the target memory block. When the maximum read count of the logical group containing the target memory block exceeds a first read count threshold, a processor interrupt is triggered, allowing a predetermined software program to perform data checks and relocation on the memory blocks within the corresponding logical group. This disclosed embodiment reduces processor resource consumption and decreases the error in read count statistics.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular, to a controller for a flash memory and a method for recording the number of reads of a storage block. Background Technology

[0002] Flash memory is a type of non-volatile memory. Read interference (READ MIMO) is a common phenomenon in flash memory that can cause errors or corruption in the data stored in the memory. When a memory cell (usually called a page) is read, the read operation generates a voltage to retrieve the data from that cell. However, this voltage can diffuse through current to adjacent memory cells, causing changes in the charge state of these adjacent cells. The extent of the impact of READ MIMO on memory cells depends on several factors; the more reads performed, the greater the interference to adjacent memory cells, and the higher the probability of data corruption.

[0003] To address the problems caused by read interference, the controller of a flash memory typically records the number of reads for each memory block. When a certain threshold is reached, the data on the corresponding memory block is moved to other free memory blocks.

[0004] In existing technologies, the aforementioned tasks are performed by the controller's firmware. Since there are a large number of storage blocks, counting the number of read operations for each block not only requires significant storage space but also consumes considerable processor resources, impacting overall performance. Furthermore, due to the characteristics of flash memory, the controller merges some read operations to reduce the actual number of reads, a behavior that the firmware cannot predict, leading to substantial errors in read count statistics. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a controller for a flash memory and a method for recording the number of reads of a memory block, so as to at least partially solve the above-mentioned problems.

[0006] In a first aspect, embodiments of this disclosure provide a controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, and all memory blocks being divided into multiple logical groups, the controller comprising:

[0007] The first storage unit is used to persistently store a total read count table, which records not only the read count of each storage block contained in each logical group, but also the maximum read count of each logical group;

[0008] The hardware circuit unit is used to receive the result feedback of the read command from the flash memory chip, increase the read count of the target memory block and update the maximum read count of the logical group where the target memory block is located based on the result feedback, and trigger a processor interrupt when it is determined that the maximum read count of the logical group where the target memory block is located exceeds the first read count threshold, so that the predetermined software processing program can perform data checking and relocation on the memory blocks in the corresponding logical group.

[0009] In a second aspect, embodiments of this disclosure provide a controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, the controller including:

[0010] The first storage unit is used to persistently store a total read count table, which records the maximum read count for each logical group.

[0011] The second storage unit is used to cache a temporary table of read counts, which records the number of reads for each storage block within a certain period of time and the maximum number of reads for the logical group to which each storage block belongs within the corresponding period of time.

[0012] The hardware circuit unit is configured to: receive feedback from the flash memory chip regarding the read command result; update or add a record of the target memory block to the temporary read count table based on the target memory block determined by the feedback result; and update the maximum read count of the corresponding logical group in the total read count table based on the record of the target memory block in the temporary read count table when the maximum read count of the logical group containing the target memory block in the temporary read count table exceeds a second read count threshold; and trigger a processor interrupt when it is determined that the maximum read count of the logical group containing the target memory block in the total read count table exceeds a first read count threshold, so that a predetermined software processing program can perform data checking and relocation on the memory blocks within the corresponding logical group.

[0013] Optionally, when the hardware circuit unit adds a record of the target storage block to the temporary read count table, it uses the free storage space in the second storage unit to store the record of the target storage block; or, it updates the maximum read count of the corresponding logical group in the total read count table based on the record with the longest current usage time or the lowest usage frequency in the temporary read count table, and then uses the corresponding storage space to store the record of the target storage block.

[0014] Optionally, after updating the maximum number of reads for the corresponding logical group in the total number of reads table, the storage space occupied by the corresponding record in the second storage unit is cleared to zero, or the corresponding record is marked as invalid.

[0015] Optionally, memory blocks with the same sequence number in all planes are grouped into the same logical group.

[0016] Optionally, the first storage unit is a non-volatile storage medium, and the second storage unit is a volatile storage medium.

[0017] Thirdly, embodiments of this disclosure provide a controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, the controller including:

[0018] The first storage unit is used to persistently store a total read count table, which records the maximum read count for each logical group.

[0019] The second storage unit is used to cache a temporary table of read counts, which records the number of reads for each storage block within a certain period of time and the maximum number of reads for the logical group to which each storage block belongs within the corresponding period of time.

[0020] The hardware circuit unit is used to receive the result feedback of the read command from the flash memory chip, and update or add the record of the target storage block to the read count temporary table according to the target storage block determined by the result feedback;

[0021] Firmware is used to update the maximum read count of the corresponding logical group in the total read count table based on the maximum read count of each logical group in the temporary read count table, and when the maximum read count of a specific logical group in the total read count table is greater than a first read count threshold, to notify a predetermined processing program to perform data inspection and relocation of the storage blocks in the corresponding logical group.

[0022] Fourthly, embodiments of this disclosure provide a method for recording the number of reads of a storage block, applied to a controller of a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple storage blocks, and all storage blocks being divided into multiple logical groups, the method comprising:

[0023] Receive feedback on the result of the read command from the flash memory chip;

[0024] Based on the target storage block determined by the feedback results, increase the read count of the target storage block and update the maximum read count of the logical group to which the target storage block belongs; and

[0025] When it is determined that the maximum number of reads in the logical group where the target storage block is located exceeds the first read count threshold, a notification is sent to a predetermined program so that the predetermined program can perform data checks and relocation on the storage blocks in the corresponding logical group.

[0026] Optionally, in the steps of increasing the read count of the target storage block and updating the maximum read count of the logical group to which the target storage block belongs,

[0027] A temporary read count table is used to store the read count of the target storage block and the maximum read count of the logical group to which the target storage block belongs. When the maximum read count of the logical group to which the target storage block belongs exceeds the second read count threshold, the maximum read count of the logical group to which the target storage block belongs in the temporary read count table is increased to the maximum read count of the logical group to which the target storage block belongs in the total read count table. The total read count table only records the maximum read count of each logical group.

[0028] Fifthly, embodiments of this disclosure provide a flash memory, including a storage medium and a controller, wherein the controller is the controller described above.

[0029] According to embodiments of this disclosure, read counts are performed based on feedback results. By excluding optimized and merged read operations from the count, the number of reads is reduced. Furthermore, using hardware circuitry allows for more convenient accumulation of read counts compared to firmware and software programs, and it also detects whether the read count has reached a maximum threshold. Further, through a cache design in the temporary read count table, the total read count table is updated only after multiple operations have been accumulated, thereby reducing the update frequency of the total table and lowering system resource consumption. Attached Figure Description

[0030] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a structural diagram of the host system;

[0032] Figure 2 This is a schematic diagram of a controller for a fast memory provided in an embodiment of this disclosure;

[0033] Figure 3 yes Figure 2 An example diagram of the total number of reads used in the implementation;

[0034] Figure 4 This is a schematic diagram of a controller for a fast memory provided in another embodiment of this disclosure;

[0035] Figure 5 and Figure 6 yes Figure 4 Example diagrams of the temporary table and total table of read counts used in the implementation;

[0036] Figure 7 This is a schematic diagram of a controller for a fast memory provided in yet another embodiment of this disclosure;

[0037] Figure 8 This is a flowchart of a method for recording the number of reads of a storage block provided in an embodiment of this disclosure. Detailed Implementation

[0038] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0039] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0040] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0041] Figure 1 This is a schematic block diagram of a host system 100. The host system 100 is, for example, a personal computer, a laptop, or a server.

[0042] Host system 100 includes host device 110 (e.g., a computer system including a main processor and memory) and storage devices. Host device 110 can issue host commands to the storage devices, causing the storage devices to manage data stored in the storage devices according to the commands. For example, host device 110 can communicatively connect to the storage devices (e.g., via host interface 121) and issue various commands to the storage devices (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.). The storage devices can store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once a command is executed, the storage devices can transmit a response to host device 110, indicating that the command has been successfully completed.

[0043] The storage device consists of a controller 120 and a storage medium 130. The controller 120 parses host commands, translates them into instructions adapted to the storage medium 130, executes the instructions, and feeds back the results to the host device 110. The controller 120 consists of various hardware and software components. The hardware includes, for example, a (micro)processor, cache units such as SRAM and DRAM, and interface circuits. The software includes, for example, a series of software programs that perform management functions, including but not limited to data read / write, bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0044] The controller 120 and the storage medium 130 have multiple channels (e.g., CH0 and CH1) through which they exchange data. Currently, the mainstream storage medium 130 is flash memory (storage devices using flash memory are called flash storage devices). Each channel (e.g., CH0 or CH1 in the diagram) typically couples to N (N being 2, 4, 8, etc.) flash memory chips, and the controller 120 needs to operate the corresponding flash memory chips through each channel. Each flash memory chip is divided into multiple planes, and each plane is further divided into multiple storage blocks, labeled Block 0 to N in the diagram.

[0045] like Figure 2 As shown, in one embodiment of this disclosure, a hardware circuit unit 1201 is added to the controller 120. The hardware circuit unit 1201 maintains a read count summary table 1202. Since the read count summary table 1202 needs to be persistently stored, it is stored in the storage medium 130, or in SRAM, or a portion is stored in both the storage medium 130 and SRAM. The storage blocks contained in the storage medium 130 are pre-divided into multiple logical groups, and the read counts of the storage blocks in the same logical group are usually relatively close. The read count summary table 1202 not only records the read counts of the storage blocks contained in each logical group, but also records the maximum read count of each logical group. Since the read counts of storage blocks with the same sequence number in different planes (such as block 0 in plane 1 and plane 2 in the figure) are usually relatively close, storage blocks with the same sequence number in different planes can be placed in the same logical group. Figure 3 An example of a total read count table 1202 is given, based on... Figure 3 The total number of reads table 1202 stores n records, which record the number of reads and the maximum number of reads for each storage block from Group 0 to Group n-1.

[0046] Hardware circuit unit 1201 receives feedback on the result of a read instruction executed on a memory block. Based on the feedback, it determines the target memory block operated on by the read instruction, then increments the read count of the target memory block in the read count statistics table 1202 by 1, and simultaneously updates the maximum read count of the logical group containing the target memory block. Hardware circuit unit 1201 also determines whether the maximum read count of the logical group containing the target memory block exceeds a first read count threshold. If so, an interrupt is triggered, allowing processor 1203 to execute a predetermined software processing program. The predetermined software processing program performs data checks and relocation on the logical group containing the target memory block. The predetermined software processing program can be formed in the FTL and can exist as firmware.

[0047] To further improve the processing efficiency of controller 120, such as Figure 4 As shown, a temporary read count table 1204 is added to hardware circuit unit 1201. The temporary read count table 1204 stores the read counts of each memory block in a portion of the logic group within a given time period. The size of the cache unit used to cache the temporary read count table 1204 can be specified by firmware, for example, specifying that the cache unit has M (M=8) cache lines, with each line caching the records of one logic group. Furthermore, based on the temporary read count table 1204, additional features are designed as follows: Figure 6 The table 1202 showing the total number of reads can be seen from the figure as being designed with... Figure 2 The total number of reads in Table 1202 is different. Figure 6 The total number of reads in table 1202 only records the maximum number of reads for each logical group, and no longer records the number of reads for each storage block.

[0048] Figure 4The hardware circuit unit 1201 performs the following functions: receiving feedback from the memory block regarding the read instruction; determining the target memory block to be read based on the feedback; if a record for the target memory block exists in the temporary read count table 1204, updating the read count of the target memory block and the maximum read count of the logic group to which the target memory block belongs in the temporary read count table 1204; if a record for the target memory block does not exist in the temporary read count table 1204, adding a record containing the read count of the target memory block and the maximum read count of the logic group to the temporary read count table 1204; when determining the read count... When the maximum number of reads for the logical group containing the target memory block in temporary table 1204 exceeds the second read count threshold, the maximum number of reads for the logical group containing the target memory block in temporary table 1204 is increased to the maximum number of reads for the target memory block in total read count table 1202. Furthermore, when it is determined that the maximum number of reads for the logical group containing the target memory block in total read count table 1202 exceeds the first read count threshold, an interrupt is triggered, allowing processor 1203 to execute a predetermined software program. This predetermined software program performs data checks and relocation on the logical group containing the target memory block. The second read count threshold is typically set relatively small (e.g., 8), and it is less than the first read count threshold.

[0049] More specifically, the update logic for the temporary read count table and the total read count table of hardware circuit unit 1201 is as follows:

[0050] 1) When a read instruction for the target storage block is completed, query the temporary table of read counts, find the cache line where the corresponding logical group is located in the cache unit, increment the read count by 1 at the corresponding count position of the target storage block, and synchronously update the maximum read count in the cache line.

[0051] 2) If the corresponding logical group number is not found in the cache unit, select an empty cache line from the cache unit, clear the cache line to zero, then increment the read count by 1 at the corresponding count position of the target storage block, and synchronously update the maximum read count of the cache line.

[0052] 3) If the corresponding logical group number is not found in the cache unit and all cache lines are occupied, then refresh the record in the cache line with the longest usage time or the lowest usage frequency to the total number of reads table, and then clear the cache line to record new data.

[0053] 4) Before or after the records in the cache line with the longest usage time or the lowest usage frequency are refreshed to the total read count table, if it is determined whether the maximum read count of the corresponding logical group in the total read count table has reached the set first read count threshold (the first read count threshold is generally set to tens of thousands to hundreds of thousands of times), if the judgment is made before the refresh, and the set first read count threshold has been reached, the total read count table will not be updated, and the records of the corresponding cache lines in the total read count table and the temporary read count table will be cleared. At the same time, an interrupt will be initiated to notify the processor. If the judgment is made after the refresh, the records of the corresponding cache lines in the total read count table and the temporary read count table will be cleared directly.

[0054] 5) If the read count of a certain storage block in the cache unit reaches the second read count threshold (generally 8 times) after the current accumulation operation is completed, then the read count of that cache line is refreshed to the total read count table, and the record in that cache line is cleared.

[0055] In this context, refreshing the cached row record to the total read count table means adding the maximum read count of that row to the maximum read count of the corresponding logical group in the total read count table.

[0056] Figure 7 Given Figure 4 A variation of an embodiment based on the given information. For example... Figure 7 As shown, the controller 120 includes a hardware circuit unit 1201 and a software program 1205, which can be implemented as firmware. In this embodiment, the hardware circuit unit 1201 is only responsible for maintaining the temporary read count table 1204, including: receiving feedback from the flash memory chip on the read command result, and updating or adding the record of the target storage block to the temporary read count table according to the target storage block determined by the result feedback. The software program 1205 reads records one by one from the temporary read count table 1204, updates the maximum read count of the corresponding logical group in the total read count table 1202 according to the maximum read count of the logical group in each record, and when the maximum read count of the logical group of a certain record in the total read count table is greater than the first read count threshold, it notifies the predetermined processing program to perform data checking and relocation of the storage block in the corresponding logical group.

[0057] The software program 1205 can also operate as follows: First, add the maximum number of reads for the logical group of each record in the temporary read count table 1204 to the maximum number of reads for the corresponding logical group in the total read count table 1202. If the sum of the two is not greater than the first read count threshold, then update the maximum number of reads for the corresponding logical group in the total read count table 1202 based on the sum of the two. If the sum of the two is greater than the first read count threshold, then do not update the total read count table 1202, but directly notify the predetermined processing program.

[0058] In some embodiments, the software program 1205 or the hardware circuit unit 1201 may also perform numerical compensation for the maximum number of reads of the corresponding logical group in the external total statistics table, including: adding the compensation value to the maximum number of reads of the total table, and determining whether the first read count threshold is reached. If the threshold is reached, the total table is not updated, and an interrupt is initiated to notify the predetermined processing program. If the threshold is not reached, the total table is updated.

[0059] Accordingly, this disclosure also proposes a method for recording the number of reads of a storage block. This embodiment can be implemented by a software program or a hardware circuit unit. Figure 8 A flowchart of the method is provided, including the following steps.

[0060] In step S801, the result feedback of the read command from the flash memory chip is received.

[0061] In step S802, based on the target storage block determined by the result feedback, the number of reads of the target storage block is increased and the maximum number of reads of the logical group to which the target storage block belongs is updated.

[0062] In step S803, it is determined whether the maximum number of reads of the logical group to which the target storage block belongs exceeds the first read count threshold.

[0063] In step S804, a notification is sent to a predetermined software processor to perform data inspection and relocation on the storage blocks within the corresponding logical group.

[0064] The method described in this embodiment is applied to a controller for a flash memory, which includes flash memory chips coupled to the controller. Each flash memory chip is divided into multiple planes, each plane is divided into multiple memory blocks, and all memory blocks are divided into multiple logical groups. This grouping is usually based on the host device's reading habits of the memory blocks, grouping memory blocks with similar read counts into the same logical group. Therefore, memory blocks with different sequence numbers in all planes are usually grouped into the same logical group.

[0065] The method described in this embodiment also records the number of reads for each memory block and the maximum number of reads for the logical group to which the memory block belongs, based on the feedback of the read instructions returned from the flash memory chip, similar to... Figure 3 As shown.

[0066] To improve processing efficiency, this embodiment can also be implemented using a temporary read count table and a total read count table as shown in Figure 5. Specifically, when receiving feedback from the flash memory chip regarding the read command result, the result is first updated or added to the temporary read count table. Then, when the maximum read count of the corresponding logical group in the temporary read count table exceeds the second read count threshold, it is added to the total read count table. Furthermore, depending on the data requirements, the temporary read count table can be stored in a volatile or non-volatile storage medium, such as DRAM or SRAM, while the total read count table is typically stored in a non-volatile storage medium, such as SRAM.

[0067] While the embodiments disclosed above are preferred embodiments, they are not intended to limit the scope of the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention should be determined by the scope defined in the claims.

[0068] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, the controller comprising: The first storage unit is used to persistently store a total read count table, which records not only the read count of each storage block contained in each logical group, but also the maximum read count of each logical group; The hardware circuit unit is used to receive the result feedback of the read command from the flash memory chip, increase the read count of the target memory block and update the maximum read count of the logical group where the target memory block is located based on the result feedback, and trigger a processor interrupt when it is determined that the maximum read count of the logical group where the target memory block is located exceeds the first read count threshold, so that the predetermined software processing program can perform data checking and relocation on the memory blocks in the corresponding logical group.

2. A controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, the controller comprising: The first storage unit is used to persistently store a total read count table, which records the maximum read count for each logical group. The second storage unit is used to cache a temporary table of read counts, which records the number of reads for each storage block within a certain period of time and the maximum number of reads for the logical group to which each storage block belongs within the corresponding period of time. The hardware circuit unit is configured to: receive the result feedback of the read command from the flash memory chip; update or add the record of the target storage block to the read count temporary table according to the target storage block determined by the result feedback; and update the maximum read count of the corresponding logical group in the read count total table based on the record of the target storage block in the read count temporary table when the maximum read count of the logical group to which the target storage block belongs in the read count temporary table exceeds the second read count threshold. And when the maximum number of reads in the logical group where the target storage block is located in the total number of reads table exceeds the first number of reads threshold, a processor interrupt is triggered so that a predetermined software processing program can perform data checking and relocation on the storage block in the corresponding logical group.

3. The controller according to claim 2, wherein, When the hardware circuit unit adds a record of the target storage block to the temporary read count table, it uses the free storage space in the second storage unit to store the record of the target storage block; or, it updates the maximum read count of the corresponding logical group in the total read count table based on the record with the longest current usage time or the lowest usage frequency in the temporary read count table, and then uses the corresponding storage space to store the record of the target storage block.

4. The controller according to claim 2 or 3, wherein, After updating the maximum read count of the corresponding logical group in the total read count table, the storage space occupied by the corresponding record in the second storage unit is cleared to zero, or the corresponding record is marked as invalid.

5. The controller according to claim 2, wherein, Storage blocks with the same sequence number in all planes are grouped into the same logical group.

6. The controller according to claim 2, wherein, The first storage unit is a non-volatile storage medium, and the second storage unit is a volatile storage medium.

7. A controller for a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, the controller comprising: The first storage unit is used to persistently store a total read count table, which records the maximum read count for each logical group. The second storage unit is used to cache a temporary table of read counts, which records the number of reads for each storage block within a certain period of time and the maximum number of reads for the logical group to which each storage block belongs within the corresponding period of time. The hardware circuit unit is used to receive the result feedback of the read command from the flash memory chip, and update or add the record of the target storage block to the read count temporary table according to the target storage block determined by the result feedback; Firmware is used to update the maximum read count of the corresponding logical group in the total read count table based on the maximum read count of each logical group in the temporary read count table, and when the maximum read count of a specific logical group in the total read count table is greater than a first read count threshold, to notify a predetermined processing program to perform data inspection and relocation of the storage blocks in the corresponding logical group.

8. A method for recording the number of reads of a storage block, applied to a controller of a flash memory, the flash memory including flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple storage blocks, and all storage blocks being divided into multiple logical groups, the method comprising: Receive feedback on the result of the read command from the flash memory chip; Based on the target storage block determined by the feedback results, increase the read count of the target storage block and update the maximum read count of the logical group to which the target storage block belongs; as well as When it is determined that the maximum number of reads in the logical group where the target storage block is located exceeds the first read count threshold, a notification is sent to a predetermined program so that the predetermined program can perform data checks and relocation on the storage blocks in the corresponding logical group.

9. The method for recording the number of reads of a storage block according to claim 8, wherein, In the steps of increasing the read count of the target storage block and updating the maximum read count of the logical group to which the target storage block belongs, A temporary read count table is used to store the read count of the target storage block and the maximum read count of the logical group to which the target storage block belongs. When the maximum read count of the logical group to which the target storage block belongs exceeds the second read count threshold, the maximum read count of the logical group to which the target storage block belongs in the temporary read count table is increased to the maximum read count of the logical group to which the target storage block belongs in the total read count table. The total read count table only records the maximum read count of each logical group.

10. A flash memory comprising a storage medium and a controller, wherein the controller is the controller according to any one of claims 1 to 8, the storage medium comprising flash memory chips coupled to the controller, each flash memory chip being divided into multiple planes, each plane being divided into multiple memory blocks, all memory blocks being divided into multiple logical groups, and memory blocks with the same sequence number in all planes being grouped into the same logical group.

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