A timing calibration method and system for a serial flash memory device

Abstract

The application provides a timing calibration method and system for a serial flash memory device, comprising: a central processing unit controlling a flash memory controller to read first data from the serial flash memory device at a current operating frequency of the serial flash memory device according to a first sampling parameter saved by the central processing unit; then controlling the flash memory controller to adjust the current operating frequency of the serial flash memory device to a desired operating frequency input from outside; further controlling the flash memory controller to read second data from the serial flash memory device according to a second sampling parameter, and when the second data is inconsistent with the first data, continuously adjusting the second sampling parameter according to the desired operating frequency to delay the sampling time of the flash memory controller until the second data is consistent with the first data, and then saving the corresponding second sampling parameter. The beneficial effect is that the flash memory controller can support a higher upper limit of the clock frequency of the serial flash memory device, a wider clock frequency range, and more memory models.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip design technology, and in particular to a timing calibration method and system for a serial flash memory device. Background Technology

[0002] SPI (Serial Peripheral Interface) is a serial peripheral interface, and SPI Flash is a Flash memory that operates through this interface. In recent years, with the rise of the Internet of Things (IoT), SPI Flash has become increasingly popular among System-on-Chips (SoCs) manufacturers due to its low cost, high reliability, and ease of integration. The flash memory controller is a crucial bridge for communication between the SoC and SPI Flash. Currently, the maximum clock frequency supported by SPI Flash on the market is generally around 100MHz. A key consideration for chip designers when designing the interaction logic between the flash memory controller and SPI Flash is ensuring that the flash memory controller can communicate normally with the SPI Flash at the fastest possible Flash clock speed. However, simply increasing the clock frequency output to the SPI Flash is unreliable. This is because, as two chips packaged together, the transmission delay caused by the connecting wires between the SoC and SPI Flash can be significant enough to be easily ignored. If the flash memory controller still uses the default sampling time point after increasing the SPI Flash clock frequency, it may fail to sample the correct data.

[0003] To address this, existing technologies often take a digital circuit back-end design approach, introducing compensation circuits between the flash memory controller and the SPI Flash, and during the placement and routing process, keeping the pins for communication between the SoC and the SPI Flash as close as possible to minimize transmission delay caused by wires.

[0004] While the above method ensures normal communication between the flash controller and SPI Flash at higher clock frequencies, its drawbacks are also significant: this method heavily relies on the back-end layout and routing of the digital circuitry, and is highly dependent on factors such as the SoC chip manufacturing process, Flash chip manufacturing process, and the material and length of the wires connecting the SoC and Flash, resulting in limited versatility. For example, this solution claims to achieve stable read / write speeds of 120MHz for SPI Flash on a 40nm SoC, which is currently the highest speed achievable by mainstream SPI Flash. However, if manufacturing processes need to be changed due to certain factors, or if the digital back-end cannot achieve ideal layout and routing, it may result in the inability to operate the SPI Flash at the highest supported read / write speed. Alternatively, if SPI Flash with a maximum clock speed greater than 120MHz becomes available on the market in the future, SoCs designed using this approach may face the need to redesign and optimize their back-end chip design. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a timing calibration method for a serial flash memory device, wherein the serial flash memory device is connected to a system-on-a-chip (SoC), and the SoC includes a flash memory controller and a central processing unit (CPU) connected to the flash memory controller; the timing calibration method includes:

[0006] Step S1: When timing calibration of the serial flash memory device is required, the central processing unit controls the flash memory controller to read a first data at the current operating frequency of the serial flash memory device according to a first sampling parameter stored in the controller.

[0007] Step S2, the central processing unit controls the flash memory controller to adjust the current operating frequency of the serial flash memory device to a desired operating frequency input from an external source;

[0008] Step S3: The central processing unit controls the flash memory controller to read second data from the serial flash memory device operating at the desired operating frequency according to a second sampling parameter. The address range of the second data is consistent with that of the first data, and it is determined whether the second data is consistent with the first data.

[0009] If so, save the corresponding second sampling parameter and then exit;

[0010] If not, proceed to step S4;

[0011] In step S4, the central processing unit adjusts the second sampling parameter according to the desired operating frequency to delay the sampling time of the flash memory controller, and then returns to step S3.

[0012] Preferably, a timing calibration program is pre-configured in the serial flash memory device;

[0013] In step S1, when timing calibration of the serial flash memory device is required, the timing calibration program is first copied to the random access memory of the central processing unit, and then the execution of the timing calibration program is performed to continue executing step S1.

[0014] Preferably, the flash memory controller is equipped with a clock generator unit, which is connected to the input clock pin of the serial flash memory device;

[0015] In step S2, the flash memory controller acts on the input clock pin of the serial flash memory device through the clock generator unit to adjust the current operating frequency of the serial flash memory device to the desired operating frequency.

[0016] Preferably, before executing step S3 for the first time, the central processing unit first resets the second sampling parameter to its default value.

[0017] Preferably, each time step S4 is executed, the central processing unit adjusts the second sampling parameter to delay the sampling time of the flash memory controller according to a preset time period.

[0018] Preferably, the second sampling parameter includes a sampling edge and a sampling delay period, and the flash memory controller is configured with a sampling edge controller and a sampling delay controller;

[0019] In step S4, the central processing unit adjusts the sampling edge by controlling the sampling edge controller and / or adjusts the sampling delay period by controlling the sampling delay controller, so as to adjust the second sampling parameter according to the desired operating frequency.

[0020] Preferably, the desired working frequency corresponds to a desired working cycle, and the preset time period is half of the desired working cycle.

[0021] Preferably, the sampling edge controller and the sampling delay controller are each configured with a register interface;

[0022] In step S4, the central processing unit controls the sampling edge controller and the sampling delay controller through the corresponding register interfaces.

[0023] Preferably, the desired operating frequency is higher than the current operating frequency of the serial flash memory device in step S1.

[0024] The present invention also provides a timing calibration system for a serial flash memory device, which applies the above-described timing calibration method. The timing calibration system includes:

[0025] Serial flash memory device, connected to a single system chip;

[0026] The system-on-a-chip includes a flash memory controller and a central processing unit connected to the flash memory controller, the central processing unit including:

[0027] The first sampling module is used to control the flash memory controller to read a first data at the current operating frequency of the serial flash memory device according to a first sampling parameter stored in itself when timing calibration of the serial flash memory device is required;

[0028] A frequency adjustment module, connected to the first sampling module, is used to control the flash memory controller to adjust the current operating frequency of the serial flash memory device to a desired operating frequency input from an external source.

[0029] The second sampling module is connected to the first sampling module and the frequency adjustment module respectively. It is used to control the flash memory controller to read a second data from the serial flash memory device operating at the desired operating frequency according to a second sampling parameter. The address range of the second data is consistent with the first data. When it is determined that the second data is consistent with the first data, the corresponding second sampling parameter is saved. When it is determined that the second data is inconsistent with the first data, an adjustment signal is output.

[0030] A timing calibration module, connected to the second sampling module, is used to continuously adjust the second sampling parameters according to the desired operating frequency, so as to continuously delay the sampling time of the flash controller until the second data read by the second sampling module is consistent with the first data.

[0031] The above technical solution has the following advantages or beneficial effects:

[0032] 1) Enables the flash controller to support higher upper limits of serial flash device clock frequencies, a wider range of serial flash device clock frequencies, and more serial flash device models under complex conditions;

[0033] 2) It only involves the digital circuit front-end design scope of chip design, hardly requires the support of analog circuits, and is not related to the digital circuit back-end design, chip process, etc. It has a simple structure and strong feasibility. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating the timing calibration method in a preferred embodiment of the present invention.

[0035] Figure 2 A schematic diagram of the timing calibration system in a preferred embodiment of the present invention;

[0036] Figure 3 In a preferred embodiment of the present invention, a schematic diagram of the interaction timing between the flash memory controller and the serial flash memory device at the current operating frequency is provided.

[0037] Figure 4 In a preferred embodiment of the present invention, a schematic diagram of the interaction timing between the flash memory controller and the serial flash memory device is provided that the serial flash memory device is operating at its current operating frequency, and the clock of the serial flash memory device is increased to the desired operating frequency. Detailed Implementation

[0038] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0039] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a timing calibration method for a serial flash memory device is provided, such as... Figure 1 and Figure 2 As shown, a serial flash memory device 1 is connected to a system-on-a-chip 2, the system-on-a-chip 2 including a flash memory controller 21 and a central processing unit 22 connected to the flash memory controller 21; then the timing calibration method includes:

[0040] Step S1: When timing calibration of the serial flash memory device is required, the central processing unit controls the flash memory controller to read a first data at the current operating frequency of the serial flash memory device according to a first sampling parameter stored in the controller.

[0041] Step S2: The central processing unit controls the flash memory controller to adjust the current operating frequency of the serial flash memory device to the desired operating frequency of an external input.

[0042] Step S3: The central processing unit controls the flash memory controller to read second data from the serial flash memory device operating at the desired operating frequency according to a second sampling parameter. The address range of the second data is consistent with that of the first data, and it is determined whether the second data is consistent with the first data.

[0043] If so, save the corresponding second sampling parameters and then exit;

[0044] If not, proceed to step S4;

[0045] In step S4, the central processing unit adjusts the second sampling parameter according to the desired operating frequency to delay the sampling time of the flash memory controller, and then returns to step S3.

[0046] Specifically, in this embodiment, if timing calibration is required after the central processing unit 22 is powered on, timing calibration of the flash memory device can be triggered by inputting a timing calibration command to the central processing unit 22. The first sampling parameters stored by the flash memory controller 21 are parameters that allow for correct read and write operations at the current operating frequency of the serial flash memory device 1. Based on this, the first data read by the flash memory controller 21 using its stored first sampling parameters at the current operating frequency of the serial flash memory device 1 can be considered reliable and can be used as reference data for subsequent timing calibration processes. Preferably, an address range can be preset, and the aforementioned first data and second data are both data within the preset address range.

[0047] Preferably, the central processing unit 22 can establish communication with a human-machine interface. When timing calibration is required, the user can input timing calibration commands through the human-machine interface and view the timing calibration results. The aforementioned desired operating frequency can be configured according to requirements, preferably not exceeding the highest frequency of data read supported by the corresponding serial flash memory device 1. Before timing calibration, the clock frequency of the serial flash memory device 1 is first adjusted to the desired operating frequency, and then the sampling frequency of the flash memory controller 21 is calibrated according to this desired operating frequency.

[0048] In this embodiment, the sampling time of the flash memory controller 21 is delayed by continuously adjusting the second sampling parameter. This causes the second data read under the adjusted second sampling parameter to continuously change until it matches the first data. This indicates that the sampling frequency of the flash memory controller 21 has been successfully calibrated. The calibrated serial flash memory device 1 can work normally at the desired operating frequency. In other words, it ensures that the flash memory controller 21 can still sample the correct data even when the clock frequency of the serial flash memory device 1 is adjusted. It is understood that the first sampling parameter and the second sampling parameter can be represented by the same parameter variable.

[0049] In a preferred embodiment of the present invention, a timing calibration program is pre-configured in the serial flash memory device 1;

[0050] In step S1, when timing calibration of the serial flash memory device is required, the timing calibration program is first copied to the random access memory unit of the central processing unit 22, and then the timing calibration program is executed to continue executing step S1.

[0051] Specifically, in this embodiment, it can be understood that after completing the timing calibration process for the serial flash memory device 1, the timing calibration program is exited and the program before receiving the timing calibration instruction is executed. That is, in step S3, preferably when the second data is consistent with the first data, the timing calibration result of successfully adjusting the clock frequency of the flash memory controller to the desired operating frequency is output, and the corresponding second sampling parameters are saved. Then, the timing calibration program is exited and the program before receiving the timing calibration instruction is executed is executed.

[0052] In a preferred embodiment of the present invention, a clock generator unit 211 is configured in the flash memory controller 21 and connected to the input clock pin of the serial flash memory device 1;

[0053] In step S2, the flash memory controller 21 acts on the input clock pin of the serial flash memory device 1 through the clock generator unit 211 to adjust the current operating frequency of the serial flash memory device 1 to the desired operating frequency.

[0054] Specifically, the flash memory controller 21 can also be configured with clock output logic. The clock generator unit 211 is connected to the input clock pin of the serial flash memory device 1 through this clock output logic. The clock generator unit 211 generates a configurable high-speed clock, which acts on the clock output logic and serves as the clock source for operating the serial flash memory device 1. Preferably, the clock generator unit 211 also provides an external clock input port, and can also generate a configurable high-speed clock based on an external clock configured through this external clock port. It is understood that the high-speed clock configured based on the external clock is the clock frequency at which the serial flash memory device 1 can perform normal read and write operations without timing calibration. More preferably, the high-speed clock is not limited by the system clock of the central processing unit 22; that is, the frequency of the configurable high-speed clock generated by the clock generator unit 211 can be greater than, equal to, or less than the frequency of the system clock. The clock generator unit 211 is preferably implemented through corresponding hardware circuitry. The specific circuit structure of this hardware circuitry is not limited, as long as it can achieve the above functions.

[0055] In a preferred embodiment of the present invention, before the first execution of step S3, the central processing unit first resets the second sampling parameter to a default value;

[0056] In step S4, the central processing unit adjusts the second sampling parameter based on the default value according to the desired operating frequency.

[0057] Specifically, in this embodiment, in order to avoid the serial flash memory device 1 being calibrated and causing the second sampling parameter to be the parameter after the last timing calibration to affect the current timing calibration, it is preferable to reset the second sampling parameter to the default value before executing step S3. The default value can be a sampling value that is compatible with the high-speed clock of the serial flash memory device 1 generated based on the external clock.

[0058] In a preferred embodiment of the present invention, each time step S4 is executed, the central processing unit adjusts the second sampling parameter to delay the sampling time of the flash memory controller according to a preset time period.

[0059] In a preferred embodiment of the present invention, the desired operating frequency corresponds to a desired operating cycle, and the preset time period is half a desired operating cycle.

[0060] In a preferred embodiment of the present invention, the second sampling parameter includes a sampling edge and a sampling delay period, and the flash memory controller 21 is configured with a sampling edge controller 212 and a sampling delay controller 213;

[0061] In step S4, the central processing unit 22 adjusts the sampling edge by controlling the sampling edge controller 212 and / or adjusts the sampling delay period by controlling the sampling delay controller 213, so as to adjust the second sampling parameter according to the desired operating frequency.

[0062] In a preferred embodiment of the present invention, the sampling edge controller 212 and the sampling delay controller 213 are respectively configured with register interfaces;

[0063] In step S4, the central processing unit 2 controls the sampling edge controller 212 and the sampling delay controller 213 through the corresponding register interfaces.

[0064] Specifically, in this embodiment, the sampling edge controller 212 and sampling delay controller 213 are preferably implemented by corresponding hardware circuits. The specific circuit structure of these hardware circuits is not limited, as long as they can achieve the above functions. If, at the current operating frequency, the interaction timing between the flash memory controller 21 and the serial flash memory device 1 is as follows... Figure 3 As shown, the flash controller 21 outputs a falling edge of the clock at time P0. Since there is a distance between the flash controller 21 and the serial flash device 1, a transmission delay t1 is generated. After that, the serial flash device 1 receives the falling edge of the clock and starts sending data to the output pin. Since the internal circuit also needs time to operate, a delay t2 is generated. After that, the data sent by the serial flash device 1 is sent to the port of the flash controller 21 after a transmission delay t3 of a wire. Finally, at the first rising edge (i.e., P1) after the falling edge P0, the flash controller 21 samples and latches the input data at the port of the flash controller 21.

[0065] During the above process, for the flash memory controller 21 to be able to correctly sample and latch the data sent by the serial flash memory device 1 at time P1, the premise is that the Flash clock characteristics satisfy the following inequality:

[0066] P1 - P0 > t1 + t2 + t3

[0067] In other words, as long as the above inequality is satisfied, the flash memory controller 21 can normally interact with the serial flash memory device 1. It should be emphasized that usually, designers can relatively easily design a flash memory controller 21 that meets the above timing requirements. When the delay t1 + t2 + t3 is determined, it only needs to reduce the clock frequency of the default serial flash memory device 1 to achieve this.

[0068] On the premise that the serial flash memory device 1 is already operating at a slower clock frequency (i.e., the current operating frequency), when the clock of the serial flash memory device 1 is increased to a faster frequency (i.e., the desired operating frequency), the interaction timing between the flash memory controller 21 and the serial flash memory device 1 is as Figure 4 shown.

[0069] Since the clock frequency of the serial flash memory device 1 increases while the delays t1, t2, and t3 remain unchanged, a situation of P1 - P0 < t1 + t2 + t3 occurs. At this time, if the flash memory controller 21 still attempts to sample and latch at time P1, it is obvious that the correct result cannot be obtained. At this time, it is necessary to use the timing calibration method and system disclosed in the present invention to find a suitable sampling time point:

[0070] First, by configuring the register interfaces corresponding to the sampling edge controller and the sampling delay controller, the time point for the flash memory controller 21 to sample and latch data is reset to time P1 (i.e., the default value). It is found that the sampled data is inconsistent with the expected data, so this sampling point is considered invalid. Then, the time for the flash memory controller 21 to sample and latch data is configured to time P2, and it is found that the sampled data is still inconsistent with the expected data, so this sampling point is also considered invalid. Then, continue to modify the time when the flash memory controller 21 samples and latches data until it is found that a certain configuration can correctly read the expected data. For Figure 4 the situation shown, when the time for the flash memory controller 21 to sample and latch data is time P3, it can be found that the latched data is consistent with the expectation at this time. Repeating the above operations at different clock frequencies of the serial flash memory device 1, a calibration parameter table at different clock frequencies of the serial flash memory device 1 can be obtained, which is convenient for subsequent applications.

[0071] Among them, the process of the central processing unit adjusting the sampling parameters according to the desired operating frequency by controlling the sampling edge controller to adjust the sampling edge and / or by controlling the sampling delay controller to adjust the sampling delay period specifically includes:

[0072] The sampling edges mentioned above can preferably be represented using an edge dataset containing 0 and 1, where 0 represents a rising edge and 1 represents a falling edge; the sampling delay period can be represented using a period dataset containing {0, 1, ..., n}, where 0 represents half a desired working cycle, 1 represents one desired working cycle, 2 represents 1.5 desired working cycles, and n represents (n+1)*0.5 desired working cycles. The sampling parameters can be adjusted by permuting and combining the edge dataset and the period dataset.

[0073] The specific adjustment process for the sampling parameters is illustrated by taking an adjustment period of half the expected working cycle as an example. Figure 4 As shown, the current sampling time P0 is the falling edge. The first adjustment is half of the expected working cycle, which is to adjust to P1. Then the sampling edge needs to be adjusted to the falling edge, and the sampling delay period needs to be adjusted to half of the expected working cycle. If the second data is still inconsistent with the first data at this time, it needs to be adjusted from P0 to P2. At this time, the sampling edge remains unchanged, and it only needs to be adjusted by one expected working cycle. And so on.

[0074] In a preferred embodiment of the present invention, it is desirable that the operating frequency is higher than the current operating frequency of the serial flash memory device in step S1.

[0075] This invention also provides a timing calibration system for a serial flash memory device, which applies the timing calibration method described above, such as... Figure 2 As shown, the timing calibration system includes:

[0076] Serial flash memory device 1 is connected to an on-system 2;

[0077] System-on-a-chip 2 includes a flash memory controller 21 and a central processing unit 22 connected to the flash memory controller 21. The central processing unit 22 includes:

[0078] The first sampling module 221 is used to control the flash memory controller 21 to read a first data at the current operating frequency of the serial flash memory device 1 according to a first sampling parameter stored in itself when timing calibration of the serial flash memory device 1 is required.

[0079] The frequency adjustment module 222 is connected to the first sampling module 221 and is used to control the flash memory controller 21 to adjust the current operating frequency of the serial flash memory device 1 to a desired operating frequency input from an external source.

[0080] The second sampling module 223 is connected to the first sampling module 221 and the frequency adjustment module 222 respectively. It is used to control the flash memory controller 21 to read a second data from the serial flash memory device 1 operating at the desired operating frequency according to a second sampling parameter. The address range of the second data is consistent with the first data. When it is determined that the second data is consistent with the first data, the corresponding second sampling parameter is saved. When it is determined that the second data is inconsistent with the first data, an adjustment signal is output.

[0081] The timing calibration module 224 is connected to the second sampling module 223 and is used to continuously adjust the second sampling parameters according to the desired operating frequency, so as to continuously delay the sampling time of the flash controller 21 until the second data read by the second sampling module 223 is consistent with the first data.

[0082] Specifically, in this embodiment, the first sampling module 221, frequency adjustment module 222, second sampling module 223 and timing calibration module 224 are implemented by software programs.

[0083] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A method of timing calibration of a serial flash memory device, characterized by, The serial flash memory device is connected with a system on chip, the system on chip comprises a flash memory controller and a central processing unit connected with the flash memory controller; the timing calibration method comprises the following steps: In step S1, when timing calibration of the serial flash memory device is needed, the central processing unit controls the flash memory controller to read a first data from the serial flash memory device at a current working frequency of the serial flash memory device according to a first sampling parameter saved by itself; In step S2, the central processing unit controls the flash memory controller to adjust the current working frequency of the serial flash memory device to a desired working frequency inputted from outside; In step S3, the central processing unit controls the flash memory controller to read a second data from the serial flash memory device working at the desired working frequency according to a second sampling parameter, the address range of the second data is consistent with that of the first data, and judges whether the second data is consistent with the first data: If yes, the corresponding second sampling parameter is saved, and then the process is exited; If no, the process is transferred to step S4; In step S4, the central processing unit adjusts the second sampling parameter according to the desired working frequency to delay the sampling time of the flash memory controller, and then returns to step S3. The first sampling parameter is a parameter that can correctly perform read / write operation at the current working frequency of the serial flash memory device, and the second sampling parameter comprises a sampling edge and a sampling delay period.

2. The timing calibration method of claim 1, wherein, The serial flash memory device is pre-configured with a timing calibration program; In step S1, when timing calibration of the serial flash memory device is needed, the timing calibration program is first copied to the random access memory unit of the central processing unit, and then the timing calibration program is executed to continue step S1.

3. The timing calibration method of claim 1, wherein, The flash memory controller is configured with a clock generator unit connected with the input clock pin of the serial flash memory device; In step S2, the flash memory controller adjusts the current working frequency of the serial flash memory device to the desired working frequency by acting on the input clock pin of the serial flash memory device through the clock generator unit.

4. The timing calibration method of claim 1, wherein, Before step S3 is executed for the first time, the central processing unit first resets the second sampling parameter to a default value.

5. The timing calibration method of claim 1, wherein, In each execution of step S4, the central processing unit adjusts the second sampling parameter to delay the sampling time of the flash memory controller according to a preset time period.

6. The timing calibration method of claim 1 or 5, wherein, The flash memory controller is configured with a sampling edge controller and a sampling delay controller; In step S4, the central processing unit adjusts the sampling edge by controlling the sampling edge controller and / or adjusts the sampling delay period by controlling the sampling delay controller to adjust the second sampling parameter according to the desired working frequency.

7. The timing calibration method of claim 5, wherein, The desired working frequency corresponds to a desired working period, and the preset time period is half of the desired working period.

8. The timing calibration method of claim 6, wherein, The sampling edge controller and the sampling delay controller are respectively configured with register interfaces; The central processor controls the sampling edge controller and the sampling delay controller through the corresponding register interface respectively in the step S4.

9. The method for timing calibration of claim 1, wherein, The expected working frequency is higher than the current working frequency of the serial flash device in the step S1.

10. A timing calibration system for a serial flash memory device, comprising: The timing calibration system comprises: A serial flash device connected to a system on chip; The system on chip comprises a flash controller and a central processor connected to the flash controller, and the central processor comprises: A first sampling module for controlling the flash controller to read a first data from the serial flash device at a current working frequency according to a first sampling parameter saved by the flash controller when timing calibration of the serial flash device is needed; A frequency adjustment module connected to the first sampling module for controlling the flash controller to adjust the current working frequency of the serial flash device to an expected working frequency inputted from outside; A second sampling module connected to the first sampling module and the frequency adjustment module respectively for controlling the flash controller to read a second data from the serial flash device working at the expected working frequency according to a second sampling parameter, the address range of the second data being consistent with that of the first data, and saving the corresponding second sampling parameter when the second data is consistent with the first data, and outputting an adjustment signal when the second data is not consistent with the first data; A timing calibration module connected to the second sampling module for continuously adjusting the second sampling parameter according to the expected working frequency to constantly delay the sampling time of the flash controller until the second data read by the second sampling module is consistent with the first data.

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