Instruction out-of-order transmitting method and device, equipment and medium

Abstract

The invention discloses an instruction out-of-order transmitting method and device, equipment and a medium, and relates to the field of instruction processing, and the method comprises the steps that a universal graphics processor obtains a plurality of to-be-transmitted instructions from an instruction cache, and constructs a dependency matrix based on the dependency relationship between each to-be-transmitted instruction and other to-be-transmitted instructions; the other to-be-transmitted instructions are instructions, the generation time of which is earlier than that of each to-be-transmitted instruction, in the plurality of to-be-transmitted instructions; determining a target to-be-transmitted instruction from the plurality of to-be-transmitted instructions by using the dependency matrix and based on the priority corresponding to each instruction; the target to-be-transmitted instruction is an instruction which does not have a dependency relationship with other instructions in the plurality of to-be-transmitted instructions and has the highest priority; and transmitting the target to-be-transmitted instruction to an instruction processing unit in the general graphic processor for processing. According to the method, efficient out-of-order emission of the instructions can be achieved through the dependency matrix, the utilization rate of processor resources is increased, and quick response to some important instructions is achieved according to the priority.

Description

Technical Field

[0001] The present invention relates to the field of instruction processing, and particularly to an instruction out-of-order issue method, apparatus, device and medium. Background Art

[0002] In the traditional execution mode of GPGPU (General-Purpose computing on Graphics Processing Units), instructions are usually fetched and executed sequentially from the instruction buffer in the order of program writing. However, this sequential execution method may cause the instruction pipeline to stall due to data dependencies between instructions, such as RAW (Read After Write), WAW (Write After Write), WAR (Write After Read), etc., thereby reducing the processing efficiency of instructions. For example, when an instruction needs to wait for the calculation result of the previous instruction as an operand (RAW dependency), in the sequential execution mode of instructions, all subsequent instructions must be suspended until the previous instruction is processed, which will cause idle and waste of processor resources to a certain extent. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an instruction out-of-order issue method, apparatus, device and medium, which can preferentially issue the instructions that have no dependencies with other instructions and have the highest priority to the instruction processing unit for processing, realize efficient out-of-order issue of instructions, improve the utilization rate of processor resources, and achieve fast response to some important instructions according to the priority. The specific solutions are as follows:

[0004] In a first aspect, the present application provides an instruction out-of-order issue method, which is applied to a general graphics processor and includes:

[0005] Obtain a number of instructions to be issued from the instruction cache, and determine the dependency relationships between each instruction to be issued and other instructions to be issued; the other instructions to be issued are the instructions in the number of instructions to be issued whose generation time is earlier than that of each instruction to be issued;

[0006] Construct a dependency matrix based on the dependency relationships between each instruction to be issued and the other instructions to be issued;

[0007] Determine a target instruction to be issued from the number of instructions to be issued by using the dependency matrix and based on the priorities corresponding to the respective instructions; the target instruction to be issued is the instruction that has no dependency relationship with other instructions in the number of instructions to be issued and has the highest priority;

[0008] Transmit the target instruction to be launched to the instruction processing unit in the general graphics processor for processing.

[0009] Optionally, before obtaining a number of instructions to be launched from the instruction cache, it further includes:

[0010] Take out instructions from the preset memory in the order of generation, and decode the currently taken out instruction to obtain instruction parameters corresponding to the currently taken out instruction; the instruction parameters include the instruction type and the identifier of the register required by the instruction; the registers required by the instruction include source registers and destination registers;

[0011] Based on the instruction parameters corresponding to the currently taken out instruction, fill the corresponding fields in the data structure corresponding to the currently taken out instruction, and by newly adding a priority field and a launch field in the data structure, fill the priority field based on the priority identifier corresponding to the priority of the currently taken out instruction, and fill the launch field based on the first launch identifier indicating that the instruction has not been launched, so as to obtain the filled data structure; where different priorities correspond to different priority identifiers;

[0012] Store the currently taken out instruction and the corresponding filled data structure into the instruction cache.

[0013] Optionally, obtaining a number of instructions to be launched from the instruction cache includes:

[0014] Determine the unlaunched instructions from the instruction cache; the launch identifier of the unlaunched instructions is the first launch identifier;

[0015] Select a preset number of instructions from the unlaunched instructions in the order of generation to obtain a number of instructions to be launched.

[0016] Optionally, determining the dependency relationship between each instruction to be launched and other instructions to be launched includes:

[0017] Based on the instruction types corresponding to each instruction to be launched and other instructions to be launched, determine the dependency relationship between each instruction to be launched and other instructions to be launched;

[0018] And / or, based on the identity between the identifiers of the registers required by each instruction to be launched and other instructions to be launched, determine the dependency relationship between each instruction to be launched and other instructions to be launched.

[0019] Optionally, after transmitting the target instruction to be launched to the instruction processing unit in the general graphics processor for processing, it further includes:

[0020] Change the transmission identifier of the target instruction to be transmitted from the first transmission identifier to a second transmission identifier indicating that the instruction has been transmitted, and then return to the step of obtaining a number of instructions to be transmitted from the instruction cache.

[0021] Optionally, after determining the target instruction to be transmitted from the number of instructions to be transmitted, the method further includes:

[0022] If the number of target instructions to be transmitted is multiple, determine the instruction with the earliest generation time from the multiple target instructions to be transmitted as the target instruction to be finally transmitted.

[0023] Optionally, the method further includes:

[0024] When detecting an instruction pipeline flush operation, determine the flushed instructions corresponding to the instruction pipeline flush operation;

[0025] Delete the flushed instructions and / or the instructions that depend on the flushed instructions from the current instructions used to construct the dependency matrix;

[0026] Based on the number of deleted instructions, obtain a corresponding number of new instructions to be transmitted from the instruction cache, and reconstruct the dependency matrix using the new instructions to be transmitted and the undeleted instructions in the current instructions used to construct the dependency matrix.

[0027] In a second aspect, the present application provides an instruction out-of-order transmission device applied to a general-purpose graphics processor, including:

[0028] A dependency relationship determination module, configured to obtain a number of instructions to be transmitted from an instruction cache and determine the dependency relationship between each instruction to be transmitted and other instructions to be transmitted; the other instructions to be transmitted are the instructions whose generation time is earlier than that of each instruction to be transmitted among the number of instructions to be transmitted;

[0029] A dependency matrix construction module, configured to construct a dependency matrix based on the dependency relationship between each instruction to be transmitted and the other instructions to be transmitted;

[0030] An instruction determination module, configured to use the dependency matrix and based on the priorities corresponding to each instruction, determine a target instruction to be transmitted from the number of instructions to be transmitted; the target instruction to be transmitted is the instruction that has no dependency relationship with other instructions among the number of instructions to be transmitted and has the highest priority;

[0031] An instruction transmission module, configured to transmit the target instruction to be transmitted to an instruction processing unit in the general-purpose graphics processor for processing.

[0032] In a third aspect, the present application provides an electronic device, including:

[0033] a memory for storing a computer program;

[0034] a processor for executing the computer program to implement the foregoing instruction out-of-order issue method.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, and when the computer program is executed by a processor, the foregoing instruction out-of-order issue method is implemented.

[0036] In the present application, a general graphics processor obtains a number of instructions to be issued from an instruction cache, and determines the dependency relationship between each instruction to be issued and other instructions to be issued; the other instructions to be issued are instructions whose generation time is earlier than that of each instruction to be issued among the number of instructions to be issued; based on the dependency relationship between each instruction to be issued and the other instructions to be issued, a dependency matrix is constructed; using the dependency matrix and based on the priorities corresponding to each instruction, a target instruction to be issued is determined from the number of instructions to be issued; the target instruction to be issued is an instruction that has no dependency relationship with other instructions among the number of instructions to be issued and has the highest priority; the target instruction to be issued is issued to an instruction processing unit in the general graphics processor for processing. It can be seen that the present application constructs a dependency matrix based on the dependency relationship between instructions, so as to preferentially issue an instruction that has no dependency relationship with other instructions and has the highest priority to the instruction processing unit for processing based on the dependency matrix and the priorities corresponding to each instruction, thereby dynamically adjusting the processing order of instructions, realizing efficient out-of-order issue of instructions, and compared with the way of sequential instruction issue, it can significantly improve the utilization rate of processor resources, and can realize fast response to some important instructions according to the priorities, meeting the diverse requirements for instruction issue. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings according to the provided drawings without creative efforts.

[0038] Figure 1 It is a flowchart of an instruction out-of-order issue method disclosed in the present application;

[0039] Figure 2 It is a schematic diagram of a dependency matrix disclosed in the present application;

[0040] Figure 3A flowchart of out-of-order instruction issue disclosed in this application;

[0041] Figure 4 A schematic structural diagram of an out-of-order instruction issue device disclosed in this application;

[0042] Figure 5 A structural diagram of an electronic device disclosed in this application. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] In the traditional GPGPU execution mode, instructions are usually fetched and executed sequentially from the instruction buffer in the order of program writing. However, this sequential execution method may cause the instruction pipeline to stall due to data dependency relationships between instructions, thereby reducing the processing efficiency of instructions. To this end, this application provides an out-of-order instruction issue method, which dynamically adjusts the processing order of instructions by preferentially issuing the instructions that have no dependency relationship with other instructions and have the highest priority to the instruction processing unit for processing, so as to achieve efficient out-of-order issue of instructions, improve the utilization rate of processor resources, and can also achieve fast response to some important instructions according to the priority.

[0045] See Figure 1 As shown, an out-of-order instruction issue method disclosed in an embodiment of the present invention is applied to a general-purpose graphics processor and includes:

[0046] Step S11: Obtain a plurality of instructions to be issued from the instruction cache, and determine the dependency relationship between each instruction to be issued and other instructions to be issued; the other instructions to be issued are the instructions among the plurality of instructions to be issued whose generation time is earlier than that of each instruction to be issued.

[0047] In an embodiment of the present invention, before a general - purpose graphics processor fetches a number of instructions to be issued from an instruction cache, it needs to first fetch instructions from a preset memory in the order of generation one by one, and decode the currently fetched instruction to obtain instruction parameters corresponding to the currently fetched instruction. Then, based on the instruction parameters corresponding to the currently fetched instruction, corresponding fields in the data structure corresponding to the currently fetched instruction are filled, and by newly adding a priority field and an issue field in the data structure, the priority field is filled based on a priority identifier corresponding to the priority of the currently fetched instruction, and the issue field is filled based on a first issue identifier indicating that the instruction has not been issued, so as to obtain a data structure with filling completed. After that, the currently fetched instruction and the corresponding data structure with filling completed are stored in the instruction cache. It should be noted that different priorities correspond to different priority identifiers, and the priority identifiers can be represented by binary numbers.

[0048] The instruction parameters include an instruction type and an identifier of a register required by the instruction. Among them, the registers required by the instruction include source registers and destination registers. The source registers are used to store source operands required by the instruction, and the destination registers are used to store results obtained after the instruction is processed. And, the instruction types include load instructions and store instructions. The load instructions are used to read data from the memory into the registers, and the store instructions are used to write data in the registers into the memory.

[0049] Further, the general - purpose graphics processor fetches a number of instructions to be issued from the instruction cache, and determines the dependency relationships between each instruction to be issued and other instructions to be issued whose generation time is earlier than that of each instruction to be issued. Among them, the dependency relationships between each instruction to be issued and other instructions to be issued include two cases: there is a dependency relationship and there is no dependency relationship. When there is a dependency relationship between each instruction to be issued and other instructions to be issued, it means that each instruction to be issued depends on other instructions to be issued.

[0050] For example, a number of instructions to be issued include instruction 0, instruction 1, instruction 2, and instruction 3. And, the generation time of instruction 0 is earlier than that of instruction 1, the generation time of instruction 1 is earlier than that of instruction 2, and the generation time of instruction 2 is earlier than that of instruction 3. At this time, if each instruction to be issued is instruction 0, there are no other instructions to be issued; if each instruction to be issued is instruction 1, the other instruction to be issued is instruction 0; if each instruction to be issued is instruction 2, the other instructions to be issued are instruction 0 and instruction 1; if each instruction to be issued is instruction 3, the other instructions to be issued are instruction 0, instruction 1, and instruction 2.

[0051] According to one embodiment, obtaining a number of instructions to be issued from an instruction cache may include: determining, from the instruction cache, instructions with an issue flag being a first issue flag to obtain unissued instructions, that is, the issue flag of the unissued instructions is the first issue flag indicating that the instructions are not issued; and then selecting a preset number of instructions from the unissued instructions in the order of generation of the instructions to obtain a number of instructions to be issued.

[0052] It should be noted that the preset number can be either a pre-set value or a value dynamically adjusted according to the real-time resource usage of the general-purpose graphics processing unit. For example, if the current general-purpose graphics processing unit has more resource usage, the preset number can be dynamically adjusted to a smaller value; if the current general-purpose graphics processing unit has less resource usage, the preset number can be dynamically adjusted to a larger value. The amount of resource usage can be divided according to a pre-set usage rate. For example, if the resource usage rate of the current general-purpose graphics processing unit is greater than the pre-set usage rate, it indicates that the current general-purpose graphics processing unit has more resource usage; if the resource usage rate of the current general-purpose graphics processing unit is less than or equal to the pre-set usage rate, it indicates that the current general-purpose graphics processing unit has less resource usage. In this way, this embodiment can make the preset number more in line with the resource usage of the general-purpose graphics processing unit and improve the resource usage rate of the general-purpose graphics processing unit.

[0053] According to another embodiment, obtaining a number of instructions to be issued from an instruction cache may include: determining, from the instruction cache, instructions with an issue flag being a first issue flag to obtain a number of unissued instructions, and directly determining the number of unissued instructions as the number of instructions to be issued.

[0054] In one case, for determining the dependency relationship between each instruction to be issued and other instructions to be issued, the dependency relationship between each instruction to be issued and other instructions to be issued can be determined based on the respective instruction types of each instruction to be issued and other instructions to be issued.

[0055] Exemplarily, if the instruction type of each instruction to be issued is a load instruction and the instruction type of a certain instruction to be issued among other instructions to be issued is a store instruction, it is determined that there is a data dependency relationship between each instruction to be issued and the certain instruction to be issued.

[0056] Exemplarily, if the instruction type of each instruction to be issued is a store instruction and the instruction type of a certain instruction to be issued among other instructions to be issued is a load instruction or a store instruction, it is determined that there is a data dependency relationship between each instruction to be issued and the certain instruction to be issued.

[0057] In another case, for determining the dependency relationship between each instruction to be issued and other instructions to be issued, the dependency relationship between each instruction to be issued and other instructions to be issued can also be determined based on the identity between the identifiers of the registers required by each instruction to be issued and other instructions to be issued.

[0058] Specifically, it is determined whether there are identical identifiers among the identifiers of the registers required by each instruction to be issued and other instructions to be issued, and the dependency relationship between each instruction to be issued and other instructions to be issued is determined based on the judgment result.

[0059] Exemplarily, if the identifier of the source register required by each instruction to be issued is the same as the identifier of the destination register required by a certain instruction among other instructions to be issued, it is determined that there is a RAW dependency relationship between each instruction to be issued and a certain instruction to be issued.

[0060] Exemplarily, if the identifier of the destination register required by each instruction to be issued is the same as the identifier of the destination register required by a certain instruction among other instructions to be issued, it is determined that there is a WAW dependency relationship between each instruction to be issued and a certain instruction to be issued.

[0061] Exemplarily, if the identifier of the destination register required by each instruction to be issued is the same as the identifier of the source register required by a certain instruction among other instructions to be issued, it is determined that there is a WAR dependency relationship between each instruction to be issued and a certain instruction to be issued.

[0062] Step S12: Construct a dependency matrix based on the dependency relationship between each instruction to be issued and the other instructions to be issued.

[0063] In the embodiment of the present invention, after determining the dependency relationship between each instruction to be issued and other instructions to be issued, a dependency matrix is constructed based on the dependency relationship between each instruction to be issued and other instructions to be issued.

[0064] Wherein, the number of rows and columns of the dependency matrix is equal to the number of instructions of several instructions to be issued, and when there is a dependency relationship between each instruction to be issued and other instructions to be issued, the corresponding position in the dependency matrix is set to 1, otherwise it is set to 0.

[0065] Taking several instructions to be issued including instruction 0, instruction 1, instruction 2, and instruction 3 as an example, if there is a dependency relationship between instruction 1 and instruction 0, and there is a dependency relationship between instruction 3 and instruction 2, then the position in the second row and the first column and the position in the fourth row and the third column of the dependency matrix are set to 1, and the remaining positions are set to 0. The dependency matrix is specifically as Figure 2 shown.

[0066] Step S13: Determine a target instruction to be issued from the several instructions to be issued by using the dependency matrix and based on the priorities corresponding to the respective instructions; the target instruction to be issued is the instruction that has no dependency relationship with other instructions among the several instructions to be issued and has the highest priority.

[0067] Step S14: Issue the target instruction to be issued to the instruction processing unit in the general graphics processor for processing.

[0068] In an embodiment of the present invention, after the dependency matrix is constructed, an instruction that has no dependency relationship with other instructions is determined from several instructions to be issued by using the dependency matrix, and based on the priorities corresponding to the respective instructions, an instruction with the highest priority is determined from the instructions that have no dependency relationship with other instructions as the target instruction to be issued. That is, the target instruction to be issued is the instruction that has no dependency relationship with other instructions among the several instructions to be issued and has the highest priority.

[0069] It should be noted that if the number of target instructions to be issued is multiple, an instruction with the earliest generation time can be determined from the multiple target instructions to be issued as the target instruction to be finally issued, and the target instruction to be finally issued is issued to the instruction processing unit in the general graphics processor for processing. Further, after the instruction processing unit finishes processing the received instruction, the processing result is written back to the destination register corresponding to the received instruction.

[0070] Moreover, after the target instruction to be issued is issued to the instruction processing unit in the general graphics processor for processing, it is also necessary to change the issue flag of the target instruction to be issued from the first issue flag to the second issue flag indicating that the instruction has been issued, and then return to step S11 to continuously update the dependency matrix, so as to achieve efficient out-of-order issue of instructions.

[0071] It should be noted that the first issue flag and the second issue flag can be represented by binary numbers. For example, the first issue flag is 0 and the second issue flag is 1, or the first issue flag is 1 and the second issue flag is 0.

[0072] It should also be noted that the priority of each instruction can be set according to the urgency of the instruction, latency requirements, response requirements, etc. Specifically, based on the information carried by the instruction, the object of the instruction, the generation object of the instruction, etc., the urgency of the instruction, latency requirements, and response requirements are scored respectively to obtain the score values corresponding to the urgency of the instruction, latency requirements, and response requirements respectively. Then, through the weights preset for the urgency of the instruction, latency requirements, and response requirements respectively, the three score values are weighted and calculated to obtain the final score value of the instruction. Then, the priority of the instruction is determined according to the score range where the final score value is located; among them, different priorities correspond to different score ranges. In this way, through the above calculation method, not only can the determination of the instruction priority be realized, but also the scientificity and rationality of the instruction priority determination can be improved.

[0073] Furthermore, if an instruction pipeline flush operation is detected during the instruction emission process, the flushed instruction corresponding to the instruction pipeline flush operation is determined, and the flushed instruction and / or the instruction dependent on the flushed instruction are deleted from the instructions currently used to construct the dependency matrix; then, based on the number of deleted instructions, the corresponding number of new instructions to be emitted are obtained from the instruction cache, and the dependency matrix is reconstructed using the new instructions to be emitted and the undeleted instructions among the instructions currently used to construct the dependency matrix. In this way, in this embodiment, for the flushed instruction and the instruction dependent on the flushed instruction, they are removed from the dependency matrix, and new instructions are obtained from the instruction cache and filled into the dependency matrix. For the instructions that have no dependency relationship with the flushed instruction, they are retained in the dependency matrix, thus realizing the update of the dependency matrix.

[0074] It can be seen that this application constructs a dependency matrix based on the dependency relationships among instructions, and based on the dependency matrix and the priorities corresponding to each instruction, preferentially emits the instruction with the highest priority and no dependency relationship with other instructions to the instruction processing unit for processing, so that the processing order of instructions can be dynamically adjusted, realizing the efficient out-of-order emission of instructions. Compared with the way of in-order instruction emission, it can significantly improve the utilization rate of processor resources, and can quickly respond to some important instructions according to the priority, meeting the diverse requirements for instruction emission.

[0075] See Figure 3 As shown, an embodiment of the present invention discloses an instruction out-of-order emission method applied to a general-purpose graphics processor, including:

[0076] The instruction fetch unit in the general-purpose graphics processor sequentially fetches instructions from a preset memory in the order of instruction generation, and sends the currently fetched instruction to the decoding unit in the general-purpose graphics processor.

[0077] The decoding unit in the general-purpose graphics processor decodes the currently fetched instruction to obtain instruction parameters corresponding to the currently fetched instruction, and based on the instruction parameters corresponding to the currently fetched instruction, fills the corresponding fields in the data structure corresponding to the currently fetched instruction, and by newly adding a priority field and an issue field in the data structure, fills the priority field based on the priority identifier corresponding to the priority of the currently fetched instruction, and fills the issue field based on the first issue identifier indicating that the instruction has not been issued, so as to obtain the filled data structure, and then stores the currently fetched instruction and the corresponding filled data structure into the instruction cache.

[0078] The general-purpose graphics processor fetches a number of instructions to be issued from the instruction cache, and determines the dependency relationships between each instruction to be issued and other instructions to be issued whose generation times are earlier than each instruction to be issued, so as to construct a dependency matrix based on the dependency relationships.

[0079] The issue unit in the general-purpose graphics processor uses the dependency matrix and based on the priorities corresponding to the respective instructions, determines the target instruction to be issued from the number of instructions to be issued, and issues the target instruction to be issued fetched from the instruction cache to the instruction processing unit in the general-purpose graphics processor.

[0080] The instruction processing unit in the general-purpose graphics processor processes the received instruction, and sends the processing result to the write-back unit in the general-purpose graphics processor to write back the processing result to the instruction cache, and at the same time changes the issue identifier of the target instruction to be issued from the first issue identifier to the second issue identifier indicating that the instruction has been issued. At this time, it is also necessary to fetch a number of instructions to be issued from the instruction cache again to update the dependency matrix. It should be noted that the instruction processing unit can adopt the SIMT (Single Instruction Multiple Threads) architecture.

[0081] When the instruction flush detection unit in the general-purpose graphics processor detects an instruction pipeline flush operation, it determines the flushed instructions corresponding to the instruction pipeline flush operation, and deletes the flushed instructions and / or the instructions that depend on the flushed instructions from the currently used instructions for constructing the dependency matrix, and then fetches the corresponding number of new instructions to be issued from the instruction cache based on the number of deleted instructions, and uses the new instructions to be issued and the non-deleted instructions in the currently used instructions for constructing the dependency matrix to reconstruct the dependency matrix, so as to realize the update of the dependency matrix.

[0082] It can be seen that the present application constructs a dependency matrix based on the dependencies between instructions, and preferentially sends the instruction that has no dependency relationship with other instructions and has the highest priority to the instruction processing unit for processing based on the dependency matrix and the priorities corresponding to each instruction, so that the processing order of instructions can be dynamically adjusted, realizing efficient out-of-order emission of instructions. Compared with the method of in-order instruction emission, it can significantly improve the utilization rate of processor resources, and can achieve fast response to some important instructions according to the priorities, meeting the diverse requirements for instruction emission.

[0083] See Figure 4 As shown, an embodiment of the present invention discloses an instruction out-of-order emission device, which is applied to a general graphics processor and includes:

[0084] A dependency relationship determination module 11, configured to obtain a plurality of instructions to be emitted from an instruction cache, and determine the dependency relationship between each instruction to be emitted and other instructions to be emitted; the other instructions to be emitted are the instructions among the plurality of instructions to be emitted whose generation time is earlier than that of each instruction to be emitted;

[0085] A dependency matrix construction module 12, configured to construct a dependency matrix based on the dependency relationship between each instruction to be emitted and the other instructions to be emitted;

[0086] An instruction determination module 13, configured to use the dependency matrix and based on the priorities corresponding to each instruction, determine a target instruction to be emitted from the plurality of instructions to be emitted; the target instruction to be emitted is the instruction that has no dependency relationship with other instructions among the plurality of instructions to be emitted and has the highest priority;

[0087] An instruction emission module 14, configured to emit the target instruction to be emitted to an instruction processing unit in the general graphics processor for processing.

[0088] It can be seen that the present application constructs a dependency matrix based on the dependencies between instructions, and preferentially sends the instruction that has no dependency relationship with other instructions and has the highest priority to the instruction processing unit for processing based on the dependency matrix and the priorities corresponding to each instruction, so that the processing order of instructions can be dynamically adjusted, realizing efficient out-of-order emission of instructions. Compared with the method of in-order instruction emission, it can significantly improve the utilization rate of processor resources, and can achieve fast response to some important instructions according to the priorities, meeting the diverse requirements for instruction emission.

[0089] In some specific embodiments, the instruction out-of-order emission device further includes:

[0090] An instruction decoding unit, configured to sequentially fetch instructions from a preset memory in the order of instruction generation, and decode the currently fetched instruction to obtain instruction parameters corresponding to the currently fetched instruction; the instruction parameters include an instruction type and an identifier of a register required by the instruction; the registers required by the instruction include a source register and a destination register;

[0091] A field filling unit, configured to fill corresponding fields in a data structure corresponding to the currently fetched instruction based on the instruction parameters corresponding to the currently fetched instruction, and by newly adding a priority field and a dispatch field in the data structure, fill the priority field based on a priority identifier corresponding to the priority of the currently fetched instruction, and fill the dispatch field based on a first dispatch identifier indicating that the instruction has not been dispatched, to obtain the filled data structure; wherein, different priorities correspond to different priority identifiers;

[0092] An instruction cache unit, configured to store the currently fetched instruction and the corresponding filled data structure into the instruction cache.

[0093] In some specific embodiments, the dependency determination module 11 includes:

[0094] An undispatched instruction determination unit, configured to determine undispatched instructions from the instruction cache; the dispatch identifier of the undispatched instruction is the first dispatch identifier;

[0095] A to-be-dispatched instruction determination unit, configured to select a preset number of instructions from the undispatched instructions in the order of instruction generation to obtain a number of to-be-dispatched instructions.

[0096] In some specific embodiments, the dependency determination module 11 includes:

[0097] A first dependency determination unit, configured to determine the dependency relationship between each to-be-dispatched instruction and other to-be-dispatched instructions based on the instruction types corresponding to each to-be-dispatched instruction and other to-be-dispatched instructions respectively;

[0098] A second dependency determination unit, configured to determine the dependency relationship between each to-be-dispatched instruction and other to-be-dispatched instructions based on the identity between the identifiers of the registers required by each to-be-dispatched instruction and other to-be-dispatched instructions respectively.

[0099] In some specific embodiments, the instruction out-of-order dispatch device further includes:

[0100] A transmission identification change unit, configured to change the transmission identification of the target instruction to be transmitted from the first transmission identification to a second transmission identification indicating that the instruction has been transmitted, and then return to the step of obtaining a plurality of instructions to be transmitted from the instruction cache.

[0101] In some specific embodiments, the instruction out-of-order transmission device further includes:

[0102] A target instruction determination unit, configured to, if the number of the target instructions to be transmitted is multiple, determine the instruction with the earliest generation time from the multiple target instructions to be transmitted as the target instruction to be finally transmitted.

[0103] In some specific embodiments, the instruction out-of-order transmission device further includes:

[0104] A flushed instruction determination unit, configured to determine the flushed instruction corresponding to the instruction pipeline flushing operation when detecting the instruction pipeline flushing operation;

[0105] An instruction deletion unit, configured to delete the flushed instruction and / or the instruction depending on the flushed instruction from the instructions currently used to construct the dependency matrix;

[0106] A dependency matrix reconstruction unit, configured to obtain a corresponding number of new instructions to be transmitted from the instruction cache based on the number of the deleted instructions, and reconstruct the dependency matrix by using the new instructions to be transmitted and the undeleted instructions among the instructions currently used to construct the dependency matrix.

[0107] Furthermore, an embodiment of the present application also discloses an electronic device, Figure 5 which is a structural diagram of an electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation to the scope of use of the present application.

[0108] Figure 5 This is a schematic structural diagram of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Wherein, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the instruction out-of-order transmission method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0109] In this embodiment, the power supply 23 is used to provide operating voltages for the various hardware devices on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed thereon here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application requirements, and no specific limitation is made here.

[0110] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0111] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device 20, and it can be Windows Server, Netware, Unix, Linux, etc. The computer program 222 can further include a computer program capable of performing other specific tasks in addition to the computer program capable of implementing the instruction out-of-order emission method executed by the electronic device 20 disclosed in any of the foregoing embodiments.

[0112] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the instruction out-of-order emission method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

[0113] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0114] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0115] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0116] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0117] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this document to illustrate the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for issuing instructions out of order, characterized in that: Applicable to general-purpose graphics processors, including: Acquire a plurality of to-be-issued instructions from the instruction cache, and determine the dependency relationship between each to-be-issued instruction and other to-be-issued instructions; the other to-be-issued instructions are instructions among the plurality of to-be-issued instructions whose generation time is earlier than that of each to-be-issued instruction; Constructing a dependency matrix based on the dependency relationship between each of the instructions to be issued and the other instructions to be issued; Determine a target instruction to be transmitted from the plurality of instructions to be transmitted by using the dependency matrix and based on the priorities corresponding to the instructions respectively; the target instruction to be transmitted is an instruction that has no dependency relationship with other instructions in the plurality of instructions to be transmitted and has the highest priority; The target to-be-issued instruction is transmitted to an instruction processing unit in the general purpose graphics processor for processing.

2. The method for issuing instructions out of order according to claim 1, characterized in that: Before obtaining a plurality of instructions to be issued from the instruction cache, the method further includes: fetching instructions from a preset memory in sequence according to the order in which the instructions are generated, and decoding the currently fetched instruction to obtain instruction parameters corresponding to the currently fetched instruction; the instruction parameters include the instruction type and the identifier of the register required by the instruction; the register required by the instruction includes a source register and a destination register; Based on the instruction parameters corresponding to the currently fetched instruction, fill the corresponding fields in the data structure corresponding to the currently fetched instruction, and by newly adding a priority field and a transmission field in the data structure, fill the priority field based on the priority identifier corresponding to the priority of the currently fetched instruction, and fill the transmission field based on a first transmission identifier representing that the instruction has not been transmitted, so as to obtain the filled data structure; wherein different priorities correspond to different priority identifiers; The currently fetched instruction and the corresponding filled data structure are stored in the instruction cache.

3. The method for issuing instructions out of order according to claim 2, characterized in that: The obtaining of a plurality of instructions to be issued from the instruction cache includes: Determining an unissued instruction from the instruction cache; the emission identifier of the unissued instruction is the first emission identifier; According to the order in which the instructions are generated, a preset number of instructions are selected from the unissued instructions to obtain a number of instructions to be issued.

4. The method for issuing instructions out of order according to claim 2, characterized in that: Determining the dependency relationship between each instruction to be issued and other instructions to be issued includes: Determine a dependency relationship between each instruction to be issued and the other instructions to be issued based on instruction types corresponding to each instruction to be issued and the other instructions to be issued; And / or, based on the sameness between identifiers of registers required by each instruction to be issued and the other instructions to be issued, the dependency relationship between each instruction to be issued and the other instructions to be issued is determined.

5. The method for issuing instructions out of order according to claim 2, characterized in that: After transmitting the target to-be-transmitted instruction to the instruction processing unit in the general purpose graphics processor for processing, the method further includes: The transmission identifier of the target to-be-transmitted instruction is changed from the first transmission identifier to a second transmission identifier indicating that the instruction has been transmitted, and the process returns to the step of obtaining a plurality of to-be-transmitted instructions from the instruction cache.

6. The method for issuing instructions out of order according to claim 1, characterized in that: After determining the target to-be-launched instruction from the plurality of to-be-launched instructions, the method further comprises: If there are multiple target instructions to be issued, the instruction with the earliest generation time is determined from the multiple target instructions to be issued to serve as the target instruction to be issued that needs to be issued eventually.

7. The method for issuing instructions out of order according to any one of claims 1 to 6, characterized in that: Also includes: When an instruction pipeline flush operation is detected, determining a flushed instruction corresponding to the instruction pipeline flush operation; Deleting the flushed instruction and / or the instruction that depends on the flushed instruction from the instructions currently used to construct the dependency matrix; Based on the number of deleted instructions, a corresponding number of new instructions to be issued are obtained from the instruction cache, and the dependency matrix is ​​reconstructed using the new instructions to be issued and the non-deleted instructions in the instructions currently used to construct the dependency matrix.

8. A device for transmitting out-of-order instructions, characterized in that: Applicable to general-purpose graphics processors, including: A dependency determination module, used to obtain a number of instructions to be issued from the instruction cache, and determine the dependency between each instruction to be issued and other instructions to be issued; the other instructions to be issued are instructions among the number of instructions to be issued that are generated earlier than each instruction to be issued; A dependency matrix construction module, configured to construct a dependency matrix based on the dependency relationship between each of the instructions to be issued and the other instructions to be issued; An instruction determination module is used to determine a target instruction to be transmitted from the plurality of instructions to be transmitted by using the dependency matrix and based on the priorities corresponding to the instructions respectively; the target instruction to be transmitted is an instruction that has no dependency relationship with other instructions in the plurality of instructions to be transmitted and has the highest priority; The instruction transmitting module is used to transmit the target to-be-transmitted instruction to the instruction processing unit in the general purpose graphics processor for processing.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the method for out-of-order instruction transmission as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the instruction out-of-order transmission method as described in any one of claims 1 to 7.

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