Abnormal self-recovery system and method and electronic equipment

Abstract

The invention discloses an abnormal self-recovery system and method and electronic equipment, and the system comprises a micro-control unit which is used for outputting a power supply signal to a power control circuit and outputting a power-on signal to a power management unit when the abnormal shutdown of a central processing unit is detected; the power control circuit is used for supplying power to the power management unit in response to the power supply signal; the power supply management unit is used for supplying power to the central processing unit according to the startup signal so as to realize restartup of the central processing unit; and the central processing unit is used for outputting a reset signal to the micro-control unit when detecting that the micro-control unit is shut down abnormally, so as to control the micro-control unit to reset and realize the restarting of the micro-control unit. According to the abnormity self-recovery system, power supply can be automatically recovered when any one of the central processing unit and the micro-control unit is shut down abnormally, work can be recovered, the reliability of the system is greatly improved, the intelligent degree is high, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to an abnormal self-recovery system, method, and electronic device. Background Art

[0002] With the progress of technologies, the application fields of Interactive Flat Panel Displays (IFPDs) have been widely expanded. An IFPD is an all-in-one device that uses a liquid crystal screen for display and has functions such as writing, annotation, drawing, screen capture, multimedia playback, multi-screen interaction, video conferencing, file management, whiteboard sharing, intelligent browsing, and remote control. Currently, intelligent interactive flat panels are mainly used in educational and conferencing scenarios. However, due to their property of integrating the functions of multiple products such as TVs, computers, projectors, touchscreens, and electronic whiteboards, intelligent interactive flat panels are applicable to all scenarios that require discussion, communication, and display, and there is huge room for imagination in the application fields. Currently, they have been expanded to fields such as medical care, finance, and hotels.

[0003] With the expansion of their application fields, there are more and more circuit design solutions with the coexistence of a Central Processing Unit (CPU) and a Microcontroller Unit (MCU). However, either the CPU or the MCU has a risk of sudden breakdown. If there is no one on-site, it is impossible to power on or restart by pressing a button again, resulting in the entire machine being unable to work properly. Summary of the Invention

[0004] In view of the above problems, this application provides an abnormal self-recovery system, method, and electronic device to solve the above technical problems.

[0005] In a first aspect, this application provides an abnormal self-recovery system, which includes a central processing unit, a microcontroller unit, a power control circuit, and a power management unit, where:

[0006] The microcontroller unit is configured to output a power supply signal to the power control circuit and an on signal to the power management unit when detecting that the central processing unit abnormally shuts down;

[0007] The power control circuit is configured to supply power to the power management unit in response to the power supply signal;

[0008] The power management unit is configured to supply power to the central processing unit according to the on signal to achieve restarting of the central processing unit;

[0009] The central processing unit is configured to output a reset signal to the microcontroller unit when detecting that the microcontroller unit abnormally shuts down, so as to control the reset of the microcontroller unit and achieve restarting of the microcontroller unit.

[0010] In a possible implementation of the present application, the central processing unit is further configured to output a second secondary signal to the power management unit and output a first secondary signal to the power control circuit after power-on;

[0011] The power control circuit is configured to: supply power to the power management unit in response to the power supply signal when receiving both the power supply signal and the first secondary signal; supply power to the power management unit in response to the first secondary signal when the micro control unit abnormally shuts down;

[0012] The power management unit is configured to: supply power to the central processing unit in response to the power-on signal when receiving both the power-on signal and the second secondary signal; supply power to the central processing unit in response to the second secondary signal when the micro control unit abnormally shuts down.

[0013] In a possible implementation of the present application, the power control circuit includes a first switch unit. The control end of the first switch unit is connected to the micro control unit. A power supply end is connected to the first end of the first switch unit, and the second end of the first switch unit is connected to the power input end of the power management unit;

[0014] The first switch unit is configured to conduct in response to the power supply signal, so that the power supply end supplies power to the power management unit through the conducted first switch unit.

[0015] In a second aspect, the present application further provides an abnormal self-recovery method, which is applied to the micro control unit in the above abnormal self-recovery system. The abnormal self-recovery method includes:

[0016] If it is detected that the central processing unit of the abnormal self-recovery system abnormally shuts down during the operation of the abnormal self-recovery system, then output a power supply signal to the power control circuit of the abnormal self-recovery system, so that the power control circuit supplies power to the power management unit of the abnormal self-recovery system;

[0017] Output a power-on signal to the power management unit to drive the power management unit to supply power to the central processing unit, so as to realize the restart of the central processing unit.

[0018] In a possible implementation of the present application, the abnormal self-recovery method further includes:

[0019] Obtain a first status monitoring signal, where the first status monitoring signal is used to characterize the power-on and power-off status of the central processing unit;

[0020] Judge whether the central processing unit abnormally shuts down according to the first status monitoring signal.

[0021] In a possible implementation of the present application, judging whether the central processing unit abnormally shuts down according to the first status monitoring signal includes:

[0022] If the first status monitoring signal indicates that the central processing unit is in the shutdown state and the microcontroller unit does not receive the key shutdown signal, it is determined that the central processing unit has an abnormal shutdown.

[0023] In a third aspect, the present application further provides an abnormal self-recovery method, which is applied to the central processing unit in the above abnormal self-recovery system. The abnormal self-recovery method includes:

[0024] If it is detected that the microcontroller unit of the abnormal self-recovery system has an abnormal shutdown during the operation of the abnormal self-recovery system, a reset signal is output to the microcontroller unit to control the reset of the microcontroller unit and achieve the restart of the microcontroller unit.

[0025] In a possible implementation manner of the present application, the abnormal self-recovery method further includes:

[0026] Obtain a second status monitoring signal, where the second status monitoring signal is used to indicate the on / off state of the microcontroller unit;

[0027] Judge whether the microcontroller unit has an abnormal shutdown according to the second status monitoring signal.

[0028] In a possible implementation manner of the present application, judging whether the microcontroller unit has an abnormal shutdown according to the second status monitoring signal includes:

[0029] If the second status monitoring signal indicates that the microcontroller unit is in the shutdown state, it is determined that the microcontroller unit has an abnormal shutdown.

[0030] In a fourth aspect, the present application further provides an electronic device, which includes a device main body and the above abnormal self-recovery system provided on the device main body.

[0031] From the above content, the following beneficial effects of the present application can be obtained:

[0032] For the abnormal self-recovery system provided by the present application, when it is detected that the central processing unit has an abnormal shutdown, the microcontroller unit outputs a power supply signal to control the power control circuit to supply power to the power management unit. When the power management unit is powered on, it then responds to the power-on signal output by the microcontroller unit to supply power to the central processing unit, thereby achieving the restart of the central processing unit. When it is detected that the microcontroller unit has an abnormal shutdown, the central processing unit controls the microcontroller unit to reset. Compared with the related art where the user needs to press a key again to turn on or restart, it can automatically restore the power supply when any one of the central processing unit and the microcontroller unit has an abnormal shutdown, enabling it to resume work, greatly improving the reliability of the system, with a high degree of intelligence and enhancing the user experience.

[0033] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. Brief Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0035] Figure 1 is a schematic structural diagram of an abnormal self - recovery system provided in an embodiment of the present application;

[0036] Figure 2 is another schematic structural diagram of an abnormal self - recovery system provided in an embodiment of the present application;

[0037] Figure 3 is yet another schematic structural diagram of an abnormal self - recovery system provided in an embodiment of the present application;

[0038] Figure 4 is a schematic flowchart of an abnormal self - recovery method provided in an embodiment of the present application;

[0039] Figure 5 is a schematic structural diagram of a first detection unit provided in an embodiment of the present application;

[0040] Figure 6 is another schematic flowchart of an abnormal self - recovery method provided in an embodiment of the present application;

[0041] Figure 7 is a schematic structural diagram of a second detection unit provided in an embodiment of the present application. Detailed implementation manners

[0042] The following will describe in detail the implementation manners of the present application. Examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as a limitation of the present application.

[0043] In order to enable those skilled in the art to better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0044] In the embodiments of the present application, it should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0045] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising said element.

[0046] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations or descriptions. Any embodiment or design described as "for example" or "example" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0047] It should be noted that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0048] Before introducing the abnormal self-recovery system, method and electronic device of the present application, the relevant background information of the embodiments of the present application will be introduced first.

[0049] With the wide expansion of the application fields of Interactive Flat Panel Displays (IFPDs), there are more and more IFPDs with a Central Processing Unit (CPU) and a Microcontroller Unit (MCU). Only when the CPU and the MCU work together can the entire IFPD operate normally and implement corresponding functions. If either the CPU or the MCU suddenly loses power or breaks down, the entire machine will be abnormal.

[0050] Currently, when the entire machine is abnormal and cannot operate normally, it is necessary for humans to intervene to troubleshoot the cause of the abnormality, and then turn on or restart the machine by pressing a button. However, if the entire machine becomes abnormal when there is no one on duty, it is impossible to turn on or restart the machine by pressing the button again, which will cause the entire machine to be unable to work normally.

[0051] Based on this, the embodiments of the present application provide an abnormal self-recovery system, method and electronic device, which will be described in detail below.

[0052] The abnormal self-recovery system of the present application interconnects the central processing unit and the micro control unit, monitors the power-on and power-off states of each other, and when detecting that the central processing unit abnormally shuts down, the micro control unit outputs a power supply signal to control the power control circuit to supply power to the power management unit. When the power management unit is powered on, it responds to the power-on signal output by the micro control unit to supply power to the central processing unit, thereby realizing the restart of the central processing unit; when detecting that the micro control unit abnormally shuts down, the central processing unit controls the micro control unit to reset, so that power supply can be automatically restored when either the central processing unit or the micro control unit abnormally shuts down, enabling it to resume operation.

[0053] Please refer to Figure 1 , Figure 1 FIG. is a schematic structural diagram of the abnormal self-recovery system provided in the embodiments of the present application. The abnormal self-recovery system 100 may include a central processing unit 110, a micro control unit 120, a power control circuit 130, and a power management unit 140.

[0054] Among them, the micro control unit 120 can be used to output a power supply signal to the power control circuit 130 and a power-on signal to the power management unit 140 when detecting that the central processing unit 110 abnormally shuts down.

[0055] The power control circuit 130 can be used to supply power to the power management unit 140 in response to the power supply signal.

[0056] The power management unit 140 can be used to supply power to the central processing unit 110 according to the power-on signal to realize the restart of the central processing unit 110.

[0057] The central processing unit 110 can be used to output a reset signal to the micro control unit 120 when detecting that the micro control unit 120 abnormally shuts down, so as to control the micro control unit 120 to reset and realize the restart of the micro control unit 120.

[0058] In the embodiments of the present application, the central processing unit 110 can be any existing CPU, the micro control unit 120 can be any existing MCU, and the power management unit 140 can be any existing power management unit (Power Management Unit, PMU). The selection of the foregoing units and devices can be determined according to the actual application scenario, and specific details are not limited herein.

[0059] It can be understood that the central processing unit 110 can be interconnected with the micro control unit 120, so that the power-on and power-off states of each other can be monitored. That is to say, the central processing unit 110 can monitor the power-on and power-off state of the micro control unit 120, and the micro control unit 120 can also monitor the power-on and power-off state of the central processing unit 110, so as to restore the working state of the other party in time when the other party shuts down abnormally.

[0060] The following will be combined with Figure 1 to illustrate the working principle of the abnormal self-recovery system 100 in the embodiments of the present application.

[0061] System startup: Connect the abnormal self-recovery system 100 to an external power supply (not shown in the figure), such as 220V AC mains, for hard startup. At this time, the micro control unit 120 is powered on and working, and the central processing unit 110 has not been powered on yet. Then, press the physical button 150 for soft startup. The physical button 150 is respectively connected to the micro control unit 120 and the central processing unit 110. Therefore, after the physical button 150 is pressed, both the central processing unit 110 and the micro control unit 120 will receive the button startup signal. Since the central processing unit 110 has not been powered on yet, the central processing unit 110 will not respond to this button startup signal, while the micro control unit 120 will respond to this button startup signal and output a power supply signal to the power control circuit 130.

[0062] After receiving this power supply signal, the power control circuit 130 can supply power to the power management unit 140. Then, the micro control unit 120 sends a startup signal to the power management unit 140. At this time, since the power management unit 140 is powered on, the power management unit 140 can respond to this startup signal and start working to supply power to the central processing unit 110, so that the central processing unit 110 can start up and work normally, completing the startup.

[0063] System shutdown: Long press the physical button 150. Similarly, both the central processing unit 110 and the micro control unit 120 will receive the button shutdown signal. Since the micro control unit 120 will not respond to the external shutdown request, only the central processing unit 110 will respond to this button shutdown signal and shut down.

[0064] After the micro control unit 120 monitors that the central processing unit 110 has shut down, it can output a power-off signal to the power control circuit 130 to stop supplying power to the power management unit 140. When the power management unit 140 is powered off, it stops supplying power to the central processing unit 110, realizing the complete power-off of the central processing unit 110, thus completing the shutdown.

[0065] Based on this, in the embodiments of the present application, when the abnormal self-recovery system 100 is operating normally, if the microcontroller unit 120 detects that the central processing unit 110 abnormally shuts down, it can output a power supply signal to the power control circuit 130 based on the above-mentioned power-on principle, so that the power control circuit 130 responds to the power supply signal to supply power to the power management unit 140. Moreover, the microcontroller unit 120 outputs a power-on signal to the power management unit 140, so that when powered on, it responds to the power-on signal to supply power to the central processing unit 110, enabling the central processing unit 110 to be powered on again, that is, to restart.

[0066] If the central processing unit 110 detects that the microcontroller unit 120 abnormally shuts down, it can directly output a reset signal to the microcontroller unit 120 to control the reset of the microcontroller unit 120, thereby realizing the restart of the microcontroller unit 120.

[0067] It can be understood that since the key signals during power-on or power-off are received by both the central processing unit 110 and the microcontroller unit 120, the central processing unit 110 and the microcontroller unit 120 can judge whether the other party abnormally shuts down according to the detected power-on and power-off states of the other party and the received key signal situation. Thus, when it is determined that the other party abnormally shuts down, corresponding recovery means are taken.

[0068] In the abnormal self-recovery system 100 provided by the embodiments of the present application, when it is detected that the central processing unit 110 abnormally shuts down, the microcontroller unit 120 outputs a power supply signal to control the power control circuit 130 to supply power to the power management unit 140. When the power management unit 140 is powered on, it then responds to the power-on signal output by the microcontroller unit 120 to supply power to the central processing unit 110, thereby realizing the restart of the central processing unit 110. When it is detected that the microcontroller unit 120 abnormally shuts down, the central processing unit 110 controls the reset of the microcontroller unit 120. Compared with the related art where the user needs to press the key again to power on or restart, it can automatically restore the power supply of either the central processing unit 110 or the microcontroller unit 120 when either of them abnormally shuts down, enabling it to resume work, greatly improving the reliability of the system, with a high degree of intelligence and enhancing the user experience.

[0069] Next, continue with Figure 1 a detailed elaboration of each unit module shown and the specific implementation manners that may be adopted in practical applications.

[0070] Please refer to Figure 2 , in some embodiments of the present application, the central processing unit 110 can also be used to output a second-level signal to the power management unit 140 and output a first-level signal to the power control circuit 130 after power-on.

[0071] The power control circuit 130 can be configured to: when receiving a power supply signal and a first secondary signal simultaneously, supply power to the power management unit 140 in response to the power supply signal; when the microcontroller unit 120 abnormally shuts down, supply power to the power management unit 140 in response to the first secondary signal.

[0072] The power management unit 140 can be configured to: when receiving a power-on signal and a second secondary signal simultaneously, supply power to the central processing unit 110 in response to the power-on signal; when the microcontroller unit 120 abnormally shuts down, supply power to the central processing unit 110 in response to the second secondary signal.

[0073] Since the power management unit 140 that supplies power to the central processing unit 110 supplies power to the central processing unit 110 in response to the power-on signal sent by the microcontroller unit 120, and the power control circuit 130 that supplies power to the power management unit 140 supplies power to the power management unit 140 in response to the power supply signal sent by the microcontroller unit 120, therefore, when the microcontroller unit 120 abnormally shuts down, in order to ensure the normal operation of the central processing unit 110, the central processing unit 110 can take over the control rights of the power control circuit 130 and the power management unit 140, so that the power control circuit 130 and the power management unit 140 can operate normally, and thus the power management unit 140 can supply power to the central processing unit 110 normally.

[0074] Therefore, after the central processing unit 110 is powered on and starts up, it can output a first secondary signal to the power control circuit 130 and a second secondary signal to the power management unit 140 respectively.

[0075] In the embodiments of the present application, the control right of the microcontroller unit 120 can be set to be prior to that of the central processing unit 110. That is to say, when the system is running normally, the power control circuit 130 will receive a power supply signal from the microcontroller unit 120 and a first secondary signal from the central processing unit 110 simultaneously. At this time, since the control right of the microcontroller unit 120 is prior to that of the central processing unit 110, therefore, the power control circuit 130 will supply power to the power management unit 140 in response to the power supply signal from the microcontroller unit 120.

[0076] The power management unit 140 will receive a power-on signal from the microcontroller unit 120 and a second secondary signal from the central processing unit 110 simultaneously. Similarly, since the control right of the microcontroller unit 120 is prior to that of the central processing unit 110, therefore, the power management unit 140 will supply power to the central processing unit 110 in response to the power-on signal from the microcontroller unit 120.

[0077] After the micro control unit 120 abnormally shuts down, the micro control unit 120 does not output a power supply signal and a power-on signal. At this time, the power control circuit 130 can respond to the first secondary signal from the central processing unit 110 to supply power to the power management unit 140, and the power management unit 140 can respond to the second secondary signal from the central processing unit 110 to supply power to the central processing unit 110 to ensure that the central processing unit 110 can work normally.

[0078] It can be understood that after the micro control unit 120 resumes work, the control right will return to the micro control unit 120 again.

[0079] In some other embodiments, the control right of the central processing unit 110 can also be set to be prior to the micro control unit 120. At this time, when receiving the power-on signal and the first secondary signal at the same time, the power control circuit 130 will respond to the first secondary signal from the central processing unit 110 to supply power to the power management unit 140, and the power management unit 140 will respond to the second secondary signal from the central processing unit 110 to supply power to the central processing unit 110.

[0080] It should be noted that the priority setting of the control right can be determined according to the actual application scenario, and specific details are not limited here.

[0081] Please refer to Figure 3 , in some embodiments of the present application, the power control circuit 130 may include a first switch unit 131. The control end of the first switch unit 131 is connected to the micro control unit 120. A power supply terminal 160 is connected to the first end of the first switch unit 131, and the second end of the first switch unit 131 is connected to the power input terminal of the power management unit 140; the first switch unit 131 can be used to conduct in response to a power supply signal, so that the power supply terminal 160 supplies power to the power management unit 140 through the conducting first switch unit 131.

[0082] In the embodiments of the present application, the first switch unit 131 can be any existing controllable switch device. For example, a triode, an Insulate-Gate Bipolar Transistor (IGBT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), etc., can be specifically determined according to the actual application scenario.

[0083] For example, if the first switch unit 131 includes an N-channel MOSFET, that is, an NOMS tube, the gate of the NOMS tube is connected to the micro control unit 120 for receiving a power supply signal, the drain of the NOMS tube is connected to the power supply terminal 160, and the source of the NOMS tube is connected to the power management unit 140.

[0084] When the power supply signal is at a high level, when the microcontroller unit 120 outputs a power supply signal at a high level, the NMOS transistor responds to the power supply signal at a high level and conducts, so that the power supply terminal 160 connected to the drain can supply power to the power management unit 140 connected to the source; when the system is shut down, the microcontroller unit 120 outputs a power-off signal at a low level, and the NMOS transistor responds to the power-off signal at a low level and disconnects, so that the power management unit 140 is powered off.

[0085] Based on the above embodiments, the embodiment of the present application further provides an abnormal self-recovery method, which can be applied to the microcontroller unit 120 in the above abnormal self-recovery system 100. Please refer to Figure 4 , Figure 4 FIG. is a schematic flowchart of an abnormal self-recovery method provided in an embodiment of the present application. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in an order different from that here. The abnormal self-recovery method provided by the present application specifically may include the following steps:

[0086] Step S401, if it is detected that the central processing unit 110 abnormally shuts down during the operation of the abnormal self-recovery system 100, output a power supply signal to the power control circuit 130 so that the power control circuit 130 supplies power to the power management unit 140;

[0087] Step S402, output a power-on signal to the power management unit 140 to drive the power management unit 140 to supply power to the central processing unit 110, and realize the restart of the central processing unit 110.

[0088] In the embodiment of the present application, when the microcontroller unit 120 detects that the central processing unit 110 abnormally shuts down, according to the system power-on principle, a power supply signal can be output to the power control circuit 130, so that the power control circuit 130 supplies power to the power management unit 140. When the power management unit 140 is powered on, when the microcontroller unit 120 outputs a power-on signal, the power management unit 140 can respond to the power-on signal and supply power to the central processing unit 110, so that the central processing unit 110 can be powered on and restarted.

[0089] It can be understood that the microcontroller unit 120 can output a power supply signal and a power-on signal simultaneously in response to a key power-on signal from a physical button; it can also output a power supply signal in response to a key power-on signal from a physical button, and then after a certain delay or when it is determined that the power management unit 140 is powered on, output a power-on signal, which can be specifically selected according to the actual application scenario.

[0090] In the embodiments of the present application, before the system runs, the power supply timing of the power management unit 140 can be set according to the power-on timing of the central processing unit 110, so as to ensure that when the power management unit 140 supplies power to the central processing unit 110, it can supply power to the central processing unit 110 based on the power-on timing of the central processing unit 110, ensuring that the central processing unit 110 can work properly.

[0091] In the embodiments of the present application, when the central processing unit 110 abnormally shuts down, the micro control unit 120 can autonomously resume power supply to the central processing unit 110, enabling the central processing unit 110 to restart, which can ensure the normal operation of the system.

[0092] Next, continue to elaborate in detail on Figure 4 the steps shown below and the specific implementation manners that may be adopted in actual applications.

[0093] In some embodiments of the present application, the abnormal self-recovery method may further include:

[0094] Obtain a first status monitoring signal, where the first status monitoring signal is used to characterize the power-on and power-off status of the central processing unit 110; determine whether the central processing unit 110 abnormally shuts down according to the first status monitoring signal.

[0095] According to the description of the above embodiments, it can be known that the micro control unit 120 in the embodiments of the present application is interconnected with the central processing unit 110. Therefore, the micro control unit 120 can determine whether the central processing unit 110 is abnormal through the first status monitoring signal from the central processing unit 110.

[0096] In a specific implementation manner, a first detection unit 170 may be connected between the micro control unit 120 and the central processing unit 110. The micro control unit 120 can sample the first status monitoring signal through the first detection unit 170, and thus determine the power-on and power-off status of the central processing unit 110 according to the high and low levels of the received first status monitoring signal.

[0097] For example, if the first status monitoring signal is a low-level signal, it can characterize that the central processing unit 110 is in the power-on state; if the first status monitoring signal is a high-level signal, it can characterize that the central processing unit 110 is in the power-off state; or, if the first status monitoring signal is a high-level signal, it can characterize that the central processing unit 110 is in the power-on state, and if the first status monitoring signal is a low-level signal, it can characterize that the central processing unit 110 is in the power-off state. Specifically, it can be determined according to the actual application scenario and is not limited here.

[0098] In one example, such as Figure 5As shown in the figure, the first detection unit 170 may include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first triode Q1. Among them, the base of the first triode Q1 is connected to the output port of the central processing unit 110 through the second resistor R2. The emitter of the first triode Q1 is grounded to GND. The collector of the first triode Q1 is connected to the power supply terminal 3V3_MCU through the third resistor R3 and to the input port of the micro control unit 120 through the fourth resistor R4.

[0099] For example, it is set that the first status monitoring signal is a low-level signal, indicating that the central processing unit 110 is in the power-on state, and the first status monitoring signal is a high-level signal, indicating that the central processing unit 110 is in the power-off state. When the central processing unit 110 works normally, the output port outputs a high-level signal. At this time, the first triode Q1 is turned on in response to this high-level signal. Since the emitter of the first triode Q1 is grounded to GND, when it is turned on, the collector potential of the first triode Q1 is pulled down to the ground, so that the input port of the micro control unit 120 receives the first status monitoring signal of low level. Based on this low-level first status monitoring signal, the micro control unit 120 can determine that the central processing unit 110 is in the power-on state at this time;

[0100] On the contrary, when the central processing unit 110 shuts down abnormally, no signal is output from the output port. At this time, the first triode Q1 is not turned on. Since the collector of the first triode Q1 is connected to the power supply terminal 3V3_MCU through the third resistor R3, at this time, the input port of the micro control unit 120 receives the first status monitoring signal of high level. Based on this high-level first status monitoring signal, the micro control unit 120 can determine that the central processing unit 110 is in the power-off state at this time.

[0101] In some embodiments of the present application, determining whether the central processing unit shuts down abnormally according to the first status monitoring signal may further include:

[0102] If the first status monitoring signal indicates that the central processing unit 110 is in the power-off state and the micro control unit 120 does not receive the key shutdown signal, it is determined that the central processing unit 110 shuts down abnormally.

[0103] According to the description of the system shutdown principle in the above embodiments, it can be known that when the system shuts down normally, both the central processing unit 110 and the micro control unit 120 will receive the key shutdown signal from the key, and the central processing unit 110 will respond to this key shutdown signal to shut down.

[0104] Therefore, if the micro control unit 120 receives a key shutdown signal and the first status monitoring signal indicates that the central processing unit 110 is in the shutdown state, the micro control unit 120 can determine that the central processing unit 110 is normally shut down; conversely, if the micro control unit 120 does not receive a key shutdown signal and the first status monitoring signal indicates that the central processing unit 110 is in the shutdown state, the micro control unit 120 can determine that the central processing unit 110 is abnormally shut down.

[0105] In the embodiment of the present application, the micro control unit 120 monitors the power-on and power-off states of the central processing unit 110 by interconnecting with the central processing unit 110, and can determine whether the central processing unit 110 is abnormally shut down by combining whether it itself receives a key shutdown signal, with a high degree of intelligence, ensuring the real-time performance and reliability of the status monitoring of the central processing unit 110.

[0106] Based on the above embodiment, the embodiment of the present application further provides an abnormal self-recovery method, and this abnormal self-recovery method can be applied to the central processing unit 110 in the above abnormal self-recovery system 100. Please refer to Figure 6 , Figure 6 is another process schematic diagram of the abnormal self-recovery method provided in the embodiment of the present application. It should be noted that although the logical order is shown in the process schematic diagram, in some cases, the steps shown or described can be executed in a different order from here. The abnormal self-recovery method provided by the present application specifically may include the following steps:

[0107] Step 601, if it is detected that the micro control unit 120 is abnormally shut down during the operation of the abnormal self-recovery system, output a reset signal to the micro control unit 120 to control the reset of the micro control unit 120 and realize the restart of the micro control unit 120.

[0108] In the embodiment of the present application, since the micro control unit 120 is interconnected with the central processing unit 110, the central processing unit 110 can determine whether the micro control unit 120 is abnormally shut down by monitoring the state of the micro control unit 120. Since the micro control unit 120 itself does not respond to external shutdown requests, when it is determined that the micro control unit 120 is abnormally shut down, the central processing unit 110 can control the reset of the micro control unit 120 through a reset signal to restart it to ensure the normal operation of the system.

[0109] In some embodiments of the present application, this abnormal self-recovery method may further include:

[0110] Obtain a second status monitoring signal, where the second status monitoring signal is used to characterize the power-on and power-off states of the micro control unit 120; determine whether the micro control unit 120 is abnormally shut down according to the second status monitoring signal.

[0111] According to the description of the above embodiments, it can be known that the microcontroller unit 120 in the embodiment of the present application is interconnected with the central processing unit 110. Therefore, the central processing unit 110 can determine whether the microcontroller unit 120 is abnormal through the second status monitoring signal from the microcontroller unit 120.

[0112] In a specific implementation manner, a second detection unit 180 may be connected between the microcontroller unit 120 and the central processing unit 110. The central processing unit 110 may sample the second status monitoring signal through the second detection unit 180, so as to determine the on / off state of the microcontroller unit 120 according to the high and low levels of the received second status monitoring signal.

[0113] For example, when the second status monitoring signal is a low-level signal, it may indicate that the microcontroller unit 120 is in the on state; when the second status monitoring signal is a high-level signal, it may indicate that the microcontroller unit 120 is in the off state. Or, when the second status monitoring signal is a high-level signal, it may indicate that the microcontroller unit 120 is in the on state; when the second status monitoring signal is a low-level signal, it may indicate that the microcontroller unit 120 is in the off state. Specifically, it can be determined according to the actual application scenario and is not limited here.

[0114] In one example, as Figure 7 shown, the second detection unit 180 may include a fifth resistor R5, a second six-resistor R6, a seventh resistor R7, an eighth resistor R8, and a second triode Q2. Among them, the base of the second triode Q2 is connected to the output port of the microcontroller unit 120 through the sixth resistor R6, the emitter of the second triode Q2 is grounded to GND, and the collector of the second triode Q2 is connected to the power supply terminal 1V8_M through the seventh resistor R7 and to the input port of the central processing unit 110 through the eighth resistor R8.

[0115] For example, it is set that the second status monitoring signal is a low-level signal, indicating that the microcontroller unit 120 is in the on state, and the second status monitoring signal is a high-level signal, indicating that the microcontroller unit 120 is in the off state. Then, when the microcontroller unit 120 is working normally, the output port outputs a high-level signal. At this time, the second triode Q2 is turned on in response to the high-level signal. Since the emitter of the second triode Q2 is grounded to GND, when it is turned on, the collector potential of the second triode Q2 is pulled down to the ground, so that the input port of the central processing unit 110 receives the second status monitoring signal of low level. The central processing unit 110 can determine that the microcontroller unit 120 is in the on state at this time based on the second status monitoring signal of low level;

[0116] Conversely, when the microcontroller unit 120 abnormally shuts down, no signal is output from the output port. At this time, the second triode Q2 is not conducting. Since the collector of the second triode Q2 is connected to the power supply terminal 1V8_M through the seventh resistor R7, therefore, at this time, the input port of the central processing unit 110 receives a high-level second status monitoring signal. Based on this high-level second status monitoring signal, the central processing unit 110 can determine that the microcontroller unit 120 is in the shutdown state at this time.

[0117] In some embodiments of the present application, determining whether the microcontroller unit 120 abnormally shuts down according to the second status monitoring signal may further include:

[0118] If the second status monitoring signal indicates that the microcontroller unit 120 is in the shutdown state, it is determined that the microcontroller unit 120 abnormally shuts down.

[0119] According to the description of the system shutdown principle in the above embodiments, it can be known that when the system shuts down normally, both the central processing unit 110 and the microcontroller unit 120 will receive a key shutdown signal from the key. The central processing unit 110 will respond to the key shutdown signal to shut down, and the microcontroller unit 120 will not respond to the key shutdown signal.

[0120] Therefore, when the second status monitoring signal received by the central processing unit 110 indicates that the microcontroller unit 120 is in the shutdown state, the central processing unit 110 can directly determine that the microcontroller unit 120 abnormally shuts down, and then outputs a reset signal such as a high-level signal to the reset pin of the microcontroller unit 120, and pulls up the reset pin to reset the microcontroller unit 120, so as to keep the system working normally.

[0121] In the embodiments of the present application, the central processing unit 110 monitors the power-on and power-off states of the microcontroller unit 120 by interconnecting with the microcontroller unit 120, so as to determine whether the microcontroller unit 120 abnormally shuts down, and timely controls the microcontroller unit 120 to reset when the microcontroller unit 120 abnormally shuts down, ensuring the normal operation of the system and improving the system reliability.

[0122] Based on the above embodiments, the embodiments of the present application further provide an electronic device, which may include a device body and the abnormal self-recovery system as described above provided on the device body. The electronic device may be but is not limited to an intelligent interaction tablet, an intelligent wearable device, a mobile terminal device, a smart home device, etc.

[0123] Among them, the intelligent wearable device includes but is not limited to a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes but is not limited to a smart phone, a notebook computer, a tablet computer, and a point of sales terminal (POS). The smart home device includes but is not limited to a smart floor sweeper and a smart light.

[0124] Since the electronic device is provided with the abnormal self-recovery system 100 of the above embodiment, it has all the beneficial effects of the abnormal self-recovery system 100 in any of the above embodiments, which will not be elaborated here.

[0125] The above are only the preferred embodiments of the present application and do not impose any formal restrictions on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. An abnormal self - recovery system, characterized in that, the system includes a central processing unit, a micro - control unit, a power control circuit, and a power management unit, where: the micro - control unit is configured to output a power - supply signal to the power control circuit and an on - signal to the power management unit when detecting that the central processing unit abnormally shuts down; the power control circuit is configured to supply power to the power management unit in response to the power - supply signal; the power management unit is configured to supply power to the central processing unit according to the on - signal to achieve restart of the central processing unit; the central processing unit is configured to output a reset signal to the micro - control unit when detecting that the micro - control unit abnormally shuts down, to control reset of the micro - control unit and achieve restart of the micro - control unit.

2. The system according to claim 1, characterized in that, the central processing unit is further configured to output a second - level signal to the power management unit and a first - level signal to the power control circuit after power - on; the power control circuit is configured as follows: when receiving both the power - supply signal and the first - level signal, it supplies power to the power management unit in response to the power - supply signal; when the micro - control unit abnormally shuts down, it supplies power to the power management unit in response to the first - level signal; the power management unit is configured as follows: when receiving both the on - signal and the second - level signal, it supplies power to the central processing unit in response to the on - signal; when the micro - control unit abnormally shuts down, it supplies power to the central processing unit in response to the second - level signal.

3. The system according to claim 1, characterized in that, the power control circuit includes a first switch unit, the control end of the first switch unit is connected to the micro - control unit, the first end of the first switch unit is connected to a power - supply end, and the second end of the first switch unit is connected to the power - supply input end of the power management unit; the first switch unit is configured to conduct in response to the power - supply signal, so that the power - supply end supplies power to the power management unit through the conducted first switch unit.

4. An abnormal self - recovery method, characterized in that, applied to the micro - control unit in the abnormal self - recovery system according to any one of claims 1 - 3, the method includes: if it is detected that the central processing unit of the abnormal self - recovery system abnormally shuts down during the operation of the abnormal self - recovery system, then output a power - supply signal to the power control circuit of the abnormal self - recovery system, so that the power control circuit supplies power to the power management unit of the abnormal self - recovery system; output an on - signal to the power management unit to drive the power management unit to supply power to the central processing unit and achieve restart of the central processing unit.

5. The method according to claim 4, characterized in that, the method further includes: acquiring a first status monitoring signal, where the first status monitoring signal is used to characterize the power - on / off status of the central processing unit; judging whether the central processing unit abnormally shuts down according to the first status monitoring signal.

6. The method according to claim 5, characterized in that, Determining whether the central processing unit abnormally shuts down according to the first status monitoring signal includes: If the first status monitoring signal indicates that the central processing unit is in a shutdown state and the micro control unit does not receive a key shutdown signal, it is determined that the central processing unit abnormally shuts down.

7. An abnormal self-recovery method Characterized in that Applied to the central processing unit in the abnormal self-recovery system according to any one of claims 1-3, the method includes: If it is detected that the micro control unit of the abnormal self-recovery system abnormally shuts down during the operation of the abnormal self-recovery system, a reset signal is output to the micro control unit to control the reset of the micro control unit and achieve the restart of the micro control unit.

8. The method according to claim 7 Characterized in that The method further includes: Obtaining a second status monitoring signal, where the second status monitoring signal is used to characterize the power-on and power-off status of the micro control unit; Judging whether the micro control unit abnormally shuts down according to the second status monitoring signal.

9. The method according to claim 8 Characterized in that Judging whether the micro control unit abnormally shuts down according to the second status monitoring signal includes: If the second status monitoring signal indicates that the micro control unit is in a shutdown state, it is determined that the micro control unit abnormally shuts down.

10. An electronic device Characterized in that The electronic device includes a device main body and the abnormal self-recovery system according to any one of claims 1-3 provided on the device main body.

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