Implementation method and system for PCIE physical layer built-in self-test code

Abstract

The invention aims to provide a method and a system for realizing a built-in self-test code of a PCIE (Peripheral Component Interface Express) physical layer. The method comprises the following steps of: integrating PCIE BIST GEN module packaging data in a controller layer and sending the data to a physical coding sub-layer; the physical coding sub-layer codes the packaged data and sends the coded data to the physical medium adaptation layer; and the physical medium adaptation layer converts the coded data into serial data and transmits the serial data back to the controller layer. According to the invention, the BIST test assembly meeting the PIPE protocol requirement is embedded in the PCS layer, and compared with a traditional BIST test scheme, through early-stage simulation and post-silicon test data result analysis, not only can the electrical performance test requirement of an original analog circuit be met, but also the test coverage of the PCS layer is increased. And the full-stack coverage test from the physical signal to the protocol logic is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and specifically to a method and system for implementing built-in self-test code within a PCIE physical layer. Background Art

[0002] As the PCIE (Peripheral Component Interconnect Express) protocol iterates to high-speed versions such as Gen5, the signal rate of its physical layer has reached the order of 32 GT / s, posing unprecedented challenges to the signal integrity, timing accuracy, and anti-interference ability of circuit design. The PCIe protocol (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect various components inside a computer, such as graphics cards, network cards, and sound cards, to achieve efficient data transmission. The PCIe protocol adopts a high-speed serial point-to-point dual-channel high-bandwidth transmission method, where each device has an independent channel and does not share the bus, thus significantly improving the data transmission speed and system performance. The PCIe protocol has been widely used in the connection of various peripherals in computer systems, such as graphics cards, network cards, and solid-state drives. With the continuous progress of technology, the PCIe protocol is also constantly evolving and upgrading to meet the growing data transmission requirements.

[0003] In the research and development of physical layer SerDes IP, the problems of attenuation, crosstalk, and jitter of high-speed serial signals are significantly exacerbated, making it difficult for traditional testing methods to accurately evaluate chip performance. At the same time, the PCIe protocol mandatorily requires the use of efficient coding schemes such as 128b / 130b and 8b / 10b. How to synchronously plan the built-in test architecture in the early stage of circuit design so that it can not only meet the simulation requirements of real scenarios in the early stage (such as the reproduction of dynamic signal degradation), but also support the quantitative diagnosis of post-silicon testing (such as bit error rate detection and eye diagram analysis) has become the core problem in shortening the R & D cycle and ensuring the functional reliability of the chip. Currently, the industry generally adopts a scheme of integrating a PRBS pattern generator and checker in the PMA (Physical Medium Attachment) layer. Although it can achieve basic quality testing of high-speed serial signals, its test scope is limited to analog circuit characteristics (such as signal integrity and jitter tolerance), and it cannot cover the protocol-related function verification of the PCS (Physical Coding Sublayer). This defect makes it difficult to comprehensively detect key protocol behaviors such as link state machine control, training sequence interaction, and power management during IP development, forming a testing blind spot. Summary of the Invention

[0004] The object of the present invention is to provide an implementation method and system for PCIE physical layer built-in self-test code. The method embeds a BIST test component that meets the requirements of the PIPE protocol in the PCS layer. Through the analysis of the data results of pre-simulation and post-silicon testing, compared with the traditional BIST test scheme, it can not only meet the electrical performance test requirements of the original analog circuit, but also increase the test coverage of the PCS layer. It realizes the full-stack coverage test from physical signals to protocol logic.

[0005] An implementation method for PCIE physical layer built-in self-test code, characterized by including: Integrate the PCIE BIST GEN module in the controller layer to pack data and send it to the physical coding sublayer; The physical coding sublayer encodes the packed data and sends it to the physical medium adaptation layer; The physical medium adaptation layer converts the encoded data into serial data and sends it back to the controller layer.

[0006] Preferably, the physical medium adaptation layer converting the encoded data into serial data and sending it back to the controller layer includes: The physical medium adaptation layer converts the encoded data into serial data and sends it to the physical coding sublayer; The physical coding sublayer aligns and decodes the serial data; Send the decoded data to the controller layer for unpacking processing; Integrate the PCIE BIST CHK module in the controller layer to complete the full-link closed-loop verification.

[0007] Preferably, the integrating the PCIE BIST GEN module in the controller layer to pack data and send it to the physical coding sublayer includes: Build a PRBS generator in the PCIE BIST GEN module to support three standard polynomial sequences of PRBS-7, PRBS-23, and PRBS-31 and user-defined UDP patterns, and support dynamically inserting error patterns to simulate protocol violation scenarios.

[0008] Preferably, the integrating the PCIE BIST CHK module in the controller layer to complete the full-link closed-loop verification includes: The integrated PCIE BIST CHK module supports receiving data streams with multiple programmable data bit widths of 8 / 16 / 32-bit; After receiving the data stream that conforms to the PIPE protocol output by the elastic buffer, filter and remove the K code and OS code control characters and invalid data; Perform real-time exclusive OR verification on the received PRBS data and the reference data generated by the local PRBS generator. For UDP data, perform bit-by-bit comparison with the template data preset by the user. Verification anomalies trigger the error count accumulation mechanism, and finally determine the link quality based on the bit error rate within the continuous statistical period.

[0009] Preferably, the physical coding sublayer encodes the packed data and sends it to the physical medium adaptation layer, including: When the transmitter starts transmission, set the txelecidle signal low. In Gen1 / Gen2 mode, the physical coding sublayer adopts an 8b / 10b coding mechanism. Identify the data type through the txdata_k signal, where 1 represents regular data and 0 represents K code. When in Gen3 / Gen4 / Gen5 mode, the coding mechanism switches to 128b / 130b, and fine control is performed through a combined signal group including marking the start of a new data block txstartblock with a high level, the synchronous control signal and data txdatavalid within the high-level valid window, identifying the OS code with 2'b01, and identifying regular data with 2'b10. According to the data bit width requirement of the bus, periodically set the txdatavalid low to balance the encoding and decoding throughput. When the data transmission is completed, set the txelecidle signal high.

[0010] Preferably, the physical coding sublayer aligns and decodes the serial data, including: Perform physical layer alignment and decoding operations on the data stream. Among them, the decoding module performs synchronous control according to the OS code and completes the decoding output according to the protocol timing. Perform cross-clock domain processing of the receive clock and the protocol layer clock through an elastic buffer. By real-time monitoring the difference between the read and write pointers, dynamically perform SKP code deletion / insertion operations to maintain the balance state of the buffer.

[0011] Preferably, integrating the PCIE BIST GEN module in the controller layer and sending the packed data to the physical coding sublayer further includes: Insert a COMMA code or an EIEOS code with a configurable length in the sequence preamble to assist the receiving end in completing the initial data alignment and locking. For the frequency difference compensation between the RX end CDR recovery clock and the PLL generated clock, support the dynamic insertion of SKP code strategy under programmable configuration.

[0012] An implementation system for PCIE physical layer built-in self-test code, including: A data transmission module, configured to integrate a PCIE BIST GEN module at the controller layer to pack data and send it to the physical coding sublayer; A data encoding module, configured to encode the packed data by the physical coding sublayer and send it to the physical medium adaptation layer; A data conversion module, configured to convert the encoded data into serial data by the physical medium adaptation layer and send it back to the controller layer.

[0013] An electronic device, comprising: a chip, a processor, and a memory, where the memory is configured to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for implementing PCIE physical layer built-in self-test code.

[0014] A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for implementing PCIE physical layer built-in self-test code.

[0015] The beneficial effects of the present invention are as follows: Compared with the traditional solution of integrating a PRBS pattern generator and checker in the PMA layer, the present invention adds a BIST generation and check module compatible with the PIPE interface protocol in the PCS, which can not only implement the basic quality test of high-speed serial signals, but also cover the protocol-related function verification of the PCS (physical coding sub) layer. The present invention greatly reduces the test blind area of IP development and improves the test coverage of IP. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and form a part of the specification, indicating embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a flowchart of a method for implementing PCIE physical layer built-in self-test code of the present invention; Figure 2 It is an architecture diagram of a system for implementing PCIE physical layer built-in self-test code of the present invention; Figure 3 It is a schematic hardware structure diagram of an electronic device of the present invention. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0021] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0022] In the research and development of physical layer SerDes IP, the problems of attenuation, crosstalk, and jitter of high-speed serial signals are significantly aggravated, making it difficult for traditional testing methods to accurately evaluate the chip performance. At the same time, the PCIe protocol forcibly requires the adoption of efficient coding schemes such as 128b / 130b and 8b / 10b. How to synchronously plan the built-in test architecture in the early stage of circuit design, so that it can not only meet the simulation requirements of real scenarios in the early-stage simulation (such as the reproduction of dynamic signal degradation), but also support the quantitative diagnosis of post-silicon testing in the later stage (such as bit error rate detection, eye diagram analysis), has become the core problem for shortening the R & D cycle and ensuring the functional reliability of the chip. Currently, the industry generally adopts the scheme of integrating a PRBS pattern generator and checker in the PMA (Physical Medium Attachment) layer. Although it can achieve the basic quality testing of high-speed serial signals, its testing scope is limited to analog circuit characteristics (such as signal integrity, jitter tolerance), and it cannot cover the protocol-related function verification of the PCS (Physical Coding Sublayer) layer. This defect makes it difficult to comprehensively detect key protocol behaviors such as link state machine control, training sequence interaction, and power management in IP development, forming a testing blind spot.

[0023] Compared with the traditional solution of integrating PRBS pattern generators and checkers in the PMA layer, the present invention adds a BIST generation and check module compatible with the PIPE interface protocol in the PCS, which can not only perform basic quality tests on high-speed serial signals, but also cover protocol-related function verification of the PCS (Physical Coding Sublayer) layer. The present invention greatly reduces the test blind spots in IP development and improves the test coverage rate of the IP.

[0024] Embodiment 1 An implementation method for the built-in self-test code of the PCIE physical layer, characterized in that, referring to Figure 1 , including: S100, integrating a PCIE BIST GEN module in the controller layer to package data and send it to the physical coding sublayer; The PCIE BIST GEN module is a built-in self-test (BIST) signal generation module for the PCI Express (PCIE) interface. It is mainly used to verify and test the functions and performance of the PCIE interface to ensure that it meets the design specifications and standards. The PCIE BIST GEN module includes: Pattern Generator: Generates test data patterns, such as PRBS, fixed patterns or custom patterns. Control Logic: Controls the start, stop and pattern selection of the test. Configures test parameters, such as data rate, packet size, etc. Error Detection and Statistics: Detects data errors at the receiving end (such as bit error rate, BER). Statistics test results, such as the amount of data transmitted, the number of errors, etc. Interface Adapter: Adapts the generated test signals to the physical layer and protocol layer of the PCIe interface.

[0025] S200, the physical coding sublayer encodes the packaged data and sends it to the physical medium adaptation layer; S300, the physical medium adaptation layer converts the encoded data into serial data and sends it back to the controller layer.

[0026] The PCIE subsystem mainly consists of two parts: the PCIe Controller and the PCIE PHY. Among them, the physical layer is further divided into the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA). The controller layer communicates with the physical layer through the PIPE (PHY Interface for PCI Express) interface. During data transmission, the data is first packed in the controller layer and sent to the PCS through the PIPE interface. The PCS selects 8b / 10b or 128b / 130b encoding according to the transmission rate, and then passes the data to the PMA. The PMA is responsible for converting the parallel data into serial data and sending it out through the high-speed serial port. At the receiving end, the PMA reconverts the received serial data into parallel data and sends it back to the PCS. The PCS aligns and decodes the data, processes the cross-clock domain problem through the elastic buffer, and finally sends the data back to the controller layer through the PIPE interface for unpacking and processing. Such a structure ensures the efficient transmission and processing of data in the PCIe subsystem. Although the present invention is used in the PCIE protocol, the present invention patent can also be directly applied to the USB protocol that also meets the PIPE requirements.

[0027] The present invention innovatively embeds a protocol-aware BIST (Built-In Self-Test) architecture in the PCS layer: by integrating a programmable timing controller, it accurately generates training sequences (such as EIEOS, SKP, SDS) that conform to the PIPE interface specification, and supports dynamically inserting error code patterns to simulate protocol violation scenarios. This solution can not only verify the functional integrity of the 8b / 10b or 128b / 130b encoding and decoding modules. Combining the generation and detection functions of the electrical idle exit sequence (EIEOS) specified by the protocol, it realizes the full-stack coverage test from physical signals to protocol logic, increases the verification of protocol consistency compared with traditional solutions, and significantly reduces the dependence on high-end oscilloscopes and protocol analyzers in post-silicon testing.

[0028] Preferably, in S300, the physical medium attachment layer converts the encoded data into serial data and sends it back to the controller layer, including: S310, the physical medium attachment layer converts the encoded data into serial data and sends it to the physical coding sublayer; S320, the physical coding sublayer aligns and decodes the serial data; S330, sends the decoded data to the controller layer for unpacking processing; S340, integrates a PCIE BIST CHK module in the controller layer to complete the full-link closed-loop verification.

[0029] The PCIE BIST CHK module is a Built-In Self-Test Checker in the PCI Express (PCIe) interface. Its main function is to receive and verify the test data from the PCIE BIST GEN module (test signal generation module) to ensure the normal function of the receiving end (RX) of the PCIe interface and detect errors in data transmission. The PCIE BIST CHK module receives the test data from the PCIE BIST GEN module and verifies its correctness. For example, it checks whether the data matches the expected pattern (such as the PRBS pseudo-random sequence). It detects errors in data transmission, such as bit errors, packet loss, or protocol errors. For example, it checks the data integrity through CRC (Cyclic Redundancy Check) or LCRC (Link CRC). It statistics the test results, such as the bit error rate (BER), transmission delay, and throughput. It generates test reports for analyzing the performance of the PCIe interface. Fault diagnosis: It helps to locate problems at the receiving end, such as poor signal integrity, clock jitter, or logic errors.

[0030] The structure of the PCIE BIST CHK module includes: Data Receiver: Receives the test data from the PCIe interface. Pattern Checker: Compares the received data with the expected pattern to detect errors. For example, it checks whether the data matches the PRBS sequence. Error Detection Logic: Implements error detection mechanisms, such as CRC check, LCRC check, or protocol check. Statistics and Reporting Module: Statistics the test results (such as bit error rate, throughput) and generates reports. Control Logic: Controls the start, stop, and mode selection of the checking process. Configures the check parameters, such as data pattern, error detection method, etc.

[0031] The PCIE BIST GEN module is responsible for generating test signals and sending them to the PCIe interface. The PCIE BIST CHK module is responsible for receiving and verifying these test signals. The two are used in combination to comprehensively test the sending (TX) and receiving (RX) functions of the PCIe interface.

[0032] Preferably, in S100, integrating the PCIE BIST GEN module in the controller layer and packing data to send to the physical coding sublayer includes: Build a PRBS generator in the PCIE BIST GEN module to support three standard polynomial sequences of PRBS-7, PRBS-23, and PRBS-31 and user-defined UDP patterns, and support dynamically inserting error patterns to simulate protocol violation scenarios.

[0033] The present invention only supports PRBS-7, PRBS-23 and PRBS-31, and the present invention can also be directly applied to other PRBS code types.

[0034] The present invention integrates a PCIE BIST GEN module at the transmitting end. The self-built PRBS generator in the module supports three standard polynomial sequences of PRBS-7, PRBS-23, and PRBS-31 and user-defined UDP code patterns, and supports dynamic insertion of error code patterns to simulate protocol violation scenarios.

[0035] The BIST test generates test data through a built-in pseudo-random binary sequence (PRBS) generator to evaluate the link signal quality. Its core code types include three standard modes: PRBS-7 (polynomial X^7+X^6+1, sequence length 2^7-1 bits), PRBS-23 (X^23+X^18+1, 2^23-1 bits), and PRBS-31 (X^31+X^28+1, 2^31-1 bits), as well as user-defined code types (UDP). The standard PRBS sequence implements periodic cycles based on the principle of linear feedback shift registers, while the UDP mode supports configuring custom test templates through registers and implementing cyclic transmission, providing flexible programmable test capabilities for high-speed links.

[0036] Preferably, S340, integrating a PCIE BIST CHK module at the controller layer to complete full-link closed-loop verification includes: S341, integrated PCIE BIST CHK module supports receiving data streams with programmable data bit widths of 8 / 16 / 32-bit; The data bit width in the present invention supports 8-bit, 16-bit and 32-bit. If the data bit width is widened to 64-bit, the present invention can also be directly applied.

[0037] S342, after receiving the data stream outputted by the elastic buffer and conforming to the PIPE protocol, filter and remove the K code and OS code control characters and invalid data; K code is a control character, which is used to indicate non-data information (such as control commands, frame start / end flags, etc.). In 8b / 10b encoding, K code is distinguished from data characters (D code) so that the receiving end can recognize and process control information. OS code is an ordered set, which is used to transmit specific control information or status information in high-speed serial communication. An ordered set usually consists of multiple K codes or D codes, and is used to implement functions such as link training, state switching, and error recovery.

[0038] S343 performs real-time exclusive OR (XOR) verification on the received PRBS data and the reference data generated by the local PRBS generator. For UDP data, it performs a bit-by-bit comparison with the template data preset by the user. The received data is represented as: ; M is a set of binary numbers with m bits and a quantity of n. The "XOR" operation is performed on all the data to obtain the operation result: ; The error rate of the XOR verification is represented as: ; S344 triggers the error count accumulation mechanism for verification exceptions and finally determines the link quality based on the bit error rate within the continuous statistical period.

[0039] The present invention deploys a PCIE BIST CHK module at the receiving end to complete the full-link closed-loop verification. This module supports the reception of data streams with multiple programmable data bit widths (8 / 16 / 32-bit). After receiving the data stream that conforms to the PIPE protocol output by the elastic buffer, it first filters and eliminates control characters such as K codes and OS codes and some invalid data, and then performs real-time XOR verification on the received PRBS data and the reference data generated by the local PRBS generator. For UDP data, it performs a bit-by-bit comparison with the template data preset by the user. Verification exceptions trigger the error count accumulation mechanism, and finally the link quality is determined based on the bit error rate (BER) within the continuous statistical period. This dual-end collaborative architecture can completely cover the function and fault tolerance verification of the entire SerDes path.

[0040] Preferably, S200, the physical coding sublayer encodes the packed data and sends it to the physical medium adaptation layer, including: S210, when the transmitter starts transmission, it sets the txelecidle signal low. In Gen1 / Gen2 mode, the physical coding sublayer adopts the 8b / 10b coding mechanism; S220, identifies the data type through the txdata_k signal, where 1 represents regular data and 0 represents K code; S230, when in Gen3 / Gen4 / Gen5 mode, the coding mechanism switches to 128b / 130b, and fine control is performed through a combined signal group including marking the start of a new data block txstartblock with a high level, the synchronous control signal and data txdatavalid within the high-level effective window, identifying the OS code with 2'b01, and identifying regular data with 2'b10; S240, according to the data bit width requirement of the bus, periodically sets the txdatavalid low to balance the encoding and decoding throughput; S250, set the txelecidle signal high when data transmission is completed.

[0041] The PIPE protocol has strict constraints on the timing control of data transmission and reception: when the transmitter starts transmission, it needs to first set the txelecidle signal low. In Gen1 / Gen2 mode, the PCS layer uses an 8b / 10b encoding mechanism, and at this time, the data type is identified by the txdata_k signal (1 for regular data, 0 for K code); when upgraded to Gen3 / Gen4 / Gen5 mode, the encoding scheme switches to 128b / 130b, and fine control needs to be achieved through the combined signal group of txstartblock (high level marks the start of a new data block), txdatavalid (synchronization control signal and data within the high-level valid window), and txheader (2'b01 identifies the OS code, 2'b10 identifies regular data). At the same time, according to the data bit-width requirements of the bus, it is necessary to periodically set txdatavalid low to balance the encoding and decoding throughput. When data transmission is completed, the txelecidle signal needs to be set high. All signal timings must strictly follow the protocol specifications to ensure the stable operation of the physical layer encoder.

[0042] Preferably, S320, the physical coding sublayer aligns and decodes serial data, including: S321, perform physical layer alignment and decoding operations on the data stream, where the decoding module performs synchronization control based on the OS code and completes decoding output according to the protocol timing; S322, perform cross-clock domain processing of the receive clock and the protocol layer clock through an elastic buffer, and dynamically implement SKP code deletion / insertion operations by monitoring the difference between the read and write pointers in real time to maintain the balance state of the buffer.

[0043] The data processing flow at the receiver follows strict protocol timing specifications: the data stream first undergoes physical layer alignment and decoding operations, where the decoding module highly depends on the OS code for synchronization control - detecting the data boundary by detecting the OS code and completing decoding output according to the protocol timing. Since the receive clock rxclk comes from a clock data recovery (CDR) circuit, and the pclk used by the protocol layer is generated by a PLL, cross-clock domain processing needs to be performed through an elastic buffer (EBUF). Given the inherent frequency difference between the two clock domains, long-term operation will pose a risk of EBUF overflow, which may lead to abnormal data reception. Therefore, the system dynamically implements SKP code deletion / insertion operations (Delete / Add SKP Ordered Sets) by monitoring the difference between the read and write pointers in real time to maintain the balance state of the buffer and ensure the continuity of the data stream.

[0044] Preferably, S340, integrating the PCIE BIST GEN module in the controller layer to package data and send it to the physical coding sublayer further includes: S341 inserts a COMMA code or an EIEOS code with a configurable length in the sequence preamble to assist the receiving end in completing the alignment and locking of the initial data; S342 performs frequency difference compensation for the RX - side CDR - recovered clock and the PLL - generated clock, and supports a programmable configuration for the dynamic insertion of SKP code strategy.

[0045] In the embodiments of the present invention, a COMMA code or an EIEOS code with a configurable length can be inserted in the sequence preamble to assist the receiving end in completing the alignment and locking of the initial data; for the frequency difference compensation between the rxclk (CDR - recovered clock) and the pclk (PLL - generated clock) on the RX side, the present invention supports a programmable configuration for the dynamic insertion of SKP code strategy. In addition, the present invention supports the output of test data streams that meet the timing requirements of the PIPE protocol under multiple programmable data bit - widths (8 / 16 / 32 - bit). Subsequently, the test data stream can cover the functional and electrical performance tests of the PCS, PMA, and the link.

[0046] Embodiment 2 An implementation system for the built - in self - test code of the PCIE physical layer, refer to Figure 2 , including: A data transmission module, which is used to integrate the PCIE BIST GEN module in the controller layer to pack data and send it to the physical coding sub - layer; A data encoding module, which is used for the physical coding sub - layer to encode the packed data and send it to the physical medium adaptation layer; A data conversion module, which is used for the physical medium adaptation layer to convert the encoded data into serial data and send it back to the controller layer.

[0047] Embodiment 3 An electronic device, including: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes the implementation method for the built - in self - test code of the PCIE physical layer.

[0048] Refer to Figure 3 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled through a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling means being interconnected in a specific manner, including being directly connected or indirectly connected through other devices, for example, being connected through various interfaces, transmission lines, buses, etc.

[0049] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0050] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for implementing the solution of the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and the memory is used for relevant instructions and data.

[0051] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0052] Embodiment 4 A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for implementing PCIE physical layer built-in self-test code.

[0053] Compared with the traditional solution of integrating a PRBS pattern generator and checker in the PMA layer, in the present invention, by adding a BIST generation and check module compatible with the PIPE interface protocol in the PCS, not only can the basic quality test of high-speed serial signals be realized, but also the protocol-related function verification of the PCS (physical coding sublayer) can be covered. The present invention greatly reduces the test blind area in IP development and improves the test coverage rate of the IP.

[0054] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for implementing a PCIE physical layer built-in self-test code, characterized in that: include: Integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer; The PCIE BIST GEN module is used to verify and test the function and performance of the PCIE interface, and the PCIE BIST GEN module includes: a pattern generator, a control logic module, an error detection and statistics module and an interface adapter; The physical coding sublayer encodes the packaged data and sends it to the physical medium adaptation layer; The physical medium adaptation layer converts the encoded data into serial data and transmits it back to the controller layer; The PCIE BIST CHK module is integrated in the controller layer to complete the full link closed loop verification and send it to the physical medium adaptation layer; The PCIE BIST CHK module is used to receive and verify the test data from the PCIE BIST GEN module (, and the PCIE BIST CHK module includes: a data receiver, an error detection logic module, a statistics and reporting module and a control logic module; The integrating the PCIE BIST CHK module at the controller layer to complete the full-link closed-loop verification includes: The integrated PCIE BIST CHK module supports receiving data streams with programmable data bit widths of 8 / 16 / 32-bit; After receiving the data stream outputted by the elastic buffer in accordance with the PIPE protocol, the K code and OS code control characters and invalid data are filtered and removed; The received PRBS data is subjected to real-time XOR verification with the reference data generated by the local PRBS generator, and the UDP data is compared bit by bit with the template data preset by the user; Verification anomalies trigger the error count accumulation mechanism, and ultimately the link quality is determined based on the bit error rate within a continuous statistical period.

2. The method for implementing a PCIE physical layer built-in self-test code according to claim 1, characterized in that: The physical medium adaptation layer converts the encoded data into serial data and transmits it back to the controller layer, including: The physical medium adaptation layer converts the encoded data into serial data and sends it to the physical coding sublayer; The physical coding sublayer aligns and decodes the serial data; The decoded data is sent to the controller layer for unpacking.

3. The method for implementing a PCIE physical layer built-in self-test code according to claim 1, characterized in that: The step of integrating the PCIE BIST GEN module in the controller layer to package data and send it to the physical coding sublayer includes: The self-built PRBS generator in the PCIE BIST GEN module supports three standard polynomial sequences, PRBS-7, PRBS-23, and PRBS-31, and user-defined UDP code patterns, and supports dynamic insertion of error code patterns to simulate protocol violation scenarios.

4. The method for implementing a PCIE physical layer built-in self-test code according to claim 1, characterized in that: The physical coding sublayer encodes the packaged data and sends it to the physical medium adaptation layer, including: The transmitter sets the txelecidle signal low when starting transmission. In Gen1 / Gen2 mode, the physical coding sublayer uses the 8b / 10b encoding mechanism; The data type is identified by the txdata_k signal, 1 is regular data, and 0 is K code; When in Gen3 / Gen4 / Gen5 mode, the encoding mechanism is switched to 128b / 130b, and fine control is performed through a combination of high-level marking of the start of a new data block txstartblock, high-level valid window synchronization control signal and data txdatavalid, 2'b01 to identify the OS code, and 2'b10 to identify the regular data; According to the data width requirements of the bus, txdatavalid is periodically set low to balance the encoding and decoding throughput; When the data is sent, the txelecidle signal is set high.

5. The method for implementing a PCIE physical layer built-in self-test code according to claim 2, characterized in that: The physical coding sublayer aligns and decodes serial data including: The data stream performs physical layer alignment and decoding operations, where the decoding module performs synchronization control according to the OS code and completes the decoding output according to the protocol timing; The cross-clock domain processing of the receiving clock and the protocol layer clock is performed through the elastic buffer. The SKP code deletion / insertion operation is dynamically implemented by real-time monitoring of the read-write pointer difference to maintain the balance of the buffer area.

6. The method for implementing a PCIE physical layer built-in self-test code according to claim 3, characterized in that: The step of integrating the PCIE BIST GEN module in the controller layer to package data and send it to the physical coding sublayer also includes: Insert a COMMA code or EIEOS code of configurable length into the leading segment of the sequence to assist the receiving end in completing the alignment and locking of the initial data; The system compensates for the frequency difference between the CDR recovered clock and the PLL generated clock at the RX end and supports the dynamic insertion of SKP code strategy under programmable configuration.

7. A system for implementing a PCIE physical layer built-in self-test code, applied to the method for implementing a PCIE physical layer built-in self-test code according to claims 1-6, characterized in that: include: Data transmission module, used to integrate PCIE BIST GEN module in the controller layer to package data and send it to the physical coding sublayer; A data encoding module, used for the physical coding sublayer to encode the packaged data and send it to the physical medium adaptation layer; The data conversion module is used for the physical medium adaptation layer to convert the encoded data into serial data and transmit it back to the controller layer.

8. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes the implementation method for the PCIE physical layer built-in self-test code as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: A computer program is stored in the computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the implementation method for the PCIE physical layer built-in self-test code described in any one of claims 1 to 6.

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