Dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on RISC-V architecture

Abstract

The invention relates to a dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on an RISC-V architecture. The method comprises the following steps: 1) initializing a dynamic adjustable multi-core cooperation system; comprising the steps that a hardware module is initialized, and the hardware module comprises a high-performance core P-core, a low-power-consumption core E-core, a hardware scheduling unit HSU and a power management unit PMU; loading a task queue, and marking task characteristics; 2) core state monitoring; comprising the following steps: an HSU monitors a core state; the power management unit PMU monitors voltage and frequency; 3) dynamic task scheduling; comprising the steps that task characteristics are allocated to a high-performance core P-core or a low-power-consumption core E-core; the idle core enters a low-power-consumption mode; and 4) self-adaptive energy saving is realized, and task migration is carried out. And through a dynamic task scheduling and energy-saving optimization algorithm, the flexibility and efficiency of the RISC-V multi-core processor are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-core processors, and particularly to a method for dynamic multi-core collaboration and power consumption optimization based on the RISC-V architecture, specifically including a dynamically adjustable multi-core collaboration mechanism and its application in energy saving and efficient operation. Background Art

[0002] With the increasing complexity of computing tasks and the continuous growth of the demand for high performance and low power consumption, multi-core processor architectures have become the core technology of modern computing devices. Traditional multi-core architectures usually include high-performance cores (Performance Core, P-core) and energy-efficient cores (Efficiency Core, E-core), which achieve a balance between performance and power consumption by collaborating to process different load tasks. For example, the big.LITTLE technology of the ARM architecture significantly improves the energy efficiency of the system by dynamically allocating tasks to different cores. However, the implementation of this technology usually depends on highly specialized instruction sets and hardware designs, making it difficult to flexibly migrate to other open architecture platforms.

[0003] Existing RISC-V multi-core processors lack mature solutions in task collaboration and power consumption optimization. Currently, most multi-core designs in the RISC-V ecosystem are based on symmetric multi-processing (SMP), and do not fully utilize the potential of heterogeneous multi-cores, and cannot flexibly schedule tasks to adapt to diverse workloads. At the same time, traditional RISC-V power consumption optimization mainly relies on static frequency and voltage adjustment (such as DVFS), and in the case of large dynamic load changes, the response speed is insufficient, resulting in low power efficiency. Moreover, the functions of the current hardware scheduling unit (HSU) and power management unit (PMU) of the RISC-V architecture are limited, unable to provide fine-grained monitoring and scheduling of multi-core states, and no complete ecological standard has been formed.

[0004] Therefore, for the RISC-V architecture, using new methods to overcome the deficiencies in the prior art and improve the performance and energy efficiency of RISC-V multi-core processors has become an urgent problem to be solved. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention proposes a dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on the RISC-V architecture;

[0006] The present invention proposes a dynamically adjustable multi-core cooperation mechanism based on the RISC-V architecture. By innovatively combining hardware monitoring, task scheduling algorithms, and power consumption optimization strategies, and by extending the control and status registers of RISC-V, it provides multi-core status monitoring, task load prediction, and dynamic task migration functions, realizing efficient cooperation between heterogeneous multi-cores. At the same time, combined with lightweight AI algorithms and dynamic voltage and frequency scaling (DVFS) technology, it further optimizes the startup, shutdown, and frequency control of cores, improving the accuracy and real-time performance of power consumption control. A hardware scheduling unit (HSU) and a power management unit (PMU) based on RISC-V are designed to provide real-time acquisition and analysis of core status, forming a complete software-hardware combined solution.

[0007] Through the implementation of the present invention, the RISC-V architecture will possess multi-core cooperation capabilities similar to those of ARM big.LITTLE technology. At the same time, relying on its openness and scalability, it will demonstrate strong innovation and practicality in more scenarios (such as the Internet of Things, embedded devices, and high-performance computing).

[0008] The present invention also proposes a dynamically adjustable multi-core cooperation mechanism and power consumption optimization system based on the RISC-V architecture;

[0009] Term Explanation:

[0010] 1. HSU: The Hardware Scheduler Unit (HSU) is a dedicated hardware module integrated into the processor, responsible for managing task allocation and scheduling in a multi-core processor. The HSU is an important component for implementing the dynamic multi-core cooperation mechanism. The HSU can collect the running status of each core in real time, including information such as task execution, power consumption, and temperature. These data are obtained through extended control and status registers (CSRs) and used as the basis for scheduling decisions; at the same time, the HSU can dynamically determine whether a task should be assigned to a performance core (P-core) or an energy-efficient core (E-core) according to the characteristics of the task (such as computational intensity and real-time requirements) and the current status of the core (such as load, power consumption, temperature), achieving efficient task load balancing; the HSU works in coordination with the power management unit (PMU) to dynamically adjust the operating frequency, voltage, and startup / shutdown status of the core by analyzing the core load trend and task requirements, optimizing the overall energy efficiency of the system.

[0011] 2. CSR: The Control and Status Register (CSR) is a set of dedicated registers within a processor used to store and manage information related to the processor's status, configuration, and control. The CSR is mainly used to store the operating status of the processor core, such as the current task context being executed, performance counter information, etc. These status information provide the basis for task scheduling and system management; at the same time, the CSR can record the task running status of the current core, such as the register content, the position of the program counter (PC), etc. During task migration, by accessing the CSR, the task context can be saved or restored to achieve seamless task switching; the CSR stores the performance count data of the core, such as the number of instructions executed, cache hit rate, etc. These data can help the Hardware Scheduling Unit (HSU) analyze the current core load and provide a basis for task allocation; the extended CSR can work in collaboration with the Power Management Unit (PMU) to record the power consumption and temperature information of the core, and control frequency, voltage adjustment, and core startup and shutdown operations through software interfaces to achieve real-time power consumption optimization.

[0012] The technical solution of the present invention is as follows:

[0013] A dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture, including:

[0014] 1) Initialization of the dynamic adjustable multi-core cooperation system; including:

[0015] Initializing the hardware modules, where the hardware modules include a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU;

[0016] Loading the task queue and marking the task characteristics (priority, real-time performance, etc.);

[0017] 2) Core status monitoring; including:

[0018] The HSU monitors the core status (load, power consumption, temperature);

[0019] The power management unit PMU monitors the voltage and frequency;

[0020] 3) Dynamic task scheduling; including:

[0021] Allocating according to the task characteristics to the high-performance core P-core or the low-power core E-core;

[0022] Idle cores enter the low-power mode;

[0023] 4) Adaptive energy saving and task migration;

[0024] Adaptive energy saving; including: predicting task load changes; starting or shutting down cores in advance;

[0025] Task migration; including: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency;

[0026] Return to step 2) to continue monitoring.

[0027] Preferably according to the present invention, the hardware module is initialized using RISC-V startup and interrupt control instructions.

[0028] Preferably according to the present invention, load the task queue and mark the task characteristics; including:

[0029] Analyze the current task queue, determine the priority, load type, and real-time requirements of the task, and store the task characteristics in the task scheduling table.

[0030] Preferably according to the present invention, the HSU monitors the core status, and the core status includes load, power consumption, and temperature;

[0031] The PMU periodically collects the core status;

[0032] Adopt a step-by-step threshold trigger mechanism, including:

[0033] When any one of the load, power consumption, or temperature exceeds 80% of the threshold of the load, power consumption, or temperature, a single indicator warning is given, and the core status is recorded;

[0034] When two or more indicators exceed the threshold at the same time, dynamic task scheduling is immediately triggered to perform task migration or core start / stop;

[0035] When two or more indicators are in a low occupancy state for a long time, the scheduler reallocates multiple processor tasks and shuts down the redundant idle processors.

[0036] Preferably according to the present invention, dynamic task scheduling; including: high-performance core P-core or low-power core E-core

[0037] Apply dynamic frequency adjustment to the high-performance core P-core and low-power core E-core, set independent frequencies and voltages for each core, increase the frequency of the high-load core, i.e., the high-performance core P-core, and reduce the frequency and voltage of the low-load core, i.e., the low-power core E-core;

[0038] According to the task characteristics and core status, use RISC-V scheduling extension instructions to implement task allocation; assign compute-intensive tasks to the high-performance core P-core, lightweight tasks or background tasks to the low-power core E-core; assign low-priority tasks to the low-power core E-core or delay scheduling.

[0039] Further preferably, the cores are dynamically started and stopped using the RISC-V low-power extension instructions; when the load increases, more cores are woken up; when the load decreases, the idle cores are turned off and switched to the low-power mode.

[0040] Preferably according to the present invention, adaptive energy saving; includes:

[0041] Based on the lightweight AI model, predicting future load changes through task historical data, and starting or shutting down cores in advance to adapt to the predicted load changes;

[0042] If the current task queue is empty, all high-performance cores P-core are turned off, and only one low-power core E-core is kept running in the low-power mode.

[0043] Preferably according to the present invention, task migration; includes:

[0044] Task migration is triggered when one of the following conditions is met:

[0045] ① The current core temperature exceeds the temperature setting threshold or the current core power consumption exceeds the power consumption setting threshold;

[0046] ② The current core load is continuously too high or too low;

[0047] ③ The task characteristics do not match the current core type;

[0048] During task migration, the extended instructions are used to save the task state to the shared memory, and then the task context is restored on the target core.

[0049] A computer device, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture are implemented.

[0050] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture are implemented.

[0051] The dynamic adjustable multi-core cooperation mechanism and power consumption optimization system based on the RISC-V architecture, includes:

[0052] An initialization module, configured to: initialize the dynamic adjustable multi-core cooperation system; includes: initializing the hardware module, the hardware module includes high-performance cores P-core, low-power cores E-core, a hardware scheduling unit HSU, and a power management unit PMU; loading the task queue and marking the task characteristics;

[0053] The core status monitoring module is configured to: the HSU monitors the core status; the power management unit PMU monitors the voltage and frequency;

[0054] The dynamic task scheduling module is configured to: allocate tasks to the high-performance core P-core or the low-power core E-core according to task characteristics; the idle core enters the low-power mode;

[0055] The adaptive energy-saving and task migration module is configured to: adaptively save energy; including: predicting changes in task load; starting or shutting down cores in advance; task migration; including: saving the task context to shared content, restoring the task context on the target core, and ensuring cache coherence.

[0056] The beneficial effects of the present invention are as follows:

[0057] The core innovation of the present invention lies in the co-design of software and hardware. Through dynamic task scheduling and energy-saving optimization algorithms, the flexibility and efficiency of the RISC-V multi-core processor are significantly improved. The functions of the present invention are reflected in many aspects: through the task allocation of heterogeneous multi-cores, fast response to high-performance tasks and efficient execution of low-power-consuming tasks are achieved; through the adaptive energy-saving mechanism, energy consumption is reduced and the device battery life is extended; through the extended hardware module and instruction set, the function and ecological adaptability of the RISC-V architecture are enhanced, providing an innovative technical solution for fields such as embedded devices, the Internet of Things, edge computing, and high-performance computing. Description of the Drawings

[0058] Figure 1 It is a schematic flow diagram of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture of the present invention;

[0059] Figure 2 It is a schematic overall flow diagram of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture of the present invention. Detailed Embodiments

[0060] The present invention will be further limited below in conjunction with the description drawings and embodiments, but not limited thereto.

[0061] Embodiment 1

[0062] The dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture, as Figure 1 and Figure 2 shown, includes:

[0063] 1) Initialization of the dynamic adjustable multi-core cooperation system; the dynamic adjustable multi-core cooperation system includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU; including:

[0064] Initialize the hardware module, which includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU;

[0065] Load the task queue and mark the task characteristics (priority, real-time performance, etc.);

[0066] 2) Core status monitoring; including:

[0067] HSU monitors the core status (load, power consumption, temperature);

[0068] The power management unit PMU monitors the voltage and frequency; the required voltage and frequency of the processor are different in different modes. The PMU monitors the current voltage and frequency of each processor and compares them with the target voltage and frequency set by the HSU to achieve real-time monitoring of the processor status.

[0069] 3) Dynamic task scheduling; including:

[0070] Allocate tasks to the high-performance core P-core or the low-power core E-core according to task characteristics;

[0071] Idle cores enter the low-power mode;

[0072] 4) Adaptive energy saving and task migration;

[0073] Adaptive energy saving; including: predicting task load changes (lightweight AI module); starting or shutting down cores in advance;

[0074] Task migration; including: saving the task context to shared content, restoring the task context on the target core, and ensuring cache coherence;

[0075] Return to step 2) to continue monitoring.

[0076] Embodiment 2

[0077] According to the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture described in Embodiment 1, the difference is that:

[0078] Initialize the hardware module using RISC-V startup and interrupt control instructions.

[0079] The P-core is a high-performance core (Performance Core, P-core): supports high-frequency operation, large caches, and vector instruction set extensions (such as RVV), and is suitable for compute-intensive tasks.

[0080] The core is configured to high-performance mode by using extended CSR registers. This mode allows the core to run at a higher frequency while enabling all computing units. The initial operating frequency and voltage of the P-core are set through PMU and CSR extension instructions (maintained at a medium-high level within its supported range to exert its performance). The cache and prefetch mechanisms are enabled, and the cache prefetcher is configured to provide the ability to preload data for high-performance computing tasks, so as to reduce memory access latency. Hardware acceleration units such as vector processors and matrix calculation accelerators are enabled to improve the performance of compute-intensive tasks. After initialization, the core self-check program is run and the core enters the standby state.

[0081] The E-core is a low-power core (Efficiency Core, E-core): optimized for low-frequency and low-voltage operation, only supporting basic instruction sets (such as RV32I or RV64I), suitable for background tasks or lightweight tasks.

[0082] The core is configured to low-power mode by using extended CSR registers. This mode allows the core to run at a lower frequency and voltage while activating specific energy-saving functions such as dynamic clock gating and power gating. An automatic idle detection mechanism is configured for the E-core. When the core is in a long-term idle state, it automatically switches to the deep sleep mode to further reduce power consumption. The initial operating frequency and voltage of the P-core are set through PMU and CSR extension instructions (maintained at a medium-low level within its supported range to reduce power consumption). The level-1 cache (L1Cache) of the E-core is started, and the cache size is restricted to reduce energy consumption. At the same time, the shared level-2 cache (L2 Cache) is enabled to support multi-core collaboration. The cache coherence protocol is set to ensure that the data shared by the E-core and other cores remains consistent during task migration and collaboration. A lightweight data prefetch mechanism is activated to optimize the memory access path for common background tasks (such as data collection or logging), reducing unnecessary cache accesses. The simplified arithmetic logic unit built into the E-core is enabled, focusing on low-complexity computing tasks. After initialization, the core self-check program is run and the core enters the standby state.

[0083] Initialize the hardware scheduling unit (HSU), which is responsible for real-time analysis of core status and task allocation, and cooperates with extended RISC-V instructions to achieve efficient scheduling signal processing.

[0084] Initialize the main hardware modules of the HSU, including the task queue management unit, task allocation logic circuit, and core status monitoring module. Configure the task queue management, allocate multi-level task queues (high-priority queue, medium-priority queue, and low-priority queue) for task scheduling, set the capacity and scheduling policy of the task queues, configure the synchronization mechanism between the task queues and the shared memory, so that task information can be read and modified by multiple cores; Initialize the task scheduling algorithm, load the multi-core task scheduling algorithm inside the HSU, including the dynamic scheduling policy based on lightweight AI prediction, configure the optimization options of the HSU scheduling logic, including task packing, task decomposition, and dynamic adjustment, to ensure the lowest scheduling overhead in the allocation between cores; Configure multi-core monitoring and status collection, activate the core status monitoring module of the HSU, and collect the running status of each core by extending the CSR register; Configure the communication interface between the HSU and the power management unit (PMU), so that the HSU can dynamically adjust the frequency and voltage (DVFS) of the core according to the task allocation requirements. Finally, perform a self-check and enter the standby mode.

[0085] Initialize the power management unit (PMU), which monitors voltage and frequency information and dynamically adjusts the power state of the core;

[0086] Activate the power supply module of the PMU, set an independent clock signal to provide a high-precision and low-latency working environment for the PMU; Initialize the low-power mode logic of the PMU so that it can automatically enter the energy-saving state to reduce power consumption when the system load is low; Initialize the multi-core dynamic voltage and frequency control module of the PMU to be able to configure the P-core and E-core separately; Configure the communication interface with the HSU so that the PMU can receive voltage and frequency adjustment requests sent by the HSU; Initialize the DVFS mapping table of the PMU to associate the voltage and frequency configuration of the core with the load demand; Initialize the low-power mechanism to support the fast switching of core states (high-performance mode, low-power mode, sleep); Finally, perform a self-check and enter the standby mode.

[0087] Initialize the shared cache module: Use the RISC-V cache coherence protocol to ensure data coherence and efficient communication between multiple cores.

[0088] Load the task queue and mark the task characteristics (priority, real-time, etc.); including:

[0089] Analyze the current task queue, determine the priority, load type (compute-intensive or lightweight) and real-time requirements of the task, and store the task characteristics in the task scheduling table.

[0090] Task priorities: Read predefined priority tags (for example, operating system kernels, real-time tasks, etc. usually have higher priorities, while ordinary background service tasks have lower priorities; priority tags are set by developers during the task definition phase); Dynamically adjust through real-time monitoring of task running status (tasks that have not been completed for a long time may need to have their priorities increased; sudden high-load real-time tasks (such as audio and video decoding, sensor data processing) will be temporarily set to high priority).

[0091] Load type: Analyze task characteristics before task allocation: Compute-intensive tasks mainly consist of complex algorithms or a large number of floating-point / integer operations, such as image processing, data encryption, AI inference, etc.; Lightweight tasks consume fewer resources and are usually simple logical judgment or short-time input / output tasks, such as sensor data reading, status detection, etc.; Analyze during task runtime: Tasks with a long execution time and a high CPU occupancy rate are classified as compute-intensive tasks; Tasks that consume fewer resources and frequently enter the idle waiting state are classified as lightweight tasks; The system uses the historical records of task execution (such as execution duration, resource occupancy pattern) and lightweight AI algorithms to predict the load type of the current task.

[0092] Real-time requirements: Annotate during task definition: During the system design phase, developers annotate the real-time requirements for tasks (hard real-time tasks, such as device control, communication protocol processing; soft real-time tasks, such as audio and video playback, sensor data processing; non-real-time tasks, such as log recording, background computing); Dynamically adjust during runtime: If a task's delay exceeds the set threshold, its real-time requirements can be upgraded to a higher level; If a task executes quickly and has low resource occupancy, its real-time requirements can be lowered.

[0093] The HSU monitors the core status, and the core status includes load (current instruction execution rate), power consumption (obtain the core power consumption through the PMU), and temperature (monitor through hardware sensors).

[0094] The PMU periodically collects the core status; for real-time analysis by the scheduler in the PMU.

[0095] Adopt a step-by-step threshold trigger mechanism, including:

[0096] When any one of the indicators of load, power consumption, or temperature exceeds 80% of the threshold of load, power consumption, or temperature, a single indicator warning is issued and the core status is recorded; However, task scheduling is not immediately triggered, and only the task allocation strategy is optimized.

[0097] When two or more metrics simultaneously exceed the thresholds (e.g., load > 80%, power consumption > 80%, temperature > 75°C), dynamic task scheduling is immediately triggered for task migration or core start / stop; it is only considered that the metrics exceed the thresholds when they have been exceeding the thresholds within a certain time window, thus excluding false judgments due to jitter.

[0098] When two or more metrics are in a low occupancy state for a long time (e.g., the loads of multiple processors are all < 10%, power consumption < 10%), the scheduler reallocates the tasks of multiple processors and shuts down the redundant idle processors to save energy consumption.

[0099] Dynamic task scheduling; including: high-performance core P-core or low-power core E-core

[0100] Apply dynamic voltage and frequency scaling (DVFS) to the high-performance core P-core and low-power core E-core, set independent frequencies and voltages for each core, increase the frequency of the high-load core (i.e., the high-performance core P-core) to improve performance, and reduce the frequency and voltage of the low-load core (i.e., the low-power core E-core) to save energy consumption; during the processor initialization phase, several P-cores and E-cores will be allocated to handle different types of tasks. During operation, although the P-core and E-core cannot be directly converted, the operating frequencies and power consumption of the P-core and E-core can be adjusted to a certain extent through DVFS technology. For example: in an overall low-load scenario, the P-core can operate at a reduced frequency to simulate the energy efficiency characteristics of the E-core; in an overall high-load scenario, the E-core can increase the frequency to improve performance for a short time.

[0101] According to the task characteristics and core status, use the RISC-V scheduling extension instructions to achieve task allocation; allocate compute-intensive tasks to the high-performance core P-core, lightweight tasks or background tasks to the low-power core E-core; allocate low-priority tasks to the low-power core E-core or postpone scheduling.

[0102] Use the RISC-V low-power extension instructions (such as WFI) to dynamically start and stop cores; when the load increases, wake up more cores; when the load decreases, shut down the idle cores and switch to the low-power mode. When it is found that the task load of the P-core is too low, or the tasks of the E-core require higher performance, task migration will be triggered.

[0103] Adaptive energy saving; including:

[0104] Based on a lightweight AI model, predict future load changes through task historical data, and start or shut down cores in advance to adapt to the predicted load changes;

[0105] The lightweight AI model adopts a simplified shallow neural network structure. The training process is completed in the development stage, and during runtime, only the trained model weights need to be loaded for fast inference. The PMU inputs data such as the collected load, power consumption, temperature, and task characteristics into the model to predict the load change trend in the short term and give optimization suggestions.

[0106] The AI model will save the load change history within a past time window. By predicting the load change in the future time window from historical load data (load change trend, periodic characteristics), current task characteristics (which may trigger other high-load tasks, etc.), analyzing the running cycle of the task, the frequency and duration of the load peak, and combining with the collaborative states of other cores, it predicts the load trend in the next time window. At the same time, by comparing the actual load change with the prediction result, it adjusts the model parameters (such as decision thresholds or network weights) to improve the accuracy of future predictions.

[0107] If the current task queue is empty, turn off all high-performance cores (P-cores) and only keep one low-power core (E-core) running in the low-power mode to further reduce power consumption.

[0108] Task migration; including:

[0109] Task migration is triggered when one of the following conditions is met:

[0110] ① The current core temperature exceeds the temperature setting threshold or the current core power consumption exceeds the power consumption setting threshold;

[0111] ② The current core load is continuously too high or too low; to avoid ineffective task migration caused by sudden short-term high occupancy during the operation of low-load tasks, the present invention uses a time-window-based load evaluation mechanism. If the core load continuously exceeds the threshold within the time window, it is marked as exceeding the threshold to trigger a step-by-step threshold trigger mechanism. This effectively reduces the occurrence frequency of ineffective task migrations and improves the stability and energy efficiency of system scheduling.

[0112] ③ The task characteristics do not match the current core type; for example, high-load tasks running on E-cores; high-real-time tasks (real-time video decoding tasks), short-time peak tasks (such as short-time animation rendering triggered by users, which have high demand for processor resources in a short time but usually have a short duration), etc. are assigned to E-cores for operation; background low-priority tasks occupying P-cores for a long time, etc.

[0113] During task migration, use extended instructions to save the task state to shared memory, and then restore the task context on the target core to ensure seamless task switching. To ensure cache coherence, it is necessary to maintain data consistency among multiple cores through the RISC-V cache coherence protocol.

[0114] Task status (task data): The register status of the current task under the current core (general-purpose registers, program registers, status registers, etc.); memory context (stack pointer, global and local variables, etc.); current task scheduling information; cache data of the current core, etc.

[0115] Write the task data of the current core into the target core specified by the task migration module to ensure that no critical data and process status are lost when the task continues to execute on the new core.

[0116] Embodiment 3

[0117] A computer device includes a memory and a processor. When the processor executes the computer program stored in the memory, it implements the steps of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture described in Embodiment 1 or 2.

[0118] Embodiment 4

[0119] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, it implements the steps of the dynamic adjustable multi-core cooperation mechanism and power consumption optimization method based on the RISC-V architecture described in Embodiment 1 or 2.

[0120] Embodiment 5

[0121] A dynamic adjustable multi-core cooperation mechanism and power consumption optimization system based on the RISC-V architecture includes:

[0122] An initialization module, configured to: initialize the dynamic adjustable multi-core cooperation system; including: initializing the hardware module, which includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU; loading the task queue and marking the task characteristics;

[0123] A core status monitoring module, configured to: the HSU monitors the core status; the power management unit PMU monitors the voltage and frequency;

[0124] A dynamic task scheduling module, configured to: allocate tasks to the high-performance core P-core or the low-power core E-core according to the task characteristics; the idle core enters the low-power mode;

[0125] An adaptive energy-saving and task migration module, configured to: adaptive energy-saving; including: predicting the change of task load; starting or shutting down the core in advance; task migration; including: saving the task context to the shared content and restoring the task context on the target core to ensure cache consistency.

Claims

1. A dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture, characterized in that: include: 1) Dynamically adjustable multi-core collaborative system initialization; including: Initialize the hardware module, which includes the high-performance core P-core, the low-power core E-core, the hardware scheduling unit HSU, and the power management unit PMU; Load the task queue and mark the task characteristics; 2) Core status monitoring; including: HSU monitors the core status; The power management unit PMU monitors voltage and frequency; 3) Dynamic task scheduling; including: Assign to high-performance core P-core or low-power core E-core according to task characteristics; Idle cores enter low-power mode; 4) Adaptive energy saving and task migration; Adaptive energy saving; including: predicting task load changes; starting or shutting down cores in advance; Task migration: including: saving task context to shared content, restoring task context on the target core, and ensuring cache consistency; Return to step 2) to continue monitoring.

2. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1 is characterized in that: Initialize hardware modules using RISC-V startup and interrupt control instructions.

3. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that: Load the task queue and mark the task characteristics; including: Analyze the current task queue, determine the task priority, load type and real-time requirements, and store the task characteristics in the task scheduling table.

4. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that: HSU monitors the core status, which includes load, power consumption and temperature; PMU periodically collects core status; Adopt a step-by-step threshold trigger mechanism, including: When any of the load, power consumption or temperature indicators exceeds 80% of the threshold value of load, power consumption or temperature, a single indicator warning is issued to record the core status; When two or more indicators exceed the threshold at the same time, dynamic task scheduling is triggered immediately to perform task migration or core start and stop; When two or more indicators are in a low occupancy state for a long time, the scheduler reallocates tasks among multiple processors and shuts down excess idle processors.

5. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that: Dynamic task scheduling; including: high-performance core P-core or low-power core E-core Dynamic frequency adjustment is applied to the high-performance core P-core and the low-power core E-core. Independent frequency and voltage are set for each core. The high-load core, i.e., the high-performance core P-core, increases the frequency, while the low-load core, i.e., the low-power core E-core, decreases the frequency and voltage. According to the task characteristics and core status, RISC-V scheduling extension instructions are used to implement task allocation; computing-intensive tasks are allocated to the high-performance core P-core, and lightweight tasks or background tasks are allocated to the low-power core E-core; low-priority tasks are allocated to the low-power core E-core or delayed scheduling; Further preferably, RISC-V low-power extended instructions are used to dynamically start and stop cores; when the load increases, more cores are woken up; when the load decreases, idle cores are shut down and switched to low-power mode.

6. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that: Adaptive energy saving; including: Based on a lightweight AI model, future load changes are predicted through historical task data, and the core is started or shut down in advance to adapt to the predicted load changes; If the current task queue is empty, all high-performance cores P-core are turned off, and only one low-power core E-core is kept running in low-power mode.

7. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to any one of claims 1 to 6, characterized in that: Task migration; including: Task migration is triggered when one of the following conditions is met: ① The current core temperature exceeds the temperature setting threshold or the current core power consumption exceeds the power consumption setting threshold; ②The current core load is continuously too high or too low; ③The task characteristics do not conform to the current core type; During task migration, extended instructions are used to save the task state to shared memory, and then the task context is restored on the target core.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on the RISC-V architecture described in any one of claims 1-7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on the RISC-V architecture described in any one of claims 1 to 7 are implemented.

10. A dynamically adjustable multi-core collaboration mechanism and power consumption optimization system based on RISC-V architecture, characterized in that: include: The initialization module is configured to: initialize the dynamically adjustable multi-core collaborative system; including: initialize the hardware module, the hardware module includes the high-performance core P-core, the low-power core E-core, the hardware scheduling unit HSU, and the power management unit PMU; load the task queue and mark the task characteristics; The core status monitoring module is configured as follows: the HSU monitors the core status; the power management unit PMU monitors the voltage and frequency; The dynamic task scheduling module is configured to: allocate tasks to high-performance cores P-core or low-power cores E-core according to their characteristics; idle cores enter low-power mode; The adaptive energy saving and task migration module is configured as: adaptive energy saving; including: predicting task load changes; starting or shutting down cores in advance; task migration; including: saving task context to shared content, restoring task context in the target core, and ensuring cache consistency.

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