A data prefetching method, device, equipment, medium and product

Abstract

The present invention discloses a data prefetching method, apparatus, device, medium and product, which are applied to the field of data storage technology, and include: obtaining target missing information; the target missing information includes first instruction address information corresponding to a program counter and first missing data address information; obtaining stream prefetching mode determination information from a preset program counter table based on the target missing information, and generating a prefetch address corresponding to the stream prefetching mode to perform data prefetching when the preset stream prefetching mode condition is satisfied; if the preset stream prefetching mode condition is not satisfied, determining a first target entry in the preset program counter table; determining other prefetching modes based on the position information in the first target entry, and generating a prefetch address corresponding to the other prefetching mode when it is determined to adopt the other prefetching mode, so as to perform data prefetching based on the prefetch address. In this way, the prefetching mode search overhead and storage cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and particularly to a data prefetching method, apparatus, device, medium and product. Background Art

[0002] For complex application scenarios, a single data prefetching algorithm cannot exhibit optimal performance in different types of memory access sequences. Currently, in the general design of a multi-mode data prefetching algorithm, a miss request is simultaneously sent to multiple data prefetching units to attempt to find a suitable prefetching mode, which brings a large search overhead, and each data prefetching algorithm maintains its own table to record content, resulting in a large storage cost.

[0003] Obviously, how to reduce the prefetching mode search overhead and storage cost is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a data prefetching method, apparatus, device, medium and product to reduce the prefetching mode search overhead and storage cost. The specific solutions are as follows:

[0005] In a first aspect, the present invention provides a data prefetching method, including:

[0006] Obtaining target miss information; wherein, the target miss information includes first instruction address information corresponding to a program counter and first missing data address information;

[0007] Obtaining stream prefetching mode determination information from a preset program counter table based on the target miss information, and generating a prefetch address corresponding to the stream prefetching mode when it is determined that a preset stream prefetching mode condition is satisfied based on the target miss information and the stream prefetching mode determination information, so as to perform data prefetching based on the prefetch address;

[0008] If the preset stream prefetching mode condition is not satisfied, determining a first target entry in the preset program counter table, where the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetching mode determination tables;

[0009] Determining other prefetching modes based on the position information in the first target entry, and generating a prefetch address corresponding to the other prefetching mode when it is determined to adopt the other prefetching mode, so as to perform data prefetching based on the prefetch address.

[0010] In a second aspect, the present invention provides a data prefetching apparatus, including:

[0011] A missing information acquisition module, configured to acquire target missing information; wherein, the target missing information includes first instruction address information corresponding to a program counter and first missing data address information;

[0012] A stream prefetch mode processing module, configured to acquire stream prefetch mode determination information from a preset program counter table based on the target missing information, and generate a prefetch address corresponding to the stream prefetch mode when it is determined that a preset stream prefetch mode condition is satisfied based on the target missing information and the stream prefetch mode determination information, so as to perform data prefetch based on the prefetch address;

[0013] A target entry determination module, configured to determine a first target entry in the preset program counter table if the preset stream prefetch mode condition is not satisfied, wherein the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetch mode determination tables;

[0014] A multi-prefetch mode processing module, configured to perform determination of other prefetch modes based on the position information in the first target entry, and generate a prefetch address corresponding to the other prefetch mode when it is determined to adopt the other prefetch mode, so as to perform data prefetch based on the prefetch address.

[0015] In a third aspect, the present invention provides an electronic device, including:

[0016] A memory, configured to store a computer program;

[0017] A processor, configured to execute the computer program to implement the steps of the foregoing data prefetch method.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the foregoing data prefetch method are implemented.

[0019] In a fifth aspect, the present invention provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the foregoing data prefetch method are implemented.

[0020] As can be seen from the above solution, the present invention provides a data prefetching method, including: obtaining target missing information; wherein, the target missing information includes first instruction address information corresponding to a program counter and first missing data address information; obtaining stream prefetching mode determination information from a preset program counter table based on the target missing information, and generating a prefetch address corresponding to the stream prefetching mode when it is determined that a preset stream prefetching mode condition is satisfied based on the target missing information and the stream prefetching mode determination information, so as to perform data prefetching based on this prefetch address; if the preset stream prefetching mode condition is not satisfied, determining a first target entry in the preset program counter table, wherein the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetching mode determination tables; performing determination of other prefetching modes based on the position information in the first target entry, and generating a prefetch address corresponding to the other prefetching mode when it is determined to adopt the other prefetching mode, so as to perform data prefetching based on this prefetch address.

[0021] It can be seen that the beneficial effects of the present invention are as follows: determining whether to adopt the stream prefetching mode through a preset program counter table, and performing determination of other prefetching modes when the stream prefetching mode is not adopted. In this way, multi-mode hierarchical determination is carried out, avoiding the process of triggering the search and determination of all prefetching modes for the same missing information. Moreover, the preset program counter table includes position information of data entries corresponding to the first instruction address information in multiple other prefetching mode determination tables, realizing the indexing of other prefetching mode determination tables and being able to avoid redundant information in various prefetching mode determination tables. In this way, the prefetching mode search overhead and storage cost are reduced.

[0022] Correspondingly, a data prefetching device, equipment, medium and product provided by the present invention also have the above technical effects. Description of the Drawings

[0023] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a flowchart of a data prefetching method provided by an embodiment of the present invention;

[0025] Figure 2 It is a block diagram of the overall structure of a multi-mode data prefetching unit provided by an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of a prefetching process provided by an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of a prefetching training provided by an embodiment of the present invention;

[0028] Figure 5 Schematic diagram of a space division provided by an embodiment of the present application;

[0029] Figure 6 Schematic diagram of a training process of a space bit vector sequence provided by an embodiment of the present application;

[0030] Figure 7 Schematic diagram of a prefetching process provided by an embodiment of the present application;

[0031] Figure 8 Schematic diagram of an arbitration filtering unit provided by an embodiment of the present invention;

[0032] Figure 9 Schematic diagram of a prefetch degree training process provided by an embodiment of the present invention;

[0033] Figure 10 Schematic diagram of a structure of a data prefetching device disclosed by an embodiment of the present invention;

[0034] Figure 11 Schematic diagram of a structure of an electronic device disclosed by an embodiment of the present invention. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0036] The terms "including" and "having" in the specification of the present invention and any deformations related to "including" and "having" are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0037] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0038] Next, a data prefetching method provided by an embodiment of the present invention will be introduced in detail. Figure 1The following is a flowchart of a data prefetching method provided by an embodiment of the present invention. The data prefetching method includes:

[0039] Step S11: Obtain target missing information; wherein, the target missing information includes first instruction address information corresponding to a program counter and first missing data address information.

[0040] It can be understood that the program counter is a key register in the CPU, which is used to store the memory address of the next instruction. In the embodiment of the present invention, the instruction address information stored in the program counter is used to identify the instruction, and any instruction can access the cache once or multiple times. The missing data address information is the address where there is no data in the cache and a miss occurs when accessing the cache.

[0041] In an optional implementation manner, when a preset data prefetching condition is satisfied, the missing information is added to a trigger queue, where the missing information includes instruction address information corresponding to the program counter and missing data address information; correspondingly, obtaining the target missing information includes: obtaining the target missing information from the trigger queue.

[0042] Among them, the preset data prefetching condition may be the occurrence of preset missing information, such as L2_Miss information. The L2_Miss information is the missing information generated when the corresponding data cannot be found in the secondary cache in a multi-level cache. The trigger queue follows the first-in, first-out principle, and the target missing information is the missing information dequeued from the trigger queue following the first-in, first-out principle. And, in an optional implementation manner, before adding the missing information to the trigger queue, it can be checked whether there is consistent missing information in the trigger queue. If not, it is added; otherwise, it is not added.

[0043] Step S12: Obtain stream prefetching mode determination information from a preset program counter table based on the target missing information, and generate a prefetch address corresponding to the stream prefetching mode when it is determined that a preset stream prefetching mode condition is satisfied based on the target missing information and the stream prefetching mode determination information, so as to perform data prefetching based on the prefetch address.

[0044] Among them, the preset program counter table is a preset table, and the table contains multiple data entries. Each data entry contains predefined fields. The stream prefetching mode determination information is information related to judging the stream prefetching mode, and may be the recorded data missing address.

[0045] In an alternative embodiment, the first target entry and the second target entry may be determined from a preset program counter table, where the second target entry is a data entry containing the instruction address information in the most recently matched missing information; the second missing data address information is obtained from the first target entry and the second target entry; the second missing data address information is the previous missing data address information corresponding to the instruction address information in the first target entry or the second target entry. That is, in the first target entry, the second missing data address information is the previous missing data address information corresponding to the first instruction address information, and in the second target entry, it is the previous missing data address information included in this entry. If the difference between any obtained second missing data address information and the first missing data address information is 1, it is determined that the preset stream prefetch mode condition is satisfied. Add 1 to the first missing data address information to obtain the prefetch address corresponding to the stream prefetch mode. There is no need to perform subsequent judgments of other prefetch modes for this target missing information.

[0046] Step S13: If the preset stream prefetch mode condition is not satisfied, determine the first target entry in the preset program counter table, where the first target entry is a data entry containing the second instruction address information that is the same as the first instruction address information, and the first target entry contains the position information of the data entry corresponding to the first instruction address information in multiple other prefetch mode determination tables.

[0047] Step S14: Based on the position information in the first target entry, perform the determination of other prefetch modes. In the case where it is determined to adopt other prefetch modes, generate the prefetch address corresponding to the other prefetch modes, so as to perform data prefetch based on this prefetch address.

[0048] In an alternative embodiment, other prefetching modes include a stride prefetching mode, and the corresponding prefetching mode decision table is a preset stride table; correspondingly, determining other prefetching modes based on the position information in the first target entry includes: if the first target entry exists and the difference between the second missing data address information and the first missing data address information in the first target entry is not 1, then according to the position information of the data entry corresponding to the first instruction address information in the preset stride table in the first target entry, determine a third target entry corresponding to this position information from the preset stride table; obtain stride information from the third target entry to obtain a first stride information, if the first stride information is the same as the difference between the second missing data address information and the first missing data address information, and the first stride information meets the preset credibility condition, then determine that the stride prefetching mode is adopted. Generate a prefetch address corresponding to the other prefetching mode, add the first missing data address information and the first stride information to obtain the prefetch address corresponding to the stride prefetching mode. There is no need to perform subsequent judgments of other prefetching modes for this target missing information.

[0049] In an alternative embodiment, other prefetching modes include a space-based prefetching mode, and the corresponding prefetching mode decision table is a preset region table; correspondingly, determining other prefetching modes based on the position information in the first target entry includes: if the first stride information is inconsistent with the difference or does not meet the preset credibility condition, then according to the position information of the data entry corresponding to the first instruction address information in the preset region table in the first target entry, determine a fourth target entry corresponding to this position information from the preset region table; extract the data within a preset bit range in the first missing data address information to obtain a first offset value; if a fifth target entry is determined in the preset region table, then determine that the space-based prefetching mode is adopted; wherein, the fifth target entry is a data entry including a second offset value consistent with the first offset value. It can be understood that there may be multiple fourth target entries, and the embodiments of the present application can determine the fifth target entry therefrom. Further, generating a prefetch address corresponding to the other prefetching mode includes: obtaining the prefetch address of the space-based prefetching mode based on the first missing data address information and the bit vector sequence in the fifth target entry. Wherein, the space bit vector sequence characterizes the access situation corresponding to the same space base address in the fifth target entry.

[0050] In an alternative embodiment, if the first target entry or the second target entry does not exist in the preset program counter table, the prefetch mode is determined as offset prefetch; if the first stride information is inconsistent with the difference value, or does not meet the preset credibility condition, and the position information of the data entry corresponding to the first instruction address information in the preset region table does not exist in the first target entry, it is determined to adopt the offset prefetch mode. Further, if the optimal offset value is recorded in the preset offset value record, the prefetch address corresponding to the offset prefetch mode is determined based on the first missing data address information and the optimal offset value.

[0051] Further, for the offset prefetch process, if there is no optimal offset value, the offset value is set to 0, indicating that the prefetch address is not calculated, and no prefetch is issued at this time (because this is already the last level, and if there is no suitable one here, no pattern is found overall). The calculation of the prefetch address is the trigger address + the offset value. If the prefetch degree is 2, in addition to issuing the trigger address + the offset value, the trigger address + 2 * the offset value is also issued, and so on.

[0052] It can be understood that in the embodiments of the present invention, the main storage structures involved in the present invention include Trigger_queue (trigger queue), PC_table (program counter table, i.e., the preset program counter table), Stride_table (stride table, i.e., the preset stride table), region_table (region table, i.e., the preset region table), delta (offset value record, i.e., the preset offset value record), train_table (training table, i.e., the preset training table), score_table (score table, i.e., the preset score table), and RR_table (past memory access table, i.e., the preset address table), and the main logical structure is the arbiter & fliter (arbitration and filtering unit) module. See Figure 2 shown Figure 2 It is a block diagram of the overall structure of a multi-mode data prefetch unit provided by an embodiment of the present invention. It may include an index unit, a stride unit, a region unit, a training unit, an offset unit, and an arbitration and filtering unit, and may include a trigger queue, a prefetch queue, and a training queue.

[0053] See Figure 3 shown Figure 3 It is a schematic diagram of a prefetch process provided by an embodiment of the present invention. The prefetch process is as Figure 3As shown, the prefetch trigger information is the missing information. Taking the L2_Miss information as the address information for triggering prefetch as an example, the L2_Miss related information sent out will first be sent to the trigger queue for buffering. When it is determined that there is no request duplication, the missing request information, that is, the missing information, will be added to the end of the trigger queue, and then the trigger queue will be sent to the index unit in the order of first in first out. The index unit will first look up the entry corresponding to the same PC (i.e., the instruction address information corresponding to the program counter) and the most recent missing address in the PC table (i.e., the program counter table). After taking it out, calculate the difference between the missing address and the recorded address. If the difference is 1, it indicates the trigger stream access feature, and the missing address is incremented by 1 and sent to the arbitration filtering unit, and the trigger address does not perform subsequent trigger prefetch work. If there is an entry with the same PC and the difference is not 1, the missing information and the difference will be sent to the stride unit for triggering. If the above conditions are not met, it will be directly sent to the offset unit. The stride unit will directly determine the entry position in the stride table according to the information provided by the PC table, and compare the difference with the recorded stride to check whether the counter meets the emission threshold condition, that is, the preset credibility condition. When it is met, the missing address is added to the stride to obtain the prefetch address and sent to the arbitration filtering unit. If it is not met, it is judged whether the corresponding information of the region table is found in the PC table. If it is found, it is sent to the region table. If it is not found, it is sent to the offset unit. The region unit will compare the entry (which can be a group) returned by the PC in the region table with the offset (i.e., the offset value) in the region table to find whether there is an entry with the same offset. If it is found, the prefetch address is calculated according to the stored bit vector sequence and sent to the arbitration filtering module. If it is not found, the prefetch trigger ends. The best offset value obtained by training the score table and the RR table is stored in the delta. When a missing address is sent and there is a valid best offset value, they are added together to obtain the prefetch address and sent to the arbitration filtering unit. The arbitration filtering unit is used to receive prefetch requests (i.e., requests corresponding to prefetch addresses) from different modules and perform arbitration. It comprehensively judges whether the prefetch request is emitted according to information such as the accuracy information of historical prefetch requests, cache status information, and the empty / full status of the prefetch queue, and feedbacks the relevant information of the prefetch degree to other modules through the cache status, and emits the prefetch address to the prefetch queue to queue. The arbitration filtering unit also records the relevant information of the prefetch address at the same time, so as to judge the accuracy of the prefetch.

[0054] Further, in an alternative embodiment, it is also possible to: obtain training information; wherein the training information includes third instruction address information corresponding to a program counter and third missing data address information; check whether a sixth target entry exists in a preset program counter table; wherein the sixth target entry is a data entry including fourth instruction address information identical to the third instruction address information, and if the sixth target entry exists in the preset program counter table and the sixth target entry includes position information of a data entry corresponding to the third instruction address information in the preset stride table, then record this position information as first position information; obtain fourth missing data address information from the sixth target entry; wherein the fourth missing data address information is the previous missing data address information corresponding to the third instruction address information; calculate the difference between the fourth missing data address information and the third missing data address information to obtain stride information, denoted as second stride information; obtain the stride information in the data entry corresponding to the first position information in the preset stride table, denoted as third stride information; if the third stride information is the same as the second stride information, then perform an increment operation on a preset counter in the data entry corresponding to the first position information in the preset stride table, otherwise perform a decrement operation on the counter; wherein, if the count value of the preset counter is greater than a preset threshold, it indicates that the third stride information meets the preset credibility condition.

[0055] Further, embodiments of the present invention can also split the third missing data address information in the training information based on a preset high bit range, a preset middle bit range, and a preset low bit range to obtain a high part, a middle part, and a low part; perform a hash calculation on the high part to obtain a spatial region index; perform a preset calculation on the spatial region index and the middle part to obtain spatial base address identification information, and store this spatial base address in a preset training table; remove the in-block offset bits from the low part to obtain an offset value within the spatial region, and record this offset value in the preset training table; when an eviction address of the cache is obtained, calculate the spatial base address and the offset address corresponding to the eviction address, and if a spatial base address and an offset address identical to those corresponding to the eviction address are found in the preset training table, then determine that the training of the data entry corresponding to the eviction address in the preset region table is completed, and add the position information of this data entry in the preset region table to the preset program counter table. Wherein, the eviction address of the cache is the address at which data needs to be evicted when the cache is full when placing data in the cache. The in-block offset bits are the offset bits in the cache line for storing data.

[0056] Further, in the embodiment of the present invention, the third missing data address information can also be subtracted from the historical training address in the preset address table to obtain a first address difference, where the historical training address is the missing data address information in the historical training information; check whether there is a second address difference identical to the first address difference in the preset score table; if there is an identical second address difference, increase the score corresponding to the identical second address difference; when the preset optimal offset value update condition is satisfied, use the second address difference with the highest score and exceeding the preset score threshold as the optimal offset value and update it to the preset offset value record.

[0057] See Figure 4 as shown in Figure 4 FIG. 1 is a prefetch training schematic diagram provided by the present invention, taking L1D_Miss (i.e., the missing information corresponding to the first-level cache) and prefetch success as training requests as an example. The missing information and prefetch success information of L1D are used as training information and will be first sent to the training queue. After error checking to ensure there are no duplicates, they are sent to the PC table, training table, and offset unit in the first-in, first-out order. After the training request information arrives at the PC table, it will first check whether the entry information in the stride table has been recorded in it. If found, determine the position information of the entry and send it to the stride table. If not found, select the replacement entry information according to the replacement policy (such as LRU (i.e., Least Recently Used), PLRU (i.e., Pseudo-Least Recently Used), etc.) and update the entry situation, and then send the relevant information to the stride table for training. After the stride table obtains the training request information and the PC table search result, it updates the entry. If it is an update of an existing entry, subtract the training address from the recorded address to obtain the current stride, and compare it with the stride stored in the entry. If they are the same, increment the corresponding counter by 1; otherwise, decrement the counter by 1. If the counter has reached 0 and a decrement operation occurs, update the stride value recorded in the entry to the newly calculated stride and set the counter to 1. If it is a replacement of an existing entry, set the counter and stride to 0, indicating that no calculation steps have been experienced. In any case, after the search, update the address recorded in the entry to the latest missing address. After the training table obtains the training information, it will divide and split the training address, obtain the index information of the spatial region through high-order hash calculation, and perform operations (such as splicing, AND, OR, etc.) with the median to obtain the tag information, i.e., the spatial base address. The remaining low-order part after removing the in-block offset bits is used as the offset value within the spatial region, and the corresponding entry information is updated.

[0058] After receiving the eviction information in the training table, it will search for the corresponding entry according to the obtained information. If found and the corresponding conditions are met, the corresponding entry information will be evicted to the specified entry in the region table (if the region table is full, the replacement entry will be determined according to the replacement algorithm), and the PC (instruction address) and the stored entry position will be sent to the PC table for update operation.

[0059] The offset value training logic includes three parts: the score table, the RR table, and delta. The RR table records the training addresses that have occurred in the past. The score table maintains multiple different offset values and their corresponding score values. When a new training address arrives, it will be subtracted from the past training addresses, and then it will be checked whether there are the same entries in the score table to maintain the scores. Every other training cycle, the offset with the highest score and meeting the threshold will be selected as the best offset and stored in delta. If the conditions are not met, the corresponding delta will be set to 0 indicating that there is no suitable delta.

[0060] The information recorded in the PC table includes PC (instruction address information), last_address (the previous missing address under this PC), the Stride_table entry position, the region_table entry position, the r bit (the most recent missing address), and the v bit (valid bit, indicating whether this entry contains valid data). Thanks to the lookup method similar to the multi-level page table, the PC and last_address do not need to be recorded in the other tables, which can save a large amount of storage space. The Stride_table only needs to record the stride, the v bit, and the counter. The region_table needs to record the spatial region base address, the bit vector sequence, the prefetch mode (starting from the left or right of the offset value in the spatial vector sequence to calculate the prefetch address), and the v bit. Delta only includes the best offset value. The Train_table records more information, including the P index and label generated by the PC, the label of the spatial region, the offset value for creating the spatial region, the access times of the cache blocks in this spatial region, the prefetch direction, i.e., the aforementioned prefetch mode, and the v bit.

[0061] Before designing the prefetch unit, the size of the spatial region will be set according to the number of entries that can be recorded in the table, and the memory address will be divided into multiple spatial regions according to the size of the spatial region. The high bits of each spatial region are the same, which is called the spatial base address. Figure 5 For example, if the size of the spatial region is set to 10 cache lines, all memory addresses will be divided into multiple regions based on 10, with the high bits as the spatial base address and the low bits as the offset value within the space. Before the occurrence, all the first offsets and the spatial bit vector sequences are 0. When the size of the spatial region is 10, ten spatial bit vectors are maintained, and the initial sequence is ten 0s. For example, see Figure 5As shown Figure 5 It is a schematic diagram of space division provided by an embodiment of the present application.

[0062] Further, referring to Figure 6 As shown Figure 6 It is a schematic diagram of the training process of a space bit vector sequence provided by an embodiment of the present application, which is the content in the training table. Assume that the access to this space area has not occurred yet. At this time, the first memory access address that comes will be set as the address for the first access to this space area. When accessing for the first time, if the memory access address is 12, at this time, split the high-order 10 as the space base address and 2 as the offset. Take 2 as the first offset, and set the 2nd position in the space bit vector sequence to 1 (counting from the 0th). After that, the memory access address is 24. At this time, it is retrieved that the space base address is different from the space base address recorded before the current entry. Since it is not maintained in this entry, it is maintained in its corresponding entry. Then come a memory access address of 15, split it into 10 and 5, and set the 5th bit vector in the corresponding sequence to 1, and so on. When the memory access address is 10, set the 0th bit to 1. When a cache eviction signal is received, end the maintenance of this space bit vector and record it as a space stream memory access feature. And during the recording process, each time an address in this area is accessed, the access count is incremented. And so on, continuously maintain the table entry information. The PC index and the tag are used to identify and find the corresponding entry, which are recorded after the first memory access. Since the same PC may access multiple space areas, there may be multiple entries under the same PC. Therefore, the PC and the base address are used to determine the specific entry position. It should be noted that, for the sake of easy understanding, in the embodiment of the present application, the memory access address is 12, and at this time, the high-order 10 is split as the space base address and 2 as the offset for description. However, in actual applications, the base address and offset determination method adopted is the aforementioned method, that is, based on the preset high-order bit range, preset middle-order bit range, and preset low-order bit range, the data address information is split to obtain the high-order part, middle-order part, and low-order part; perform a hash calculation on the high-order part to obtain a space area index; perform a preset calculation on the space area index and the middle-order part to obtain a space base address identification information, and remove the in-block offset bits from the low-order part to obtain the offset value within the space area.

[0063] The training process continues until an eviction address is received from the cache (i.e., a new address arrives in the cache and needs to be stored, and an entry needs to be found to be replaced by the new entry. The address recorded in the replaced entry is the eviction address). The eviction address is split in the same way to obtain the spatial base address and the offset value. The spatial base address and the offset value are used to find the entry in the training table with the same spatial base address and offset value. If found, it is considered that the training of the spatial region where the entry is located is completed, and it is judged whether it can be recorded in the region table. First, check whether the access count exceeds the threshold. If it exceeds the threshold, calculate the prefetch pattern (i.e., the prefetch direction). If there are more bit vectors larger than the first offset, it is increment, recorded as 1, otherwise 0, and the entry is recorded in the region table. The record position in the region table and the position of the evicted entry are fed back to the PC table.

[0064] See Figure 7 as shown Figure 7 is a schematic diagram of a prefetch process provided by an embodiment of the present application, and the process of the stride table is omitted. Figure 7 The identifier in it is the PC tag, the cache eviction address is the cache eviction address, and the entry position corresponding to the PC will be found in the PC table. The memory access address is split into a spatial base address and an offset and compared. Assume that the memory access address (trigger address) is 32, split into a spatial base address 30 and an offset 2. At this time, the offset 2 is the same as the first offset recorded in the entry row of the region table, so the match is successful. As Figure 7 can be seen, at this time, bits 0, 2, 3, 5, and 8 are 1, so the corresponding offsets in this space are 0, 2, 3, 5, and 8. Add the spatial base address 30 obtained by splitting the trigger address to the offset values in turn to obtain the prefetch addresses 33, 35, 38, 30, which are sent according to the position from near to far, and the number of sent addresses is related to the prefetch degree. If the prefetch degree is 1, only one address 33 is sent. If the prefetch degree is 2, two addresses 33 and 35 are sent, and so on. The prefetch addresses are calculated in one direction (increasing / decreasing) preferentially. Further, in an alternative embodiment, data prefetching is performed according to the prefetch addresses of each prefetch pattern based on a preset priority.

[0065] Further, in an alternative embodiment, data prefetching is performed based on the prefetch addresses of each prefetch pattern, including: performing data prefetching based on the prefetch addresses of each prefetch pattern and the prefetch degree; wherein, the prefetch degree is determined based on one or more performance information.

[0066] Further, see Figure 8 as shown Figure 8Schematic diagram of an arbitration filtering unit provided by an embodiment of the present invention. Prefetch requests from PC_table, stride_table, delta, and region_tabled are sent to this unit. When simultaneous arrivals occur, the prefetch requests sent to the fliter (i.e., the arbitration filtering unit) are determined according to the priority order of PC_table > stride_table > delta > region_table.

[0067] To prevent the situation where a certain prefetcher (i.e., the unit of the corresponding prefetch mode) has been unable to issue a prefetch address for too long, resulting in timeliness problems, a starvation counter counter is set. When there is a prefetch request from this source, the corresponding valid bit is set to 1, and the corresponding counter is incremented by 1 each time it is not selected. When the preset value is reached, the priority of the prefetch request from this source is forcibly increased to ensure that prefetch requests are not issued too long.

[0068] The fliter will comprehensively consider the received prefetch accuracy rate, performance status, cache status, and bus bandwidth status to judge information such as the prefetch degree. As shown below, the fliter will obtain the corresponding information from the CSR (i.e., Control and Status Registers) register bank, prefetch history table, and bus every fixed clock cycle and make a judgment.

[0069] The filter first judges the value of the accuracy rate. If it is lower than the accuracy rate threshold 0, it means that the value of the accuracy rate is too low. At this time, the prefetch address issuance of the prefetcher is first suspended. The prefetch address issued during the suspension is stored in a specific area of the prefetch history table and continuously tracked and trained (not actually issued). Wait until the accuracy rate obtained by training is higher than this threshold and then make a judgment.

[0070] Then the filter judges whether the bus bandwidth pressure score is lower than the set threshold. If it is higher than the threshold, it means that the bus is already under too much pressure when processing existing miss requests. Too many prefetch requests will cause the bus bandwidth to be occupied, affecting normal fill requests. At this time, it is judged whether the accuracy rate corresponding to each type of prefetch request is higher than the first accuracy rate. If it is higher, the original prefetch degree is maintained. If it is lower, the prefetch degree is reduced.

[0071] If the bus bandwidth pressure fraction is lower than the set threshold, a comprehensive evaluation score is calculated based on the cache status returned by the CSR register. The evaluation factors include cache miss rate, cache line replacement rate, cache line free quantity, memory access latency, etc. If the evaluated score is lower than the threshold, the prefetch accuracy rate is compared with the first accuracy rate threshold. If it is lower than the threshold, the prefetch degree is decreased by one; if it is higher than the threshold, the original prefetch degree is maintained. If the score evaluated for the cache status is higher than the set threshold, a second accuracy rate threshold is evaluated. If it is lower than this value, the original prefetch degree is maintained; if it is higher than this value, the prefetch degree is increased by one.

[0072] As Figure 9 shown, Figure 9 FIG. is a schematic diagram of a prefetch degree training process provided by an embodiment of the present invention. This module sets three situations for the prefetch unit to stop. The first is when the prefetch accuracy rate is lower than the accuracy rate threshold 0, which indicates that the prefetch accuracy rate is too low and may cause excessive negative impacts, and at this time, the prefetch unit is paused first; the second is when the bus bandwidth pressure is too high, and this threshold can have a multiple relationship with the previously mentioned bus bandwidth pressure fraction threshold. At this time, the prefetch request will affect the time of the normal memory access fill request and may have a negative impact on performance. The third is when the software requests to stop, and the prefetch unit is controlled through the corresponding CSR register. At this time, the prefetch unit stops sending the prefetch address to the prefetch queue.

[0073] When the prefetch unit stops, training continues. The calculated prefetch address is sent to a dedicated register for storage and continuously tracked. When the corresponding conditions are met, the prefetch degree is set to the default value and the normal process resumes. The corresponding conditions include that the accuracy rate meets the threshold, the bus bandwidth pressure is not so high, and the software stops the prefetch unit. When restarting, except for the accuracy rate factor, the other prefetch degrees maintained during training are adopted. After the stop and restart caused by the accuracy rate factor, the prefetch degree is set to 1. In the embodiments of the present application, accuracy rate threshold 0, accuracy rate threshold 1, and accuracy rate threshold 2 are set.

[0074] The prefetch queue issues prefetch addresses according to the first-in, first-out principle. When the prefetch address is full, the filter is paused from sending prefetch addresses. Before sending, it will first check whether there are existing entries in the MSHR (i.e., the miss status register) and CacheLine (i.e., the cache line). If there are existing entries, they are fed back to the filter as one of the bases for cache status score evaluation.

[0075] The prefetch requests sent by the filter to the prefetch queue are simultaneously recorded in the prefetch history table. When bus backfill occurs, the entries are checked in the prefetch history table and the backfill time is recorded. When a memory access hit occurs, the prefetch history table is searched to determine whether it is a hit for a prefetch request, and the corresponding prefetch success requests and backfill-related information are fed back to the prefetch module as the basis for training prefetch addresses. When the table is full, the earliest entry is evicted and recorded as a prefetch failure (even if the prefetch address is used, it is a premature prefetch with timeliness issues), and the corresponding counter is incremented by 1. The prefetch accuracy is calculated based on the value of this counter at fixed clock intervals and fed back to the filter.

[0076] The embodiments of the present invention adopt a method similar to a multi-level page table. By indexing through the PC table, the storage of duplicate information in the remaining storage tables is reduced. When prefetching is triggered, it can be determined through the PC table which type of prefetch request is satisfied, without the need to search multiple tables in parallel, reducing the power consumption required for searching. The judgment logic for the same triggered prefetch address is set inside the multi-mode prefetch unit, and the implicit priority conditions are used to avoid issuing prefetch addresses for data that will not be used, reducing performance losses. Through multiple judgment logics for the triggered prefetch address, the likelihood of finding a suitable memory access pattern and issuing a prefetch address is maximized. A filter is set up to dynamically adjust the prefetch degree by combining cache status, bus bandwidth, and prefetch performance. When there is high bus bandwidth pressure, too low accuracy, or software regulation, the prefetch unit can be turned off to avoid performance losses. When the prefetch address is turned off, the prefetch address and prefetch degree are continuously trained to achieve fast recovery. A prefetch history table is set up to evaluate the prefetch performance internally and feed back the signals required by other prefetch units, improving the design versatility and avoiding modifying the cache to implement functions.

[0077] It can be seen that the method of indexing the multi-level page table through the PC table can effectively reduce the storage cost. When prefetching is triggered, it is not necessary to check multiple tables simultaneously. Some requests can be filtered out through the PC table, reducing the additional power consumption caused by searching. By using the internal implicit priority conditions, unnecessary prefetch requests are reduced, lowering power consumption and arithmetic losses. Through multi-level judgments, the likelihood of issuing a prefetch address is maximized, increasing the coverage rate. The prefetch degree is adjusted through the filter and software adjustment is supported, improving the adaptability to different types of application programs. The prefetch performance parameters are recorded inside the prefetch unit, avoiding modifying external units during reuse and improving the reusability.

[0078] In addition, in the embodiments of the present invention, the best offset value determination unit can adopt different types of offset prefetches. For example, the example uses a modified structure of BOP (Best Offset Prefetcher), and other types such as Berti (a prefetch based on local increment) and SandBox (Sandbox Prefetcher) can also achieve similar effects. Similarly, the spatial prefetcher in this example is a modified structure of SMS (Spatial Memory Streaming Prefetcher), and using other spatial prefetches can achieve similar effects. More different types of prefetches can be added in the form of lookup tables at more levels based on performance metrics such as accuracy or coverage to achieve complementary effects. The prefetch degree can be directly adjusted by software.

[0079] See Figure 10 As shown, the embodiments of the present invention disclose a data prefetching device, including:

[0080] A missing information acquisition module 71, configured to acquire target missing information; wherein, the target missing information includes first instruction address information corresponding to a program counter and first missing data address information;

[0081] A stream prefetch mode processing module 72, configured to acquire stream prefetch mode determination information from a preset program counter table based on the target missing information, and generate a prefetch address corresponding to the stream prefetch mode when it is determined that the preset stream prefetch mode condition is satisfied based on the target missing information and the stream prefetch mode determination information, so as to perform data prefetching based on the prefetch address;

[0082] A target entry determination module 73, configured to determine a first target entry in the preset program counter table if the preset stream prefetch mode condition is not satisfied, where the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetch mode determination tables;

[0083] A multi-prefetch mode processing module 74, configured to determine other prefetch modes based on the position information in the first target entry, and generate a prefetch address corresponding to the other prefetch mode when it is determined to adopt the other prefetch mode, so as to perform data prefetching based on the prefetch address.

[0084] In an alternative embodiment, the stream prefetch mode processing module 72 may specifically be configured to:

[0085] Determine the first target entry and the second target entry from a preset program counter table, where the second target entry is a data entry containing the instruction address information in the most recently matched missing information;

[0086] Obtain second missing data address information from the first target entry and the second target entry; wherein the second missing data address information is the previous missing data address information corresponding to the instruction address information in the first target entry or the second target entry.

[0087] In an alternative embodiment, the stream prefetch mode processing module 72 may specifically be configured to:

[0088] If the difference between any obtained second missing data address information and the first missing data address information is 1, it is determined that the preset stream prefetch mode condition is satisfied.

[0089] In an alternative embodiment, the stream prefetch mode processing module 72 may specifically be configured to:

[0090] Add 1 to the first missing data address information to obtain a prefetch address corresponding to the stream prefetch mode.

[0091] In an alternative embodiment, the multi-prefetch mode processing module 74 may specifically be configured to: when other prefetch modes include a stride prefetch mode and the corresponding prefetch mode determination table is a preset stride table; if there is the first target entry and the difference between the second missing data address information in the first target entry and the first missing data address information is not 1, then determine a third target entry corresponding to the position information from the preset stride table according to the position information of the data entry corresponding to the first instruction address information in the preset stride table in the first target entry; obtain stride information from the third target entry to obtain a first stride information, if the first stride information is the same as the difference between the second missing data address information and the first missing data address information and the first stride information meets the preset credibility condition, then determine to adopt the stride prefetch mode. Add the first missing data address information to the first stride information to obtain a prefetch address corresponding to the stride prefetch mode.

[0092] In an alternative embodiment, the multi-prefetch mode processing module 74 may be specifically configured to: when other prefetch modes include a space-based prefetch mode and the corresponding prefetch mode determination table is a preset area table; determine, from the preset area table, a fourth target entry corresponding to the position information of the data entry corresponding to the first instruction address information in the preset area table according to the position information of the data entry corresponding to the first instruction address information in the first target entry in the preset area table; extract data within a preset bit range in the first missing data address information to obtain a first offset value; if a fifth target entry is determined in the preset area table, determine that the space-based prefetch mode is adopted; wherein, the fifth target entry is a data entry including a second offset value consistent with the first offset value. Obtain a prefetch address for the space-based prefetch mode based on the first missing data address information and the bit vector sequence in the fifth target entry. Wherein, the space bit vector sequence characterizes the access situation corresponding to the same space base address in the fifth target entry.

[0093] In an alternative embodiment, the apparatus may also be configured to: if the first target entry or the second target entry does not exist in the preset program counter table, determine the prefetch mode as offset prefetch; if the first stride information is inconsistent with the difference or does not meet the preset confidence condition, and the position information of the data entry corresponding to the first instruction address information in the preset area table does not exist in the first target entry, determine that the offset prefetch mode is adopted. If an optimal offset value is recorded in the preset offset value record, determine a prefetch address corresponding to the offset prefetch mode based on the first missing data address information and the optimal offset value.

[0094] In an alternative embodiment, the apparatus further includes a queue adding module, configured to add missing information to a trigger queue when a preset data prefetch condition is satisfied, where the missing information includes instruction address information corresponding to a program counter and missing data address information; correspondingly, the missing information obtaining module 71 is specifically configured to obtain target missing information from the trigger queue.

[0095] Further, the apparatus further includes a training module, configured to:

[0096] Obtain training information; wherein the training information includes third instruction address information corresponding to a program counter and third missing data address information;

[0097] Check whether a sixth target entry exists in the preset program counter table; wherein the sixth target entry is a data entry including fourth instruction address information identical to the third instruction address information.

[0098] If there is a sixth target entry in the preset program counter table, and the position information of the data entry corresponding to the third instruction address information in the preset stride table is included in the sixth target entry, then record this position information as the first position information;

[0099] Obtain fourth missing data address information from the sixth target entry; wherein, the fourth missing data address information is the previous missing data address information corresponding to the third instruction address information;

[0100] Calculate the difference between the fourth missing data address information and the third missing data address information to obtain stride information, and record it as the second stride information;

[0101] Obtain the stride information in the data entry corresponding to the first position information in the preset stride table, and record it as the third stride information;

[0102] If the third stride information is the same as the second stride information, perform an addition operation on the preset counter in the data entry corresponding to the first position information in the preset stride table, otherwise perform a subtraction operation on the preset counter;

[0103] Wherein, if the count value of the preset counter is greater than a preset threshold, it indicates that the third stride information meets the preset credibility condition.

[0104] Based on a preset high-order bit range, a preset middle-order bit range, and a preset low-order bit range, split the third missing data address information in the training information to obtain a high-order part, a middle-order part, and a low-order part;

[0105] Perform a hash calculation on the high-order part to obtain a spatial region index;

[0106] Perform a preset calculation on the spatial region index and the middle-order part to obtain a spatial base address, and store this spatial base address in a preset training table;

[0107] Remove the in-block offset bits from the low-order part to obtain an offset value within the spatial region, and record this offset value in the preset training table;

[0108] When an eviction address cached is obtained, calculate the spatial base address and the offset address corresponding to the eviction address. If a spatial base address and an offset address that are the same as those corresponding to the eviction address are found in the preset training table, then determine that the training of the data entry corresponding to the eviction address in the preset region table is completed, and add the position information of this data entry in the preset region table to the preset program counter table.

[0109] Subtract the third missing data address information from the historical training address in the preset address table to obtain a first address difference, where the historical training address is the missing data address information in the historical training information;

[0110] Check whether there is a second address difference identical to the first address difference in the preset score table;

[0111] If there is an identical second address difference, increase the score corresponding to the identical second address difference;

[0112] When the preset optimal offset value update condition is satisfied, use the second address difference with the highest score and exceeding the preset score threshold as the optimal offset value and update it to the preset offset value record.

[0113] Furthermore, the device includes a data prefetch module: used to perform data prefetch based on the prefetch addresses of each prefetch mode according to a preset priority.

[0114] In an alternative embodiment, the data prefetch module is specifically configured to perform data prefetch based on the prefetch addresses and prefetch degrees of each prefetch mode; wherein, the prefetch degree is determined based on one or more performance information.

[0115] It can be seen that the beneficial effect of the present invention is as follows: Determine whether to adopt the stream prefetch mode through the preset program counter table. In the case of not adopting the stream prefetch mode, perform the determination of other prefetch modes. In this way, multi-mode step-by-step determination avoids the situation where the same missing information triggers the search and determination processes of all prefetch modes. Moreover, the preset program counter table contains the position information of the data entries corresponding to the first instruction address information in various other prefetch mode determination tables, realizing the indexing of other prefetch mode determination tables and avoiding redundant information in various prefetch mode determination tables. In this way, the prefetch mode search overhead and storage cost are reduced.

[0116] Figure 10 For the description of the features in the corresponding embodiments, reference can be made to Figure 1 the relevant descriptions of the corresponding embodiments, which will not be elaborated here one by one.

[0117] Figure 11 The following is a structural diagram of an electronic device provided by an embodiment of the present invention, as Figure 11 shown, the electronic device includes: a memory 80 for storing a computer program;

[0118] a processor 81 for implementing the steps of the data prefetch method in the above embodiment when executing the computer program.

[0119] Among them, the processor 81 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 81 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 81 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 81 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 81 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0120] The memory 80 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 80 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 80 is at least used to store the following computer program 801. After the computer program is loaded and executed by the processor 81, it can implement the relevant steps of the data prefetch method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 80 may further include an operating system 802 and data 803, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system 802 may include Windows, Unix, Linux, etc. The data 803 may include, but is not limited to, cache data, etc.

[0121] In some embodiments, the electronic device may further include a display screen 82, an input / output interface 83, a communication interface 84, a power supply 85, and a communication bus 86.

[0122] Those skilled in the art can understand that Figure 11 the structure shown in

[0123] It can be understood that if the data prefetching method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), electrically erasable programmable ROMs, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical discs, etc., all of which can store program codes.

[0124] Based on this, the embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data prefetching method as described above are implemented.

[0125] Next, a computer program product provided by the embodiments of the present invention will be introduced. A computer program product described below can be referred to each other with other embodiments described in this article.

[0126] A computer program product includes a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the data prefetching method disclosed above are implemented.

[0127] The above has introduced in detail a data prefetching method, device, equipment, medium, and product provided by the embodiments of the present invention. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, refer to the description of the method part.

[0128] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0129] The above has introduced in detail a data prefetching method, apparatus, device, medium and product provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A data prefetching method, characterized in that, Including: Obtaining target missing information; wherein the target missing information includes first instruction address information corresponding to a program counter and first missing data address information; Obtaining stream prefetch mode determination information from a preset program counter table based on the target missing information, and generating a prefetch address corresponding to the stream prefetch mode when it is determined that a preset stream prefetch mode condition is satisfied based on the target missing information and the stream prefetch mode determination information, so as to perform data prefetch based on the prefetch address; If the preset stream prefetch mode condition is not satisfied, determining a first target entry in the preset program counter table, where the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetch mode determination tables; Performing determination of other prefetch modes based on the position information in the first target entry, and generating a prefetch address corresponding to the other prefetch mode when it is determined to adopt the other prefetch mode, so as to perform data prefetch based on the prefetch address.

2. The data prefetching method according to claim 1, wherein Obtaining stream prefetch mode determination information from a preset program counter table based on the target missing information includes: Determining the first target entry and a second target entry from the preset program counter table, where the second target entry is a data entry including instruction address information that was most recently matched in the missing information; Obtaining second missing data address information from the first target entry and the second target entry; wherein the second missing data address information is the previous missing data address information corresponding to the instruction address information in the first target entry or the second target entry.

3. The data prefetching method according to claim 2, wherein Also including: If the difference between any obtained second missing data address information and the first missing data address information is 1, it is determined that the preset stream prefetch mode condition is satisfied.

4. The data prefetching method according to claim 3, wherein Generating a prefetch address corresponding to the stream prefetch mode includes: Adding 1 to the first missing data address information to obtain the prefetch address corresponding to the stream prefetch mode.

5. The data prefetching method according to claim 3, wherein The other prefetch mode includes a stride prefetch mode, and the corresponding prefetch mode determination table is a preset stride table; Correspondingly, performing determination of other prefetch modes based on the position information in the first target entry includes: If the first target entry exists and the difference between the second missing data address information in the first target entry and the first missing data address information is not 1, then determining a third target entry corresponding to the position information from the preset stride table according to the position information of the data entry corresponding to the first instruction address information in the preset stride table in the first target entry; Obtaining stride information from the third target entry to obtain first stride information, and if the first stride information is the same as the difference between the second missing data address information and the first missing data address information and the first stride information satisfies a preset credibility condition, it is determined to adopt the stride prefetch mode.

6. The data prefetching method according to claim 5, wherein Generating a prefetch address corresponding to the other prefetch mode includes: Add the first missing data address information to the first stride information to obtain a prefetch address corresponding to the stride prefetch mode.

7. The data prefetching method according to claim 5, wherein Other prefetch modes include a space-based prefetch mode, and the corresponding prefetch mode decision table is a preset region table; Correspondingly, determining other prefetch modes based on the position information in the first target entry includes: According to the position information of the data entry corresponding to the first instruction address information in the preset region table in the first target entry, determine a fourth target entry corresponding to the position information from the preset region table; Extract the data within the preset bit range in the first missing data address information to obtain a first offset value; If a fifth target entry is determined in the preset region table, it is determined that the space-based prefetch mode is adopted; Wherein, the fifth target entry is a data entry including a second offset value consistent with the first offset value.

8. The data prefetching method according to claim 7, wherein Generating a prefetch address corresponding to other prefetch modes includes: Based on the first missing data address information and the space bit vector sequence in the fifth target entry, obtain a prefetch address of the space-based prefetch mode, where the space bit vector sequence characterizes the access situation corresponding to the same space base address in the fifth target entry.

9. The data prefetching method according to claim 7, wherein Also included is: If the first target entry or the second target entry does not exist in the preset program counter table, the prefetch mode is determined as offset prefetch; If the first stride information is inconsistent with the difference value, or does not meet the preset credibility condition, and the position information of the data entry corresponding to the first instruction address information in the preset region table does not exist in the first target entry, it is determined that the offset prefetch mode is adopted.

10. The data prefetching method according to claim 9, wherein Also included is: If the optimal offset value is recorded in the preset offset value record, determine a prefetch address corresponding to the offset prefetch mode based on the first missing data address information and the optimal offset value.

11. The data prefetching method according to claim 1, wherein Also included is: When the preset data prefetch condition is met, add the missing information to the trigger queue, where the missing information includes the instruction address information corresponding to the program counter and the missing data address information; Correspondingly, obtaining the target missing information includes: Obtain the target missing information from the trigger queue.

12. The data prefetching method according to claim 10, wherein Also included is: Obtain training information; wherein, the training information includes the third instruction address information corresponding to the program counter and the third missing data address information; Check whether a sixth target entry exists in the preset program counter table; wherein, the sixth target entry is a data entry including a fourth instruction address information identical to the third instruction address information; If the sixth target entry exists in the preset program counter table, and the position information of the data entry corresponding to the third instruction address information in the preset stride table is included in the sixth target entry, record the position information as the first position information; Obtain the fourth missing data address information from the sixth target entry; wherein, the fourth missing data address information is the previous missing data address information corresponding to the third instruction address information; Calculate the difference between the fourth missing data address information and the third missing data address information to obtain a stride information, denoted as the second stride information; Obtain the stride information in the data entry corresponding to the first position information in the preset stride table, and denote it as the third stride information; If the third stride information is the same as the second stride information, perform an increment operation on the preset counter in the data entry corresponding to the first position information in the preset stride table; otherwise, perform a decrement operation on the counter; Wherein, if the count value of the preset counter is greater than a preset threshold, it indicates that the third stride information meets the preset credibility condition.

13. The data prefetching method according to claim 12, wherein Further included: Based on a preset high-order bit range, a preset middle-order bit range, and a preset low-order bit range, split the third missing data address information in the training information to obtain a high-order part, a middle-order part, and a low-order part; Perform a hash calculation on the high-order part to obtain a spatial region index; Perform a preset calculation on the spatial region index and the middle-order part to obtain a spatial base address, and store the spatial base address in a preset training table; Remove the in-block offset bits from the low-order part to obtain an offset value within the spatial region, and record the offset value in the preset training table; When the eviction address cached is obtained, calculate the spatial base address and the offset address corresponding to the eviction address. If the spatial base address and the offset address found in the preset training table are the same as the spatial base address and the offset address corresponding to the eviction address, it is determined that the training of the data entry corresponding to the eviction address in the preset region table is completed, and add the position information of the data entry in the preset region table to the preset program counter table.

14. The data prefetching method according to claim 13, wherein Further included: Subtract the third missing data address information from the historical training address in the preset address table to obtain a first address difference, where the historical training address is the missing data address information in the historical training information; Check whether there is a second address difference identical to the first address difference in the preset score table; If there is an identical second address difference, increase the score corresponding to the identical second address difference; When the preset optimal offset value update condition is met, use the second address difference with the highest score and exceeding the preset score threshold as the optimal offset value to update the preset offset value record.

15. The data prefetching method according to claim 14, wherein Further included: Perform data prefetching based on the prefetch addresses of each prefetch mode according to a preset priority.

16. The data prefetching method according to any one of claims 1 to 15, characterized in that, Performing data prefetching based on the prefetch addresses of each prefetch mode includes: Performing data prefetching based on the prefetch addresses of each prefetch mode and the prefetch degree; Wherein, the prefetch degree is determined based on one or more performance information.

17. A data prefetching device, characterized in that, Included: A missing information acquisition module for acquiring target missing information; wherein, the target missing information includes the first instruction address information corresponding to the program counter and the first missing data address information; A stream prefetch mode processing module for obtaining stream prefetch mode determination information from a preset program counter table based on the target missing information, and generating a prefetch address corresponding to the stream prefetch mode when it is determined that the preset stream prefetch mode condition is met based on the target missing information and the stream prefetch mode determination information, so as to perform data prefetching based on the prefetch address; A target entry determination module, configured to determine a first target entry in the preset program counter table if the preset stream prefetch mode condition is not satisfied, where the first target entry is a data entry including second instruction address information identical to the first instruction address information, and the first target entry includes position information of data entries corresponding to the first instruction address information in multiple other prefetch mode determination tables; A multi-prefetch mode processing module, configured to determine other prefetch modes based on the position information in the first target entry, and generate a prefetch address corresponding to the other prefetch mode in case it is determined to adopt the other prefetch mode, so as to perform data prefetch based on the prefetch address.

18. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the data prefetch method according to any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the data prefetch method according to any one of claims 1 to 16 are implemented.

20. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the data prefetch method according to any one of claims 1 to 16 are implemented.

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