Time sequence parameter training method of Ethernet interface, electronic equipment and storage medium

Abstract

The invention discloses a time sequence parameter training method of an Ethernet interface, electronic equipment and a storage medium. The method comprises the following steps: performing time sequence training on initial parameters of a set Ethernet interface to obtain a transmission delay available range, a second initial transmission delay, a receiving delay available range and a second initial receiving delay; on the basis of the second initial sending delay or a second target time sequence parameter obtained by training, traversing the receiving delay available range to perform a first data transceiving test, and obtaining a receiving delay window after traversing the receiving delay available range; determining a first intermediate value of the receiving delay window as a first target time sequence parameter; on the basis of the second initial receiving delay or the first target time sequence parameter, traversing the available range of the sending delay to perform a second data transceiving test, and after traversing the available range of the sending delay, obtaining a sending delay window; and determining a second intermediate value of the sending delay window as a second target time sequence parameter. And the throughput performance and the working efficiency of the Ethernet can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of Ethernet interfaces, and in particular, to a method for training timing parameters of an Ethernet interface, an electronic device, and a storage medium. Background Art

[0002] With the development of Ethernet technology, the Ethernet transmission rate is getting faster and faster. To ensure the transmission performance, the requirements for read / write timing of Ethernet interfaces are becoming stricter. For example, when using an RGMII interface for data transceiver, data changes at the edge of the clock. To stably sample at the receiving end, a delay is usually added to the clock signal to align its edge with the stable interval of the data bus, so as to ensure that both the setup time and hold time of transmission / reception meet the protocol requirements.

[0003] In related technologies, it is necessary to incur a relatively high cost to fixedly configure timing parameters for chips of the same model; and when the chips are mass-produced, process corner chips will introduce timing deviations. At this time, when using the fixedly configured timing parameters for reading and writing, there may be a situation where the read / write timing is critical; thus resulting in low Ethernet throughput performance or abnormal operation of individual batches of chips. Therefore, how to determine the timing parameters of an adapted Ethernet interface is an urgent problem to be solved. Summary of the Invention

[0004] Embodiments of the present application provide a method for training timing parameters of an Ethernet interface, an electronic device, and a storage medium, which can obtain the timing parameters of an adapted Ethernet interface through training, thereby improving the Ethernet throughput performance and working efficiency.

[0005] In a first aspect, an embodiment of the present application provides a method for training timing parameters of an Ethernet interface, which is applied to a MAC controller in a system-on-chip, and the system-on-chip is communicatively connected to a target device;

[0006] The method includes:

[0007] Set a transmission delay value range, a reception delay value range, a first initial transmission delay, and a first initial reception delay of the Ethernet interface; wherein, the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range;

[0008] Perform first timing training according to the transmission delay value range and the first initial transmission delay to obtain a transmission delay available range and a second initial transmission delay; perform second timing training according to the reception delay value range and the first initial reception delay to obtain a reception delay available range and a second initial reception delay;

[0009] Based on the second target timing parameter obtained from the second initial transmission delay or training, traverse the available range of the reception delay to perform the first data transceiver test. After traversing the available range of the reception delay, a reception delay window is obtained;

[0010] Determine the first intermediate value of the reception delay window as the first target timing parameter;

[0011] Based on the second initial reception delay or the first target timing parameter, traverse the available range of the transmission delay to perform the second data transceiver test. After traversing the available range of the transmission delay, a transmission delay window is obtained;

[0012] Determine the second intermediate value of the transmission delay window as the second target timing parameter; wherein, both the first target timing parameter and the second target timing parameter are the timing parameters of the Ethernet interface between the MAC controller and the physical layer chip in the system-on-chip.

[0013] According to some embodiments of the present application, when the target device is a physical layer chip, the physical layer chip is connected to the system-on-chip through an Ethernet interface;

[0014] Before setting the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface, it further includes:

[0015] After initializing the MAC controller, configure a standard loopback test function for the physical layer chip; the standard loopback test function is used for: in response to the test data sent by the system-on-chip, returning the test data as loopback data to the system-on-chip.

[0016] According to some embodiments of the present application, the step of based on the second target timing parameter obtained from the second initial transmission delay or training, traversing the available range of the reception delay to perform the first data transceiver test, and obtaining a reception delay window after traversing the available range of the reception delay includes:

[0017] Send first test data to the physical layer chip according to the second target timing parameter obtained from the second initial transmission delay or training;

[0018] Receive the first feedback data returned by the physical layer chip in response to the first test data with the reception delay to be measured; the reception delay to be measured belongs to the available range of the reception delay;

[0019] Compare and determine whether the first test data and the first feedback data are consistent; if so, confirm that the reception delay to be measured passes the test, and record the reception delay to be measured as the available reception delay; if not, do not record the current reception delay to be measured;

[0020] Determine whether the available range of the reception delay has been traversed according to the current reception delay to be measured; if not, determine the next reception delay to be measured from the available range of the reception delay according to the current reception delay to be measured and a preset traversal rule, so as to perform the next first data transmission and reception test; if so, obtain a more accurate reception delay window according to the recorded available reception delay.

[0021] According to some embodiments of the present application, the traversing the available range of the transmission delay to perform a second data transmission and reception test based on the second initial reception delay or the first target timing parameter, and obtaining a transmission delay window after traversing the available range of the transmission delay includes:

[0022] Send second test data to the physical layer chip according to the transmission delay to be measured; the transmission delay to be measured belongs to the available range of the transmission delay;

[0023] Receive second feedback data returned by the physical layer chip in response to the second test data at the second initial reception delay or the first target timing parameter;

[0024] Compare and determine whether the second test data and the second feedback data are consistent; if so, confirm that the transmission delay to be measured passes the test, and record the transmission delay to be measured as an available transmission delay; if not, do not record the current transmission delay to be measured;

[0025] Determine whether the available range of the transmission delay has been traversed according to the current transmission delay to be measured; if not, determine the next transmission delay to be measured from the available range of the transmission delay according to the current transmission delay to be measured and a preset traversal rule, so as to perform the next second data transmission and reception test; if so, obtain a more accurate transmission delay window according to the recorded available transmission delay.

[0026] According to some embodiments of the present application, when the target device is an Ethernet device, the Ethernet device is connected to the physical layer chip through a network cable;

[0027] Before setting the transmission delay value range, reception delay value range, first initial transmission delay and first initial reception delay of the Ethernet interface, the method further includes:

[0028] After initializing the MAC controller, establish a network connection with the Ethernet device according to a preset thread.

[0029] According to some embodiments of the present application, for the second target timing parameter obtained based on the second initial transmission delay or training, traverse the available range of the reception delay to perform the first data transceiver test. After traversing the available range of the reception delay, obtaining a reception delay window includes:

[0030] Receive a first test packet sent by an Ethernet device through the physical layer chip with the reception delay to be measured, where the reception delay to be measured belongs to the available range of the reception delay;

[0031] In response to the first test packet, return a first response signal to the Ethernet device through the physical layer chip according to the second target timing parameter obtained based on the second initial transmission delay or training; and count the reception bandwidth statistic value at the current reception delay to be measured;

[0032] Judge whether the available range of the reception delay has been traversed according to the current reception delay to be measured; if not, determine the next reception delay to be measured from the available range of the reception delay according to the current reception delay to be measured and a preset traversal rule to perform the next first data transceiver test; if so, obtain the reception bandwidth statistic values corresponding to all the reception delays to be measured;

[0033] Determine the reception delay window from the available range of the reception delay according to a preset screening rule, all the reception bandwidth statistic values, and the corresponding reception delays to be measured.

[0034] According to some embodiments of the present application, for the second initial reception delay or the first target timing parameter, traverse the available range of the transmission delay to perform the second data transceiver test. After traversing the available range of the transmission delay, obtaining a transmission delay window includes:

[0035] Send a second test packet to the Ethernet device through the physical layer chip according to the transmission delay to be measured, where the transmission delay to be measured belongs to the available range of the transmission delay;

[0036] Receive a second response signal returned by the Ethernet device in response to the second test packet through the physical layer chip with the second initial reception delay or the first target timing parameter;

[0037] Count the transmission bandwidth statistic value at the current transmission delay to be measured;

[0038] Determine whether the available range of the transmission delay has been traversed according to the currently measured transmission delay to be measured; if not, determine the next measured transmission delay to be measured from the available range of the transmission delay according to the currently measured transmission delay to be measured and a preset traversal rule, so as to perform the next second data transceiver test; if so, obtain the transmission bandwidth statistical values corresponding to all the measured transmission delays to be measured.

[0039] Determine the transmission delay window from the available range of the transmission delay according to a preset screening rule, all the transmission bandwidth statistical values, and the corresponding measured transmission delays to be measured.

[0040] According to some embodiments of the present application, the preset traversal rule is to increment by 1 or decrement by 1.

[0041] In a second aspect, an embodiment of the present application provides an electronic device, including at least one processor and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method for training the timing parameters of an Ethernet interface according to any one of the embodiments of the first aspect.

[0042] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to execute the method for training the timing parameters of an Ethernet interface according to any one of the embodiments of the first aspect.

[0043] Embodiments of the present application include: A system-on-chip is communicatively connected to a target device; by using the MAC controller in the system-on-chip, first, set the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface; where the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range; secondly, perform first timing training according to the transmission delay value range and the first initial transmission delay to obtain the available range of transmission delay and the second initial transmission delay; perform second timing training according to the reception delay value range and the first initial reception delay to obtain the available range of reception delay and the second initial reception delay; then, based on the second initial transmission delay or the second target timing parameter obtained by training, traverse the available range of reception delay to perform the first data transmission and reception test, and after traversing the available range of reception delay, obtain the reception delay window; then, determine the first intermediate value of the reception delay window as the first target timing parameter; then, based on the second initial reception delay or the first target timing parameter, traverse the available range of transmission delay to perform the second data transmission and reception test, and after traversing the available range of transmission delay, obtain the transmission delay window; furthermore, determine the second intermediate value of the transmission delay window as the second target timing parameter; where the first target timing parameter and the second target timing parameter are both the timing parameters of the Ethernet interface between the MAC controller in the system-on-chip and the physical layer chip. Thus, two timing parameters of the Ethernet interface adapted between the actual system-on-chip and the physical layer chip are determined. Embodiments of the present application can obtain the timing parameters of the adapted Ethernet interface through training, thereby improving the Ethernet throughput performance and working efficiency. Description of the Drawings

[0044] Figure 1 is a schematic diagram of the system architecture for performing the timing parameter training method of the Ethernet interface provided by an embodiment of the present application;

[0045] Figure 2 is a schematic diagram of the first data transmission and reception test when the target device is a physical layer chip provided by an embodiment of the present application;

[0046] Figure 3 is a schematic diagram of the second data transmission and reception test when the target device is an Ethernet device provided by an embodiment of the present application;

[0047] Figure 4 is a schematic flowchart of the timing parameter training method of the Ethernet interface provided by an embodiment of the present application;

[0048] Figure 5 is a schematic flowchart of the first data transmission and reception test and the second data transmission and reception test performed when the target device is a physical layer chip;

[0049] Figure 6It is a schematic flow diagram of the first data transceiver test and the second data transceiver test when the target device is an Ethernet device;

[0050] Figure 7 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0051] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0052] It should be noted that although the logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be executed in an order different from that in the flowchart. In the description of the present application, the meaning of "a number of" is one or more, and the meaning of "a plurality of" is two or more. The description of "first" and "second" is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0054] First, several nouns involved in the present invention are explained:

[0055] System On Chip, abbreviated as SOC, that is, System on a Chip.

[0056] TX_delay and RX_delay are two timing parameters. TX_delay refers to the delay during transmission, which is used to determine the timing of sending data. RX_delay refers to the delay during reception, which is used to correct the timing of receiving data.

[0057] TCP (Transmission Control Protocol) refers to the Transmission Control Communication Protocol, which is a connection-oriented, reliable, byte-stream-based transport layer communication protocol.

[0058] Loopback: Standard loopback test function. It refers to the function of sending back electronic signals, data streams, etc. to the sender as they are.

[0059] MAC (Medium Access Control): Refers to the Media Access Control layer under the data link layer.

[0060] PHY (Port Physical Layer, PHY): port physical layer.

[0061] In the related art, there are three solutions for adding delay to the clock signal: the first solution is to realize the delay through PCB routing, that is, to extend the clock signal routing and maintain a reasonable deviation between the clock and data routing lengths; the second solution is to realize the delay inside the PHY chip, that is, to realize the clock and data delay through a pull-up or pull-down resistor on a PIN pin of the PHY chip; the third solution is to realize the delay on the controller side, that is, to realize it through the delay register inside the controller; the third solution is to realize the delay on the controller side, that is, generally to realize it through the delay register inside the controller. However, in solution 1, the clock line on the PCB is longer than the data line by a certain length to ensure the phase deviation between the clock and the data, which invisibly increases the difficulty of PCB layout; at the same time, board-level winding may affect the signal quality, and the winding length increases the PCB size and cost; solution 2 implements the delay of clock and data through Ethernet PHY. Its implementation scheme is to add pull-up or pull-down resistors to a certain PIN. Although it is simple to implement, it increases the BOM cost, and the tolerance for deviations introduced by factors such as chip design, manufacturing, process, and PCB routing is low, making it difficult to ensure that different Ethernet devices can achieve optimal performance; solution 3 implements the delay in the integrated driver by configuring the delay register of the Ethernet controller and debugging a set of appropriate timing parameters based on a small number of chips during the verification phase, but chips with different designs, packages, and processes need to be re-debugged, which increases the workload. The above three methods require a high cost to configure the timing parameters for the same model chip; and when the chip is mass-produced, the process corner chip will introduce timing deviation. In the case of timing deviation, the chip may have critical read and write timing when reading and writing based on the fixed configuration timing parameters; thus, the Ethernet throughput performance of individual batches of chips is low or they cannot work properly, thus reducing work efficiency. Therefore, how to determine the timing parameters of the adapted Ethernet interface is an urgent problem to be solved.

[0062] Based on this, the present application provides a timing parameter training method, an electronic device, and a computer-readable storage medium for an Ethernet interface. The method includes: performing timing training on the initial parameters of the set Ethernet interface to obtain the available range of transmission delay, the second initial transmission delay, the available range of reception delay, and the second initial reception delay; based on the second initial transmission delay or the second target timing parameters obtained through training, traversing the available range of reception delay to perform the first data transmission and reception test, and after traversing the available range of reception delay, obtaining the reception delay window; determining the first intermediate value of the reception delay window as the first target timing parameter; based on the second initial reception delay or the first target timing parameter, traversing the available range of transmission delay to perform the second data transmission and reception test, and after traversing the available range of transmission delay, obtaining the transmission delay window; determining the second intermediate value of the transmission delay window as the second target timing parameter. This can improve the Ethernet throughput performance and working efficiency.

[0063] The following further elaborates on the embodiments of the present application in conjunction with the accompanying drawings.

[0064] As Figure 1 shown, the system framework includes: a system-on-chip 100 and a target device 200. Among them, the system-on-chip 100 is communicatively connected to the target device 200, and the system-on-chip 100 further includes a MAC controller 110.

[0065] Among them, the target device 200 is used to cooperate with the system-on-chip 100 to complete the data transmission and reception test.

[0066] The MAC controller 110 is used to: set the transmission delay value range, reception delay value range, the first initial transmission delay, and the first initial reception delay of the Ethernet interface; among them, the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range; perform the first timing training according to the transmission delay value range and the first initial transmission delay to obtain the available range of transmission delay and the second initial transmission delay; perform the second timing training according to the reception delay value range and the first initial reception delay to obtain the available range of reception delay and the second initial reception delay; based on the second initial transmission delay or the second target timing parameters obtained through training, traverse the available range of reception delay to perform the first data transmission and reception test, and after traversing the available range of reception delay, obtain the reception delay window; determine the first intermediate value of the reception delay window as the first target timing parameter; based on the second initial reception delay or the first target timing parameter, traverse the available range of transmission delay to perform the second data transmission and reception test, and after traversing the available range of transmission delay, obtain the transmission delay window; determine the second intermediate value of the transmission delay window as the second target timing parameter; among them, both the first target timing parameter and the second target timing parameter are the timing parameters of the Ethernet interface between the MAC controller in the system-on-chip and the physical layer chip.

[0067] According to the system framework provided by the embodiments of the present application, a timing parameter training method for an Ethernet interface is realized through the cooperation between the MAC controller and the target device, and the timing parameters of the Ethernet interface can be obtained through training, thereby improving the Ethernet throughput performance and working efficiency.

[0068] According to some embodiments of the present application, the target device 200 is a physical layer chip or an Ethernet device.

[0069] In one embodiment, as Figure 2 shown, when the target device 200 is the physical layer chip 210, the physical layer chip 210 is connected to the system on chip 100 through an Ethernet interface. Specifically, the Ethernet interface used to connect the physical layer chip 210 and the system on chip 100 can be: MII interface, RMII interface, GMII interface, RGMII interface, and SGMII interface, etc. The present application does not specifically limit the type of the Ethernet interface used to connect the physical layer chip 210 and the system on chip 100. In addition, the physical layer chip 210 has a standard function: loopback function, which can cooperate with the system on chip to perform timing training and obtain the parameter configuration of the Ethernet interface.

[0070] When the target device 200 is the physical layer chip 210, in the initialization stage of the Ethernet bottom layer driver in the embodiments of the present application, data transceiver tests are performed, and the windows of the transceiver timing of the Ethernet interface are scanned through certain software strategies, and the automatic training and adaptation of the timing parameters of the Ethernet interface transceiver are realized at the physical layer.

[0071] In one embodiment, as Figure 3 shown, when the target device 200 is the Ethernet device 220, the Ethernet device 220 is communicatively connected to the system on chip 100 through the physical layer chip 210, wherein the Ethernet device 220 is connected to the physical layer chip 210 through a network cable. Specifically, Figure 3 in, the network cable interface used to connect the Ethernet device 220 and the physical layer chip 210 is an RJ45 interface, and the Ethernet interface used to connect the physical layer chip 210 and the system on chip 100 can be: MII interface, RMII interface, GMII interface, RGMII interface, and SGMII interface, etc.

[0072] When the target device 200 is the Ethernet device 220, in the application layer network transmission stage of the embodiments of the present application, data transceiver tests are performed, and the automatic training and adaptation of the timing parameters of the Ethernet interface transceiver are realized at the application layer by scanning the windows of the transceiver timing. The scanning and training of the timing window are performed in the application layer network transmission stage, and the timing training in the network transmission stage is performed along with the TCP packet transmission after the system on chip SOC establishes a network link with other Ethernet devices.

[0073] It can be seen that the embodiments of the present application can adapt to the diversity and complexity of the Ethernet application scenario, and perform a timing parameter training method for the Ethernet interface at the physical layer and the application layer, ensuring that the Ethernet interface has a good timing parameter configuration when performing transceiver read and write operations.

[0074] Those skilled in the art can understand that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or combine some components, or have different component arrangements.

[0075] Those skilled in the art can understand that the system architecture and application scenario described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0076] Based on the above system structure, various embodiments of the timing parameter training method for the Ethernet interface of the present application are proposed below.

[0077] In a first aspect, as Figure 4 shown, the timing parameter training method can be applied to the MAC controller of the system-on-chip as Figure 1 shown, and the system-on-chip is communicatively connected to the target device. The method may include, but is not limited to, steps S110 to S160.

[0078] Step S110: Set the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface; wherein, the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range.

[0079] Step S120: Perform first timing training according to the transmission delay value range and the first initial transmission delay to obtain the available range of the transmission delay and the second initial transmission delay; perform second timing training according to the reception delay value range and the first initial reception delay to obtain the available range of the reception delay and the second initial reception delay.

[0080] Step S130: Based on the second initial transmission delay or the second target timing parameter obtained by training, traverse the available range of the reception delay to perform the first data transceiver test. After traversing the available range of the reception delay, obtain the reception delay window.

[0081] Step S140: Determine the first intermediate value of the reception delay window as the first target timing parameter.

[0082] Step S150: Based on the second initial reception delay or the first target timing parameter, traverse the available range of transmission delays to perform the second data transceiver test. After traversing the available range of transmission delays, obtain the transmission delay window.

[0083] Step S160: Determine the second intermediate value of the transmission delay window as the second target timing parameter; wherein, both the first target timing parameter and the second target timing parameter are the timing parameters of the Ethernet interface between the MAC controller in the system-on-chip and the physical layer chip.

[0084] It should be noted that the target device is a physical layer chip or an Ethernet device.

[0085] It should be noted that the first timing training means: sending data with the first initial transmission delay, traversing the value range of the reception delay for data reception, so as to train the available range of reception delay and the second initial reception delay that can be used for further timing training from the value range of the reception delay. The second timing training means: traversing the available range of transmission delays for data sending, and receiving data with the first initial reception delay, so as to train the available range of transmission delays and the second initial transmission delay that can be used for further timing training from the available range of transmission delays.

[0086] For example, specifically, it can be trained that the available range of transmission delays is from 0 to 7, the second initial transmission delay is 7, the available range of reception delays is from 0 to 31, and the second initial reception delay is 31. It should be emphasized that the second initial transmission delay can also be other values within the available range of transmission delays, such as the intermediate value, or other values; similarly, the second initial reception delay can also be other values within the available range of reception delays, such as the intermediate value, or other values. Therefore, this application does not make specific restrictions on the values of the second initial transmission delay and the second initial reception delay.

[0087] Therefore, through steps S110 to S120, after setting the initial parameters of the Ethernet interface (i.e., the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface), performing the first timing training and the second timing training on the initial parameters can quickly attempt to obtain the available range of transmission delays, the second initial transmission delay, the available range of reception delays, and the second initial reception delay; providing a data basis for further timing training.

[0088] It should be emphasized that in the overall timing training, steps S110 to S120 perform the timing training of the first stage, and steps S130 to S160 perform the timing training of the second stage. The available range of reception delay and the available range of transmission delay obtained from the timing training of the first stage can be defined as the results of fast and lightweight timing training; the timing training of the second stage is a large-data-volume or overloaded timing training, and the obtained transmission delay window and reception delay window are more accurate.

[0089] It should be noted that in steps S110 to S160, after obtaining better first target timing parameters for reception through the first data transceiver test, the obtained first target timing parameters are applied to the timing training of the second data transceiver test to obtain second target timing parameters for transmission. It can be understood that it is also possible to obtain better second target timing parameters for transmission through the training of the second data transceiver test and then apply the obtained second target timing parameters to the timing training of the first data transceiver test to obtain first target timing parameters for reception. Therefore, the present application does not specifically limit the sequence of the first data transceiver test and the second data transceiver test.

[0090] Through steps S110 to S160, the system-on-chip communicates with the target device; by using the MAC controller in the system-on-chip, first, set the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface; wherein, the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range; secondly, perform first timing training according to the transmission delay value range and the first initial transmission delay to obtain the available range of transmission delay and the second initial transmission delay; perform second timing training according to the reception delay value range and the first initial reception delay to obtain the available range of reception delay and the second initial reception delay; then, based on the second initial transmission delay or the second target timing parameter obtained by training, traverse the available range of reception delay to perform the first data transmission and reception test, and after traversing the available range of reception delay, obtain the reception delay window; then, determine the first intermediate value of the reception delay window as the first target timing parameter; then, based on the second initial reception delay or the first target timing parameter, traverse the available range of transmission delay to perform the second data transmission and reception test, and after traversing the available range of transmission delay, obtain the transmission delay window; furthermore, determine the second intermediate value of the transmission delay window as the second target timing parameter; wherein, the first target timing parameter and the second target timing parameter are both the timing parameters of the Ethernet interface between the MAC controller in the system-on-chip and the physical layer chip. Thus, two timing parameters of the Ethernet interface adapted between the actual system-on-chip and the physical layer chip are determined. The embodiments of the present application can obtain the timing parameters of the adapted Ethernet interface through training, thereby improving the Ethernet throughput performance and working efficiency.

[0091] According to some embodiments of the present application, when the target device is a physical layer chip, the physical layer chip is connected to the system-on-chip through an Ethernet interface; before step S110, the method further includes: after initializing the MAC controller, configure the standard loopback test function for the physical layer chip; the standard loopback test function is used for: in response to the test data sent by the system-on-chip, return the test data as loopback data to the system-on-chip. It is beneficial to perform the first data transmission and reception test between the MAC controller and the physical layer chip through the configured standard loopback test function, thereby training and determining the timing parameters of the adapted Ethernet interface.

[0092] Combined Figure 2 and Figure 5 , further illustrate: the process of the first data transmission and reception test and the second data transmission and reception test performed when the target device is a physical layer chip.

[0093] According to some embodiments of the present application, when the target device is a physical layer chip, step S130 includes but is not limited to the following steps.

[0094] Step S1301: Send the first test data to the physical layer chip according to the second initial transmission delay or the second target timing parameter obtained through training.

[0095] Step S1302: Receive the first feedback data returned by the physical layer chip in response to the first test data with the to-be-tested reception delay; the to-be-tested reception delay belongs to the available range of reception delays.

[0096] Step S1303: Compare and determine whether the first test data and the first feedback data are consistent. If so, jump to execute Step S1304; if not, jump to execute Step S1305.

[0097] Step S1304: Confirm that the to-be-tested reception delay passes the test, and record the to-be-tested reception delay as the available reception delay.

[0098] Step S1305: Do not record the current to-be-tested reception delay.

[0099] Step S1306: Determine whether the available range of reception delays has been traversed according to the current to-be-tested reception delay. If not, jump to execute Step S1307; if so, jump to execute Step S1308.

[0100] Step S1307: Determine the next to-be-tested reception delay from the available range of reception delays according to the current to-be-tested reception delay and the preset traversal rule for the next first data transmission and reception test.

[0101] If so, Step S1308: Obtain a more accurate reception delay window according to the recorded available reception delay.

[0102] It can be understood that the second initial transmission delay or the second target timing parameter obtained through training determines the timing of sending data, and the to-be-tested reception delay determines the timing of receiving data.

[0103] It can be understood that when executing Step S1307, based on the preset traversal rule, when the available range of reception delays has not been traversed, increment or decrement the current to-be-tested reception delay by 1 to obtain the to-be-tested reception delay for the next first data transmission and reception test. For example, the available range of reception delays is from 0 to 31; when the available range of reception delays has not been traversed, subtract 1 from the currently used to-be-tested reception delay of 31 to determine that the to-be-tested reception delay for the next use is 30; and so on until the available range of reception delays is traversed. It should be emphasized that when traversing the available range of reception delays, it can be traversed from the middle value of the available range of reception delays to both ends, or it can also be traversed from one end of the available range of reception delays to the other end. Therefore, the present application does not make specific restrictions on the preset traversal rule, that is, on the way of traversing the available range of reception delays.

[0104] Through steps S1301 to S1308, the MAC controller sends first test data to the physical layer chip based on the second initial transmission delay or the second target timing parameter obtained through training. After receiving the first test data, the physical layer chip returns first feedback data to the MAC controller. After the MAC controller receives the first feedback data with the to-be-tested reception delay, if the first test data and the first feedback data are consistent, it is determined that the to-be-tested reception delay passes the test, and the to-be-tested reception delay is recorded as the available reception delay; if they are inconsistent, it is determined that the to-be-tested reception delay fails the test, and the current to-be-tested reception delay is not recorded. Then, the next to-be-tested reception delay is determined in an orderly manner for the first data transceiver test. In this way, between the MAC controller and the physical layer chip, the available range of the reception delay is traversed in an orderly manner for the first data transceiver test, and a reception delay window with better data transceiver effect is obtained, laying a data foundation for further determining the first target timing parameter later.

[0105] According to some embodiments of the present application, when the target device is the physical layer chip, step S150 includes but is not limited to the following steps.

[0106] Step S1501: Send second test data to the physical layer chip according to the to-be-tested transmission delay; the to-be-tested transmission delay belongs to the available range of the transmission delay.

[0107] Step S1502: Receive the second feedback data returned by the physical layer chip in response to the second test data with the second initial reception delay or the first target timing parameter.

[0108] Step S1503: Compare and determine whether the second test data and the second feedback data are consistent. If so, jump to execute step S1504; if not, jump to execute step S1505.

[0109] Step S1504: Confirm that the to-be-tested transmission delay passes the test, and record the to-be-tested transmission delay as the available transmission delay.

[0110] Step S1505: Do not record the current to-be-tested transmission delay.

[0111] Step S1506: Determine whether the available range of the transmission delay is traversed according to the current to-be-tested transmission delay. If not, jump to execute step S1507; if so, jump to execute step S1508.

[0112] Step S1507: Determine the next to-be-tested transmission delay from the available range of the transmission delay according to the current to-be-tested transmission delay and the preset traversal rule for the next second data transceiver test.

[0113] Step S1508: Obtain a more accurate transmission delay window according to the recorded available transmission delay.

[0114] It can be understood that the to-be-tested transmission delay determines the timing of sending data, and the second initial reception delay or the first target timing parameter determines the timing of receiving data.

[0115] It can be understood that when executing S1507, based on a preset traversal rule, without traversing the available range of the transmission delay, increase or decrease the current to-be-tested transmission delay by 1 to obtain the to-be-tested transmission delay for the next second data transceiver test. For example, if the available range of the transmission delay is from 0 to 7, without traversing the available range of the transmission delay, subtract 1 from the currently used to-be-tested transmission delay 7 to determine that the to-be-tested transmission delay for the next use is 6; and so on, then next, the second data transceiver test will be successively based on the transmission delays 5, 4, 3, 2, 1, 0 until the available range of the reception delay is traversed. It should be emphasized that when traversing the available range of the transmission delay, it can be traversed from the middle value of the available range of the transmission delay to both ends, or it can also be traversed from one end of the available range of the transmission delay to the other end. Therefore, this application does not make specific restrictions on the preset traversal rule, that is, on the way of traversing the available range of the transmission delay.

[0116] By steps S1501 to S1508, the available range of the transmission delay is traversed orderly, and a transmission delay window with better data transceiver effect can be obtained, laying a data foundation for further determining the second target timing parameter subsequently.

[0117] According to some embodiments of this application, when the target device is an Ethernet device, the Ethernet device is connected to the physical layer chip through a network cable; before step S110, the method further includes: after initializing the MAC controller, establishing a network link with the Ethernet device according to a preset thread. This is beneficial to performing the second data transceiver test between the MAC controller and the Ethernet device through the established network link and the physical layer chip, thereby training and determining the timing parameters of the adapted Ethernet interface.

[0118] Combined with Figure 3 and Figure 6 , further illustrate: the process of the first data transceiver test and the second data transceiver test performed when the target device is an Ethernet device.

[0119] According to some embodiments of this application, when the target device is an Ethernet device, Figure 4 step S130 in

[0120] Step S1309: Receive the first test packet sent by the Ethernet device through the physical layer chip with the to-be-tested reception delay; wherein, the to-be-tested reception delay belongs to the available range of the reception delay.

[0121] Step S1310: In response to the first test message, return a first response signal to the Ethernet device through the physical layer chip according to the second initial transmission delay or the second target timing parameter obtained through training.

[0122] Step S1311: Statistically calculate the received bandwidth statistic value under the current received delay to be measured.

[0123] Step S1312: Determine whether the available range of received delays has been traversed according to the current received delay to be measured; if not, jump to execute Step S1313; if so, jump to execute Step S1314.

[0124] Step S1313: Determine the next received delay to be measured from the available range of received delays according to the current received delay to be measured and the preset traversal rule, so as to perform the next first data transmission and reception test.

[0125] Step S1314: Obtain the received bandwidth statistic values corresponding to all received delays to be measured.

[0126] Step S1315: Determine the received delay window from the available range of received delays according to the preset screening rule, all the received bandwidth statistic values, and the corresponding received delays to be measured.

[0127] It can be understood that the first test message can be a TCP message.

[0128] It can be understood that the preset traversal rule means that: when the available range of received delays has not been traversed, increase or decrease the current received delay to be measured by 1 to obtain the received delay to be measured for the next first data transmission and reception test.

[0129] It can be understood that when the received delay to be measured is not properly matched, it may lead to poor received bandwidth statistic values. Therefore, in Step S1315, the preset screening rule means that: the high or low of the received bandwidth statistic values corresponding to each received delay to be measured can be used to determine whether the received delay to be measured is properly matched; if the received bandwidth statistic value is high, it means that the corresponding received delay to be measured is properly matched; otherwise, it is not properly matched. For example, after traversing the available range of received delays from 0 to 31, if the received bandwidth statistic values corresponding to the received delays to be measured from 0 to 10 are relatively low, it is further determined that the timing range from 0 to 10 in the available range of received delays is not properly matched; if the received bandwidth statistic values corresponding to the received delays to be measured from 10 to 25 are stably high, and the received bandwidth statistic values corresponding to the received delays to be measured from 25 to 31 are relatively low, it can be comprehensively determined that the timing range from 26 to 31 in the available range of received delays is properly matched, and the timing range from 26 to 31 is determined as the received delay window. It can be understood that this is only an example for auxiliary understanding here, and the specific value of the received delay window will be determined by the result of actual timing training.

[0130] Through steps S1309 to S1315, between the MAC controller and the Ethernet device, the available range of receive delay is traversed in an orderly manner to perform the first data transceiver test, obtaining a receive delay window with better data transceiver effect, laying a data foundation for further determining the first target timing parameter subsequently.

[0131] According to some embodiments of the present application, when the target device is an Ethernet device, Figure 4 step S150 in also includes but is not limited to the following steps.

[0132] Step S1509: Send a second test message to the Ethernet device through the physical layer chip according to the to-be-tested transmission delay; the to-be-tested transmission delay belongs to the available range of transmission delay.

[0133] Step S1510: Receive, through the physical layer chip, a second response signal returned by the Ethernet device in response to the second test message with the second initial receive delay or the first target timing parameter.

[0134] Step S1511: Statistically calculate the transmission bandwidth statistical value at the current to-be-tested transmission delay.

[0135] Step S1512: Determine whether the available range of transmission delay has been traversed according to the current to-be-tested transmission delay. If not, jump to execute step S1513; if so, jump to execute step S1514.

[0136] Step S1513: Determine the next to-be-tested transmission delay from the available range of transmission delay according to the current to-be-tested transmission delay and the preset traversal rule for the next second data transceiver test.

[0137] Step S1514: Obtain the transmission bandwidth statistical values corresponding to all to-be-tested transmission delays.

[0138] Step S1515: Determine the transmission delay window from the available range of transmission delay according to the preset screening rule, all the transmission bandwidth statistical values, and the corresponding to-be-tested transmission delays.

[0139] It can be understood that the second test message can be a TCP message.

[0140] It can be understood that the preset traversal rule means that: when the available range of transmission delay has not been traversed, increase or decrease the current to-be-tested transmission delay by 1 to obtain the to-be-tested transmission delay for the next second data transceiver test.

[0141] It can be understood that when the transmission delay to be measured is not adaptable, it may lead to poor statistical values of the transmission bandwidth. Therefore, in step S1515, the preset screening rule means that the adaptability of the transmission delay to be measured can be judged by the level of the statistical value of the transmission bandwidth corresponding to each transmission delay to be measured; a high statistical value of the transmission bandwidth indicates that the corresponding transmission delay to be measured is adaptable; otherwise, it is not adaptable. For example, after traversing the available range of the transmission delay, if the statistical values of the transmission bandwidth corresponding to the transmission delays to be measured of 0, 1, and 2 are relatively low, it is further judged that the time sequence range from 0 to 2 in the available range of the transmission delay is not adaptable; the statistical values of the transmission bandwidth corresponding to the transmission delays to be measured of 3, 4, and 5 are stably high, and the statistical values of the transmission bandwidth corresponding to the transmission delays to be measured of 6 and 7 are relatively low, then it can be comprehensively judged that the time sequence range from 3 to 5 in the available range of the transmission delay is adaptable, and the time sequence range from 3 to 5 is determined as the transmission delay window. It can be understood that this is only an example for auxiliary understanding here, and the specific value of the transmission delay window will be determined by the result of actual time sequence training.

[0142] Through steps S1509 to S1515, a second data transceiver test is orderly carried out by traversing the available range of the transmission delay between the MAC controller and the Ethernet device, and a transmission delay window with better data transceiver effect is obtained, laying a data foundation for further determining the second target timing parameter subsequently.

[0143] According to some embodiments of the present application, the preset traversal rule is to increment by 1 or decrement by 1. In order to orderly and without omission traverse the available range of the transmission delay and the available range of the reception delay.

[0144] According to some embodiments of the present application, step S140 is further described: determining the first intermediate value of the reception delay window as the first target timing parameter. Specifically, if the obtained reception delay window is [27, 31]; calculating the first intermediate value of the reception delay window is: (27 + 31) / 2 = 29; then the first intermediate value 29 is determined as the first target timing parameter. In this way. The adaptable first target timing parameter is determined, so as to ensure that the Ethernet interface can receive data based on good and adaptable timing parameters, and improve the working efficiency of receiving data.

[0145] According to some embodiments of the present application, step S160 is further described: determining the second intermediate value of the transmission delay window as the second target timing parameter. Specifically, if the obtained transmission delay window is [3, 7]; calculating the second intermediate value of the transmission delay window is: (3 + 7) / 2 = 5; then the second intermediate value 5 is determined as the second target timing parameter. In this way, the adaptable second target timing parameter is determined, so as to ensure that the Ethernet interface can send data based on good and adaptable timing parameters, and improve the working efficiency of sending data.

[0146] Take an example and combineFigure 2 When the target device is a physical layer chip, briefly describe the overall process of the timing parameter training method.

[0147] First, initialize the Ethernet MAC controller.

[0148] Second, configure the physical layer chip to the loopback function.

[0149] Next, set the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay of the Ethernet interface.

[0150] Furthermore, perform the first-stage timing training on the transmission delay value range, reception delay value range, first initial transmission delay, and first initial reception delay to obtain a more accurate transmission delay TX_delay value range, reception delay RX_delay value range, as well as the initial value of the transmission delay TX_delay and the initial value of the reception delay RX_delay. Then perform the second-stage timing training as described below:

[0151] Then, gradually traverse the reception delay RX_delay, send data TX_DATA to the Ethernet PHY based on the initial value of the transmission delay TX_delay, and receive the data RX_DATA returned by the Ethernet PHY based on the reception delay RX_delay.

[0152] After that, compare the transmitted data TX_DATA with the received data RX_DATA. If they match, record RX_delay. After the traversal is completed, obtain the available RX_delay window.

[0153] Subsequently, select the middle value of the available RX_delay window to set the reception delay parameter.

[0154] Next, gradually traverse the transmission delay TX_delay, send data TX_DATA to the Ethernet PHY based on the transmission delay TX_delay, and receive the data RX_DATA returned by the Ethernet PHY based on the set reception delay.

[0155] Then, compare the transmitted data TX_DATA with the received data RX_DATA. If they match, record TX_delay. After the traversal is completed, obtain the available TX_delay window.

[0156] Finally, select the middle value of the available TX_delay window to set the transmission delay parameter. Thus, the training of the timing parameters of the Ethernet interface is completed.

[0157] It can be seen that in the embodiment of the present application, a clock signal delay is added at the MAC controller end, and by using the standard loopback test function of the Ethernet PHY, during the initialization stage of the Ethernet underlying driver, the window of the read / write timing of the Ethernet interface is scanned through a certain software policy, realizing the automatic training and adaptation of the read / write timing of the Ethernet interface.

[0158] In addition, considering the diversity and complexity of the application scenarios of Ethernet products, when the use of the Ethernet PHY loopback function is restricted, refer to Figure 3 During the application layer network transmission stage, the scanning and training of the timing window are carried out. The timing training during the network transmission stage is carried out along with the TCP packet transmission after the network link is established between the system on chip (SOC) and other Ethernet devices.

[0159] It should be emphasized that the timing parameter training method provided by the embodiment of the present application has been implemented and verified on actual devices, proving that there is sufficient margin for the read / write timing of the Ethernet interface of chips with different process corners, and it is feasible. It has also been implemented on Ethernet chips using GMAC IP.

[0160] In summary, aiming at the problems that there are phase deviations between the Ethernet interface clock line and data line introduced by design, manufacturing, and process among different chips, different packages, and different batches, and the board-level Ethernet layout design is difficult, the timing parameter training method proposed by the embodiment of the present application can use the delay register inside the Ethernet controller to increase the delay at the MAC end; through multiple transceiver read / write trainings of the Ethernet, find out the read / write timing window of the Ethernet interface of each chip, and then select the intermediate timing parameters of the timing window as the final configuration, realizing the automatic training and adaptation of the timing parameters of the Ethernet interface, and ensuring that there is sufficient margin for the read / write timing of the Ethernet interface of each chip. Moreover, while ensuring the Ethernet performance, the solution cost is reduced and the work efficiency is improved. In addition, considering the diversity and complexity of the Ethernet application scenarios, the timing parameter training method of the present invention can be flexibly applied at the Ethernet driver bottom layer and application layer of the chip, and the application scenarios are relatively wide.

[0161] In a second aspect, as Figure 7 shown, the present invention also provides an electronic device 600, including:

[0162] A processor 601, which can be implemented in ways such as a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present application;

[0163] The memory 602 can be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, a random access memory, etc. The memory 602 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 602 and are called by the processor 601 to execute the timing parameter training method of the Ethernet interface in the embodiments of this application;

[0164] The input / output interface 603 is used to implement information input and output;

[0165] The communication interface 604 is used to implement communication and interaction between this device and other devices. Communication can be achieved through a wired method (such as USB, network cable, etc.) or through a wireless method (such as a mobile network, WIFI, Bluetooth, etc.);

[0166] The bus 605 transmits information between the various components of the device (such as the processor 601, the memory 602, the input / output interface 603, and the communication interface 604);

[0167] Among them, the processor 601, the memory 602, the input / output interface 603, and the communication interface 604 achieve communication connections with each other inside the device through the bus 605.

[0168] In a third aspect, the embodiments of this application also provide a storage medium. The storage medium is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, it implements the above-mentioned timing parameter training method of the Ethernet interface.

[0169] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some implementation manners, the memory may optionally include a memory remotely provided with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and may be located in one place, or may also be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solutions in this embodiment.

[0170] Those of ordinary skill in the art will understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media.

[0171] The above is a specific description of the preferred embodiment of the present application. However, the present application is not limited to the above embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present application, and these equivalent deformations or substitutions are all included within the scope defined by the present application.

Claims

1. A timing parameter training method for an Ethernet interface, characterized in that, it is applied to a MAC controller in a system-on-chip, and the system-on-chip is communicatively connected to a target device; the method includes: setting a transmission delay value range, a reception delay value range, a first initial transmission delay, and a first initial reception delay of the Ethernet interface; wherein, the first initial transmission delay belongs to the transmission delay value range, and the first initial reception delay belongs to the reception delay value range; performing first timing training according to the transmission delay value range and the first initial transmission delay to obtain a transmission delay available range and a second initial transmission delay; performing second timing training according to the reception delay value range and the first initial reception delay to obtain a reception delay available range and a second initial reception delay; based on the second initial transmission delay or the second target timing parameter obtained by training, traversing the reception delay available range to perform a first data transmission and reception test, and after traversing the reception delay available range, obtaining a reception delay window; determining a first intermediate value of the reception delay window as a first target timing parameter; based on the second initial reception delay or the first target timing parameter, traversing the transmission delay available range to perform a second data transmission and reception test, and after traversing the transmission delay available range, obtaining a transmission delay window; determining a second intermediate value of the transmission delay window as a second target timing parameter; wherein, both the first target timing parameter and the second target timing parameter are timing parameters of the Ethernet interface between the MAC controller in the system-on-chip and the physical layer chip.

2. The timing parameter training method according to claim 1, characterized in that, when the target device is a physical layer chip, the physical layer chip is connected to the system-on-chip through an Ethernet interface; before setting the transmission delay value range, the reception delay value range, the first initial transmission delay, and the first initial reception delay of the Ethernet interface, it further includes: after initializing the MAC controller, configuring a standard loopback test function for the physical layer chip; the standard loopback test function is used for: in response to test data sent by the system-on-chip, returning the test data as loopback data to the system-on-chip.

3. The timing parameter training method according to claim 2, characterized in that, the step of based on the second initial transmission delay or the second target timing parameter obtained by training, traversing the reception delay available range to perform a first data transmission and reception test, and after traversing the reception delay available range, obtaining a reception delay window includes: sending first test data to the physical layer chip according to the second initial transmission delay or the second target timing parameter obtained by training; receiving first feedback data returned by the physical layer chip in response to the first test data with a reception delay to be measured; the reception delay to be measured belongs to the reception delay available range; Compare and determine whether the first test data and the first feedback data are consistent; if so, confirm that the to-be-tested reception delay passes the test, and record the to-be-tested reception delay as the available reception delay; if not, do not record the current to-be-tested reception delay; Judge whether the available range of the reception delay is traversed according to the current to-be-tested reception delay; if not, determine the next to-be-tested reception delay from the available range of the reception delay according to the current to-be-tested reception delay and the preset traversal rule, so as to perform the next first data transceiver test; if so, obtain a more accurate reception delay window according to the recorded available reception delay.

4. The timing parameter training method according to claim 2, characterized in that the traversing the available range of the transmission delay to perform the second data transceiver test based on the second initial reception delay or the first target timing parameter, and obtaining a transmission delay window after traversing the available range of the transmission delay, includes: Sending second test data to the physical layer chip according to the to-be-tested transmission delay; the to-be-tested transmission delay belongs to the available range of the transmission delay; Receiving second feedback data returned by the physical layer chip in response to the second test data with the second initial reception delay or the first target timing parameter; Compare and determine whether the second test data and the second feedback data are consistent; if so, confirm that the to-be-tested transmission delay passes the test, and record the to-be-tested transmission delay as the available transmission delay; if not, do not record the current to-be-tested transmission delay; Judge whether the available range of the transmission delay is traversed according to the current to-be-tested transmission delay; if not, determine the next to-be-tested transmission delay from the available range of the transmission delay according to the current to-be-tested transmission delay and the preset traversal rule, so as to perform the next second data transceiver test; if so, obtain a more accurate transmission delay window according to the recorded available transmission delay.

5. The timing parameter training method according to claim 1, characterized in that when the target device is an Ethernet device, the Ethernet device is connected to the physical layer chip through a network cable; before setting the transmission delay value range, reception delay value range, first initial transmission delay and first initial reception delay of the Ethernet interface, the method further includes: After initializing the MAC controller, establish a network connection with the Ethernet device according to a preset thread.

6. The timing parameter training method according to claim 5, characterized in that the traversing the available range of the reception delay to perform the first data transceiver test based on the second initial transmission delay or the second target timing parameter obtained by training, and obtaining a reception delay window after traversing the available range of the reception delay, includes: Receiving a first test packet sent by the Ethernet device through the physical layer chip with the to-be-tested reception delay; wherein, the to-be-tested reception delay belongs to the available range of the reception delay; In response to the first test message, return a first response signal to the Ethernet device through the physical layer chip according to the second target timing parameter obtained by training based on the second initial transmission delay; and count the receive bandwidth statistic value at the current receive delay to be measured. Determine whether the available range of the receive delay has been traversed according to the current receive delay to be measured; if not, determine the next receive delay to be measured from the available range of the receive delay according to the current receive delay to be measured and a preset traversal rule, so as to perform the next first data transceiver test; if so, obtain the receive bandwidth statistic values corresponding to all the receive delays to be measured. Determine the receive delay window from the available range of the receive delay according to a preset screening rule, all the receive bandwidth statistic values, and the corresponding receive delays to be measured.

7. The timing parameter training method according to claim 5, wherein, The second data transceiver test is performed by traversing the available range of the transmission delay based on the second initial receive delay or the first target timing parameter. After traversing the available range of the transmission delay, a transmission delay window is obtained, including: Send a second test message to the Ethernet device through the physical layer chip according to the transmission delay to be measured; the transmission delay to be measured belongs to the available range of the transmission delay. Receive a second response signal returned by the Ethernet device in response to the second test message through the physical layer chip with the second initial receive delay or the first target timing parameter. Count the transmission bandwidth statistic value at the current transmission delay to be measured. Determine whether the available range of the transmission delay has been traversed according to the current transmission delay to be measured; if not, determine the next transmission delay to be measured from the available range of the transmission delay according to the current transmission delay to be measured and a preset traversal rule, so as to perform the next second data transceiver test; if so, obtain the transmission bandwidth statistic values corresponding to all the transmission delays to be measured. Determine the transmission delay window from the available range of the transmission delay according to a preset screening rule, all the transmission bandwidth statistic values, and the corresponding transmission delays to be measured.

8. The timing parameter training method according to any one of claims 3, 4, 6, or 7, wherein, The preset traversal rule is to increment by 1 or decrement by 1.

9. An electronic device, wherein, It includes at least one processor and a memory for communicatively connecting with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the timing parameter training method of the Ethernet interface according to any one of claims 1 to 8.

10. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer-executable instructions for causing a computer to execute the timing parameter training method of the Ethernet interface according to any one of claims 1 to 8.

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