Computing system architecture with efficient bus connections

Abstract

The invention relates to a computing system architecture with efficient bus connections. A computing system may include a memory controller, an interface circuit, and a memory device. The interface circuit may be in parallel data communication with the memory controller and with the memory device. A clock rate of a bus between the interface circuit and the memory controller may be greater than or equal to a clock rate of a bus between the interface circuit and the memory device.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 604,718, filed on November 30, 2023; U.S. Provisional Application No. 63 / 566,570, filed on March 18, 2024; Korean Application No. 10 - 2024 - 0088306, filed on July 4, 2024, with the Korean Intellectual Property Office; and U.S. Application No. 18 / 955,468, filed on November 21, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] Various embodiments generally relate to integrated circuit technology and, more particularly, to a computing system architecture having an efficient bus connection. Background art

[0004] Generally, a computing system may have a structure in which a host device and a memory device are electrically connected. The host device may include a processing core and a memory controller. The memory device may include a memory cell array. The host device may be electrically connected to the memory device via a memory channel, where the memory channel employs serial data transmission. Serial data transmission can minimize the number of data signal transmission lines included in the memory channel and can reduce the deviation between the data signal and the clock signal. However, for serial data transmission, the host device may require a controller physical interface (e.g., a double - data - rate (DDR) PHY), and the memory device may require a memory physical interface. For example, both the controller physical interface and the memory physical interface may include a serializer - deserializer (SerDes).

[0005] The controller physical interface can convert parallel data generated by a processing core and a memory controller into serial data, and can transmit the serial data to a memory device via a memory channel. In addition, the controller physical interface can convert serial data transmitted from the memory device into parallel data, and provide the parallel data to the memory controller and the host device. The memory physical interface can convert parallel data output from a memory cell array into serial data, and transmit the serial data to the host device via a memory channel. The memory physical interface can convert serial data transmitted from the host device through the memory channel into parallel data, and can provide the parallel data to the memory cell array. In an environment where both the host device and the memory device are manufactured in a single chip or a single package, the above structure of a traditional computing system may already be the optimal signal transmission structure. However, in an environment where advanced packaging technology increases the number of signal transmission lines electrically connecting the host device and the memory device, and where the host device and the memory device are manufactured as chiplets, a computing system architecture that can more effectively connect the host device and the memory device is needed. Summary of the Invention

[0006] In one embodiment, a computing system may include a host, a memory controller, an interface circuit, and a memory device. The memory controller may be electrically connected to the host via a host bus. The interface circuit may be electrically connected to the memory controller via a first data bus. The memory device may be electrically connected to the interface circuit via a second data bus. The width of the second data bus may be greater than or equal to the width of the first data bus.

[0007] In one embodiment, a computing system may include a host, a memory controller, an interface circuit, and a memory device. The memory controller may be electrically connected to the host via a first bus. The interface circuit may be electrically connected to the memory controller via a second bus. The memory device may be electrically connected to the interface circuit via a third bus. The clock rate of the third bus may be less than or equal to the clock rate of the second bus.

[0008] In one embodiment, a computing system may include a host, a memory controller, a first interface circuit, a second interface circuit, a first memory device, and a second memory device. The memory controller may be electrically connected to the host via a host bus. The first interface circuit may be electrically connected to the memory controller via a first controller bus. The second interface circuit may be electrically connected to the memory controller via a second controller bus. The first memory device may be electrically connected to the first interface circuit via a first memory bus. The second memory device may be electrically connected to the second interface circuit via a second memory bus. The clock rate of the first controller bus may be greater than or equal to the clock rate of the first memory bus.

[0009] In one embodiment, a computing system may include a host, a first memory controller, a second memory controller, a first interface circuit, a second interface circuit, a first memory device, and a second memory device. The first memory controller may be electrically connected to the host via a first host bus. The second memory controller may be electrically connected to the host via a second host bus. The first interface circuit may be electrically connected to the first memory controller via a first controller bus. The second interface circuit may be electrically connected to the second memory controller via a second controller bus. The first memory device may be electrically connected to the first interface circuit via a first memory bus. The second memory device may be electrically connected to the second interface circuit via a second memory bus. The clock rate of the first controller bus may be greater than or equal to the clock rate of the first memory bus.

[0010] In one embodiment, a computing system may include a main host, a first memory controller, a sub-host, a second memory controller, a first interface circuit, a second interface circuit, a first memory device, and a second memory device. The first memory controller may be electrically connected to the main host via a first host bus. The sub-host may be electrically connected to the main host via a system bus. The second memory controller may be electrically connected to the sub-host via a second host bus. The first interface circuit may be electrically connected to the first memory controller via a first controller bus. The second interface circuit may be electrically connected to the second memory controller via a second controller bus. The first memory device may be electrically connected to the first interface circuit via a first memory bus. The second memory device may be electrically connected to the second interface circuit via a second memory bus. The clock rate of the first controller bus may be greater than or equal to the clock rate of the first memory bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0012] Figure 2 To show Figure 1 A diagram showing the connection relationship between the memory controller, interface circuit, and memory device shown in

[0013] Figure 3 To show Figure 2 A block diagram showing the configuration of the address control circuit shown in

[0014] Figure 4 To show Figure 2 A block diagram showing the configuration of the data input / output circuit shown in

[0015] Figure 5 To show Figure 2 A block diagram showing the configuration of the clock control circuit shown in

[0016] Figure 6 A diagram showing the configuration of a memory die according to an embodiment of the present disclosure.

[0017] Figure 7 A diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0018] Figure 8 A diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0019] Figure 9A A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0020] Figure 9B A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0021] Figure 9C A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0022] Figure 9D A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0023] Figure 9E A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0024] Figure 10A A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0025] Figure 10B A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0026] Figure 10C A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0027] Figure 10D A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0028] Figure 10E A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0029] Figure 10F A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0030] Figure 10G A diagram showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0031] Figure 10H A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0032] Figure 10I A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0033] Figure 10J A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0034] Figure 10K A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0035] Figure 10L A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0036] Figure 10M A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0037] Figure 10N A diagram for showing the configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0038] Figure 11 A diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0039] Figure 12 A diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0040] Figures 13A to 13C A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0041] Figures 14A to 14C A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0042] Figures 15A to 15C A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0043] Figures 16A to 16C A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0044] Figures 17A to 17C A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0045] Figure 18 A diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0046] Figure 19 This is a diagram showing the configuration of a semiconductor device according to an embodiment of the present disclosure. Detailed implementation

[0047] Figure 1 This is a diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Refer to Figure 1 , the computing system 100 may include a host 110, a memory controller 120, an interface circuit 130, and a memory device 140. The host 110 may generate an access request to the memory device 140 in response to an input from a user (e.g., execution of an application or software). The access request may include a write request and a read request. The host 110 may include any computing architecture most suitable for executing the application required by the user. For example, the host 110 may include at least one of the following: a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor (DSP), an application processor (AP), a data processing unit (DPU), a neural processing unit (NPU), a system on a chip (SoC), or any combination of two or more of the above. The host 110 may be electrically connected to the memory controller 120 through a first bus 150. The first bus 150 may be any set of signal transmission lines for electrically connecting the host 110 and the memory controller 120. For example, the first bus 150 may include at least one of an advanced extensible interface (AXI), a universal chip interconnect express interface (UCIe), an advanced microcontroller bus architecture (AMBA), a super path interconnect (UPI), an infinity fabric, and an NVLINK.

[0048] The memory controller 120 may be electrically connected to the host 110 via the first bus 150. The memory controller 120 may facilitate data transmission between the host 110 and the memory device 140. The memory controller 120 may receive write requests and read requests from the host 110 via the first bus 150, and may generate or receive various control signals for accessing the memory device 140 based on these requests. For example, the various control signals may include an address signal, a command signal, a write data signal, a read data signal, a clock signal, etc. The memory controller 120 may be electrically connected to the interface circuit 130 via the second bus 160. The second bus 160 may include a first data bus 161. The first data bus 161 may transmit the write data signal from the memory controller 120 to the interface circuit 130, and may transmit the read data signal from the interface circuit 130 to the memory controller 120. The memory controller 120 and the interface circuit 130 may perform parallel data communication via the first data bus 161. In one embodiment, the memory controller 120 and the interface circuit 130 may perform partial parallel data communication via the first data bus 161, that is, a combination of serial data communication and parallel data communication. The remaining part of the second bus 160, that is, the part other than the first data bus 161, may transmit the address signal, the command signal, the clock signal, etc. from the memory controller 120 to the interface circuit 130.

[0049] The interface circuit 130 may be electrically connected between the memory controller 120 and the memory device 140. The interface circuit 130 may relay data transmission between the memory controller 120 and the memory device 140 and signal transmission to and from the memory controller 120 and the memory device 140. The interface circuit 130 may convert various signals received from the memory controller 120 to generate signals suitable for use by the memory device 140 (e.g., serialization or deserialization). The interface circuit 130 may convert signals received from the memory device 140 to generate signals suitable for use by the memory controller 120 (e.g., serialization or deserialization). The interface circuit 130 may be electrically connected to the memory controller 120 via a second bus 160. The interface circuit 130 may receive an address signal, a command signal, a clock signal, and a write data signal from the memory controller 120 via the second bus 160, and may transmit a read data signal to the memory controller 120. The interface circuit 130 may receive the write data signal from the memory controller 120 via a first data bus 161, and may transmit the read data signal to the memory controller 120 via the first data bus 161. The interface circuit 130 may be electrically connected to the memory device 140 via a third bus 170. Via the third bus 170, the interface circuit 130 may provide the address signal, the command signal, the clock signal, and the memory data signal received from the memory controller 120 to the memory device 140, and may receive the memory data signal from the memory device 140. The third bus 170 may include a second data bus 171. The second data bus 171 may transmit the memory data signal from the interface circuit 130 to the memory device 140, and may transmit the memory data signal from the memory device 140 to the interface circuit 130. The third bus 170 other than the second data bus 171 may transmit the address signal, the command signal, the clock signal, etc. from the interface circuit 130 to the memory device 140. The interface circuit 130 may generate a memory data signal based on the write data signal received from the memory controller 120, and may generate a read data signal based on the memory data signal received from the memory device 140. The interface circuit 130 and the memory device 140 may perform parallel data communication via the second data bus 171. The interface circuit 130 and the memory device 140 may perform full parallel data communication via the second data bus 171.

[0050] The memory device 140 may be electrically connected to the interface circuit 130 through the third bus 170. Through the third bus 170, the memory device 140 may receive an address signal, a command signal, a clock signal, and a memory data signal from the interface circuit 130, and may transmit the memory data signal to the interface circuit 130. The memory device 140 may transmit the memory data signal to the interface circuit 130 through the second data bus 171, and may receive the memory data signal transmitted from the interface circuit 130 through the second data bus 171. The memory device 140 may include a memory cell array, and a specific area of the memory cell array may be accessed based on the address signal. The memory device 140 may perform a write operation and a read operation based on the command signal. The write operation may be an operation of storing the memory data signal transmitted from the interface circuit 130 in the accessed area of the memory cell array based on the address signal. The read operation may be an operation of providing the data stored in the accessed area of the memory cell array to the interface circuit 130 as a memory data signal based on the address signal.

[0051] The memory device 140 may include at least one memory die. The memory device 140 may include one memory die, or may include two or more memory dies disposed on an interposer and / or a substrate. When the memory device includes two or more memory dies, the two or more memory dies may independently form a plurality of channels, and the plurality of channels are independently electrically connected to the interface circuit 130. There may be a plurality of third buses 170 corresponding to the number of channels. In one embodiment, two or more memory dies may form a common channel and may be commonly electrically connected to the interface circuit 130. In one embodiment, the memory device 140 may include a plurality of memory banks, the memory banks each including two or more memory dies, and the plurality of memory banks may form a plurality of channels. The memory dies included in the plurality of memory banks may form a common channel. A plurality of third buses 170 corresponding to the number of channels may be provided.

[0052] In a traditional computing system, a memory controller and a memory device are electrically connected via a high-speed serial bus, and the memory controller and the memory device perform high-speed serial data communication. The high-speed serial bus has the advantages of lower implementation cost and a reduced number of signal transmission lines required. However, the high-speed serial bus has limitations in expanding data bandwidth, and as the frequency of the computing system increases, the integrity of the signals transmitted via the high-speed serial bus may decrease. In addition, in order to perform serial data communication via the high-speed serial bus, the memory controller and the memory device must be equipped with serializer-deserializer (SerDes). In addition, in order to transmit symbol-based data signals, such as pulse amplitude modulation (PAM), the memory controller and the memory device must be equipped with dedicated data encoders and data decoders in addition to SerDes. As the trend of integrated circuit miniaturization continues, the additional circuits required for serial data communication may impose a heavy burden on the host device and the memory device including the memory controller.

[0053] By using a substrate and / or an interposer having a plurality of signal transmission lines and the development of advanced packaging technology, the physical limitation of the number of signal transmission lines can be alleviated. For example, in a computing system 100, a memory controller 120 can be electrically connected to a memory device 140 via a parallel bus through an interface circuit 130, and can perform parallel data communication with the memory device 140. When parallel data communication is performed between the memory controller 120 and the memory device 140, the data bandwidth can be greatly increased, and the memory device 140 can provide the data required for the host 110 to perform computing operations faster. With the advancement of artificial intelligence (AI) technology, the amount of data that the host 110 needs to process at one time is continuously increasing. Therefore, increasing the data bandwidth between the memory controller 120 and the memory device 140 will be a key factor in optimizing the performance of the host 110. In addition, when the memory controller 120 and the memory device 140 perform parallel data communication via the interface circuit 130, the memory controller 120 and the memory device 140 may not require additional circuits, such as SerDes, data encoders, and data decoders. Therefore, the number and / or size of the computing circuits can be increased, and the increase in the computing circuits can improve the computing performance of the host 110. In addition, by forming a larger number of memory cells using the same area, the area of the memory die can be reduced, or the data storage capacity of the memory die can be increased.

[0054] In computing system 100, the clock rate of the second bus 160 can be greater than or equal to the clock rate of the third bus 170. The clock rate of a bus can refer to the clock frequency of the bus and / or the clock period of the bus. The clock frequency of the bus and / or the clock period of the bus can define the duration of the signal transmitted through the bus. The higher the clock frequency of the bus and the shorter the clock period of the bus, the shorter the duration of the signal transmitted through the bus. The lower the clock frequency of the bus and the longer the clock period, the longer the duration of the signal transmitted through the bus. The second bus 160 can operate based on the system clock signal CCK, while the third bus 170 can operate based on the memory clock signal MCK. The computing system 100 can set the ratio of the clock rate of the second bus 160 to the clock rate of the third bus 170 in various ways to ensure the operating efficiency of the computing system 100. For example, the ratio of the clock rate of the second bus 160 to the clock rate of the third bus 170 can be selected to be one of 1:1, 2:1, or 4:1. In one embodiment, the system clock signal CCK can have the same frequency as the memory clock signal MCK. In one embodiment, the system clock signal CCK can have twice the frequency of the memory clock signal MCK. In one embodiment, the system clock signal CCK can have four times the frequency of the memory clock signal MCK.

[0055] In computing system 100, the first data bus 161 and the second data bus 171 can be parallel data buses that transmit parallel data. The width of the first data bus 161 can be less than or equal to the width of the second data bus 171. The width of a data bus can define the number of data signals and / or the number of bits of data that can be transmitted through the data bus in one go. In one embodiment, the width of a data bus can also define the number of signal transmission lines carrying the data signals. In one embodiment, the width of the second data bus 171 can be substantially the same as the width of the first data bus 161, and the number of data signals and bits transmitted through the second data bus 171 in one go can be substantially the same as the number of data signals and bits transmitted through the first data bus 161 in one go. In one embodiment, the width of the second data bus 171 can be twice the width of the first data bus 161, and the number of data signals and bits transmitted through the second data bus 171 in one go can be twice the number of data signals and bits transmitted through the first data bus 161 in one go. In one embodiment, the width of the second data bus 171 can be four times the width of the first data bus 161, and the number of data signals and bits transmitted through the second data bus 171 in one go can be four times the number of data signals and bits transmitted through the first data bus 161 in one go. For example, the first data bus 161 can include n signal transmission lines, and n bits of data can be transmitted through the first data bus 161 in one go. Here, n can be a multiple of 2. The second data bus 171 can include m signal transmission lines, and m bits of data can be transmitted through the second data bus 171 in one go. Here, m can be equal to n or can be a multiple of n. The clock rates of the second bus 160 and the third bus 170 and the widths of the first data bus 161 and the second data bus 171 can be changed such that the second data bus 171 can have substantially the same data bandwidth as the first data bus 161.

[0056] In one embodiment, the host 110, the memory controller 120, and the interface circuit 130 may be integrated into a first device, and the memory device 140 may be a second device. The first bus 150 and the second bus 160 may be internal buses, and the third bus 170 may be an external bus. The host 110, the memory controller 120, and the interface circuit 130 may be disposed on a first interposer and / or a first substrate, and the memory device 140 may be disposed on a second interposer and / or a second substrate. In one embodiment, the host 110 and the memory controller 120 may be integrated into a first device, and the interface circuit 130 and the memory device 140 may be integrated into a second device. The first and third buses 150, 170 may be internal buses, and the second bus 160 may be an external bus. The host 110 and the memory controller 120 may be disposed on a first interposer and / or a first substrate, and the interface circuit 130 and the memory device 140 may be disposed on a second interposer and / or a second substrate. In one embodiment, the host 110 may be a first device, and the memory controller 120, the interface circuit 130, and the memory device 140 may be integrated into a second device. The first bus 150 may be an external bus, and the second bus 160 and the third bus 170 may be internal buses. The host 110 may be disposed on a first interposer and / or a first substrate, and the memory controller 120, the interface circuit 130, and the memory device 140 may be disposed on a second interposer and / or a second substrate. In one embodiment, the host 110, the memory controller 120, the interface circuit 130, and the memory device 140 may be integrated into a single device. The first to third buses 150, 160, 170 may be internal buses. The host 110, the memory controller 120, the interface circuit 130, and the memory device 140 may be disposed on the same interposer and / or substrate. In one embodiment, some or all of the host 110, the memory controller 120, the interface circuit 130, and the memory device 140 may be fabricated as dielets.

[0057] Figure 2 is a diagram showing the connection relationship between a memory controller 220, an interface circuit 230, and a memory device 240 according to an embodiment of the present disclosure. The memory controller 220 may be applied as Figure 1 the memory controller 120 shown in Figure 1 and the interface circuit 230 may be applied as Figure 1 the interface circuit 130 shown in Figure 2 and the memory device 240 may be applied as Figure 1The host 110 shown generates or receives various control signals in response to an access request. The various control signals may include an address signal ADD, a bank group signal BG, a bank address signal BK, a command signal CMD, a write data signal WTD, a read data signal RDD, and the like. The address signal ADD may be a signal for accessing rows and columns of a memory cell array of the memory device 240. The bank group signal BG may be an address signal for accessing one of a plurality of bank groups included in the memory device 240. The bank address signal BK may be an address signal for accessing one of a plurality of banks constituting a bank group. The memory controller 220 may be electrically connected to the interface circuit 230 through an address bus 251. The address bus 251 may be a unidirectional bus from the memory controller 220 to the interface circuit 230. The address signal ADD, the bank group signal BG, and the bank address signal BK may be provided from the memory controller 220 to the interface circuit 230 through the address bus 251. The address bus 251 may include a plurality of signal transmission lines, and the address signal ADD, the bank group signal BG, and the bank address signal BK may be transmitted through respective signal transmission lines. The address bus 251 may be included in a portion of the second bus 160 shown in Figure 1 that does not include the first data bus 161.

[0058] The command signal CMD may include multiple signals. By way of non-limiting example, the command signal CMD may include an activation command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE. The activation command signal ACT may be a command signal for instructing the memory device 240 to enter the active mode from the standby mode, or to enter the standby mode from the active mode. The memory device 240 may perform write operations and read operations in the active mode, while the standby mode may be a low power consumption mode of the memory device 240. The row access command signal RAS may be a row address strobe signal and may be a command signal for indicating access to a row of the memory device 240. The column access command signal CAS may be a column address strobe signal and may be a command signal for indicating access to a column of the memory device 240. The write enable signal WE may be a signal for determining whether the operation to be performed by the memory device is a write operation or a read operation. For example, when the column access command signal CAS is enabled and the write enable signal WE has a first logic level, the write enable signal WE may be a command signal for instructing the memory device 240 to perform a write operation. When the column access command signal CAS is enabled and the write enable signal WE has a second logic level, the write enable signal WE may be a command signal for instructing the memory device 240 to perform a read operation. The memory controller 220 may be electrically connected to the interface circuit 230 via a command bus 252. The command bus 252 may be a unidirectional bus from the memory controller 220 to the interface circuit 230. The command signal CMD may be provided from the memory controller 220 to the interface circuit 230 via the command bus 252. The command bus 252 may include multiple signal transmission lines, and the activation command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE may be transmitted via respective signal transmission lines. The command bus 252 may be included in the portion of the second bus 160 as shown in Figure 1 that may not be included in the first data bus 161. Although not shown, the memory controller 220 may also generate control signals, such as a chip select signal, a clock enable signal, and a reset signal, and may provide the control signals to the interface circuit 230 via other signal transmission lines.

[0059] The write data signal WTD can be a data signal provided from the memory controller 220 to the memory device 240 when the memory controller 220 instructs the memory device 240 to perform a write operation, and can be the data signal to be stored in the memory device 240. The memory controller 220 can generate the write data signal WTD based on the data transmitted with the access request from the host 110. The read data signal RDD can be a data signal provided from the memory device 240 to the memory controller 220 when the memory controller 220 instructs the memory device 240 to perform a read operation. The memory controller 220 can generate the data to be transmitted to the host 110 based on the read data signal RDD. The memory controller 220 can be electrically connected to the interface circuit 230 through a write bus 253 and a read bus 254. The write bus 253 can be a unidirectional bus from the memory controller 220 to the interface circuit 230, and the read bus 254 can be a unidirectional bus from the interface circuit 230 to the memory controller 220. The write data signal WTD can be provided from the memory controller 220 to the interface circuit 230 through the write bus 253. The read data signal RDD can be provided from the interface circuit 230 to the memory controller 220 through the read bus 254. The write bus 253 and the read bus 254 can be included in Figure 1 the first data bus 161 shown in. The width of the write bus 253 and the width of the read bus 254 can be substantially the same, and the clock rate of the write bus 253 and the clock rate of the read bus 254 can be substantially the same. In one embodiment, the write bus 253 and the read bus 254 can be integrated into a single data bus, and the integrated data bus can be implemented as a bidirectional bus between the memory controller 220 and the interface circuit 230. The integrated data bus can have a width and a clock rate substantially the same as each of the write bus 253 and the read bus 254.

[0060] In one embodiment, the memory controller 220 can also provide a write select signal WTEN and a read select signal RDEN to the interface circuit 230 and the memory device 240. The write select signal WTEN can be a signal for enabling the buffer for transmitting and receiving signals related to the write operation in the interface circuit 230 and the memory device 240 when the memory controller 220 instructs the memory device 240 to perform a write operation. The read select signal RDEN can be a signal for enabling the buffer for transmitting and receiving signals related to the read operation in the interface circuit 230 and the memory device 240 when the memory controller 220 instructs the memory device 240 to perform a read operation. In one embodiment, the memory controller 220 can not separately provide the write select signal WTEN and the read select signal RDEN to the interface circuit 230, but the interface circuit 230 can generate the write select signal WTEN and the read select signal RDEN based on the command signal CMD.

[0061] The interface circuit 230 can be electrically connected to the memory controller 220, and can receive an address signal ADD, a bank group signal BG, a bank address signal BK, a command signal CMD, a write data signal WTD from the memory controller 220, and can transmit a read data signal RDD to the memory controller 220. The interface circuit 230 can be electrically connected to the memory controller 220 through an address bus 251, a command bus 252, a write bus 253, and a read bus 254. The interface circuit 230 can receive the address signal ADD, the bank group signal BG, and the bank address signal BK from the memory controller 220 through the address bus 251. The interface circuit 230 can receive an activation command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE through the command bus 252. The interface circuit 230 can receive the write data signal WTD from the memory controller 220 through the write bus 253. The interface circuit 230 can transmit the read data signal RDD to the memory controller 220 through the read bus 254. The interface circuit 230 can be electrically connected to the memory device 240, and can provide the signals received from the memory controller 220 to the memory device 240. The interface circuit 230 can buffer and convert the signals received from the memory controller 220 to generate signals suitable for use in the memory device 240 (e.g., serialization or deserialization).

[0062] The interface circuit 230 can provide the bank group signal BG, the bank address signal BK, a row address signal RADD, a column address signal CADD, the command signal CMD, and a memory data signal DQ to the memory device 240. The interface circuit 230 can buffer the bank group signal BG and the bank address signal BK received from the memory controller 220. The interface circuit 230 can generate the row address signal RADD and the column address signal CADD based on the address signal ADD and the command signal CMD received from the memory controller 220. The interface circuit 230 can be electrically connected to the memory device 240 through an address bus 261, and can provide the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD to the memory device 240 through the address bus 261. The address bus 261 can be a unidirectional bus from the interface circuit 230 to the memory device 240. The address bus 261 can include a plurality of signal transmission lines, and the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD can be transmitted through respective signal transmission lines. The address bus 261 can be included as Figure 1 a part of the third bus 170 shown in, but not as a part of the second data bus 171.

[0063] The interface circuit 230 may buffer the command signal CMD received from the memory controller 220. The interface circuit 230 may be electrically connected to the memory device 240 via the command bus 262, and may provide an activation command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE to the memory device 240 via the command bus 262. The command bus 262 may be a unidirectional bus from the interface circuit 230 to the memory device 240. The command bus 262 may include a plurality of signal transmission lines, and the activation command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE may be transmitted via respective signal transmission lines. The command bus 262 may be included as Figure 1 a part of the third bus 170 shown in FIG. other than the second data bus 171.

[0064] The interface circuit 230 may generate a memory data signal DQ based on the write data signal WTD received from the memory controller 220, and may generate a read data signal RDD based on the memory data signal DQ received from the memory device 240. The interface circuit 230 may be electrically connected to the memory device 240 via the memory data bus 263, and may transmit the memory data signal DQ to the memory device 240 or receive the memory data signal DQ transmitted from the memory device 240 via the memory data bus 263. The memory data bus 263 may be a bidirectional bus between the interface circuit 230 and the memory device 240. The width of the memory data bus 263 may be greater than or equal to the width of the write bus 253 or the read bus 254, and the clock rate of the memory data bus 263 may be less than or equal to the clock rate of the write bus 253 or the read bus 254.

[0065] The interface circuit 230 may include an address control circuit 231, a command buffer 232, and a data input / output circuit 233. The address control circuit 231 may receive a bank group signal BG, a bank address signal BK, and an address signal ADD from the memory controller 220. The address control circuit 231 may buffer the bank group signal BG and the bank address signal BK, and may provide the buffered bank group signal BG and the buffered bank address signal BK to the memory device 240. The address control circuit 231 may generate a row address signal RADD and a column address signal CADD based on the address signal ADD and a command signal CMD. The address control circuit 231 may generate the row address signal RADD based on the address signal ADD and a row access command signal RAS, and may generate the column address signal CADD based on the address signal ADD and a column access command signal CAS. For example, the address control circuit 231 may generate the address signal ADD as the row address signal RADD when the row access command signal RAS is enabled. The address control circuit 231 may generate the address signal ADD as the column address signal CADD when the column access command signal CAS is enabled. The address control circuit 231 may transmit the row address signal RADD and the column address signal CADD to the memory device 240 through an address bus 261.

[0066] The command buffer 232 may be electrically connected to the command bus 252 to receive a command signal CMD transmitted from the memory controller 220. The command buffer 232 may buffer the command signal CMD, and may transmit the buffered command signal CMD to the memory device 240 via the command bus 262. The command buffer 232 may buffer an active command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE, respectively, and may provide the buffered active command signal ACT, the buffered row access command signal RAS, the buffered column access command signal CAS, and the buffered write enable signal WE to the memory device 240. The command buffer 232 may provide the buffered row access command signal RAS and the buffered column access command signal CAS to the address control circuit 231. The address control circuit 231 may generate a row address signal RADD and a column address signal CADD based on an address signal ADD and the row access command signal RAS and the column access command signal CAS received from the command buffer 232. In one embodiment, the command buffer 232 may be modified to generate a write select signal WTEN and a read select signal RDEN based on the write enable signal WE. When the column access command signal CAS is enabled and the write enable signal WE has a first logic level, i.e., when a write operation is performed, the command buffer 232 may enable the write select signal WTEN and disable the read select signal RDEN. When the column access command signal CAS is enabled and the write enable signal WE has a second logic level, i.e., when a read operation is performed, the command buffer 232 may enable the read select signal RDEN and disable the write select signal WTEN. The command buffer 232 may provide the write select signal WTEN and the read select signal RDEN to the data input / output circuit 233 and the memory device 240.

[0067] The data input / output circuit 233 can be electrically connected to the memory controller 220 through the write bus 253 and the read bus 254, and can be electrically connected to the memory device 240 through the memory data bus 263. The data input / output circuit 233 can receive a write data signal WTD from the memory controller 220 through the write bus 253, and can generate a memory data signal DQ based on the write data signal WTD. The data input / output circuit 233 can transmit the memory data signal DQ to the memory device 240 through the memory data bus 263. The data input / output circuit 233 can receive the memory data signal DQ from the memory device 240 through the memory data bus 263, and can generate a read data signal RDD based on the memory data signal DQ. The data input / output circuit 233 can transmit the read data signal RDD to the memory controller 220 through the read bus 254. The data input / output circuit 233 can selectively electrically connect the memory data bus 263 to one of the write bus 253 and the read bus 254 based on the write enable signal WE of the command signal CMD (i.e., based on whether the signal indicates a write operation or a read operation). The data input / output circuit 233 can receive a write select signal WTEN and a read select signal RDEN transmitted from the memory controller 220. In one embodiment, the data input / output circuit 233 can receive the write select signal WTEN and the read select signal RDEN from the command buffer 232. The data input / output circuit 233 can electrically connect the write bus 253 to the memory data bus 263 based on the write select signal WTEN, and can electrically connect the read bus 254 to the memory data bus 263 based on the read select signal RDEN. When the write select signal WTEN is enabled, the data input / output circuit 233 can buffer the write data signal WTD, and can output the buffered write data signal WTD as the memory data signal DQ. When the read select signal RDEN is enabled, the data input / output circuit 233 can receive the memory data signal DQ, buffer the memory data signal DQ, and output the buffered memory data signal DQ as the read data signal RDD. In one embodiment, the data input / output circuit 233 can convert the data rate of the write data signal WTD to generate the memory data signal DQ. For example, the data input / output circuit 233 can reduce the data rate of the write data signal WTD to generate the memory data signal DQ. The data input / output circuit 233 can convert the data rate of the memory data signal DQ to generate the read data signal RDD. For example, the data input / output circuit 233 can increase the data rate of the memory data signal DQ to generate the read data signal RDD. The data input / output circuit 233 can generate a data strobe signal DQS, transmit the data strobe signal DQS to the memory device 240, and transmit the memory data signal DQ to the memory device 240 synchronously with the data strobe signal DQS.The data input / output circuit 233 may receive a data strobe signal DQS transmitted from the memory device 240, and may receive a memory data signal DQ transmitted from the memory device 240 in synchronization with the data strobe signal DQS. The data strobe signal DQS transmitted from the data input / output circuit 233 to the memory device 240 may be a write data strobe signal WDQS. The data strobe signal DQS received by the data input / output circuit 233 from the memory device 240 may be a read data strobe signal RDQS. The data input / output circuit 233 may transmit the write data strobe signal WDQS to the memory device 240 through the strobe bus 264, and may receive the read data strobe signal RDQS transmitted from the memory device 240 through the strobe bus 264. The data input / output circuit 233 may generate the write data strobe signal WDQS based on the memory clock signal MCK, which will be described later.

[0068] The memory controller 220 and the interface circuit 230 may receive a system clock signal CCK, and may operate in synchronization with the system clock signal CCK. Figure 1 The host 110 shown in may generate a system clock signal CCK, and may provide the system clock signal CCK to the memory controller 220 and the interface circuit 230. In one embodiment, the memory controller 220 may generate a system clock signal CCK, and the memory controller 220 may provide the system clock signal CCK to the interface circuit 230. The memory controller 220 may provide a write data signal WTD to the interface circuit 230 in synchronization with the system clock signal CCK, and may receive a read data signal RDD in synchronization with the system clock signal CCK. The memory controller 220 may further include a clock frequency control circuit 221. The clock frequency control circuit 221 may set and / or change the operating speeds of the interface circuit 230 and the memory device 240. The clock frequency control circuit 221 may receive a frequency control signal FS from the host 110. The clock frequency control circuit 221 may generate a clock frequency setting signal CFS based on the frequency control signal FS. The clock frequency setting signal CFS may include information for setting the clock rate of the bus electrically connecting the memory controller 220 and the interface circuit 230 and the clock rate of the bus electrically connecting the interface circuit 230 and the memory device 240.

[0069] The interface circuit 230 may further include a clock control circuit 234. The clock control circuit 234 may generate an interface clock signal ICCK and a memory clock signal MCK based on a system clock signal CCK and a clock frequency setting signal CFS. The clock control circuit 234 may generate the interface clock signal ICCK by buffering the system clock signal CCK, and the interface clock signal ICCK may have a frequency substantially the same as that of the system clock signal CCK. The clock control circuit 234 may selectively delay the system clock signal CCK in consideration of a delay occurring within the interface circuit 230 to generate the interface clock signal ICCK. The clock control circuit 234 may change the frequency of the memory clock signal MCK based on the clock frequency setting signal CFS. For example, the memory clock signal MCK generated by the clock control circuit 234 based on the clock frequency setting signal CFS may have a frequency substantially the same as that of the interface clock signal ICCK, or may have a frequency that is 1 / 2 or 1 / 4 of the interface clock signal ICCK. The clock control circuit 234 may change the frequency of the memory clock signal MCK to set a clock rate ratio of a write bus 253 and a read bus 254 to a memory data bus 263. The interface circuit 230 may be electrically connected to a memory device 240 through a memory clock bus 265, and the clock control circuit 234 may transmit the memory clock signal MCK to the memory device 240 through the memory clock bus 265. The clock control circuit 234 may provide the memory clock signal MCK together with a complementary signal, or may provide the memory clock signal MCK and the complementary signal to the memory device 240 as a differential clock signal.

[0070] The data input / output circuit 233 may also receive a clock frequency setting signal CFS, an interface clock signal ICCK, and a memory clock signal MCK. The data input / output circuit 233 may perform a data conversion operation based on the clock frequency setting signal CFS. When it is determined according to the clock frequency setting signal CFS that the frequencies of the interface clock signal ICCK and the memory clock signal MCK are substantially the same, the data input / output circuit 233 may buffer the write data signal WTD to generate a memory data signal DQ, and may buffer the memory data signal DQ to generate a read data signal RDD. When it is determined according to the clock frequency setting signal CFS that the frequency of the interface clock signal ICCK is higher than that of the memory clock signal MCK, the data input / output circuit 233 may perform a deserialization operation and a serialization operation, and may perform operations similar to SerDes. The data input / output circuit 233 may deserialize the write data signal WTD to generate a memory data signal DQ, and may serialize the memory data signal DQ to generate a read data signal RDD. For example, the data input / output circuit 233 may latch the write data signal WTD based on the interface clock signal ICCK, and transfer the latched write data signal WTD as the memory data signal DQ to the memory device 240 synchronously with the write data strobe signal WDQS. The data input / output circuit 233 may latch the memory data signal DQ based on the read data strobe signal RDQS, and transfer the latched memory data signal DQ as the memory data signal DQ to the memory controller 220 synchronously with the interface clock signal ICCK.

[0071] The interface circuit 230 may also include a training circuit 235. When the computing system is initialized or upon request of the host 110, the memory controller 220 may provide a training signal TRS to the interface circuit 230. The training circuit 235 enables a training operation to be performed on the internal circuits provided in the interface circuit 230 based on the training signal TRS. The internal circuits that perform the training operation will be described in more detail below.

[0072] Figure 3 is a block diagram showing Figure 2 the configuration of the address control circuit 231 shown in. Refer to Figure 2 and Figure 3 , the address control circuit 231 may include a bank address buffer 310, a row address generation circuit 320, and a column address generation circuit 330. The bank address buffer 310 may buffer the bank group signal BG and the bank address signal BK received from the memory controller 220 to generate the bank group signal BG and the bank address signal BK to be transferred to the memory device 240. In Figure 3In this case, the bank group signal and the bank address signal input from the memory controller 220 to the bank address buffer 310 are represented as BG(in) and BK(in), respectively, while the bank group signal and the bank address signal output from the bank address buffer 310 to the memory device 240 are represented as BG(out) and BK(out), respectively. The bank address buffer 310 can perform a general buffering operation without changing the characteristics of the bank group signal BG and the bank address signal BK.

[0073] The row address generation circuit 320 can receive the address signal ADD from the memory controller 220 and can receive the row access command signal RAS from the command buffer 232. When the row access command signal RAS is enabled, the row address generation circuit 320 can output the address signal ADD as the row address signal RADD. When the row access command signal RAS is disabled, the row address generation circuit 320 can refrain from outputting the address signal ADD as the row address signal RADD. The row address generation circuit 320 can transfer the row address signal RADD to the memory device 240.

[0074] The column address generation circuit 330 can receive the address signal ADD from the memory controller 220 and can receive the column access command signal CAS from the command buffer 232. When the column access command signal CAS is enabled, the column address generation circuit 330 can output the address signal ADD as the column address signal CADD. When the column access command signal CAS is disabled, the column address generation circuit 330 can refrain from outputting the address signal ADD as the column address signal CADD. The column address generation circuit 330 can transfer the column address signal CADD to the memory device 240.

[0075] Figure 4 is a diagram showing Figure 2 the configuration of the data input / output circuit 233 shown in Figure 2 and Figure 4 With reference to

[0076] The write control circuit 410 may include a write strobe circuit 411, a strobe transmitter 412 (TX2), a write pipeline circuit 413, and a data transmitter 414 (TX1). The write strobe circuit 411 may receive a memory clock signal MCK and generate a pre-write data strobe signal WDQSP based on the memory clock signal MCK. The write strobe circuit 411 may buffer or divide the memory clock signal MCK to generate the pre-write data strobe signal WDQSP. In one embodiment, the write strobe circuit 411 may buffer the memory clock signal MCK to generate a pre-write data strobe signal WDQSP including differential clock signals having a 180-degree phase difference. In one embodiment, the write strobe circuit 411 may divide the memory clock signal MCK to generate a pre-write data strobe signal WDQSP including poly-phase clock signals having a 90-degree phase difference. The write strobe circuit 411 may selectively delay the interface clock signal ICCK to synchronize the memory data signal DQ and the pre-write data strobe signal WDQSP, and then generate the pre-write data strobe signal WDQSP based on the delayed interface clock signal ICCK. The strobe transmitter 412 may be electrically connected to the write strobe circuit 411 to receive the pre-write data strobe signal WDQSP. The strobe transmitter 412 may receive a write select signal WTEN and may be activated when the write select signal WTEN is enabled. The strobe transmitter 412 may transmit a write strobe signal WDQS to the memory device 240 based on the pre-write data strobe signal WDQSP. The write strobe signal WDQS may be a signal substantially the same as the pre-write data strobe signal WDQSP.

[0077] The write pipeline circuit 413 can receive a write data signal WTD, an interface clock signal ICCK, and a pre-write data strobe signal WDQSP. The write pipeline circuit 413 can sequentially store the write data signal WTD synchronously with the interface clock signal ICCK. The write pipeline circuit 413 can output the sequentially stored write data signal WTD as a memory data signal DQ synchronously with the pre-write data strobe signal WDQSP. The write pipeline circuit 413 can be implemented by a deserialiser that converts the duration ratio of the write data signal WTD and the memory data signal DQ to 1:1, 1:2, or 1:4 according to the frequency ratio of the interface clock signal ICCK to the pre-write data strobe signal WDQSP and / or the write data strobe signal WDQS. The write pipeline circuit 413 can also receive a clock frequency setting signal CFS. Based on the clock frequency setting signal CFS, the write pipeline circuit 413 can determine the frequency ratio of the interface clock signal ICCK to the write data strobe signal WDQS, and can change the duration ratio of the write data signal WTD to the memory data signal DQ. The data transmitter 414 can be electrically connected to the write pipeline circuit 413 to receive the output signal of the write pipeline circuit 413. The data transmitter 414 can receive a write select signal WTEN, and can be activated when the write select signal WTEN is enabled. The data transmitter 414 can drive the memory data bus 263 based on the output signal of the write pipeline circuit 413 to transmit the memory data signal DQ to the memory device 240.

[0078] The read control circuit 420 can receive a read select signal RDEN, a memory data signal DQ, an interface clock signal ICCK, and a read data strobe signal RDQS, and can generate a read data signal RDD. The read control circuit 420 can be selectively activated based on the read select signal RDEN. The read control circuit 420 can latch the memory data signal DQ based on the read data strobe signal RDQS, and can output the latched memory data signal DQ as the read data signal RDD based on the interface clock signal ICCK.

[0079] The read control circuit 420 may include a strobe receiver 421 (RX1), a read strobe circuit 422, a data receiver 423 (RX2), and a read pipeline circuit 424. The strobe receiver 421 may receive a read select signal RDEN and a read data strobe signal RDQS. The strobe receiver 421 may be activated when the read select signal RDEN is enabled. The strobe receiver 421 may receive the read data strobe signal RDQS from the memory device 240. The read data strobe signal RDQS may include differential clock signals having a 180-degree phase difference, or may include polyphase clock signals having a 90-degree phase difference. The read strobe circuit 422 may be electrically connected to the strobe receiver 421 to receive the output signal of the strobe receiver 421, and may buffer the output signal of the strobe receiver 421. The read strobe circuit 422 may selectively delay the output signal of the strobe receiver 421 to match the delay time of the memory data signal DQ with the delay time of the read data strobe signal RDQS. The read strobe circuit 422 may generate a delayed read data strobe signal RDQSD from the output signal of the strobe receiver 421. The delayed read data strobe signal RDQSD may have substantially the same frequency characteristics as the read strobe signal RDQS.

[0080] The data receiver 423 may receive a read select signal RDEN and a memory data signal DQ. The data receiver 423 may be selectively activated based on the read select signal RDEN. The data receiver 423 may receive the memory data signal DQ using a reference voltage VREF. The reference voltage VREF may have an appropriate voltage level based on the voltage level range over which the memory data signal DQ swings. For example, when the memory data signal DQ is an NRZ (non-return-to-zero) signal, the reference voltage VREF may have a voltage level corresponding to the middle of the voltage level range over which the memory data signal DQ swings. The read pipeline circuit 424 may receive the memory data signal DQ, a delayed read data strobe signal RDQSD, and an interface clock signal ICCK. The read pipeline circuit 424 may sequentially store the memory data signal DQ synchronously with the delayed read data strobe signal RDQSD. The read pipeline circuit 424 may output the sequentially stored memory data signal DQ as a read data signal RDD synchronously with the interface clock signal ICCK. The read pipeline circuit 424 may be implemented with a serializer that converts the duration ratio of the memory data signal DQ to the read data signal RDD to 1:1, 2:1, or 4:1 according to the frequency ratio of the delayed read data strobe signal RDQSD and / or the read data strobe signal RDQS to the interface clock signal ICCK. The read pipeline circuit 424 may also receive a clock frequency setting signal CFS. The read pipeline circuit 424 may determine the frequency ratio of the interface clock signal ICCK to the read strobe signal RDQS based on the clock frequency setting signal CFS, and may change the duration ratio of the memory data signal DQ to the read data signal RDD.

[0081] Figure 5 is a diagram showing Figure 2 the configuration of the clock control circuit 234 shown in. Refer to Figure 5, the clock control circuit 234 may include a clock delay circuit 510, a clock buffer circuit 520, a first clock frequency division circuit 530, a second clock frequency division circuit 540, and a clock selection circuit 550. The clock delay circuit 510 may receive a system clock signal CCK and may buffer the system clock signal CCK. The system clock signal CCK may be selectively delayed to generate an interface clock signal pair ICCK, ICCKB. The clock delay circuit 510 may generate the interface clock signal pair ICCK, ICCKB without substantially delaying the system clock signal CCK (except for the delay caused by the buffering operation). (Except for the delay time caused by the buffering operation) The clock delay circuit 510 may also delay the system clock signal CCK by an arbitrary delay time to generate an interface clock signal pair ICCK, ICCKB having a lagging phase with respect to the system clock signal CCK. The clock delay circuit 510 may include digital and / or analog variable delay lines, and the delay time of the clock delay circuit 510 may be changed based on any digital and / or analog control signal.

[0082] The clock buffer circuit 520 may receive the system clock signal CCK and may buffer the system clock signal CCK to generate a first clock signal pair CCK11. The first clock signal pair CCK11 may have substantially the same frequency as the system clock signal CCK. The first clock frequency division circuit 530 may receive the system clock signal CCK and may divide the frequency of the system clock signal CCK by two to generate a second clock signal pair CCK21. The frequency of the second clock signal pair CCK21 may be 1 / 2 of the frequency of the system clock signal CCK. The second clock frequency division circuit 540 may divide the frequency of the second clock signal pair CCK21 by two to generate a third clock signal pair CCK41. The frequency of the third clock signal pair CCK41 may be 1 / 2 of the frequency of the second clock signal pair CCK21 and may be 1 / 4 of the frequency of the system clock signal CCK.

[0083] The clock selection circuit 550 can receive the first clock signal pair CCK11, the second clock signal pair CCK21, the third clock signal pair CCK41, and the clock frequency setting signal CFS. The clock selection circuit 550 can output one of the first to third clock signal pairs CCK11, CCK21, CCK41 as the memory clock signal pair MCK, MCKB based on the clock frequency setting signal CFS. The clock frequency setting signal CFS can be a digital signal having at least two bits. When the clock frequency setting signal CFS has a first logical value, the clock selection circuit 550 can output the first clock signal pair CCK11 as the memory clock signal pair MCK, MCKB, and the memory clock signal pair MCK, MCKB includes a memory clock signal MCK and a complementary memory clock signal MCKB whose logic levels are inverted from each other. When the clock frequency setting signal CFS has a second logical value, the clock selection circuit 550 can output the second clock signal pair CCK21 as the memory clock signal pair MCK, MCKB. When the clock frequency setting signal CFS has a third logical value, the clock selection circuit 550 can output the third clock signal pair CCK41 as the memory clock signal pair MCK, MCKB. The clock selection circuit 550 can use the clock frequency setting signal CFS as a control signal and be implemented with a 3-to-1 multiplexer. Referring again to Figure 2 , the training circuit 235 can perform a training operation on the Figures 3 to 5 components shown. For example, based on the training signal TRS, the training circuit 235 can adjust the drive strength and / or delay time of the bank address buffer 310, data transmitter 414, write strobe circuit 411, strobe transmitter 412, strobe receiver 421, read strobe circuit 422, data receiver 423, clock delay circuit 510, clock buffer circuit 520, etc.

[0084] Figure 6 FIG. is a diagram showing the configuration of a memory die 600 according to an embodiment of the present disclosure. Figure 2 The memory device 240 shown in Figure 2 and Figure 6, the memory die 600 can receive bank group signals BG, bank address signals BK, row address signals RADD, column address signals CADD, command signals CMD, memory clock signal pairs MCK, MCKB, and memory data signals DQ from the interface circuit 230. The memory die 600 can include a plurality of bank groups MBG1 to MBG4, a first address receiver 641, a second address receiver 642, a third address receiver 643, a command receiver 644, a clock receiver 645, a command control circuit 650, an input / output drive circuit 660, and an input / output buffer circuit 670. The memory die 600 can include first to fourth bank groups MBG1 to MBG4. Although Figure 6 it is shown that the number of bank groups included in the memory die 600 is four, the number of bank groups included in the memory die 600 can be two, eight, or more. Each of the first to fourth bank groups can include a plurality of banks BANK0, BANK1, BANK2, ……, BANK7. For example, the first to fourth bank groups MBG1 to MBG4 can each include two banks. The first bank group MBG1 can include a first bank BANK0 and a second bank BANK1, the second bank group MBG2 can include a third bank BANK2 and a fourth bank BANK3, the third bank group MBG3 can include a fifth bank BANK4 and a sixth bank BANK5, and the fourth bank group MBG4 can include a seventh bank BANK6 and an eighth bank BANK7. In Figure 6 this case, each bank group includes two banks, but the number of banks included in each bank group can be four or more. Each of the first to eighth banks BANK0, BANK2, BANK3, ……, BANK7 can include a memory cell array 610, a row decoding circuit 620, and a column decoding circuit 630. The same number of memory cell arrays 610, row decoding circuits 620, and column decoding circuits 630 as the number of banks can be provided. A plurality of row lines WL can be provided in the row direction of each memory cell array, a plurality of column lines BL can be provided in the column direction of each memory cell array, and a plurality of memory cells can be electrically connected at the intersections of the plurality of row lines and the plurality of column lines.

[0085] Each of the row decoding circuits 620 may receive an internal bank group signal IBG, an internal bank address signal IBK, an internal row address signal IRADD, and an activation signal ACTS. When the activation signal ACTS is enabled, each of the row decoding circuits 620 may select and / or enable row lines of the memory cell arrays 610 provided in the first to eighth banks. Each of the row decoding circuits 620 may decode the internal bank group signal IBG to select and / or access at least one bank group among the plurality of bank groups MBG1 to MBG4. Each of the row decoding circuits 620 may decode the internal bank address signal IBK to select and / or access at least one bank among the plurality of banks in the selected bank group. Each of the row decoding circuits 620 may select and / or enable at least one of the plurality of row lines provided in each memory cell array 610 based on the internal row address signal IRADD. Each of the column decoding circuits 630 may receive an internal column address signal ICADD. Each of the column decoding circuits 630 may decode the internal column address signal ICADD to select and / or access at least one of the plurality of column lines provided in each memory cell array 610.

[0086] The first address receiver 641 can receive the bank group signal BG and the bank address signal BK transmitted from the interface circuit 230 via the address bus 261. The first address receiver 641 can receive the bank group signal BG and the bank address signal BK to generate an internal bank group signal IBG and an internal bank address signal IBK. The first address receiver 641 can generate an internal bank group signal IBG and an internal bank address signal IBK having substantially the same characteristics as the bank group signal BG and the bank address signal BK without changing the characteristics of the bank group signal IBG and the bank address signal IBK. The first address receiver 641 can provide the internal bank group signal IBG and the internal bank address signal IBK to the corresponding row decoding circuit 620. The second address receiver 642 can receive the row address signal RADD transmitted from the interface circuit 230 via the address bus 261. The second address receiver 642 can receive the row address signal RADD to generate an internal row address signal IRADD. The second address receiver 642 can generate an internal row address signal IRADD having substantially the same characteristics as the row address signal RADD without changing the characteristics of the row address signal RADD. The second address receiver 642 can provide the internal row address signal IRADD to the corresponding row decoding circuit 620. The third address receiver 643 can receive the column address signal CADD transmitted from the interface circuit 230 via the address bus 261. The third address receiver 643 can receive the column address signal CADD to generate an internal column address signal ICADD. The third address receiver 643 can generate an internal column address signal ICADD having substantially the same characteristics as the column address signal CADD without changing the characteristics of the column address signal CADD. The third address receiver 643 can provide the internal column address signal ICADD to the corresponding column decoding circuit 630. The command receiver 644 can receive the command signal CMD transmitted from the interface circuit 230 via the command bus 262. The command receiver 644 can receive the command signal CMD to generate an internal command signal ICMD. The internal command signal ICMD can include an internal activation command signal IACT, an internal row access command signal IRAS, an internal column access command signal ICAS, and an internal write enable signal IWE. The command receiver 644 can provide the internal command signal ICMD to the command control circuit 650. The clock receiver 645 can receive the memory clock signal pair MCK, MCKB transmitted from the interface circuit 230 via the memory clock bus 265. The clock receiver 645 can receive the memory clock signal pair MCK, MCKB to generate an internal memory clock signal pair IMCK, IMCKB.

[0087] The command control circuit 650 may receive an internal command signal ICMD and an internal memory clock signal pair IMCK, IMCKB. The command control circuit 650 may latch the internal command signal ICMD synchronously with the internal memory clock signal pair IMCK, IMCKB. The command control circuit 650 may generate a conversion command signal CCMD based on the internal command signal ICMD. The command control circuit 650 may combine the logic levels of at least one internal command signal ICMD to generate the conversion command signal CCMD. The conversion command signal CCMD may at least include an activation signal ACTS, a write signal WTS, and a read signal RDS. The activation signal ACTS may be a signal for an activation operation of the instruction memory die 600, and the activation operation may be an operation of selecting and / or enabling the row lines of the memory cell array 610. The write signal WTS may be a signal for a write operation of the instruction memory die 600, and the write operation may be an operation of storing the memory data signal DQ received through the memory data bus 263 into the memory cell array 610 by the memory die 600. The read signal RDS may be a signal for a read operation of the instruction memory die 600, and the read operation may be an operation of outputting the data stored in the memory cell array 610 as the memory data signal DQ through the memory data bus 263 by the memory die 600. The command control circuit 650 may delay the internal command signal ICMD by a time corresponding to a latency to generate the conversion command signal CCMD. The latency may refer to the delay time from when the memory die 600 receives the command signal CMD until the memory die 600 actually executes the operation indicated by the command signal CMD. For example, the latency may include a CAS latency, a write latency, or a read latency, etc. The latency may be defined as an integer of 1 or more, and the delay of the command control circuit 650 according to the latency may be set to an integer multiple of the clock period of the memory clock signal pair MCK, MCKB. The command control circuit 650 may provide the conversion command signal CCMD to the internal circuit of the memory die 600. The command control circuit 650 may provide the activation signal ACTS to the corresponding row decoding circuit 620. The command control circuit 650 may provide the write signal WTS and the read signal RDS to the input / output drive circuit 660.

[0088] The input / output drive circuit 660 can be electrically connected to a plurality of column lines of the corresponding memory cell array 610 through each column decoding circuit 630. The input / output drive circuit 660 can receive a write signal WTS and a read signal RDS. Based on the write signal WTS, the input / output drive circuit 660 can supply internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 (where m is an integer of 4 or greater) transmitted through the global data line GIO to each memory cell array 610 through each column decoding circuit 630, and the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 can be stored in the memory cells electrically connected to the column lines accessed by each column decoding circuit 630. The input / output drive circuit 660 can include a write drive circuit for supplying the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 to the corresponding memory cell array 610 based on the write signal WTS. The input / output drive circuit 660 can receive data signals output from each memory cell array 610 based on the read signal RDS. The input / output drive circuit 660 can generate internal data signals IDQ0, IDQ1, IDQ2, ..., IDQm-1 by receiving output data signals output from the corresponding memory cell array 610 via the corresponding column decoding circuit 630. The input / output drive circuit 660 can output the internal data signals IDQ0, IDQ1, IDQ2, ..., IDQm-1 through the global data line GIO. The input / output drive circuit 660 can include a read drive circuit for supplying the data signals output from the corresponding memory cell array 610 to the global data line GIO based on the read signal RDS. The input / output drive circuit 660 can operate based on the internal memory clock signals IMCK, IMCKB. The memory die 600 can further include an internal clock generation circuit 680. The internal clock generation circuit 680 can receive the internal memory clock signals IMCK, IMCKB, and can delay the internal memory clock signals IMCK, IMCKB to generate delayed memory clock signals IMCKD, IMCKDB. The internal clock generation circuit 680 can supply the delayed memory clock signals IMCKD, IMCKDB to the input / output drive circuit 660, and the input / output drive circuit 660 can receive the internal data signals IDQ0, IDQ1, IDQ2, ..., IDQm-1 synchronously with the delayed memory clock signals IMCKD, IMCKDB, and can output the internal data signals IDQ0, IDQ1, IDQ2, ..., IDQm-1 synchronously with the delayed memory clock signals IMCKD, IMCKDB.

[0089] The input / output buffer circuit 670 can be electrically connected to the interface circuit 230 via the memory data bus 263, and can be electrically connected to the input / output drive circuit 660 via the global data line GIO. During a write operation, the input / output buffer circuit 670 can generate internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 based on the memory data signals DQ0, DQ1, DQ2, …, DQm-1 transmitted from the interface circuit 230 via the memory data bus 263, and output the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 to the global data line GIO. During a read operation, the input / output buffer circuit 670 receives the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 transmitted from the input / output drive circuit 660 via the global data line GIO, generates the memory data signals DQ0, DQ1, DQ2, …, DQm-1 based on the internal data signals IDQ0, IDQ1, DQ2, …, DQm-1, and transmits the memory data signals DQ0, DQ1, DQ2, …, DQm-1 to the interface circuit 230 via the memory data bus 263. The input / output buffer circuit 670 can buffer the memory data signals DQ0, DQ1, DQ2, …, DQm-1 during a write operation to generate the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1, and buffer the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 during a read operation to generate the memory data signals DQ0, DQ1, DQ2, …, DQm-1. The internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the memory data signals DQ0, DQ1, DQ2, …, DQm-1 can be data signals of substantially the same type or the same characteristics, and the type or characteristics of the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the memory data signals DQ0, DQ1, DQ2, …, DQm-1 can not be changed by the input / output buffer circuit 670.

[0090] For example, the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the memory data signals DQ0, DQ1, DQ2, …, DQm-1 can be parallel data signals having the same number of bits. The number of signal transmission lines included in the global data line GIO can be substantially the same as the number of signal transmission lines included in the memory data bus 263. The width of the data signal stored in each memory cell array 610 through a single write operation can be substantially the same as the width of the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the width of the memory data signals DQ0, DQ1, DQ2, …, DQm-1. The width of the data signal output from each memory cell array 610 during a single read operation can be substantially the same as the width of the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the width of the memory data signals DQ0, DQ1, DQ2, …, DQm-1. The width of the data signal can represent the number of data signals and / or the number of bits of the data signal. The input / output buffer circuit 670 can receive the write data strobe signal WDQS and generate the read data strobe signal RDQS. During a write operation, the input / output buffer circuit 670 can receive the write data strobe signal WDQS from Figure 2 the interface circuit 230 shown, and can receive the memory data signals DQ0, DQ1, DQ2, ..., DQm-1 transmitted from the interface circuit 230 synchronously with the write data strobe signal WDQS. During a read operation, the input / output buffer circuit 670 can generate the read data strobe signal RDQS based on the write data strobe signal WDQS. The input / output buffer circuit 670 can output the memory data signals DQ0, DQ1, DQ2, ..., DQm-1 to the interface circuit 230 synchronously with the read data strobe signal RDQS. The input / output buffer circuit 670 can output the read data strobe signal RDQS to the interface circuit 230 together with the memory data signals DQ0, DQ1, DQ2, …, DQm-1. The input / output buffer circuit 670 can also receive the write select signal WTEN and the read select signal RDEN. The input / output buffer circuit 670 can activate the write path of the input / output buffer circuit 670 based on the write select signal WTEN, and can activate the read path of the input / output buffer circuit 670 based on the read select signal RDEN. For example, the input / output buffer circuit 670 can include a transmitter for outputting the memory data signals DQ0, DQ1, DQ2, …, DQm-1 to the interface circuit 230 and a receiver for receiving the memory data signals DQ0, DQ1, DQ2, …, DQm-1 transmitted from the interface circuit 230. The transmitter of the input / output buffer circuit 670 can be activated based on the write select signal WTEN. The receiver of the input / output buffer circuit 670 can be activated based on the read select signal RDEN.

[0091] Since the memory die 600 receives the row address signal RADD and the column address signal CADD from the interface circuit 230, the memory die 600 may not have a circuit for converting the address signal ADD into the row address signal RADD and the column address signal CADD according to the command signal CMD and a circuit for latching the converted address signal. For example, the input / output buffer circuit 670 may not include a SerDes for serializing the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 or for deserializing the memory data signals DQ0, DQ1, DQ2, …, DQm-1. With a large number of detachable circuits, the memory die 600 can have a larger data storage capacity compared to a conventional memory die, and the memory die 600 can be smaller than a conventional memory die and maintain the same data storage capacity. In addition, when the input / output buffer circuit 670 does not perform serialization and deserialization operations on the data signals, the timing delay of the command control circuit 650, that is, the time delay of the memory die 600 and the memory device including the memory die 600, is very short compared to a conventional memory die and memory device. Therefore, compared to a conventional device, the memory die 600 can perform write operations and read operations on more data signals within a shorter time period.

[0092] Figure 7 FIG. is a diagram showing the configuration of a computing system 700 according to an embodiment of the present disclosure. Refer to Figure 7 , the computing system 700 may include a host 710, a memory controller 720, a first interface circuit 731, a second interface circuit 732, a first memory device 741, and a second memory device 742. The host 710 may be electrically connected to the memory controller 720 through a host bus 750. The memory controller 720 may be electrically connected to the first interface circuit 731 through a first controller bus 761, and may be electrically connected to the second interface circuit 732 through a second controller bus 762. The first interface circuit 731 may be electrically connected to the first memory device 741 through a first memory bus 771. The second interface circuit 732 may be electrically connected to the second memory device 742 through a second memory bus 772. The host 710 may have a configuration substantially the same as that of the host 110 shown in Figure 1 and may perform substantially the same functions. The memory controller 720 may have the same configuration as that of Figure 1The memory controller 720 has substantially the same configuration and performs substantially the same functions as the memory controller 120 shown. However, the memory controller 720 can be electrically connected to a first controller bus 761 and a second controller bus 762 to enable data communication with multiple memory devices. The host 710 can access either the first memory device 741 or the second memory device 742 through the memory controller 720 and the first controller bus 761 and the second controller bus 762, or can access both the first memory device 741 and the second memory device 742 simultaneously. The host 710 can independently generate an access request for the first memory device 741 and an access request for the second memory device 742 to access the first memory device 741 and the second memory device 742 separately or simultaneously. The memory controller 720 can independently generate a control signal for accessing the first memory device 741 and a control signal for accessing the second memory device 742 to access the first memory device 741 and the second memory device 742 separately or simultaneously.

[0093] The host bus 750 can have substantially the same type and characteristics as Figure 1 the first bus 150 shown in Figure 1 The first controller bus 761 can have substantially the same type and characteristics as Figure 1 the second bus 160 shown in Figure 1 and Figure 2 The first memory bus 771 can have substantially the same type and characteristics as Figure 1 and Figure 2 the third bus 170 shown in

[0094] In one embodiment, the width of the data bus included in the first controller bus 761 can be less than or equal to the width of the data bus included in the first memory bus 771. The first interface circuit 731 can have substantially the same configuration and perform substantially the same functions as the interface circuits 130, 230 shown in

[0095] and Figure 2 The first memory device 741 can have substantially the same configuration and perform substantially the same functions as the memory devices 140, 240 shown in Figure 1 and Figure 2 The second controller bus 762 can have substantially the same type and characteristics as the first controller bus 761. The second memory bus 772 can have substantially the same type and characteristics as the first memory bus 771. In one embodiment, the width of the data bus included in the second controller bus 762 can be less than or equal to the width of the data bus included in the second memory bus 772. The second interface circuit 732 can have substantially the same configuration as the first interface circuit 731 and can perform substantially the same functions. The second memory device 742 can have substantially the same configuration as the first memory device 741 and can perform substantially the same functions.

[0094] The second controller bus 762 can have substantially the same type and characteristics as the first controller bus 761. The second memory bus 772 can have substantially the same type and characteristics as the first memory bus 771. In one embodiment, the width of the data bus included in the second controller bus 762 can be less than or equal to the width of the data bus included in the second memory bus 772. The second interface circuit 732 can have substantially the same configuration as the first interface circuit 731 and can perform substantially the same functions. The second memory device 742 can have substantially the same configuration as the first memory device 741 and can perform substantially the same functions.

[0095] In one embodiment, the second memory bus 772 may have a different type and characteristics from the first memory bus 771. For example, the second memory bus 772 may include a serial data bus. The width of the data bus included in the second memory bus 772 may be smaller than the width of the data bus included in the second controller bus 762. The clock rate of the second memory bus 772 may be higher than the clock rate of the second controller bus 762. In this case, the second interface circuit 732 may have a different configuration and perform different functions from the first interface circuit 731, while the second memory device 742 may have a different configuration and perform different functions from the first memory device 741. For example, the first interface circuit 731 and the first memory device 741 may perform parallel data communication, while the second interface circuit 732 and the second memory device 742 may perform serial data communication. The first interface circuit 731 and the first memory device 741 do not need to perform data conversion and thus may not be equipped with SerDes. The second interface circuit 732 and the second memory device 742 need to perform data conversion for serial data communication and thus may include SerDes.

[0096] In one embodiment, the host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 may be integrated into a first device, while the first memory device 741 and the second memory device 742 may be integrated into a second device. Alternatively, the first memory device 741 may constitute a second device, while the second memory device 742 may constitute a third device. The host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 may be disposed on a first interposer and / or a first substrate. The first memory device 741 and the second memory device 742 may be disposed on a second interposer and / or a second substrate. The host bus 750, the first controller bus 761, and the second controller bus 762 may be internal buses, and the first memory bus 771 and the second memory bus 772 may be external buses. In one embodiment, the first memory device 741 may be disposed on a second interposer and / or a second substrate, while the second memory device 742 may be disposed on a third interposer and / or a third substrate.

[0097] In one embodiment, the host 710 and the memory controller 720 may be integrated into a first device, and the first interface circuit 731 and the second interface circuit 732, as well as the first memory device 741 and the second memory device 742, may be integrated into a second device. Alternatively, the first interface circuit 731 and the first memory device 741 may be integrated into a second device, and the second interface circuit 732 and the second memory device 742 may be integrated into a third device. The host 710 and the memory controller 720 may be disposed on a first interposer and / or a first substrate. The first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 may be disposed on a second interposer and / or a second substrate. The host bus 750, the first memory bus 771, and the second memory bus 772 may be internal buses, and the first controller bus 761 and the second controller bus 762 may be external buses. In one embodiment, the first interface circuit 731 and the first memory device 741 may be disposed on a second interposer and / or a second substrate, and the second interface circuit 732 and the second memory device 742 may be disposed on a third interposer and / or a third substrate.

[0098] In one embodiment, the host 710 may constitute a first device, and the memory controller 720, the first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 may be integrated into a second device. The host 710 may be disposed on a first interposer and / or a first substrate. The memory controller 720, the first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 may be disposed on a second interposer and / or a second substrate. The host bus 750 may be an external bus, and the first controller bus 761 and the second controller bus 762, as well as the first memory bus 771 and the second memory bus 772, may be internal buses. In one embodiment, the host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732, as well as the first memory device 741 and the second memory device 742, may be disposed on a single interposer and / or a single substrate. The host bus 750, the first controller bus 761, the second controller bus 762, as well as the first memory bus 771 and the second memory bus 772 may all be internal buses. In one embodiment, some or all of the host 710, the memory controller 720, the first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 may be fabricated as dielets.

[0099] Figure 8 is a diagram showing the configuration of a computing system 800 according to an embodiment of the present disclosure. Refer to Figure 8, the computing system 800 may include a host 810, a first memory controller 821, a second memory controller 822, a first interface circuit 831, a second interface circuit 832, a first memory device 841, and a second memory device 842. The first memory controller 821 may be electrically connected to the host 810 through a first host bus 851. The second memory controller 822 may be electrically connected to the host 810 through a second host bus 852. The first interface circuit 831 may be electrically connected to the first memory controller 821 through a first controller bus 861. The second interface circuit 832 may be electrically connected to the second memory controller 822 through a second controller bus 862. The first memory device 841 may be electrically connected to the first interface circuit 831 through a first memory bus 871. The second memory device 842 may be electrically connected to the second interface circuit 832 through a second memory bus 872. The host 810 may be independently electrically connected to the first memory controller 821 and the second memory controller 822 for independent access to the first memory device 841 and the second memory device 842. The host 810 may independently generate a first access request for the first memory device 841 and a second access request for the second memory device 842. In one embodiment, the host 810 may include multiple processing cores to independently generate the first access request and the second access request. The host 810 may provide the first access request to the first memory controller 821 through the first host bus 851, and may provide the second access request to the second memory controller 822 through the second host bus 852.

[0100] The first host bus 851 and the second host bus 852 may both have types and characteristics substantially the same as Figure 1 the first bus 150 shown therein. The first controller bus 861 and the second controller bus 862 may both have types and characteristics substantially the same as Figure 1 the second bus 160 shown therein. The first memory bus 871 may have a type and characteristics substantially the same as Figure 1 the third bus 170 shown therein. In one embodiment, the width of the data bus included in the first controller bus 861 may be less than or equal to the width of the data bus included in the first memory bus 871. The first interface circuit 831 may have a configuration substantially the same as Figure 1 and Figure 2 the interface circuits 130, 230 shown therein and perform substantially the same functions. The first memory device 841 may have a configuration substantially the same as Figure 1 and Figure 2 the memory devices 140, 240 shown therein and perform substantially the same functions.

[0101] The second controller bus 862 may have the same type and characteristics as the first controller bus 861. The second memory bus 872 may have the same type and characteristics as the first memory bus 871. In one embodiment, the width of the data bus included in the second controller bus 862 may be less than or equal to the width of the data bus included in the second memory bus 872. The second interface circuit 832 may have the same configuration as the first interface circuit 831 and may perform the same functions. The second memory device 842 may have the same configuration as the first memory device 841 and may perform the same functions. In one embodiment, the second memory bus 872 may have different types and characteristics from the first memory bus 871. For example, the second memory bus 872 may include a serial data bus. The width of the data bus included in the second memory bus 872 may be less than the width of the data bus included in the second controller bus 862. The clock rate of the second memory bus 872 may be higher than the clock rate of the second controller bus 862. In this case, the second interface circuit 832 may have a different configuration from the first interface circuit 831 and perform different functions, while the second memory device 842 may have a different configuration from the first memory device 841 and perform different functions. For example, the first interface circuit 831 and the first memory device 841 may perform parallel data communication, while the second interface circuit 832 and the second memory device 842 may perform serial data communication. The first interface circuit 831 and the first memory device 841 do not require data conversion and thus may not be equipped with SerDes. The second interface circuit 832 and the second memory device 842 require data conversion for serial data communication and thus may include SerDes.

[0102] In one embodiment, the host 810, the first memory controller 821, the second memory controller 822, the first interface circuit 831, and the second interface circuit 832 may be integrated into a first device. The first memory device 841 and the second memory device 842 may be integrated into a second device. Alternatively, the first memory device 841 may form the second device, and the second memory device 842 may form the third device. The host 810, the first memory controller 821, the second memory controller 822, and the first interface circuit 831 and the second interface circuit 832 may be disposed on a first interposer and / or a first substrate. The first memory device 841 and the second memory device 842 may be disposed on a second interposer and / or a second substrate. The first host bus 851 and the second host bus 852, the first controller bus 861 and the second controller bus 862 may be internal buses, while the first memory bus 871 and the second memory bus 872 may be external buses. In one embodiment, the first memory device 841 may be disposed on a second interposer and / or a second substrate, and the second memory device 842 may be disposed on a third interposer and / or a third substrate.

[0103] In one embodiment, the host 810, the first memory controller 821, and the second memory controller 822 may be integrated into a first device. The first interface circuit 831, the second interface circuit 832, the first memory device 841, and the second memory device 842 may be integrated into a second device. Alternatively, the first interface circuit 831 and the first memory device 841 may be integrated into the second device, and the second interface circuit 832 and the second memory device 842 may be integrated into a third device. The host 810, the first memory controller 821, and the second memory controller 822 may be disposed on a first interposer and / or a first substrate. The first interface circuit 831, the second interface circuit 832, the first memory device 841, and the second memory device 842 may be disposed on a second interposer and / or a second substrate. The first host bus 851 and the second host bus 852, the first memory bus 871 and the second memory bus 872 may be internal buses, while the first controller bus 861 and the second controller bus 862 may be external buses. In one embodiment, the first interface circuit 831 and the first memory device 841 may be disposed on a second interposer and / or a second substrate, and the second interface circuit 832 and the second memory device 842 may be disposed on a third interposer and / or a third substrate.

[0104] In one embodiment, the host 810 may constitute a first device, and the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 may be integrated into a second device. Alternatively, the first memory controller 821, the first interface circuit 831, and the first memory device 841 may be integrated into a second device, and the second memory controller 822, the second interface circuit 832, and the second memory device 842 may be integrated into a third device. The host 810 may be disposed on the first interposer and / or the first substrate. The first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 may be disposed on the second interposer and / or the second substrate. The first host bus 851 and the second host bus 852 may be external buses, and the first controller bus 861 and the second controller bus 862, and the first memory bus 871 and the second memory bus 872 may be internal buses. In one embodiment, the first memory controller 821, the first interface circuit 831, and the first memory device 841 may be disposed on the second interposer and / or the second substrate, and the second memory controller 822, the second interface circuit 832, and the second memory device 842 may be disposed on the third interposer and / or the third substrate.

[0105] In one embodiment, the host 810, the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 may be arranged on a single interposer and / or a single substrate. The first host bus 851 and the second host bus 852, the first controller bus 861 and the second controller bus 862, and the first memory bus 871 and the second memory bus 872 may all be internal buses. In one embodiment, some or all of the host 810, the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 may be fabricated as die.

[0106] Figure 9A is a diagram showing the configuration and connection relationship of an integrated circuit package 900a according to an embodiment of the present disclosure. Refer to Figure 9A, an integrated circuit package may include a substrate 901a, a memory controller 910a, an interface circuit 920a, and a memory device 930a. The memory controller 910a, the interface circuit 920a, and the memory device 930a may be fabricated as separate dies and / or chips. Some or all of the memory controller 910a, the interface circuit 920a, and the memory device 930a may be fabricated using process technologies with different characteristics. The memory controller 910a, the interface circuit 920a, and the memory device 930a may be disposed on the substrate 901a. The memory controller 910a may be disposed in a first area on the substrate 901a. The interface circuit 920a may be disposed in a second area on the substrate 901a. The memory device 930a may be disposed in a third area on the substrate 901a. The first area and the third area may not overlap, while the second area may be located between the first area and the third area. The memory device 930a is shown as including a single memory die. For example, the memory controller 910a, the interface circuit 920a, and the memory device 930a may be attached to the substrate 901a using an adhesive. The substrate 901a may include any substrate having pads capable of wire bonding, and may be, for example, one of a package substrate, an organic substrate, and a module substrate. The substrate 901a may include external terminals 902a under the substrate, and the external terminals 902a are used for electrical connection with an external device. The external terminals 902a may include solder balls or package balls.

[0107] The memory controller 910a may be electrically connected to the substrate 901a by wire bonding pads formed on a first side (e.g., Figure 9A the left side in ) of the memory controller 910a to pads formed on the substrate 901a. The wire bonding between the memory controller 910a and the substrate 901a may be a first wire bonding. The memory controller 910a may be connected to the substrate 901a by wire bonding pads formed on a second side (e.g., Figure 9AThe pad leads on the right side in [description] are wire-bonded to the pads formed on the first side of the interface circuit 920a to be electrically connected to the interface circuit 920a. The wire bond between the memory controller 910a and the interface circuit 920a can be the second wire bond. The interface circuit 920a can be electrically connected to the memory device 930a by wire-bonding the pad leads formed on the second side of the interface circuit 920a to the pads formed on the first side of the memory device 930a. The wire bond between the interface circuit 920a and the memory device 930a can be the third wire bond. The memory device 930a can be electrically connected to the substrate 901a by wire-bonding the pad leads formed on the second side of the memory device 930a to the pads formed on the substrate 901a. The wire bond between the memory device 930a and the substrate 901a can be the fourth wire bond. The substrate 901a, the memory controller 910a, the interface circuit 920a, and the memory device 930a can be encapsulated in a single package. Since the memory controller 910a, the interface circuit 920a, and the memory device 930a are electrically connected by wire bonds, a low-cost substrate can be used, and the manufacturing cost of the integrated circuit package can be reduced. The first wire bond between the memory controller 910a and the substrate 901a can correspond to Figure 1 part or all of the first bus 150 shown in [description]. The second wire bond between the memory controller 910a and the interface circuit 920a can correspond to Figure 1 the second bus 160 shown in [description]. The third wire bond between the interface circuit 920a and the memory device 930a can correspond to Figure 1 the third bus 170 shown in [description]. The fourth wire bond between the memory device 930a and the substrate 901a can correspond to the direct access path for an external device to access the memory device 930a. The frequency of the signal transmitted through the second wire bond can be greater than or equal to the frequency of the signal transmitted through the third wire bond. The frequency of the signal transmitted through the wire bond can be related to the clock rate or clock frequency. The signal can be transmitted through the second wire bond at a first clock rate, and the signal can be transmitted through the third wire bond at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The second wire bond can include a first data bus, and the third wire bond can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0108] Figure 9B FIG. [description] is a diagram showing the configuration and connection relationship of the integrated circuit package 900b according to an embodiment of the present disclosure. Refer to Figure 9B, the integrated circuit package 900b may include a first substrate 901b, a memory controller 910b, an interface circuit 920b, and a memory device 930b. The memory controller 910b, the interface circuit 920b, and the memory device 930b may be disposed on the first substrate 901b. The first substrate 901b may include an interposer. The memory controller 910b may be disposed in a first area on the first substrate 901b. The interface circuit 920b may be disposed in a second area on the first substrate 901b. The memory device 930b may be disposed in a third area on the first substrate 901b. The first area and the third area may not overlap, and the second area may be located between the first area and the third area. The memory device 930b is shown as including a single memory die. The integrated circuit package 900b may further include a second substrate 905b. The second substrate 905b may include a redistribution layer or an interposer. The second substrate 905b may be arranged to electrically connect the memory device 930b and the first substrate 901b, and the second substrate 905b may be disposed on the first substrate 901b. The second substrate 905b may be disposed in the third area on the first substrate 901b. The second substrate 905b may include a plurality of signal paths for electrically connecting the memory device 930b to the first substrate 901b. The memory device 930b may be disposed on the second substrate 905b. When the second substrate 905b is an interposer, the memory device 930b may be electrically connected to the second substrate 905b through micro-bumps. When the second substrate 905b is a redistribution layer, the memory device 930b may be electrically connected to the second substrate 905b through micro-bumps, or may be electrically connected to the second substrate 905b without micro-bumps. In one embodiment, the memory device 930b may be directly electrically connected to the first substrate 901b without the second substrate 905b. The first substrate 901b may include external terminals 902b located below the first substrate 901b, and the external terminals 902b are used for electrical connection with an external device. The external terminals 902b may include micro-bumps or bumps. In one embodiment, the integrated circuit package 900b may further include another substrate, and the first substrate 901b may be disposed on the another substrate. The another substrate may include another interposer or a package substrate. When the another substrate is provided, the first substrate 901b may be electrically connected to the another substrate through micro-bumps or bumps, and may be electrically connected to the external device through the another substrate.

[0109] The first substrate 901b may include a plurality of signal paths 911b, 921b, 931b, 941b for electrically connecting components disposed on the first substrate 901b. The memory controller 910b may be electrically connected to the first substrate 901b through micro-bumps 903b. The interface circuit 920b may be electrically connected to the first substrate 901b through micro-bumps 904b. The memory device 930b may be electrically connected to the first substrate 901b through micro-bumps 906b. The memory controller 910b may be electrically connected to the signal path 911b of the first substrate 901b and the external terminal 902b through the micro-bumps 903b on the first side of the memory controller 910b. Through the micro-bumps 903b on the second side of the memory controller 910b, the memory controller 910b may be electrically connected to the micro-bumps 904b on the first side of the interface circuit 920b and the signal path 921b of the first substrate 901b. The interface circuit 920b may be electrically connected to the micro-bumps 906b on the first side of the second substrate 905b through the micro-bumps 904b on the second side of the interface circuit 920b and the signal path 931b of the first substrate 901b. The memory device 930b may be electrically connected to the external terminal 902b through the micro-bumps 906b on the second side of the second substrate 905b and the signal path 941b of the first substrate 901b.

[0110] The first substrate 901b, the memory controller 910b, the interface circuit 920b, and the memory device 930b may be encapsulated in a single package. Disposing the memory controller 910b, the interface circuit 920b, and the memory device 930b on the first substrate 901b may facilitate integrated circuit package manufacturing and reduce the integrated circuit package size because wire bonding is not required. The electrical connection between the memory controller 910b and the signal path 911b of the first substrate 901b may correspond to Figure 1 part or all of the first bus 150 shown in Figure 1 . The signal path 921b of the first substrate 901b that electrically connects the memory controller 910b and the interface circuit 920b may correspond to Figure 1The third bus 170 shown. The electrical connection between the memory device 930b and the signal path 941b of the first substrate 901b may correspond to a direct access path to the memory device 930b. The frequency of the signal transmitted through the signal path 921b may be greater than or equal to the frequency of the signal transmitted through the signal path 931b. The signal may be transmitted through the signal path 921b at a first clock rate, and the signal may be transmitted through the signal path 931b at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 921b may include a first data bus, and the signal path 931b may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0111] Figure 9C is a diagram showing the configuration and connection relationship of the integrated circuit package 900c according to an embodiment of the present disclosure. Refer to Figure 9C, the integrated circuit package 900c may include a first substrate 901c, a memory controller 910c, an interface circuit 920c, and a memory device 930c. The memory controller 910c, the interface circuit 920c, and the memory device 930c may be disposed on the first substrate 901c. The first substrate 901c may include an interposer. The memory controller 910c may be disposed in a first area on the first substrate 901c. The interface circuit 920c may be disposed in a second area on the first substrate 901c. The memory device 930c may be disposed in a third area on the first substrate 901c. The first area and the third area may not overlap, and the second area may be located between the first area and the third area. The memory device 930c may include one or more memory dies. The number of memory dies included in the memory device 930c may be two, four, eight, or more. For example, the memory device 930c may include first to fourth memory dies. The number of memory dies included in the memory device 930c may be two, or may be eight or more. The integrated circuit package 900c may further include a second substrate 905c. The second substrate 905c may include a redistribution layer or an interposer. The second substrate 905c may be configured to electrically connect the memory device 930c to the first substrate 901c, and the second substrate 905c may be disposed on the first substrate 901c. The second substrate 905c may be disposed in the third area on the first substrate 901c. The second substrate 905c may include a plurality of signal paths for electrically connecting the memory device 930c to the first substrate 901c. The first to fourth memory dies may be disposed on the second substrate 905c. The memory controller 910c may be electrically connected to the first substrate 901c through microbumps 903c. The interface circuit 920c may be electrically connected to the first substrate 901c through microbumps 904c. The second substrate 905c may be electrically connected to the first substrate 901c through microbumps 906c. The first substrate 901c may include external terminals 902c located below the first substrate 901c, and the external terminals 902c are used for electrical connection with an external device. The external terminals 902c may include microbumps or bumps. In one embodiment, the integrated circuit package 900c may further include another substrate, and the first substrate 901c may be disposed on the another substrate. The another substrate may include another interposer or a package substrate. When the another substrate is provided, the first substrate 901c may be electrically connected to the another substrate through microbumps or bumps, and may be electrically connected to an external device through the another substrate.

[0112] The memory controller 910c can be electrically connected to the signal path 911c and the external terminal 902c of the first substrate 901c through the microbumps 903c on the first side of the memory controller 910c. Through the microbumps 903c on the second side of the memory controller 910c, the memory controller 910c can be electrically connected to the microbumps 904c on the first side of the interface circuit 920c and the signal path 921c of the first substrate 901c. The interface circuit 920c can be electrically connected to the microbumps 906c on the first side of the second substrate 905c through the microbumps 904c on the second side of the interface circuit 920c and the signal path 931c of the first substrate 901c. The second substrate 905c can be electrically connected to the external terminal 902c through the microbumps 906c on the second side of the second substrate 905c and the signal path 941c of the first substrate 901c. The first to fourth memory dies can be sequentially stacked on the second substrate 905c. DAF (die attach film) 907c can be respectively disposed between the first memory die and the second memory die, between the second memory die and the third memory die, and between the third memory die and the fourth memory die, and the first to fourth memory dies can be bonded using the DAF 907c. The DAF 907c can increase the strength of the memory die to prevent the memory die from warping and leave space for wire bonding. The first to fourth memory dies can be stacked in a stepped manner. The pads of the fourth memory die can be wire-bonded to the pads of the third memory die, the pads of the third memory die can be wire-bonded to the pads of the second memory die. The pads of the second memory die can be wire-bonded to the pads of the first memory die, and the pads of the first memory die can be wire-bonded to the pads formed on the second substrate 905c. In one embodiment, the pads of the first memory die can be wire-bonded to the pads formed on the second substrate 905c, and the pads of the second memory die can be wire-bonded to the pads formed on the second substrate 905c. The pads of the third memory die can be wire-bonded to the pads formed on the second substrate 905c, and the pads of the fourth memory die can be wire-bonded to the pads formed on the second substrate 905c. The pads of the first memory die and the fourth memory die can be commonly wire-bonded to the same pads on the second substrate 905c, and the first memory die and the fourth memory die can form a common channel. In one embodiment, the pads of the first to fourth memory bare chips can be wire-bonded to different pads of the second substrate 905c, and the first to fourth memory dies can form independent channels.

[0113] The first substrate 901c, the memory controller 910c, the interface circuit 920c, and the memory device 930c can be encapsulated in a single package. The signal path 911c between the memory controller 910c and the first substrate 901c can correspond toFigure 1 Part or all of the first bus 150 shown. The signal path 921c on the first substrate 901c that electrically connects the memory controller 910c and the interface circuit 920c may correspond to Figure 1 The second bus 160 shown. The signal path 931c on the first substrate 901c that electrically connects the interface circuit 920c and the second substrate 905c, and the wire bonding that electrically connects the second substrate 905c and the first to fourth memory dies may correspond to Figure 1 The third bus 170 shown. The signal path 941c on the first substrate 901c may correspond to the direct access path to the memory device 930c. The frequency of the signal transmitted through the signal path 921c may be greater than or equal to the frequency of the signal transmitted through the signal path 931c. The signal may be transmitted through the signal path 921c at a first clock rate, and the signal may be transmitted through the signal path 931c at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 921c may include a first data bus, and the signal path 931c may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0114] Figure 9D FIG. for showing the configuration and connection relationship of the integrated circuit package 900d according to an embodiment of the present disclosure. Refer to Figure 9D, the integrated circuit package 900d may include a first substrate 901d, a memory controller 910d, an interface circuit 920d, and a memory device 930d. The memory controller 910d, the interface circuit 920d, and the memory device 930d may be disposed on the first substrate 901d. The first substrate 901d may include an interposer. The memory controller 910d may be disposed in a first area on the first substrate 901d. The interface circuit 920d may be disposed in a second area on the first substrate 901d. The memory device 930d may be disposed in a third area on the first substrate 901d. The first area and the third area may not overlap, and the second area may be located between the first area and the third area. The memory device 930d may include one or more memory dies. The number of memory dies included by the memory device 930d may be two, four, eight, or more. For example, the memory device 930d may include first to fourth memory dies. The integrated circuit package 900d may further include a second substrate 905d. The second substrate 905d may include a redistribution layer or an interposer. The second substrate 905d may be configured to electrically connect the memory device 930c to the first substrate 901d, and the second substrate 905d may be disposed on the first substrate 901d. The second substrate 905d may be disposed in the third area on the first substrate 901d. The second substrate 905d may include a plurality of signal paths for electrically connecting the memory device 930d to the first substrate 901d. The first to fourth memory dies may be stacked on the second substrate 905d. The first substrate 901d may include external terminals 902d located below the first substrate 901d for electrically connecting to an external device. The external terminals 902d may include micro-bumps or bumps. In one embodiment, the integrated circuit package 900d may further include another substrate, and the first substrate 901d may be disposed on the another substrate. The another substrate may include another interposer or a package substrate. When the another substrate is provided, the first substrate 901d may be electrically connected to the another substrate through micro-bumps or bumps and electrically connected to the external device through the another substrate.

[0115] The memory controller 910d can be electrically connected to the first substrate 901d through the microbumps 903d. The interface circuit 920d can be electrically connected to the first substrate 901d through the microbumps 904d. The second substrate 905d can be electrically connected to the first substrate 901d through the microbumps 906d. The memory controller 910d can be electrically connected to the signal path 911d and the external terminal 902d of the first substrate 901d through the microbumps 903d on the first side of the memory controller 910d. Through the microbumps 903d on the second side of the memory controller 910d, the memory controller 910d can be electrically connected to the microbumps 904d on the first side of the interface circuit 920d and the signal path 921d of the first substrate 901d. Through the microbumps 904d on the second side of the interface circuit 920d, the interface circuit 920d can be electrically connected to the microbumps 906d on the first side of the second substrate 905d and the signal path 931d of the first substrate 901d. Through the microbumps 906d on the second side of the second substrate 905d, the second substrate 905d can be electrically connected to the external terminal 902d and the signal path 941d of the first substrate 901d. The first to fourth memory dies can be sequentially stacked on the second substrate 905d. The first to fourth memory dies can be vertically aligned and stacked. The vias 907d can be formed in the first to fourth memory dies, and the first to fourth memory dies can be electrically connected to each other through the vias 907d and the microbumps 908d. When the first to fourth memory dies are electrically connected through the vias 907d, the first to fourth memory dies do not need to be stacked in a stepped manner as Figure 9C shown, but can be stacked in a vertically aligned manner. Therefore, the area of the second substrate 905d and the size of the integrated circuit package can be reduced. The first to fourth memory dies can be electrically connected to the common signal path of the second substrate 905d, and the first to fourth memory dies can form a common channel. In one embodiment, the first to fourth memory dies can be electrically connected to the second substrate 905d through different signal paths, and the first to fourth memory dies can form independent channels for each other.

[0116] The first substrate 901d, the memory controller 910d, the interface circuit 920d, and the memory device 930d can be encapsulated in a single package. The signal path 911d between the memory controller 910d and the first substrate 901d can correspond to Figure 1 part or all of the first bus 150 shown in Figure 1The second bus 160 shown in []. The electrical connection interface circuit 920d of the first substrate 901d, the signal path 931d of the second substrate 905d, and the microbumps 908d and vias 907d that electrically connect the second substrate 905d to the first to fourth memory dies may correspond to Figure 1 The third bus 170 shown in []. The signal path 941d of the first substrate 901d may correspond to a direct access path to the memory device 930d. The frequency of the signal transmitted through the signal path 921d may be greater than or equal to the frequency of the signal transmitted through the signal path 931d. The signal may be transmitted through the signal path 921d at a first clock rate, and the signal may be transmitted through the signal path 931d at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 921d may include a first data bus, and the signal path 931d may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0117] Figure 9E A diagram showing the configuration and connection relationship of the integrated circuit package 900e according to an embodiment of the present disclosure. Referring to Figure 9E , the integrated circuit package 900e may include a substrate 901e, a die 91e, and a memory device 930e. The die 91e may include a memory controller 910e and an interface circuit 920e. The memory controller 910e and the interface circuit 920e may be internal circuits of the die 91e. The die 91e and the memory device 930e may be fabricated as separate dies and / or chips. The die 91e and the memory device 930e may be fabricated using process technologies with different characteristics, or may be fabricated using process technologies with the same characteristics. The die 91e and the memory device 930e may be disposed on the substrate 901e. The substrate 901e may include an interposer. The die 91e may be disposed in a first region on the substrate 901e, and the memory device 930e may be disposed in a second region on the substrate 901e. The first region and the second region may not overlap. The memory device 930e is shown as including a single memory die. The substrate 901e may include external terminals 902e below the substrate 901e for electrically connecting to an external device. The external terminals 902e may include microbumps or bumps. In one embodiment, the integrated circuit package 900e may further include another substrate, and the substrate 901e may be disposed on the another substrate. The another substrate may include another interposer or a package substrate. When another substrate is provided, the substrate 901e may be electrically connected to the another substrate through microbumps or bumps, and electrically connected to the external device through the another substrate.

[0118] The substrate 901e may include a plurality of signal paths 911e, 931e, 941e for electrically connecting components disposed on the substrate 901e. The memory controller 910e may be electrically connected to the signal path 911e and the external terminal 902e through the microbumps 903e on the first side of the die 91e. The memory controller may be electrically connected to the interface circuit 920e through the signal transmission line 921e inside the die 91e. Hereinafter, the electrical connection component for electrically connecting the internal circuits formed within one die may be referred to as a signal transmission line, and the electrical connection components formed on the interposer and / or the substrate may be referred to as signal paths. The interface circuit 920e may be electrically connected to the signal path 931e through the microbumps 904e on the second side of the die 91e. The memory device 930e may be electrically connected to the signal path 931e through the microbumps 905e on the first side of the memory device 930e. The memory device 930b may be electrically connected to the external terminal 902e through the microbumps 905e on the second side of the memory device 930b and the signal path 941e.

[0119] The substrate 901e, the die 91e, and the memory device 930e may be encapsulated in a single package. Disposing the die 91e and the memory device 930e on the substrate 901e may facilitate the manufacture of the integrated circuit package and reduce the size of the integrated circuit package because wire bonding is not required. The electrical connection between the memory controller 910e and the signal path 911e may correspond to Figure 1 a part or all of the first bus 150 shown in Figure 1 The signal transmission line 921e that electrically connects the memory controller 910e and the interface circuit 920e may correspond to Figure 1 the second bus 160 shown in

[0120] Figure 10A is a diagram showing the configuration and connection relationship of the integrated circuit package 1000a according to an embodiment of the present disclosure. Refer toFigure 10A , the integrated circuit package 1000a may include a first substrate 1001a, a second substrate 1002a, a host 1010a, a memory controller 1020a, an interface circuit 1030a, and a memory device 1040a. The memory device 1040a may include any one of the memory devices 930b to 930d shown in Figures 9B to 9D . The host 1010a, the memory controller 1020a, the interface circuit 1030a, and the memory device 1040a may be fabricated as separate dies and / or chips. Some or all of the host 1010a, the memory controller 1020a, the interface circuit 1030a, and the memory device 1040a may be fabricated using process technologies with different characteristics. The host 1010a, the memory controller 1020a, and the interface circuit 1030a may be disposed on the first substrate 1001a. The first substrate 1001a may include a first interposer. The host 1010a may be disposed in a first area on the first substrate 1001a. The memory controller 1020a may be disposed in a second area on the first substrate 1001a. The interface circuit 1030a may be disposed in a third area on the first substrate 1001a. The first area and the third area may not overlap with each other, while the second area may be located between the first area and the third area. The host 1010a may be electrically connected to the first substrate 1001a through the microbumps of the host 1010a. The memory controller 1020a may be electrically connected to the first substrate 1001a through the microbumps of the memory controller 1020a. The interface circuit 1030a may be electrically connected to the first substrate 1001a through the microbumps of the interface circuit 1030a. The memory device 1040a may be disposed on the second substrate 1002a. The second substrate 1002a may include a second interposer. The memory device 1040a may be electrically connected to the second substrate 1002a through the microbumps of the memory device 1040a. The first substrate 1001a and the second substrate 1002a may be disposed on a third substrate 1003a. The third substrate 1003a may include another interposer or a package substrate. The first substrate 1001a may be disposed in a first area on the third substrate 1003a, while the second substrate 1002a may be disposed in a second area on the third substrate 1003a. The first area and the second area may not overlap with each other. The first substrate 1001a and the second substrate 1002a may be electrically connected to the third substrate 1003a respectively through the microbumps or bumps in the first substrate 1001a and the second substrate 1002a. The third substrate 1003a may be electrically connected to an external device through the external terminals of the third substrate 1003a. The external terminals may include microbumps, bumps, solder balls, or package balls.

[0121] The host 1010a can be electrically connected to the memory controller 1020a through a signal path 1011a formed in the first substrate 1001a. The memory controller 1020a can be electrically connected to the interface circuit 1030a through a signal path 1021a of the first substrate 1001a. The interface circuit 1030a can be electrically connected to the memory device 1040a through a signal path 1031a of the first substrate 1001a, a signal path 1032a formed in the third substrate 1003a, and a signal path 1033a of the second substrate 1002a. The signal path 1011a between the host 1010a and the memory controller 1020a can correspond to Figure 1 the first bus 150 shown. The signal path 1021a between the memory controller 1020a and the interface circuit 1030a can correspond to Figure 1 the second bus 160 shown. The signal paths 1031a, 1032a, 1033a between the interface circuit 1030a and the memory device 1040a can correspond to Figure 1 the third bus 170 shown. The frequency of the signal transmitted through the signal path 1021a can be greater than or equal to the frequency of the signal transmitted through the signal paths 1031a, 1032a, 1033a. The signal can be transmitted through the signal path 1021a at a first clock rate, and the signal can be transmitted through the signal paths 1031a, 1032a, 1033a at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal path 1021a can include a first data bus, and the signal paths 1031a, 1032a, 1033a can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus. In one embodiment, the first substrate 1001a, the host 1010a on the first substrate 1001a, the memory controller 1020a, and the interface circuit 1030a can be encapsulated in a first package. The memory device 1040a on the second substrate 1002a can be encapsulated in a second package. The first package and the second package can be disposed on the third substrate 1003a and encapsulated in a third package, and the integrated circuit package 1000a can be manufactured in a PIP (package-in-package) structure.

[0122] Figure 10B FIG. is a diagram showing the configuration and connection relationship of an integrated circuit package 1000b according to an embodiment of the present disclosure. Referring to Figure 10B , the integrated circuit package 1000b can include a first substrate 1001b, a second substrate 1002b, a host 1010b, a memory controller 1020b, an interface circuit 1030b, and a memory device 1040b. The memory device 1040b can include Figures 9B to 9DAny one of the memory devices 930b to 930d shown in the figure. The host 1010b may be disposed on the first substrate 1001b. The first substrate 1001b may include a first interposer. The host 1010b may be electrically connected to the first substrate 1001b through the microbumps of the host 1010b. The memory controller 1020b, the interface circuit 1030b, and the memory device 1040b may be disposed on the second substrate 1002b. The second substrate 1002b may include a second interposer. The memory controller 1020b may be disposed in a first area on the second substrate 1002b. The interface circuit 1030b may be disposed in a second area on the second substrate 1002b. The memory device 1040b may be disposed in a third area on the second substrate 1002b. The first area and the third area may not overlap with each other, while the second area may be located between the first area and the third area. The memory controller 1020b may be electrically connected to the second substrate 1002b through the microbumps of the memory controller 1020b. The interface circuit 1030b may be electrically connected to the second substrate 1002b through the microbumps of the interface circuit 1030b. The memory device 1040b may be electrically connected to the second substrate 1002b through the microbumps of the memory device 1040b. The first substrate 1001b and the second substrate 1002b may be disposed on the third substrate 1003b. The third substrate 1003b may include another interposer or a package substrate. The first substrate 1001b may be disposed in a first area on the third substrate 1003b, and the second substrate 1002b may be disposed in a second area on the third substrate 1003b. The first area and the second area may not overlap with each other. The first substrate 1001b and the second substrate 1002b may be electrically connected to the third substrate 1003b through the microbumps or bumps in the first substrate 1001b and the second substrate 1002b, respectively. The third substrate 1003b may be electrically connected to an external device through the external terminals of the third substrate 1003b. The external terminals may include microbumps, bumps, solder balls, or package balls.

[0123] The host 1010b may be electrically connected to the memory controller 1020b through the signal path 1011b formed in the first substrate 1001b, the signal path 1012b formed in the third substrate 1003b, and the signal path 1013b formed in the second substrate 1002b. The memory controller 1020b may be electrically connected to the interface circuit 1030b through the signal path 1021b of the second substrate 1002b. The interface circuit 1030b may be electrically connected to the memory device 1040b through the signal path 1031b of the second substrate 1002b. The signal paths 1011b, 1012b, 1013b between the host 1010b and the memory controller 1020b may correspond to Figure 1The first bus 150 shown. The signal path 1021b between the memory controller 1020b and the interface circuit 1030b may correspond to Figure 1 the second bus 160 shown. The signal path 1031b between the interface circuit 1030b and the memory device 1040b may correspond to Figure 1 the third bus 170 shown. The frequency of the signal transmitted through the signal path 1021b may be greater than or equal to the frequency of the signal transmitted through the signal path 1031b. The signal may be transmitted through the signal path 1021b at a first clock rate, and the signal may be transmitted through the signal path 1031b at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 1021b may include a first data bus, and the signal path 1031b may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus. In one embodiment, the first substrate 1001b and the host 1010b may be encapsulated in a first package. The second substrate 1002b, the memory controller 1020b located on the second substrate 1002b, the interface circuit 1030b, and the memory device 1040b may be encapsulated in a second package. The first package and the second package may be disposed on a third substrate 1003b and encapsulated in a third package, and the integrated circuit package 1000b may be manufactured in a PIP (package-in-package) structure.

[0124] Figure 10C FIG. is a diagram showing the configuration and connection relationship of an integrated circuit package 1000c according to an embodiment of the present disclosure. Refer to Figure 10C , the integrated circuit package 1000c may include a first substrate 1001c, a second substrate 1002c, a host 1010c, a memory controller 1020c, an interface circuit 1030c, and a memory device 1040c. The memory device 1040c may include Figures 9B to 9DAny one of the memory devices 930b to 930d shown. The host 1010c and the memory controller 1020c may be provided on the first substrate 1001c. The first substrate 1001c may include a first interposer. The host 1010c may be provided in a first area on the first substrate 1001c, while the memory controller 1020c may be provided in a second area on the first substrate 1001c. The first area and the second area may not overlap with each other. The host 1010c may be electrically connected to the first substrate 1001c through the microbumps of the host 1010c. The memory controller 1020c may be electrically connected to the first substrate 1001c through the microbumps of the memory controller 1020c. The interface circuit 1030c and the memory device 1040c may be provided on the second substrate 1002c. The second substrate 1002c may include a second interposer. The interface circuit 1030c may be provided in a first area on the second substrate 1002c, while the memory device 1040c may be provided in a second area on the second substrate 1002c. The first area and the second area may not overlap. The interface circuit 1030c may be electrically connected to the second substrate 1002c through the microbumps of the interface circuit 1030c. The memory device 1040c may be electrically connected to the second substrate 1002c through the microbumps of the memory device 1040c. The first substrate 1001c and the second substrate 1002c may be provided on the third substrate 1003c. The third substrate 1003c may include another interposer or a package substrate. The first substrate 1001c may be provided in a first area on the third substrate 1003c, while the second substrate 1002c may be provided in a second area on the third substrate 1003c. The first area and the second area may not overlap with each other. The first substrate 1001c and the second substrate 1002c may be electrically connected to the third substrate 1003c through the microbumps or bumps in the first substrate 1001c and the second substrate 1002c, respectively. The third substrate 1003c may be electrically connected to an external device through the external terminals of the third substrate 1003c. The external terminals may include microbumps, bumps, solder balls, or package balls.

[0125] The host 1010c may be electrically connected to the memory controller 1020c through a signal path 1011c formed in the first substrate 1001c. The memory controller 1020c may be electrically connected to the interface circuit 1030c through a signal path 1021c of the first substrate 1001c, a signal path 1022c formed in the third substrate 1003c, and a signal path 1023c formed in the second substrate 1002c. The interface circuit 1030c may be electrically connected to the memory device 1040c through a signal path 1031c formed in the second substrate 1002c. The signal path 1011c between the host 1010c and the memory controller 1020c may correspond to Figure 1The first bus 150 shown. The signal paths 1021c, 1022c, 1023c between the memory controller 1020c and the interface circuit 1030c may correspond to Figure 1 the second bus 160 shown. The signal path 1031c between the interface circuit 1030c and the memory device 1040c may correspond to Figure 1 the third bus 170 shown. The frequency of the signals transmitted through the signal paths 1021c, 1022c, 1023c may be greater than or equal to the frequency of the signals transmitted through the signal path 1031c. The signals may be transmitted through the signal paths 1021c, 1022c, 1023c at a first clock rate, and the signals may be transmitted through the signal path 1031c at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal paths 1021c, 1022c, 1023c may include a first data bus, and the signal path 1031c may include a second data bus. The number of data signals transmitted at any one time through the first data bus may be less than or equal to the number of data signals transmitted at any one time through the second data bus. In one embodiment, the first substrate 1001c, the host 1010c, and the memory controller 1020c may be encapsulated in a first package. The second substrate 1002c, the interface circuit 1030c, and the memory device 1040c may be encapsulated in a second package. The first package and the second package may be disposed on a third substrate 1003c and encapsulated in a third package, and the integrated circuit package 1000c may be manufactured in a PIP (package-in-package) structure.

[0126] Figure 10D FIG. showing the configuration and connection relationship of the integrated circuit package 1000d according to an embodiment of the present disclosure. Refer to Figure 10D , the integrated circuit package 1000d may include a substrate 1001d, a host 1010d, a memory controller 1020d, an interface circuit 1030d, and a memory device 1040d. The memory device 1040d may include Figures 9B to 9DAny one of the memory devices 930b to 930d shown. The host 1010d, the memory controller 1020d, the interface circuit 1030d, and the memory device 1040d may be provided on the substrate 1001d. The substrate 1001d may be an interposer and / or a glass substrate including a plurality of signal paths. The host 1010d may be provided in a first area on the substrate 1001d. The memory controller 1020d may be provided in a second area on the substrate 1001d. The interface circuit 1030d may be provided in a third area on the substrate 1001d. The memory device 1040d may be provided in a fourth area on the substrate 1001d. The first area and the fourth area may not overlap with each other. The second area may be located between the first area and the third area, and the third area may be located between the second area and the fourth area. The host 1010d may be electrically connected to the substrate 1001d through the microbumps of the host 1010d. The memory controller 1020d may be electrically connected to the substrate 1001d through the microbumps of the memory controller 1020d. The interface circuit 1030d may be electrically connected to the substrate 1001d through the microbumps of the interface circuit 1030d. The memory device 1040d may be electrically connected to the substrate 1001d through the microbumps of the memory device 1040d. The substrate 1001d may include external terminals below the substrate 1001d for electrically connecting to an external device. The external terminals may include microbumps, bumps, solder balls, or package balls. The host 1010d, the memory controller 1020d, the interface circuit 1030d, and the memory device 1040d provided on the substrate 1001d may be encapsulated in a single package body.

[0127] The host 1010d may be electrically connected to the memory controller 1020d through the signal path 1011d formed in the substrate 1001d. The memory controller 1020d may be electrically connected to the interface circuit 1030d through the signal path 1021d formed in the substrate 1001d. The interface circuit 1030d may be electrically connected to the memory device 1040d through the signal path 1031d formed in the substrate 1001d. The signal path 1011d between the host 1010d and the memory controller 1020d may correspond to Figure 1 the first bus 150 shown in Figure 1 The signal path 1021d between the memory controller 1020d and the interface circuit 1030d may correspond to Figure 1The third bus 170 shown. The frequency of the signal transmitted through the signal path 1021d may be greater than or equal to the frequency of the signal transmitted through the signal path 1031d. The signal may be transmitted through the signal path 1021d at a first clock rate, and the signal may be transmitted through the signal path 1031d at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 1021d may include a first data bus, and the signal path 1031d may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0128] Figure 10E is a diagram showing the configuration and connection relationship of the integrated circuit package 1000e according to an embodiment of the present disclosure. Referring to Figure 10E , the integrated circuit package 1000e may include a first tile 1010e, a second tile 1020e, a third tile 1030e, and a fourth tile 1040e. In Figure 10E , a tile may refer to a die, structure, unit module, or chiplet of a single device. The first tile 1010e may correspond to Figure 1 the host 110 shown. The second tile 1020e may correspond to Figure 1 the memory controller 120 shown. The third tile 1030e may correspond to Figure 1 the interface circuit 130 shown. The fourth tile 1040e may correspond to Figure 1 the memory device 140 shown. The first to fourth tiles 1010e, 1020e, 1030e, 1040e may be mounted on the base tile 1001e. The base tile 1001e may include a plurality of tile slots or connectors to allow the first to fourth tiles 1010e, 1020e, 1030e, 1040e and additional tiles (i.e., the fifth tile 1050e) to be mounted on the base tile 1001e. The base tile 1001e may include signal paths for electrically connecting the plurality of tiles mounted on the base tile 1001e. Although not shown, a plurality of signal paths may be formed within the base tile 1001e to electrically connect each of the first to fourth tiles 1010e, 1020e, 1030e, 1040e. The base tile 1001e may be disposed on the substrate 1002e. The substrate 1002e may include any one of an interposer, a package substrate, an organic substrate, a re-tile layer. The signal path between the first tile 1010e and the second tile 1020e may correspond to Figure 1 the first bus 150 shown. The signal path between the second tile 1020e and the third tile 1030e may correspond to Figure 1The second bus 160 shown. The signal path between the third die 1030e and the fourth die 1040e can correspond to Figure 1 the third bus 170 shown. The integrated circuit package 1000e may further include a fifth die 1050e. The fifth die 1050e may be a logic die that performs the same or different functions as any of the first through fourth dice 1010e, 1020e, 1030e, 1040e. Some or all of the first through fifth dice 1010e, 1020e, 1030e, 1040e, 1050e may be fabricated using different process technologies. In one embodiment, the first and second dice 1010e, 1020e may be integrated into a single die, and the integrated die may be mounted to the base die 1001e via a single socket or connector. In one embodiment, the second and third dice 1020e, 1030e may be integrated into a single die, and the integrated die may be mounted to the base die 1001e via a single socket or connector.

[0129] Figure 10F FIG. is a diagram showing the configuration and connection relationship of an integrated circuit package 1000f according to an embodiment of the present disclosure. Referring to Figure 10F , the integrated circuit package 1000f may include a first substrate 1001f, a host die 101f, and a memory device 1040f. The memory device 1040f may include Figures 9B to 9D any one of the memory devices 930b to 930d shown in. The host die 101f may include a host 1010f, a memory controller 1020f, and an interface circuit 1030f. The host 1010f, the memory controller 1020f, and the interface circuit 1030f may be internal circuits of the host die 101f. The host die 101f and the memory device 1040f may be fabricated as separate dice and / or dies. The host die 101f and the memory device 1040f may be fabricated using process technologies having different characteristics, or may be fabricated using process technologies having the same characteristics. The host die 101f and the memory device 1040f may be disposed on the first substrate 1001f. The first substrate 1001f may include an interposer. The host die 101f may be disposed in a first region on the first substrate 1001f, while the memory device 1040f may be disposed in a second region on the first substrate 1001f. The first and second regions may not overlap each other.

[0130] The host die 101f can be electrically connected to the first substrate 1001f through the micro-bumps of the host die 101f. The memory device 1040f can be electrically connected to the first substrate 1001f through the micro-bumps of the memory device 1040f. The integrated circuit package 1000f may further include a second substrate 1002f. The first substrate 1001f may be disposed on the second substrate 1002f. The second substrate may include another interposer or package substrate. The first substrate 1001f can be electrically connected to the second substrate 1002f through the micro-bumps or bumps of the first substrate 1001f. The second substrate 1002f can be electrically connected to an external device through the external terminals of the second substrate 1002f. The external terminals may include micro-bumps, bumps, solder balls, or package balls.

[0131] The host 1010f can be electrically connected to the memory controller 1020f through the signal transmission line 1011f inside the host die 101f. The memory controller 1020f can be electrically connected to the interface circuit 1030f through the signal transmission line 1021f inside the host die 101f. The interface circuit 1030f can be electrically connected to the memory device 1040f through the micro-bumps of the host die 101f and the signal path 1031f formed in the first substrate 1001f. The memory device 1040f can be electrically connected to the signal path 1031f through the micro-bumps of the memory device 1040f. In one embodiment, the host 1010f can be directly electrically connected to an external device through the signal path formed in the first substrate 1001f, the signal path formed in the second substrate 1002f, and the external terminals of the second substrate 1002f. The memory device 1040f can be directly electrically connected to an external device through the signal path formed in the first substrate 1001f, the signal path formed in the second substrate 1002f, and the external terminals of the second substrate 1002f. The signal transmission line 1011f that electrically connects the host 1010f and the memory controller 1020f may correspond to Figure 1 the first bus 150 shown. The signal transmission line 1021f that electrically connects the memory controller 1020f and the interface circuit 1030f may correspond to Figure 1 the second bus 160 shown. The signal path 1031f between the interface circuit 1030f and the memory device 1040f may correspond to Figure 1The third bus 170 shown. The frequency of the signal transmitted through the signal transmission line 1021f may be greater than or equal to the frequency of the signal transmitted through the signal path 1031f. The signal may be transmitted through the signal transmission line 1021f at a first clock rate, and the signal may be transmitted through the signal path 1031f at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal transmission line 1021f may include a first data bus, and the signal path 1031f may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus. The first substrate 1001f, the second substrate 1002f, the host die 101f, and the memory device 1040f may be encapsulated in a single package body.

[0132] Figure 10G is a diagram showing the configuration and connection relationship of the integrated circuit package 1000g according to an embodiment of the present disclosure. Referring to Figure 10G , the integrated circuit package 1000g may include a first substrate 1001g-1, a second substrate 1001g-2, a first host die 101g, a second host die 102g, a first memory device 1040g-1, and a second memory device 1040g-2. The first memory device 1040g-1 and the second memory device 1040g-2 may both include Figures 9B to 9DAny one of the memory devices 930b to 930d shown in the figure. The first host die 101g may include a host 1010g-1, a memory controller 1020g-1, and an interface circuit 1030g-1. The host 1010g-1, the memory controller 1020g-1, and the interface circuit 1030g-1 may be internal circuits of the first host die 101g. The first host die 101g and the first memory device 1040g-1 may be disposed on a first substrate 1001g-1. The first substrate 1001g-1 may include a first interposer. The first host die 101g may be disposed in a first area on the first substrate 1001g-1, while the first memory device 1040g-1 may be disposed in a second area on the first substrate 1001g-1. The first area and the second area may not overlap. The first host die 101g may be electrically connected to the first substrate 1001g-1 through micro-bumps of the first host die 101g. The first memory device 1040g-1 may be electrically connected to the first substrate 1001g-1 through micro-bumps of the first memory device 1040g-1. The integrated circuit package 1000g may further include a third substrate 1002g. The first substrate 1001g-1 may be disposed on the third substrate 1002g. The third substrate 1002g may include another interposer or a package substrate. The first substrate 1001g-1 may be electrically connected to the third substrate 1002g through micro-bumps or bumps of the first substrate 1001g-1. The third substrate 1002g may be electrically connected to an external device through external terminals of the third substrate 1002g. The external terminals may include micro-bumps, bumps, solder balls, or package balls.

[0133] The host 1010g-1 may be electrically connected to the memory controller 1020g-1 through a signal transmission line 1011g-1 inside the first host die 101g. The memory controller 1020g-1 may be electrically connected to the interface circuit 1030g-1 through a signal transmission line 1021g-1 inside the first host die 101g. The interface circuit 1030g-1 may be electrically connected to the first memory device 1040g-1 through micro-bumps of the first host die 101g and a signal path 1031g-1 formed in the first substrate 1001g-1. The first memory device 1040g-1 may be electrically connected to the signal path 1031g-1 through micro-bumps of the first memory device 1040g-1. The signal transmission line 1011g-1 that electrically connects the host 1010g-1 and the memory controller 1020g-1 may correspond to Figure 1 the first bus 150 shown in the figure. The signal transmission line 1021g-1 that electrically connects the memory controller 1020g-1 and the interface circuit 1030g-1 may correspond to Figure 1The second bus 160 shown. The signal path 1031g-1 between the interface circuit 1030g-1 and the first memory device 1040g-1 may correspond to Figure 1 the third bus 170 shown. The frequency of the signal transmitted through the signal transmission line 1021g-1 may be greater than or equal to the frequency of the signal transmitted through the signal path 1031g-1. The signal may be transmitted through the signal transmission line 1021g-1 at a first clock rate, and the signal may be transmitted through the signal path 1031g-1 at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal transmission line 1021g-1 may include a first data bus, and the signal path 1031g-1 may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus. The first substrate 1001g-1, the first host die 101g, and the first memory device 1040g-1 may be encapsulated in a first package.

[0134] The second host die 102g may include a host 1010g-2, a memory controller 1020g-2, and an interface circuit 1030g-2. The host 1010g-2, the memory controller 1020g-2, and the interface circuit 1030g-2 may be internal circuits of the second host die 102g. The second host die 102g and the second memory device 1040g-2 may be disposed on a second substrate 1001g-2. The second substrate 1001g-2 may include a second interposer. The second host die 102g may be disposed in a first area on the second substrate 1001g-2, and the second memory device 1040g-2 may be disposed in a second area on the second substrate 1001g-2. The first area and the second area may not overlap. The second host die 102g may be electrically connected to the second substrate 1001g-2 through microbumps of the second host die 102g. The second memory device 1040g-2 may be electrically connected to the second substrate 1001g-2 through microbumps of the second memory device 1040g-2. The second substrate 1001g-2 may be disposed on a third substrate 1002g. The second substrate 1001g-2 may be disposed on the third substrate 1002g in an area different from the area where the first substrate 1001g-1 is disposed. The second substrate 1001g-2 may be electrically connected to the third substrate 1002g through microbumps or bumps of the second substrate 1001g-2.

[0135] The host 1010g-2 can be electrically connected to the memory controller 1020g-2 through the signal transmission line 1011g-2 inside the second host die 102g. The memory controller 1020g-2 can be electrically connected to the interface circuit 1030g-2 through the signal transmission line 1021g-2 inside the second host die 102g. The interface circuit 1030g-2 can be electrically connected to the second memory device 1040g-2 through the microbumps of the second host die 102g and the signal path 1031g-2 formed in the second substrate 1001g-2. The second memory device 1040g-2 can be electrically connected to the signal path 1031g-2 through the microbumps of the second memory device 1040g-2. The signal transmission line 1011g-2 that electrically connects the host 1010g-2 and the memory controller 1020g-2 can correspond to Figure 1 the first bus 150 shown. The signal transmission line 1021g-2 that electrically connects the memory controller 1020g-2 and the interface circuit 1030g-2 can correspond to Figure 1 the second bus 160 shown. The signal path 1031g-2 between the interface circuit 1030g-2 and the second memory device 1040g-2 can correspond to Figure 1The third bus 170 shown. The frequency of the signal transmitted through the signal transmission line 1021g-2 may be greater than or equal to the frequency of the signal transmitted through the signal path 1031g-2. The signal may be transmitted through the signal path 1021g-2 at a third clock rate, and the signal may be transmitted through the signal path 1031g-2 at a fourth clock rate. The third clock rate may be greater than or equal to the fourth clock rate. The third clock rate may be equal to or different from the first clock rate. The fourth clock rate may be equal to or different from the second clock rate. The signal transmission line 1021g-2 may include a third data bus, and the signal path 1031g-2 may include a fourth data bus. The number of data signals transmitted at one time through the third data bus may be less than or equal to the number of data signals transmitted at one time through the fourth data bus. In one embodiment, the first substrate 1001g-1, the first host die 101g, and the first memory device 1040g-1 may be encapsulated in a first package. The second substrate 1001g-2, the second host die 102g, and the second memory device 1040g-2 may be encapsulated in a second package. The first package and the second package may be disposed on a third substrate 1002g and encapsulated in a third package, and the integrated circuit package 1000g may be manufactured in a PIP (package-in-package) structure. The host 1010g-1 may be electrically connected to the host 1010g-2 through the microbumps of the first host die 101g, the signal path formed in the first substrate 1001g-1, the microbumps of the first substrate 1001g-1, the signal path of the third substrate 1002g, the microbumps of the second substrate 1001g-2, the signal path of the second substrate 1001g-2, and the microbumps of the second host die 102g.

[0136] Figure 10H FIG. showing the configuration and connection relationship of the integrated circuit package 1000h according to an embodiment of the present disclosure. Refer to Figure 10H , the integrated circuit package 1000h may include a first substrate 1001h, a host 1010h, a memory controller 1020h, an interface circuit 1030h, and a memory device 1040h. The memory device 1040h may include Figures 9B to 9DAny one of the memory devices 930b to 930d shown. The host 1010h and the memory device 1040h may be provided on the first substrate 1001h. The host 1010h may be provided in a first area on the first substrate 1001h, while the memory device 1040h may be provided in a second area on the first substrate 1001h. The first area and the second area may not overlap with each other. The first substrate 1001h may be an active interposer that includes not only a plurality of signal paths but also circuits that perform various functions. The host 1010h may be electrically connected to the first substrate 1001h through the microbumps of the host 1010h. The memory device 1040h may be electrically connected to the first substrate 1001h through the microbumps of the memory device 1040h. The integrated circuit package 1000h may further include a second substrate 1002h. The first substrate 1001h may be provided on the second substrate 1002h. The second substrate 1002h may include an interposer or a package substrate. The first substrate 1001h may be electrically connected to the second substrate 1002h through the microbumps or bumps of the first substrate 1001h. The second substrate 1002h may be electrically connected to an external device through the external terminals of the second substrate 1002h. The external terminals may include microbumps, bumps, solder balls, or package balls. The memory controller 1020h and the interface circuit 1030h may be formed within the first substrate 1001h. The memory controller 1020h and the interface circuit 1030h may be manufactured together with the first substrate 1001h as internal circuits of the first substrate 1001h. The memory controller 1020h and the interface circuit 1030h may be electrically connected to the host 1010h and the memory device 1040h through a plurality of signal paths formed within the first substrate 1001h. The second substrate 1002h, the first substrate 1001h, and the host 1010h and the memory device 1040h provided on the first substrate 1001h may be encapsulated in a single package. In one embodiment, the first area of the first substrate 1001h where the host 1010h is provided may be closer to the area where the memory controller 1020h is provided than the area where the interface circuit 1030h is provided in the first substrate 1001h. The second area of the first substrate 1001h where the memory device 1040h is provided may be closer to the area where the interface circuit 1030h is provided than the area where the memory controller 1020h is provided in the first substrate 1001h.

[0137] The memory controller 1020h can be electrically connected to the host 1010h through the signal path 1011h and the microbumps of the host 1010h. The memory controller 1020h can be electrically connected to the interface circuit 1030h through the signal path 1021h. The interface circuit 1030h can be electrically connected to the memory device 1040h through the signal path 1031h and the microbumps of the memory device 1040h. The signal path 1011h between the host 1010h and the memory controller 1020h can correspond to Figure 1 the first bus 150 shown. The signal path 1021h between the memory controller 1020h and the interface circuit 1030h can correspond to Figure 1 the second bus 160 shown. The signal path 1031h between the interface circuit 1030h and the memory device 1040h can correspond to Figure 1 the third bus 170 shown. The frequency of the signal transmitted through the signal path 1021h can be greater than or equal to the frequency of the signal transmitted through the signal path 1031h. The signal can be transmitted through the signal path 1021h at a first clock rate, and the signal can be transmitted through the signal path 1031h at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal path 1021h can include a first data bus, and the signal path 1031h can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus. In one embodiment, the first substrate 1001h can include part or all of the cache used by the host 1010h. If part or all of the cache used by the host 1010h is formed in the first substrate 1001h, the host 1010h can include processing cores capable of performing more computing functions without increasing the size of the host 1010h. In one embodiment, a low-speed input / output circuit allowing the host 1010h to directly communicate with an external device can also be provided, and the low-speed input / output circuit can be formed in the first substrate 1001h. In one embodiment, a test circuit allowing an external device to directly access the memory device 1040h to test the memory device 1040h can also be provided, and the test circuit can be formed in the first substrate 1001h.

[0138] Figure 10I FIG. is a diagram showing the configuration and connection relationship of the integrated circuit package 1000i according to an embodiment of the present disclosure. Referring to Figure 10I , the integrated circuit package 1000i can include a first substrate 1001i, a host 1010i, a controller die 101i, and a memory device 1040i. The memory device 1040i can include Figures 9B to 9DAny one of the memory devices 930b to 930d shown. The controller die 101i may include a memory controller 1020i and an interface circuit 1030i. The controller die 101i may be fabricated as a die or chiplet separate from the host 1010i. The memory controller 1020i and the interface circuit 1030i may be internal circuits of the controller die 101i. The host 1010i, the controller die 101i, and the memory device 1040i may be disposed on a first substrate 1001i. The first substrate 1001i may include an interposer. The host 1010i may be disposed in a first region on the first substrate 1001i. The controller die 101i may be disposed in a second region on the first substrate 1001i. The memory device 1040i may be disposed in a third region on the first substrate 1001i. The first region and the third region may not overlap with each other. The host 1010i may be electrically connected to the first substrate 1001i through microbumps of the host 1010i. The controller die 101i may be electrically connected to the first substrate 1001i through microbumps of the controller die 101i. The memory device 1040i may be electrically connected to the first substrate 1001i through microbumps of the memory device 1040i. The integrated circuit package 1000i may further include a second substrate 1002i. The first substrate 1001i may be disposed on the second substrate 1002i. The second substrate 1002i may include an interposer or a package substrate. The first substrate 1001i may be electrically connected to the second substrate 1002i through microbumps or bumps of the first substrate 1001i. The second substrate 1002i may be electrically connected to an external device through external terminals of the second substrate 1002i. The external terminals may include microbumps, bumps, solder balls, or package balls. The memory controller 1020i may be electrically connected to the first substrate 1001i through microbumps on a first side of the controller die 101i. The interface circuit 1030i may be electrically connected to the first substrate 1001i through microbumps on a second side of the controller die 101i. The second substrate 1002i, the first substrate 1001i, the host 1010i, the controller die 101i, and the memory device 1040i may be encapsulated in a single package body.

[0139] The host 1010i may be electrically connected to the memory controller 1020i through a signal path 1011i formed in the first substrate 1001i. The memory controller 1020i and the interface circuit 1030i may be electrically connected through a signal path 1021i inside the controller die 101i. The interface circuit 1030i may be electrically connected to the memory device 1040i through a signal path 1031i formed in the first substrate 1001i. The signal path 1011i between the host 1010i and the memory controller 1020i may correspond to Figure 1The first bus 150 shown. The signal path 1021i that electrically connects the memory controller 1020i and the interface circuit 1030i may correspond to Figure 1 the second bus 160 shown. The signal path 1031i between the interface circuit 1030i and the memory device 1040i may correspond to Figure 1 the third bus 170 shown. The frequency of the signal transmitted through the signal path 1021i may be greater than or equal to the frequency of the signal transmitted through the signal path 1031i. The signal may be transmitted through the signal path 1021i at a first clock rate, and the signal may be transmitted through the signal path 1031i at a second clock rate. The first clock rate may be greater than or equal to the second clock rate. The signal path 1021i may include a first data bus, and the signal path 1031i may include a second data bus. The number of data signals transmitted at one time through the first data bus may be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0140] Figure 10J A diagram showing the configuration and connection relationship of the integrated circuit package 1000j according to an embodiment of the present disclosure. Refer to Figure 10J , the integrated circuit package 1000j may include a substrate 1001j, a host die 101j, and a memory device 1040j. The memory device 1040j may include Figure 9B and Figure 9D any one of the memory devices 940b, 940d shown. Through holes may be formed in the memory device 1040j. The host die 101j may include a host 1010j, a memory controller 1020j, and an interface circuit 1030j. The host 1010j, the memory controller 1020j, and the interface circuit 1030j may be internal circuits of the host die 101j. The host die 101j and the memory device 1040j may be disposed on the substrate 1001j. The memory device 1040j may be disposed on the substrate 1001j, and the host die 101j may be disposed on the memory device 1040j. The host die 101j may be electrically connected to the memory device 1040j through the microbumps of the host die 101j. The host die 101j may be electrically connected to the substrate 1001j and the memory device 1040j through the through holes 1041j formed in the memory device 1040j. The memory device 1040j may be electrically connected to the substrate 1001j through the microbumps of the memory device 1040j. The substrate 1001j may include at least one of an interposer, a redistribution layer, and a glass substrate. In one embodiment, the integrated circuit package 1000j may further include another substrate, and the substrate 1001j may be disposed on the another substrate. The substrate 1001j may be electrically connected to an external device through the another substrate. The another substrate may include another interposer or a package substrate.

[0141] The host 1010j can be electrically connected to the memory controller 1020j through the signal transmission line 1011j inside the host die 101j. The host 1010j can be electrically connected to the signal path formed in the substrate 1001j through the micro-bumps of the host die 101j, the vias 1041j formed in the memory device 1040j, and the micro-bumps of the memory device 1040j. The signal path can be electrically connected to another substrate or an external device through the micro-bumps, bumps, solder balls, or package balls on the substrate 1001j. The memory controller 1020j can be electrically connected to the interface circuit 1030j through the signal transmission line 1021j inside the host die 101j. The interface circuit 1030j can be electrically connected to the memory device 1040j through the micro-bumps of the host die 101j and the vias 1031j formed in the memory device 1040j. The signal transmission line 1011j that electrically connects the host 1010j and the memory controller 1020j can correspond to Figure 1 the first bus 150 shown. The signal transmission line 1021j that electrically connects the memory controller 1020j and the interface circuit 1030j can correspond to Figure 1 the second bus 160 shown. The micro-bumps and vias 1031j that electrically connect the interface circuit 1030j and the memory device 1040j can correspond to Figure 1 the third bus 170 shown. The substrate 1001j, the host die 101j, and the memory device 1040j can be encapsulated in a single package. The frequency of the signal transmitted through the signal transmission line 1021j can be greater than or equal to the frequency of the signal transmitted through the via 1031j. The signal can be transmitted through the signal transmission line 1021j at a first clock rate, and the signal can be transmitted through the via 1031j at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal transmission line 1021j can include a first data bus, and the via 1031j can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0142] Figure 10K FIG. is a diagram showing the configuration and connection relationship of the integrated circuit package 1000k according to an embodiment of the present disclosure. Refer to Figure 10K , the integrated circuit package 1000k can include a substrate 1001k, a host die 101k, and a memory device 1040k. The memory device 1040k can include Figures 9B to 9DAny one of the memory devices 930b to 930d shown. The host die 101k may include a host 1010k, a memory controller 1020k, and an interface circuit 1030k. The host 1010k, the memory controller 1020k, and the interface circuit 1030k may be internal circuits of the host die 101k. The host die 101k and the memory device 1040k may be disposed on a substrate 1001k. The substrate 1001k may include a package substrate. The host die 101k may be disposed on the substrate 1001k, and the memory device 1040k may be disposed on the host die 101k. The memory device 1040k may be electrically connected to the host die 101k through micro-bumps of the memory device 1040k. The host die 101k may be electrically connected to the substrate 1001k through wire bonding. In one embodiment, the substrate 1001k may be replaced by an interposer, and the host die 101k may include micro-bumps. The host die 101k may be electrically connected to the interposer through micro-bumps instead of wire bonding, or may be electrically connected to a redistribution layer with or without micro-bumps. The substrate 1001k may be electrically connected to an external device through external terminals (such as solder balls or package balls).

[0143] The host 1010k may be electrically connected to the memory controller 1020k through a signal transmission line 1011k inside the host die 101k. The host 1010k may be electrically connected to an external device through wire bonding between the host die 101k and the substrate 1001k. The memory controller 1020k may be electrically connected to the interface circuit 1030k through a signal transmission line 1021k inside the host die 101k. The interface circuit 1030k may be electrically connected to the memory device 1040k through a signal transmission line 1031k inside the host die 101k and the micro-bumps of the memory device 1040k. The signal transmission line 1011k that electrically connects the host 1010k and the memory controller 1020k may correspond to Figure 1 the first bus 150 shown. The signal transmission line 1021k that electrically connects the memory controller 1020k and the interface circuit 1030k may correspond to Figure 1 the second bus 160 shown. The signal transmission line 1031k and the micro-bumps that electrically connect the interface circuit 1030k and the memory device 1040k may correspond to Figure 1The third bus 170 shown. The frequency of the signal transmitted through the signal transmission line 1021k can be greater than or equal to the frequency of the signal transmitted through the signal transmission line 1031k. The signal can be transmitted through the signal transmission line 1021k at a first clock rate, and the signal can be transmitted through the signal transmission line 1031k at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal transmission line 1021k can include a first data bus, and the signal transmission line 1031k can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus. The substrate 1001k, the host die 101k, and the memory device 1040k can be encapsulated in a single package.

[0144] Figure 10L FIG. is a diagram showing the configuration and connection relationship of an integrated circuit package 1000l according to an embodiment of the present disclosure. Refer to Figure 10L , the integrated circuit package 1000l can include a host die 101l and a memory die 1040l. In Figure 10L , a die can refer to a die, structure, unit module, or chiplet of a single device. The host die 101l can include a host 1010l, a memory controller 1020l, and an interface circuit 1030l. The memory die 1040l can include at least one memory die, and can include Figures 9A to 9D any one of the memory devices 930a to 930d shown in. The host die 101l and the memory die 1040l can be disposed on the base die 1001l and electrically connected to the base die 1001l. The base die 1001l can include signal paths for electrically connecting a plurality of dies mounted on the base die 1001l. The base die 1001l can be disposed on a substrate 1002l. The substrate 1002l can include any one of an interposer, a package substrate, an organic substrate, and a redistribution layer. The host 1010l and the memory controller 1020l can be electrically connected through signal transmission lines inside the host die 101l, and the memory controller 1020l and the interface circuit 1030l can be electrically connected through signal transmission lines inside the host die 101l. The interface circuit 1030l can be electrically connected to the memory die 1040l through a signal path 1031l formed inside the base die 1001l. The signal transmission line electrically connecting the host 1010l and the memory controller 1020l can correspond to Figure 1 the first bus 150 shown in. The signal transmission line electrically connecting the memory controller 1020l and the interface circuit 1030l can correspond to Figure 1The second bus 160 shown. The signal path 1031l formed inside the base die 1001l and electrically connecting the interface circuit 1030l and the memory die 1040l may correspond to Figure 1 The third bus 170 shown. Some or all of the host die 101l and the memory die 1040l may be manufactured using process technologies with different characteristics. The host die 101l, the memory die 1040l, the base die 1001l, and the substrate 1002l may be encapsulated in a package to form a single semiconductor device.

[0145] Figure 10M FIG. is a diagram showing the configuration and connection relationship of the integrated circuit package 1000m according to an embodiment of the present disclosure. Refer to Figure 10M , the integrated circuit package 1000m may include a plurality of host dies and a plurality of memory dies. The integrated circuit package 1000m may include a first host die 101m-1, a second host die 101m-2, a first memory die 1040m-1, and a second memory die 1040m-2. The first host die 101m-1 may include a first host 1010m-1, a first memory controller 1020m-1, and a first interface circuit 1030m-1. The second host die 101m-2 may include a second host 1010m-2, a second memory controller 1020m-2, and a second interface circuit 1030m-2. The first memory die 1040m-1 may include at least one memory die, and may include Figures 9B to 9D Any one of the memory devices 930b to 930d shown in. The second memory die 1040m-2 may include at least one memory die, and may include Figures 9A to 9D Any one of the memory devices 930a to 930d shown in. The second memory die 1040m-2 may have substantially the same structure as the first memory die 1040m-1, or may have a different structure from the first memory die 1040m-1. In one embodiment, the first host die 101m-1 may further include a first host interface 1050m-1, and the second host die 101m-2 may further include a second host interface 1050m-2. The first host die 101m-1 and the second host die 101m-2 may be electrically connected through the first host interface 1050m-1 and the second host interface 1050m-2.

[0146] The first host shard 101m-1, the second host shard 101m-2, the first memory shard 1040m-1, and the second memory shard 1040m-2 can be disposed on and electrically connected to the base shard 1001m. The base shard 1001m may include signal paths for electrically connecting a plurality of shards mounted on the base shard 1001m. Although not shown, a plurality of signal paths may be formed within the base shard 1001m for electrically connecting the first host shard 101m-1 and the second host shard 101m-2, the first host shard 101m-1 and the first memory shard 1040m-1, and the second host shard 101m-2 and the second memory shard 1040m-2. The base shard 1001m may be disposed on the substrate 1002m. The substrate 1002m may include any one of an interposer, a package substrate, an organic substrate, and a redistribution layer. The first host 1010m-1 and the first memory controller 1020m-1 may be electrically connected through signal transmission lines inside the first host shard 101m-1, and the first memory controller 1020m-1 and the first interface circuit 1030m-1 may be electrically connected through signal transmission lines inside the first host shard 101m-1. The first interface circuit 1030m-1 may be electrically connected to the first memory shard 1040m-1 through a signal path 1031m-1 formed in the base shard 1001m. The second host 1010m-2 and the second memory controller 1020m-2 may be electrically connected through signal transmission lines inside the second host shard 101m-2, and the second memory controller 1020m-2 and the second interface circuit 1030m-2 may be electrically connected through signal transmission lines inside the second host shard 101m-2. The second interface circuit 1030m-2 may be electrically connected to the second memory shard 1040m-2 through a signal path 1031m-2 formed in the base shard 1001m. The first host shard 101m-1 may be electrically connected to the second host shard 101m-2 through a signal path 1051m formed in the base shard 1001m. The signal path 1051m may electrically connect between the first host interface 1050m-1 and the second host interface 1050m-2. The signal transmission lines electrically connecting the first host 1010m-1 and the first memory controller 1020m-1 and the signal transmission lines electrically connecting the second host 1010m-2 and the second memory controller 1020m-2 may respectively correspond to Figure 1 the first bus 150 shown. The signal transmission lines electrically connecting the first memory controller 1020m-1 and the first interface circuit 1030m-1 and the signal transmission lines electrically connecting the second memory controller 1020m-2 and the second interface circuit 1030m-2 may respectively correspond to Figure 1The second bus 160 shown. The signal path formed in the base die 1001m that electrically connects the first interface circuit 1030m-1 and the first memory die 1040m-1 and the signal path that electrically connects the second interface circuit 1030m-2 and the second memory die 1040m-2 can respectively correspond to Figure 1 the third bus 170 shown. The first host die 101m-1, the second host die 101m-2, the first memory die 1040m-1, the second memory die 1040m-2, the base die 1001m, and the substrate 1002m can be encapsulated in a single package to form a single semiconductor device.

[0147] Figure 10N A diagram showing the configuration and connection relationship of the integrated circuit package 1000n according to an embodiment of the present disclosure. Refer to Figure 10N , the integrated circuit package 1000n can include at least one host, a plurality of controller dies, and a plurality of memory devices. In Figure 10NIn [the figure], the integrated circuit package 1000n is shown as including six controller dies and six memory devices, but this exemplary illustration is not intended to limit the number of controller dies and memory devices included in the integrated circuit package 1000n. The integrated circuit package 1000n may include two, four, eight or more controller dies, and may include two, four, eight or more memory devices electrically connected to each controller die. In one embodiment, the number of memory devices electrically connected to one controller die may be two or more. The integrated circuit package 1000n may include a host 1010n, a first controller die 101n-1, a second controller die 101n-2, a third controller die 101n-3, a fourth controller die 101n-4, a fifth controller die 101n-5, a sixth controller die 101n-6, a first memory device 1040n-1, a second memory device 1040n-2, a third memory device 1040n-3, a fourth memory device 1040n-4, a fifth memory device 1040n-5, and a sixth memory device 1040n-6. The host 1010n may be fabricated as a single die or in pieces, and may include multiple processing cores. The host 1010n may be fabricated as a core complex die that includes at least two processing cores. Each of the first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 may be fabricated as a single die or in pieces. Each of the first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 may include a memory controller MC and an interface circuit IF. The memory controller MC and the interface circuit IF of the first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 may be electrically connected respectively through signal transmission paths inside the first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6. Each of the first through sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 may include at least one memory die. Each of the first through sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 may include Figures 9A to 9DAt least one of the memory devices 940a to 940d shown. All of the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 may have the same structure, or some or all of the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 may have different structures.

[0148] The host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can be disposed on the first substrate 1001n. The first substrate 1001n may include an interposer. The first substrate 1001n may include signal paths for electrically connecting the host 1010n to the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 respectively, and signal paths for electrically connecting the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 to the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 respectively. In one embodiment, the first substrate 1001n may be replaced by a base die, and the host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 may all be fabricated as separate and independent dies electrically connected to the base die. The integrated circuit package 1000n may further include a second substrate 1002n, and the first substrate 1001n may be disposed on the second substrate 1002n. The second substrate 1002n may include an interposer or a package substrate. The memory controller MC of the host 1010n and the first controller die 101n-1 may be electrically connected through the signal path formed in the first substrate 1001n. The interface circuit IF of the first controller die 101n-1 and the first memory device 1040n-1 may be electrically connected through the signal path formed in the first substrate 1001n. The memory controller MC of the host 1010n and the second controller die 101n-2 may be electrically connected through the signal path formed in the first substrate 1001n. The interface circuit IF of the second controller die 101n-2 and the second memory device 1040n-2 may be electrically connected through the signal path formed in the first substrate 1001n. The memory controller MC of the host 1010n and the third controller die 101n-3 may be electrically connected through the signal path formed in the first substrate 1001n. The interface circuit IF of the third controller die 101n-3 and the third memory device 1040n-3 may be electrically connected through the signal path formed in the first substrate 1001n.The memory controller MC of the host 1010n and the fourth controller die 101n-4 can be electrically connected through a signal path formed in the first substrate 1001n. The interface circuit IF of the fourth controller die 101n-4 and the fourth memory device 1040n-4 can be electrically connected through a signal path formed in the first substrate 1001n. The memory controller MC of the host 1010n and the fifth controller die 101n-5 can be electrically connected through a signal path formed in the first substrate 1001n. The interface circuit IF of the fifth controller die 101n-5 and the fifth memory device 1040n-5 can be electrically connected through a signal path formed in the first substrate 1001n. The memory controller MC of the host 1010n and the sixth controller die 101n-6 can be electrically connected through a signal path formed in the first substrate 1001n. The interface circuit IF of the sixth controller die 101n-6 and the sixth memory device 1040n-6 can be electrically connected through a signal path formed in the first substrate 1001n. The signal paths respectively electrically connecting the memory controller MC of the host 1010n and the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 can all correspond to. Figure 1 the first bus 150 shown. The signal transmission lines respectively electrically connecting the memory controller MC and the interface circuit IF of the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 can all correspond to Figure 1 the second bus 160 shown. The signal paths respectively electrically connecting the interface circuit IF of the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can all correspond to Figure 1 the third bus 170 shown. The host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6, the first substrate 1001n and the second substrate 1002n can be encapsulated in a package to form a single semiconductor device.

[0149] Figure 11 is a diagram showing the configuration of the computing system 1100 according to an embodiment of the present disclosure. Refer to Figure 11, the computing system 1100 can be computing logic hardware, which includes at least one of a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a data processing unit (DPU), a vision processing unit (VPU), a neural processing unit (NPU), and an application-specific integrated circuit (ASIC) as a computing architecture suitable for executing various application programs executed by a user. The computing system 1100 can include a host 1110, a first memory controller 1121, a second memory controller 1122, a third memory controller 1123, a fourth memory controller 1124, a first interface circuit 1131, a second interface circuit 1132, a third interface circuit 1133, a fourth interface circuit 1134, a first memory device 1141, a second memory device 1142, a third memory device 1143, and a fourth memory device 1144. The host 1110 can generate access requests to access the first to fourth memory devices 1141, 1142, 1143, 1144 for data communication. The host 1110 can selectively access at least one of the first to fourth memory devices 1141, 1142, 1143, 1144, and can simultaneously access at least two of the first to fourth memory devices 1141, 1142, 1143, 1144. The host 1110 can include a processing core 1111 and a cache 1112. The processing core 1111 can generate multiple access requests to access each of the first to fourth memory devices 1141, 1142, 1143, 1144 to perform the computing operations required to run an application program. The processing core 1111 can include at least one core. The processing core 1111 can include one core, and this one core can generate multiple access requests to access the first to fourth memory devices 1141, 1142, 1143, 1144 one by one or simultaneously. The processing core 1111 can include two or more cores, and the two or more cores can independently generate multiple access requests for accessing one or more of the first to fourth memory devices 1141, 1142, 1143, 1144. The cache 1112 can be configured as a computer memory buffer for alleviating the speed difference in operation between the host 1110 and the first to fourth memory devices 1141, 1142, 1143, 1144. The cache 1112 can improve the operation speed and / or performance of the host 1110 because if the data or computing results required by the processing core 1111 are stored in the cache 1112, the processing core 1111 does not need to access the first to fourth memory devices 1141, 1142, 1143, 1144.

[0150] The host 1110 can be electrically connected to the first memory controller 1121 via the first host bus 1151. The host 1110 can transmit access requests and data to the first memory controller 1121 via the first host bus 1151 to access the first memory device 1141, and can receive data from the first memory controller 1121. The host 1110 can be electrically connected to the second memory controller 1122 via the second host bus 1152. The host 1110 can transmit access requests and data to the second memory controller 1122 via the second host bus 1152 to access the second memory device 1142, and can receive data from the second memory controller 1122. The host 1110 can be electrically connected to the third memory controller 1123 via the third host bus 1153. The host 1110 can transmit access requests and data to the third memory controller 1123 via the third host bus 1153 to access the third memory device 1143, and can receive data from the third memory controller 1123. The host 1110 can be electrically connected to the fourth memory controller 1124 via the fourth host bus 1154. The host 1110 can transmit access requests and data to the fourth memory controller 1124 via the fourth host bus 1154 to access the fourth memory device 1144, and can receive data from the fourth memory controller 1124. Figure 1 The first bus 150 shown in Figure 1 can be used as each of the first to fourth host buses 1151, 1152, 1153, 1154, and each of the first to fourth host buses 1151, 1152, 1153, 1154 can have substantially the same characteristics as the first bus 150.

[0151] The first memory controller 1121 can be electrically connected to the first interface circuit 1131 through the first controller bus 1161. The first memory controller 1121 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The first memory controller 1121 can transmit the command signals, address signals, and write data signals to the first interface circuit 1131 through the first controller bus 1161, and can receive read data signals from the first interface circuit 1131. The first memory controller 1121 can generate data to be transmitted to the host 1110 through the first host bus 1151 based on the read data signals. The second memory controller 1122 can be electrically connected to the second interface circuit 1132 through the second controller bus 1162. The second memory controller 1122 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The second memory controller 1122 can transmit the command signals, address signals, and write data signals to the second interface circuit 1132 through the second controller bus 1162, and can receive read data signals from the second interface circuit 1132. The second memory controller 1122 can generate data to be transmitted to the host 1110 through the second host bus 1152 based on the read data signals. The third memory controller 1123 can be electrically connected to the third interface circuit 1133 through the third controller bus 1163. The third memory controller 1123 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The third memory controller 1123 can transmit the command signals, address signals, and write data signals to the third interface circuit 1133 through the third controller bus 1163, and can receive read data signals from the third interface circuit 1133. The third memory controller 1123 can generate data to be transmitted to the host 1110 through the third host bus 1153 based on the read data signals. The fourth memory controller 1124 can be electrically connected to the fourth interface circuit 1134 through the fourth controller bus 1164. The fourth memory controller 1124 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The fourth memory controller 1124 can transmit the command signals, address signals, and write data signals to the fourth interface circuit 1134 through the fourth controller bus 1164, and can receive read data signals from the fourth interface circuit 1134. The fourth memory controller 1124 can generate data to be transmitted to the host 1110 through the fourth host bus 1154 based on the read data signals. Figure 1The second bus 160 shown in the figure may be applied as each of the first to fourth controller buses 1161, 1162, 1163, and 1164, and each of the first to fourth controller buses 1161, 1162, 1163, and 1164 may have substantially the same characteristics as the second bus 160.

[0152] The first interface circuit 1131 can be electrically connected to the first memory device 1141 through the first memory bus 1171. The first interface circuit 1131 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on the command signal, address signal, and write data signal received from the first memory controller 1121 through the first controller bus 1161. The first interface circuit 1131 can transmit the row address signal, column address signal, command signal, and memory data signal to the first memory device 1141 through the first memory bus 1171. The first interface circuit 1131 can receive the memory data signal transmitted from the first memory device 1141 through the first memory bus 1171, and can generate a read data signal based on the memory data signal. The first interface circuit 1131 can transmit the read data signal to the first memory controller 1121 through the first controller bus 1161. The second interface circuit 1132 can be electrically connected to the second memory device 1142 through the second memory bus 1172. The second interface circuit 1132 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on the command signal, address signal, and write data signal received from the second memory controller 1122 through the second controller bus 1162. The second interface circuit 1132 can transmit the row address signal, column address signal, command signal, and memory data signal to the second memory device 1142 through the second memory bus 1172. The second interface circuit 1132 can receive the memory data signal transmitted from the second memory device 1142 through the second memory bus 1172, and can generate a read data signal based on the memory data signal. The second interface circuit 1132 can transmit the read data signal to the second memory controller 122 through the second controller bus 1162. The third interface circuit 1133 can be electrically connected to the third memory device 1143 through the third memory bus 1173. The third interface circuit 1133 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on the command signal, address signal, and write data signal received from the third memory controller 1123 through the third controller bus 1163. The third interface circuit 1133 can transmit the row address signal, column address signal, command signal, and memory data signal to the third memory device 1143 through the third memory bus 1173. The third interface circuit 1133 can receive the memory data signal transmitted from the third memory device 1143 through the third memory bus 1173, and can generate a read data signal based on the memory data signal. The third interface circuit 1133 can transmit the read data signal to the third memory controller 1123 through the third controller bus 1163. The fourth interface circuit 1134 can be electrically connected to the fourth memory device 1144 through the fourth memory bus 1174.The fourth interface circuit 1134 may generate a row address signal, a column address signal, a command signal, and a memory data signal based on command signals, address signals, and write data signals received from the fourth memory controller 1124 via the fourth controller bus 1164. The fourth interface circuit 1134 may transmit the row address signal, the column address signal, the command signal, and the memory data signal to the fourth memory device 1144 via the fourth memory bus 1174. The fourth interface circuit 1134 may receive a memory data signal transmitted from the fourth memory device 1144 via the fourth memory bus 1174, and may generate a read data signal based on the memory data signal. The fourth interface circuit 1134 may transmit the read data signal to the fourth memory controller 1124 via the fourth controller bus 1164. Figure 1 The third bus 170 shown may be used as each of the first to fourth memory buses 1171, 1172, 1173, 1174, and each of the first to fourth memory buses 1171, 1172, 1173, 1174 may have substantially the same characteristics as the third bus 170.

[0153] Each of the first to fourth memory devices 1141, 1142, 1143, 1144 may include at least one memory die. When each of the first to fourth memory devices 1141, 1142, 1143, 1144 includes two or more memory dies, the first to fourth memory devices 1141, 1142, 1143, 1144 may each have a stacked die structure. The two or more memory dies may be electrically connected to each other by wire bonding or via vias.

[0154] In one embodiment, the host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, and the first to fourth interface circuits 1131, 1132, 1133, 1134 may be integrated into a first device, while the first to fourth memory devices 1141, 1142, 1143, 1144 may respectively constitute second to fifth devices. In one embodiment, the host 1110 and the first to fourth memory controllers 1121, 1122, 1123, 1124 may be integrated into a first device, the first interface circuit 1131 and the first memory device 1141 may be integrated into a second device. The second interface circuit 1132 and the second memory device 1142 may be integrated into a third device, the third interface circuit 1133 and the third memory device 1143 may be integrated into a fourth device, and the fourth interface circuit 1134 and the fourth memory device 1144 may be integrated into a fifth device. In one embodiment, the host 1110 may constitute a first device, while the first memory controller 1121, the first interface circuit 1131, and the first memory device 1141 may be integrated into a second device. The second memory controller 1122, the second interface circuit 1132, and the second memory device 1142 may be integrated into a third device. The third memory controller 1123, the third interface circuit 1133, and the third memory device 1143 may be integrated into a fourth device. The fourth memory controller 1124, the fourth interface circuit 1134, and the fourth memory device 1144 may be integrated into a fifth device. In one embodiment, the host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, the first to fourth interface circuits 1131, 1132, 1133, 1134, and the first to fourth memory devices 1141, 1142, 1143, 1144 may all be manufactured as independent semiconductor devices. The host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, the first to fourth interface circuits 1131, 1132, 1133, 1134, and the first to fourth memory devices 1141, 1142, 1143, 1144 may be manufactured as dies or chips and mounted on at least one base die or base chip.

[0155] The first memory device 1141 can perform parallel data communication with the first interface circuit 1131 and the first memory controller 1121 via the first memory bus 1171. The second memory device 1142 can perform parallel data communication with the second interface circuit 1132 and the second memory controller 1122 via the second memory bus 1172. The third memory device 1143 can perform parallel data communication with the third interface circuit 1133 and the third memory controller 1123 via the third memory bus 1173. The fourth memory device 1144 can perform parallel data communication with the fourth interface circuit 1134 and the fourth memory controller 1124 via the fourth memory bus 1174. In one embodiment, at least one of the first to fourth memory buses 1171, 1172, 1173, 1174 may have characteristics different from those of the third bus 170. For example, the width of the fourth memory bus 1174 may be smaller than the width of the fourth controller bus 1164, while the clock rate of the fourth memory bus 1174 may be higher than the clock rate of the fourth controller bus 1164. When the first to third memory devices 1141, 1142, 1143 perform parallel data communication via the first to third memory buses 1171, 1172, 1173, the fourth memory device 1144 can perform serial data communication via the fourth memory bus 1174. When the fourth memory device 1144 performs serial data communication, the fourth memory device 1144 and the fourth interface circuit 1134 may be equipped with SerDes for converting parallel data into serial data or converting serial data into parallel data.

[0156] Figure 12 FIG. is a diagram showing the configuration of a computing system 1200 according to an embodiment of the present disclosure. Refer to Figure 12 FIG., the computing system 1200 may include a main host 1211, a sub-host 1212, a first memory controller 1221, a first interface circuit 1231, a first memory device 1241, a second memory controller 1222, a second interface circuit 1232, and a second memory device 1242. The main host 1211 may generate an access request for accessing the first memory device 1241, and may provide the access request to the first memory controller 1221. The main host 1211 may be electrically connected to the first memory controller 1221 via the first host bus 1251, and may provide the access request to the first memory controller 1221 via the first host bus 1251. The first host bus 1251 may have the same as Figure 1The first bus 150 shown has substantially the same characteristics. The main host 1211 can perform a variety of computing operations and can access the sub-host 1212 to execute all or part of the computing operations in parallel. For example, the main host 1211 can execute a part of the total workload, while the sub-host 1212 can be controlled by the main host 1211 to execute the remaining workload in the total workload. The sub-host 1212 can have the same type of processing cores as the main host 1211 or can have different types of processing cores from the main host 1211. In one embodiment, the sub-host 1212 can be controlled by the main host 1211 to perform a function that increases the memory capacity available to the main host 1211. The sub-host 1212 can accelerate the computing performance and / or speed of the main host 1211 by providing additional data required for the computing operations of the main host 1211. The sub-host 1212 can be, for example, a Compute eXpress Link (CXL) core. The main host 1211 can be electrically connected to the sub-host 1212 via the system bus 1201 and can provide control signals for controlling the sub-host 1212 via the system bus 1201. The sub-host 1212 can generate an access request for accessing the second memory device 1242 based on the control signal provided by the main host 1211 and can provide the access request to the second memory controller 1222. The system bus 1201 can include a standard protocol for electrically connecting the main host 1211 and the sub-host 1212.

[0157] The sub-host 1212 can generate an access request for accessing the second memory device 1242 and can provide the access request to the second memory controller 1222. The sub-host 1212 can be electrically connected to the second memory controller 1222 via the second host bus 1252 and can transmit the access request to the second memory controller 1222 via the second host bus 1252. The second host bus 1252 can have substantially the same characteristics as the first host bus 1251. In one embodiment, the second host bus 1252 can have different characteristics from the first host bus 1251 and can use a standard protocol with different specifications compared to the first host bus 1251.

[0158] The first memory controller 1221 can be electrically connected to the first interface circuit 1231 via the first controller bus 1261. The first interface circuit 1231 can be electrically connected to the first memory device 1241 via the first memory bus 1271. The first controller bus 1261 can have the same characteristics as Figure 1 the second bus 160 shown, while the first memory bus 1271 can have the same characteristics as Figure 1The third bus 170 shown has substantially the same characteristics. In one embodiment, the width of the data bus included in the first controller bus 1261 may be less than or equal to the width of the data bus included in the first memory bus 1271. The second memory controller 1222 may be electrically connected to the second interface circuit 1232 through the second controller bus 1262. The second interface circuit 1232 may be electrically connected to the second memory device 1242 through the second memory bus 1272. The second controller bus 1262 may have substantially the same characteristics as the first controller bus 1261, and the second memory bus 1272 may have substantially the same characteristics as the first memory bus 1271. In one embodiment, the width of the data bus included in the second controller bus 1262 may be less than or equal to the width of the data bus included in the second memory bus 1272.

[0159] In one embodiment, the first controller bus 1261 and the first memory bus 1271 may respectively have substantially the same characteristics as the second bus 160 and the third bus 170, while the second controller bus 1262 and the second memory bus 1272 may have characteristics different from those of the first controller bus 1261 and the first memory bus 1271. For example, the first memory device 1241 may perform parallel data communication with the first interface circuit 1231, while the second memory device 1242 may perform serial data communication with the second interface circuit 1232. The width of the data bus included in the second memory bus 1272 may be less than the width of the data bus included in the second controller bus 1262. The clock rate of the second memory bus 1272 may be higher than the clock rate of the second controller bus 1262. In one embodiment, the second controller bus 1262 and the second memory bus 1272 may respectively have substantially the same characteristics as the second bus 160 and the third bus 170, while the first controller bus 1261 and the first memory bus 1271 may have characteristics different from those of the second controller bus 1262 and the second memory bus 1272. For example, the second memory device 1242 may perform parallel data communication with the second interface circuit 1232, while the first memory device 1241 may perform serial data communication with the first interface circuit 1231. The width of the first memory bus 1271 may be less than the width of the first controller bus 1261, and the clock rate of the first memory bus 1271 may be higher than the clock rate of the first controller bus 1261.

[0160] In one embodiment, the sub-host 1212, the second memory controller 1222, the second interface circuit 1232, and the second memory device 1242 may be disposed on a single interposer and / or substrate and may be fabricated as a single semiconductor device. The sub-host 1212, the second memory controller 1222, and the second interface circuit 1232 may perform the functions of a dedicated controller device to allow the second memory device 1242 to communicate data with an external host device (e.g., the main host 1211). The single semiconductor device may be fabricated as a dual in-line memory module (DIMM) to provide a large amount of data storage space to the main host 1211. For example, the single semiconductor device may be a managed DRAM solution (MDS). In one embodiment, the sub-host 1212, the second memory controller 1222, the second interface circuit 1232, and the second memory device 1242 may be fabricated as separate dies, shards, or dielets.

[0161] Figures 13A to 13C is a diagram showing the configuration of a semiconductor device 1300a according to an embodiment of the present disclosure. Figure 13A is a conceptual plan view of the semiconductor device 1300a, Figure 13B is a cross-sectional view of the semiconductor device 1300a, while Figure 13C is a perspective view of the semiconductor device 1300a. The semiconductor device 1300a may be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300a may include a controller device 1310a and a plurality of memory media MD. The semiconductor device 1300a may include a module substrate 1301a. The module substrate 1301a may include module pins 1304a and may communicate with an external device through the module pins 1304a. For example, the external device may be Figure 12 the main host 1211 shown in Figure 12The system bus 1201 shown in [figure]. The semiconductor device 1300a can be electrically connected to an external device via the module pins 1304a by inserting the module pins 1304a into slots and / or channels formed in the motherboard. The package substrate 1303a can be mounted on the module substrate 1301a, and the package substrate 1303a can be electrically connected to the module substrate 1301a through package balls and / or solder balls. On the package substrate 1303a, an interposer 1302a can be stacked. The interposer 1302a can be electrically connected to the package substrate 1303a using bumps. The controller device 1310a and multiple memory media MD can be disposed on the interposer 1302a. The package substrate 1303a, the interposer 1302a, the controller device 1310a, and the multiple memory media MD can be encapsulated in a single package body, and the single package body can be mounted on the module substrate 1301a. The controller device 1310a can be disposed on the interposer 1302a and is electrically connected to the interposer 1302a through micro-bumps. The multiple memory media MD can be disposed on the interposer 1302a. The controller device 1310a can be disposed in a first area on the interposer 1302a, and the multiple memory media MD can be disposed in a second area on the interposer 1302a. The first area and the second area may not overlap with each other.

[0162] The host H can be electrically connected to the module substrate 1301a and the external device through the system bus 1340a. The host H can be electrically connected to the memory controller MC through the host bus 1311a. The memory controller MC can be electrically connected to the interface circuit IF through the controller bus 1321a, and the interface circuit IF can be electrically connected to each of the multiple memory media MD through multiple memory buses 1331a. The controller bus 1321a can have substantially the same characteristics as Figure 1 the second bus 160 shown in [figure], and each of the multiple memory buses 1331a can have substantially the same characteristics as Figure 1 the third bus 170 shown in [figure]. Each of the multiple memory media MD can perform parallel data communication with the interface circuit IF. The interface circuit IF can perform parallel data communication with the memory controller MC, or can perform partial parallel data communication. The width of each of the multiple memory buses 1331a can be greater than or equal to the width of the controller bus 1321a, and the clock rate of each of the multiple memory buses 1331a can be less than or equal to the clock rate of the controller bus 1321a.

[0163] The controller device 1310a can relay data communication between the external device and the multiple memory media MD. The controller device 1310a can include the host H, the memory controller MC, and the interface circuit IF. The host H can correspond to Figure 12For the sub-host 1212 shown, the memory controller MC may correspond to Figure 12 the second memory controller 1222 shown, and the interface circuit IF may correspond to Figure 12 the second interface circuit 1232 shown. Redundant descriptions of corresponding components will be omitted. The controller device 1310a may be electrically connected to a plurality of memory media MD, and may perform data communication with the plurality of memory media MD. The controller device 1310a may be electrically connected to each of the plurality of memory media MD through the interface circuit IF. Each of the plurality of memory media MD may correspond to Figure 12 the second memory device 1242 shown. The plurality of memory media MD may form independent channels and may be electrically connected to the interface circuit IF of the controller device 1310a through independent memory buses respectively. In Figures 13A to 13C , the semiconductor device 1300a is shown as having eight memory media, but the number of memory media that the semiconductor device 1300a has may be less than eight or more than eight. Each of the plurality of memory media MD may include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies may be stacked to form a single memory medium. In Figure 13B and Figure 13C , one memory medium includes eight memory dies, but the number of memory dies included in one memory medium may be less than or greater than eight.

[0164] The controller device 1310a may be electrically connected to the module substrate 1301a through the signal path 1342a formed in the interposer 1302a and the signal path 1351a formed in the package substrate 1303a. The controller device 1310a may be electrically connected to the pad 1305a formed in the interposer 1302a through the signal path 1341a formed in the interposer 1302a. The host H may be electrically connected to the module substrate 1301a through the signal path 1342a and the signal path 1351a. The interface circuit IF may be electrically connected to the pad 1305a through the signal path 1341a. The plurality of memory media MD may be electrically connected to the pad 1305a through wire bonds W1a respectively. The plurality of memory media MD may be electrically connected to the controller device 1310a through the wire bonds W1a and the signal path 1341a. The interface circuit IF may be electrically connected to the plurality of memory media MD through the signal path 1341a and the wire bonds W1a respectively. The signal path 1341a and the wire bonds W1a may correspond to the plurality of memory buses 1331a.

[0165] The first memory die D1 of the memory medium MD can be bonded to the interposer 1302a using DAF. The second to eighth memory dies D2, D3, D4, D5, D6, D7, D8 can also be sequentially bonded to the first to seventh memory dies D1, D2, D3, D4, D5, D6, D7 using DAF respectively. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected using wire bonding. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected to the interposer 1302a by wire bonding to the pads 1305a. The pads 1305a can be electrically connected to the controller device 1310a through the signal path 1341a. The interface circuit IF can be electrically connected to the signal path 1341a through micro-bumps, so that an electrical connection can be formed between the interface circuit IF and the memory die. The frequency of the signals transmitted through the controller bus 1321a between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of the signals transmitted through the signal path 1341a and the wire bonding W1a between the interface circuit IF and the memory medium MD. The controller bus 1321a can include a first data bus that electrically connects the memory controller MC and the interface circuit IF, and the signal path 1341a can include a second data bus that electrically connects the interface circuit IF and the memory medium MD. The width of the first data bus can be less than or equal to the width of the second data bus.

[0166] The semiconductor device 1300a can further include a power management integrated circuit PMIC 1330a. The power management integrated circuit PMIC can be disposed on the module substrate 1301a. In one embodiment, the power management integrated circuit PMIC can be disposed on the interposer 1302a. The power management integrated circuit PMIC can receive an externally applied power voltage through the module pins 1304a, and can generate a plurality of internal voltages based on the power voltage. The power management integrated circuit PMIC can generate a plurality of internal voltages by changing or adjusting the voltage level of the externally applied power voltage. The plurality of internal voltages can be applied to the host H, the memory controller MC, the interface circuit IF, and the memory medium MD, and can be used as the operating power voltages for the components of the semiconductor device 1300a. The power management integrated circuit PMIC can independently generate internal voltages for the host H, the memory controller MC, the interface circuit IF, and the memory medium MD, and the internal voltages can have different voltage levels. In one embodiment, at least two of the internal voltages can have the same voltage level, and the remaining internal voltages can have different voltage levels.

[0167] In one embodiment, the first through eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 may be stacked in a vertical direction using vias and may be electrically connected to the interposer 1302a and adjacent memory dies through microbumps. When the first through eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 are stacked on the interposer 1302a using microbumps, the interposer 1302a should be implemented as a silicon interposer. However, if the first through eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 are stacked using wire bonding and multiple memory media MD perform parallel data communication with the controller device 1310a, the interposer 1302a may be an organic interposer instead of a silicon interposer, and the organic interposer is less expensive than the silicon interposer. Therefore, if multiple memory media MD are stacked using wire bonding, the manufacturing cost of the semiconductor device 1300a can be reduced. In addition, if multiple memory media MD perform parallel data communication with the controller device 1310a, the bandwidth of the memory bus 1331a can be expanded, so that more data can be received from or transmitted to the controller device 1310a in a shorter time.

[0168] Figures 14A to 14C is a diagram showing the configuration of a semiconductor device 1300b according to an embodiment of the present disclosure. Figure 14A may be a conceptual plan view of the semiconductor device 1300b, Figure 14B may be a cross-sectional view of the semiconductor device 1300b, and Figure 14C may be a perspective view of the semiconductor device 1300b. The semiconductor device 1300b may be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300b may include a controller device 1310b and multiple memory media MD. The semiconductor device 1300b may include a module substrate 1301b. The module substrate 1301b may include module pins 1304b and may communicate with an external device through the module pins 1304b. For example, the external device may be Figure 12 the main host 1211 shown, and the module pins 1304b may be electrically connected to Figure 12The system bus 1201 shown. The semiconductor device 1300b can be electrically connected to an external device via a motherboard by inserting module pins 1304b into slots and / or channels formed in the motherboard. The package substrate 1303b can be mounted on the module substrate 1301b, and the package substrate 1303b can be electrically connected to the module substrate 1301b by package balls and / or solder balls. On the package substrate 1303b, an interposer 1302b can be stacked. The interposer 1302b can be electrically connected to the package substrate 1303b using bumps. The controller device 1310b and a plurality of memory media MD can be provided on the interposer 1302b. The package substrate 1303b, the interposer 1302b, the controller device 1310b, and the plurality of memory media MD can be encapsulated in a single package body, and the single package body can be mounted on the module substrate 1301b. The controller device 1310b can be provided on the interposer 1302b and be electrically connected to the interposer 1302b by micro-bumps. The plurality of memory media MD can be provided on the interposer 1302b. The controller device 1310b can be provided in a first area on the interposer 1302b, and the plurality of memory media MD can be provided in a second area and a third area on the interposer 1302b. The first area, the second area, and the third area may not overlap with each other. For example, some of the plurality of memory media MD can be provided in the second area, and the remaining portions of the plurality of memory media MD can be provided in the third area.

[0169] The controller device 1310b can relay data communication between an external device and the plurality of memory media MD. The controller device 1310b can include a host H, a memory controller MC, and an interface circuit IF. The host H can correspond to Figure 12 the sub-host 1212 shown, the memory controller MC can correspond to Figure 12 the second memory controller 1222 shown, and the interface circuit IF can correspond to Figure 12 the second interface circuit 1232 shown. Repeated descriptions of corresponding components will be omitted. The controller device 1310b can be electrically connected to the plurality of memory media MD and can communicate data with the plurality of memory media MD. The controller device 1310b can be electrically connected to each of the plurality of memory media MD through the interface circuit IF. Each of the plurality of memory media MD can correspond to Figure 12 the second memory device 1242 shown. The plurality of memory media MD can form independent channels and can each be electrically connected to the interface circuit IF of the controller device 1310b through an independent memory bus. In Figures 14A to 14CIn [the figure], the semiconductor device 1300b is shown as having sixteen memory media, but the number of memory media that the semiconductor device 1300b has may be less than sixteen or more than sixteen. Each of the plurality of memory media MD may include at least one memory die. When each of the plurality of memory media includes two or more memory dies, the two or more memory dies may be stacked to form a single memory medium. In Figure 14B and Figure 14C [the figure], one memory medium is shown as including four memory dies, but the number of memory dies included in one memory medium may be less than or more than four.

[0170] The host H may be electrically connected to the module substrate 1301b and the external device through the system bus 1340b. The host H may be electrically connected to the memory controller MC through the host bus 1311b. The memory controller MC is electrically connected to the interface circuit IF through the controller bus 1321b, and the interface circuit IF may be electrically connected to the plurality of memory media MD through the plurality of memory buses 1331b, 1332b, respectively. The controller bus 1321b may have substantially the same characteristics as the second bus 160 shown in Figure 1 [the figure], and each of the plurality of memory buses 1331b, 1332b may have substantially the same characteristics as the third bus 170 shown in Figure 1 [the figure]. Each of the plurality of memory media MD may perform parallel data communication with the interface circuit IF. The interface circuit IF may perform parallel data communication with the memory controller MC, or may perform partial parallel data communication. The width of each of the plurality of memory buses 1331b, 1332b may be greater than or equal to the width of the controller bus 1321b, and the clock rate of each of the plurality of memory buses 1331b, 1332b may be less than or equal to the clock rate of the controller bus 1321b.

[0171] The controller device 1310b can be electrically connected to the module substrate 1301b through a signal path 1343b formed in the interposer 1302b and a signal path 1351b formed in the package substrate 1303b. The controller device 1310b can be electrically connected to a first pad 1305b formed in the interposer 1302b through a first signal path 1341b formed in the interposer 1302b. The controller device 1310b can be electrically connected to a second pad 1306b formed in the interposer 1302b through a second signal path 1342b formed in the interposer 1302b. The host H can be electrically connected to the module substrate 1301b through the signal path 1343b and the signal path 1351b. The interface circuit IF can be electrically connected to the first pad 1305b through the first signal path 1341b and can be electrically connected to the second pad 1306b through the second signal path 1342b. A plurality of memory media MD can be electrically connected to the first pad 1305b and the second pad 1306b respectively by wire bonding. The plurality of memory media MD can be electrically connected to the controller device 1310b through wire bonding and the first signal path 1341b and the second signal path 1342b. The first memory medium MD1 can be electrically connected to the first pad 1305b by wire bonding W1b and can be electrically connected to the controller device 1310b through the first pad 1305b and the first signal path 1341b. The second memory medium MD2 can be electrically connected to the second pad 1306b by wire W2b and can be electrically connected to the controller device 1310b through the second pad 1306b and the second signal path 1342b. The interface circuit IF can be electrically connected to the first memory medium MD1 through the first signal path 1341b and wire bonding W1b. The interface circuit IF can be electrically connected to the second memory medium MD2 through the second signal path 1342b and wire bonding W2b. The first signal path 1341b and the wire bonding W1b can correspond to a first memory bus 1331b, and the second signal path 1342b and the wire bonding W2b can correspond to a second memory bus 1332b.

[0172] The first memory die D1 of the first memory medium MD1 can be bonded to the interposer 1302b using DAF. The second to fourth memory dies D2, D3, D4 can also be sequentially bonded to the first to third memory dies D1, D2, D3 using DAF. The first to fourth memory dies D1, D2, D3, D4 can be electrically connected using wire bonding. The first to fourth memory dies D1, D2, D3, D4 can be electrically connected to the interposer 1302b by wire bonding to the first pad 1305b formed on the interposer 1302b. The first pad 1305b can be electrically connected to the controller device 1310b through the first signal path 1341b formed in the interposer 1302b. The first memory die D5 of the second memory medium MD2 can be bonded to the interposer 1302b using DAF. The second to fourth memory dies D6, D7, D8 can also be sequentially bonded to the first to third memory dies D5, D6, D7 using DAF, respectively. The first to fourth memory dies D5, D6, D7, D8 can be electrically connected using wire bonding. The first to fourth memory dies D5, D6, D7, D8 can be electrically connected to the interposer 1302b by wire bonding to the second pad 1306b formed on the interposer 1302b. The second pad 1306b can be electrically connected to the controller device 1310b through the second signal path 1342b formed in the interposer 1302b. The interface circuit IF can be electrically connected to the first signal path 1341b and the second signal path 1342b through microbumps, thereby forming an electrical connection between the interface circuit IF and the first memory medium MD1 and the second memory medium MD2. The frequency of the signals transmitted through the controller bus 1321b between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of the signals transmitted through the first signal path 1341b and the wire bonding W1b between the interface circuit IF and the first memory medium MD1 and the frequency of the signals transmitted through the second signal path 1342b and the wire bonding W2b between the interface circuit IF and the second memory medium MD2. The controller bus 1321b can include a first data bus that electrically connects the memory controller MC and the interface circuit IF. The first signal path 1341b can include a second data bus that electrically connects the interface circuit IF and the first memory medium MD1. The second signal path 1342b can include a third data bus that electrically connects the interface circuit IF and the second memory medium MD2. The width of the first data bus can be less than or equal to the width of the second data bus and the width of the third data bus. The semiconductor device 1300b can further include a power management integrated circuit PMIC 1330b. The power management integrated circuit PMIC can be disposed on the module substrate 1301b. In one embodiment, the power management integrated circuit PMIC can be disposed on the interposer 1302b.

[0173] InFigure 13A and Figure 13C In the semiconductor device 1300a shown in Figure 13C , four memory media MD can be disposed on the first side of the controller device 1310a, and another four memory media MD can be disposed on the second side of the controller device 1310a. In the semiconductor device 1300b, eight memory media MD can be disposed in two rows of four on the first side of the controller device 1310b, and eight memory media MD can be disposed in two rows of four on the second side of the controller device 1310b. The data bandwidth of the memory bus of the semiconductor device 1300a can be substantially the same as the data bandwidth of the memory bus of the semiconductor device 1300b. The structure of the semiconductor device 1300a can reduce the areas of the interposer 1302a and the package substrate 1303a, while the structure of the semiconductor device 1300b may increase the areas of the interposer 1302b and the package substrate 1303b but reduce the height of the package.

[0174] Figures 15A to 15C is a diagram showing the configuration of a semiconductor device 1300c according to an embodiment of the present disclosure. Figure 15A may be a conceptual plan view of the semiconductor device 1300c, Figure 15B may be a cross-sectional view of the semiconductor device 1300c, and Figure 15C may be a perspective view of the semiconductor device 1300c. The semiconductor device 1300c may be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300c may include a controller device 1310c and a plurality of memory media MD. The semiconductor device 1300c may include a module substrate 1301c. The module substrate 1301c may include module pins 1304c and may communicate with an external device through the module pins 1304c. For example, the external device may be Figure 12 the main host 1211 shown in Figure 12 , and the module pins 1304c may be electrically connected to Figure 12The system bus 1201 shown. The semiconductor device 1300c can be electrically connected to an external device via a motherboard by inserting module pins 1304c into slots and / or channels formed in the motherboard. The package substrate 1303c can be mounted on the module substrate 1301c, and the package substrate 1303c can be electrically connected to the module substrate 1301c by package balls and / or solder balls. The semiconductor device 1300c may not include an interposer. The package substrate 1303c, the controller device 1310c, and the plurality of memory media MD can be encapsulated in a single package body, and the single package body can be mounted on the module substrate 1301c. The controller device 1310c can be disposed on the package substrate 1303c. The first pad 1361c on the controller device 1310c can be wire-bonded to the pad 1305c on the package substrate 1303c, and the controller device 1310c can be electrically connected to the package substrate 1303c by wire bonding. The plurality of memory media MD can be disposed on the package substrate 1303c. The controller device 1310c can be disposed in a first area on the package substrate 1303c, and the plurality of memory media MD can be disposed in a second area on the package substrate 1303c. The first area and the second area may not overlap each other.

[0175] The controller device 1310c can relay data communication between an external device and the plurality of memory media MD. The controller device 1310c can include a host H, a memory controller MC, and an interface circuit IF. The host H can correspond to Figure 12 the sub-host 1212 shown, the memory controller MC can correspond to Figure 12 the second memory controller 1222 shown, and the interface circuit IF can correspond to Figure 12 the second interface circuit 1232 shown. Repeated descriptions of corresponding components will be omitted. The controller device 1310c can be electrically connected to the plurality of memory media MD and can communicate data with the plurality of memory media MD. The controller device 1310c can be electrically connected to each of the plurality of memory media MD through the interface circuit IF. Each of the plurality of memory media MD can correspond to Figure 12 the second memory device 1242 shown. The plurality of memory media MD can form independent channels and can be electrically connected to the interface circuit IF of the controller device 1310c through independent memory buses. In Figures 15A to 15C , the semiconductor device 1300c is shown as having eight memory media, but the number of memory media that the semiconductor device 1300c has can be less than eight or more than eight. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media includes two or more memory dies, the two or more memory dies can be stacked to form a single memory media. InFigure 15B and Figure 15C In Figure 15C , a memory medium is shown as including eight memory dies, but the number of memory dies included in a memory medium may be less than or more than eight.

[0176] The host H may be electrically connected to an external device through the system bus 1340c, and may be electrically connected to the memory controller MC through the host bus 1311c. The memory controller MC may be electrically connected to the interface circuit IF through the controller bus 1321c, and the interface circuit IF may be electrically connected to each of the plurality of memory media MD through a plurality of memory buses. The controller bus 1321c may have substantially the same characteristics as Figure 1 the second bus 160 shown, and each of the plurality of memory buses may have substantially the same characteristics as Figure 1 the third bus 170 shown. Each of the plurality of memory media MD may perform parallel data communication with the interface circuit IF. The interface circuit IF may perform parallel data communication with the memory controller MC, or may perform partial parallel data communication. The width of each of the plurality of memory buses may be greater than or equal to the width of the controller bus 1321c, and the clock rate of each of the plurality of memory buses may be less than or equal to the clock rate of the controller bus 1321c.

[0177] The controller device 1310c may be electrically connected to the module substrate 1301c through the wire bond W1c between the first pad 1361c and the pad 1305c and the signal path 1351c formed in the package substrate 1303c. The controller device 1310c may be electrically connected to the plurality of memory media MD through the second pad 1362c. The host H may be electrically connected to the module substrate 1301a through the wire bond W1c and the signal path 1351c. The interface circuit IF may be electrically connected to the memory medium MD through the second pad 1362c. The memory medium MD may be electrically connected to the second pad 1362c through the wire bond W2c. The interface circuit IF may be electrically connected to the memory medium MD through the wire bond W2c. The wire bond W2c may correspond to one of the plurality of memory buses.

[0178] The first memory die D1 of the memory medium MD can be bonded to the package substrate 1303c using DAF. The second to eighth memory dies D2, D3, D4, D5, D6, D7, D8 can also be bonded to the first to seventh memory dies D1, D2, D3, D4, D5, D6, D7 in sequence using DAF respectively. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected using wire bonding. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected to the interface circuit IF of the controller device 1310c by wire bonding to the second pad 1362c formed on the controller device 1310c. If multiple memory media MD are directly wire-bonded to the second pad 1362c of the controller device 1310c, the manufacturing cost of the semiconductor device 1300c can be further reduced because the semiconductor device 1300c does not need to use an interposer.

[0179] The frequency of the signal transmitted through the controller bus 1321c between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of the signal transmitted through the wire bonding W2c between the interface circuit IF and the memory medium MD. The controller bus 1321a can include a first data bus electrically connecting the memory controller MC and the interface circuit IF, while the wire bonding W2c can include a second data bus electrically connecting the interface circuit IF and the memory medium MD. The width of the first data bus can be less than or equal to the width of the second data bus. The semiconductor device 1300c can also include a power management integrated circuit PMIC 1330c. The power management integrated circuit PMIC can be disposed on the module substrate 1301c.

[0180] Figures 16A to 16C FIG. is a diagram showing the configuration of a semiconductor device 1300d according to an embodiment of the present disclosure. Figure 16A may be a conceptual plan view of the semiconductor device 1300d, [[ID may be a cross-sectional view of the semiconductor device 1300d, and ​ may be a perspective view of the semiconductor device 1300d. Redundant descriptions of corresponding components will be omitted. The semiconductor device 1300d can be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300d can include a controller device 1310d and a plurality of memory media MD. The semiconductor device 1300d can include a module substrate 1301d. The module substrate 1301d can include module pins 1304d and can communicate with an external device through the module pins 1304d. For example, the external device can be ​ the host 1211 shown, and the module pins 1304d can be electrically connected to ​The system bus 1201 shown. The semiconductor device 1300d can be electrically connected to an external device via a motherboard by inserting module pins 1304d into slots and / or channels formed in the motherboard. The package substrate 1303d can be mounted on the module substrate 1301d, and the package substrate 1303d can be electrically connected to the module substrate 1301d by package balls and / or solder balls. The semiconductor device 1300d may not include an interposer. The package substrate 1303d, the controller device 1310d, and the plurality of memory media MD can be encapsulated in a single package, and the single package can be mounted on the module substrate 1301d. The controller device 1310d can be disposed on the package substrate 1303d. The controller device 1310d can be disposed in a first area on the package substrate 1303d. The controller device 1310d can be electrically connected to the package substrate 1303d using wire bonding. The first pad 1361d of the controller device 1310d can be electrically connected to the pad 1305d on the package substrate 1303d by wire bonding. The pad 1305d can be electrically connected to a signal path 1351d formed in the package substrate 1303d. Some of the plurality of memory media MD can be disposed on the package substrate 1303d, and the remainder of the plurality of memory media MD can be disposed on the controller device 1310d. Some of the plurality of memory media MD can be disposed in a second area on the package substrate 1303d. The first area and the second area may not overlap each other. The remainder of the plurality of memory media MD can be disposed in a first area on the controller device 1310d. For example, eight memory media can be disposed on the package substrate 1303d, and the remaining eight memory media can be disposed on the controller device 1310d.

[0181] The controller device 1310d can relay data communication between an external device and the plurality of memory media MD. Although not shown, the controller device 1310d can include a host, a memory controller, and interface circuits, and has a configuration substantially the same as that of the ​ controller device 1310c shown. The controller device 1310d can be electrically connected to the plurality of memory media MD and can communicate data with the plurality of memory media MD. The controller device 1310d can be electrically connected to each of the plurality of memory media MD through interface circuits. Each of the plurality of memory media MD can correspond to the ​ second memory device 1242 shown. The plurality of memory media MD can form independent channels and can each be electrically connected to the interface circuits of the controller device 1310d through independent memory buses. In ​In [description], the semiconductor device 1300d is shown as having sixteen memory media, but the number of memory media that the semiconductor device 1300d has can be less than sixteen or more than sixteen. Each of the multiple memory media MD may include at least one memory die. When each of the multiple memory media MD includes two or more memory dies, these two or more memory dies may be stacked to form a single memory medium. In ​ and ​ In [description], one memory medium includes eight memory dies, but the number of memory dies included in one memory medium can be less than or more than eight.

[0182] The controller device 1310d can be electrically connected to the module substrate 1301d through wire bonding W1d between the first pad 1361d and the pad 1305d and the signal path 1351d formed in the package substrate 1303d. The controller device 1310d can be electrically connected to the multiple memory media MD through the second pad 1362d and the third pad 1363d. The host can be electrically connected to the module substrate 1301d through the wire bonding W1d and the signal path 1351d. The interface circuit IF can be electrically connected to the multiple memory media MD through the second pad 1362d and the third pad 1363d. The host can be electrically connected to the memory controller through the host bus. The memory controller can be connected to the interface circuit through the controller bus. The interface circuit can be electrically connected to the multiple memory media MD through wire bonding between the second and third pads 1362d, 1363d and the multiple memory media MD. The wire bonding between the second and third pads 1362d, 1363d and the multiple memory media MD can correspond to multiple memory buses. For example, the first memory medium MD1 can be electrically connected to the interface circuit through wire bonding W2d between the first memory medium MD1 and the second pad 1362d. The second memory medium MD2 can be electrically connected to the interface circuit through wire bonding W3d between the second memory medium MD2 and the third pad 1363d.

[0183] The first memory die D11 of the first memory medium MD1 can be bonded to the package substrate 1303d using DAF. The second to eighth memory dies D12, D13, D14, D15, D16, D17, D18 can also be bonded to the first to seventh memory dies D11, D12, D13, D14, D15, D16, D17 sequentially using DAF, respectively. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected using wire bonding. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected to the controller device 1310d by wire bonding to the second pad 1362d. The first memory die D21 of the second memory medium MD2 can be bonded to the top surface of the controller device 1310d using DAF. The second to eighth memory dies D22, D23, D24, D25, D26, D27, D28 can also be bonded to the first to seventh memory dies D21, D22, D23, D24, D25, D26, D27 sequentially using DAF, respectively. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected using wire bonding. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected to the controller device 1310d by wire bonding to the third pad 1363d. When multiple memory media MD are disposed on the controller device 1310d, the capacity of the semiconductor device 1300d can be increased without increasing the package area. The semiconductor device 1300d may further include a power management integrated circuit PMIC 1330d. The power management integrated circuit PMIC can be disposed on the module substrate 1301d. In one embodiment, the power management integrated circuit PMIC can be disposed on the package substrate 1303d.

[0184] ​ FIG. is a diagram showing a configuration of a semiconductor device 1300e according to an embodiment of the present disclosure. ​ may be a conceptual plan view of the semiconductor device 1300e, ​ may be a cross-sectional view of the semiconductor device 1300e, and ​It may be a perspective view of the semiconductor device 1300e. Redundant descriptions of corresponding components will be omitted. The semiconductor device 1300e may be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300e may include a controller device 1310e and a plurality of memory media MD. The semiconductor device 1300e may include a module substrate 1301e. The module substrate 1301e may include module pins 1304e and may communicate with an external device through the module pins 1304e. For example, the external device may be ​ the main host 1211 shown, and the module pins 1304e may be electrically connected to ​ the system bus 1201 shown. The semiconductor device 1300e may be electrically connected to the external device via the motherboard by inserting the module pins 1304e into slots and / or channels formed in the motherboard. The package substrate 1303e may be mounted on the module substrate 1301e, and the package substrate 1303e may be electrically connected to the module substrate 1301e through package balls and / or solder balls. The semiconductor device 1300e may not include an interposer. The package substrate 1303e, the controller device 1310e, and the plurality of memory media MD may be encapsulated in a single package body, and the single package body may be mounted on the module substrate 1301e. The controller device 1310e may be disposed on the package substrate 1303e. The controller device 1310e may be electrically connected to the package substrate 1303e using wire bonding. The first pad 1361e formed in the controller device 1310e may be electrically connected to the pad 1305e formed in the package substrate 1303e through wire bonding. The pad 1305e may be electrically connected to a signal path 1351e formed in the package substrate 1303e. All of the plurality of memory media MD may be disposed on the controller device 1310e. Some of the plurality of memory media MD may be disposed in a first region on the controller device 1310e, and the remaining portions of the plurality of memory media MD may be disposed in a second region on the controller device 1310e. The first region and the second region may not overlap with each other. For example, when the semiconductor device 1300e includes sixteen memory media, eight memory media may be disposed in the first region on the controller device 1310e, and the other eight memory media may be disposed in the second region on the controller device 1310e.

[0185] The controller device 1310e may relay data communication between the external device and the plurality of memory media MD. Although not shown, the controller device 1310e may include a host, a memory controller, and an interface circuit, and may have the same as ​a configuration substantially the same as that of the controller device 1310c shown. The controller device 1310e can be electrically connected to a plurality of memory media MD and can communicate data with the plurality of memory media MD. The controller device 1310e can be electrically connected to each of the plurality of memory media MD through an interface circuit. Each of the plurality of memory media MD can correspond to ​ the second memory device 1242 shown. The plurality of memory media MD can form independent channels and can all be electrically connected to the interface circuit of the controller device 1310e through independent memory buses. In ​ FIG., the semiconductor device 1300e is shown as having eight memory media, but the number of memory media that the semiconductor device 1300e has can be less than eight or more than eight. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In ​ and ​ FIG., one memory medium includes eight memory dies, but the number of memory dies included in one memory medium can be less than or more than eight.

[0186] The controller device 1310e can be electrically connected to the module substrate 1301e through a wire bond W1e between the first pad 1361e and the pad 1305e and a signal path 1351e formed in the package substrate 1303d. The controller device 1310e can be electrically connected to the plurality of memory media MD through a second pad 1362e and a third pad 1363e. The host can be electrically connected to the module substrate 1301e through the wire bond W1e and the signal path 1351e. The host can be electrically connected to the memory controller through a host bus. The memory controller can be connected to the interface circuit through a controller bus. The interface circuit can be connected to the plurality of memory media MD through the second pad 1362e and the third pad 1363e. The interface circuit can be electrically connected to the plurality of memory media MD through wire bonds between the second and third pads 1362e, 1363e and the plurality of memory media MD. The wire bonds between the second and third pads 1362e, 1363e and the plurality of memory media MD can correspond to a plurality of memory buses. For example, the first memory medium MD1 can be electrically connected to the interface circuit through a wire bond W2e between the first memory medium MD1 and the second pad 1362e. The second memory medium MD2 can be electrically connected to the interface circuit through a wire bond W3e between the second memory medium MD2 and the third pad 1363e.

[0187] The first memory die D11 of the first memory medium MD1 can be bonded to the controller device 1310e using DAF. The second to eighth memory dies D12, D13, D14, D15, D16, D17, D18 can also be sequentially bonded to the first to seventh memory dies D11, D12, D13, D14, D15, D16, D17 using DAF, respectively. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected using wire bonding. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected to the controller device 1310e by wire bonding to the second pad 1362e formed on the controller device 1310e. The first memory die D21 of the second memory medium MD2 can be bonded to the top surface of the controller device 1310e using DAF. The second to eighth memory dies D22, D23, D24, D25, D26, D27, D28 can also be sequentially bonded to the first to seventh memory dies D21, D22, D23, D24, D25, D26, D27 using DAF, respectively. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected using wire bonding. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected to the controller device 1310e by wire bonding to the third pad 1363e formed on the controller device 1310e. When multiple memory media MD are arranged on the controller device 1310e, the capacity of the semiconductor device 1300e can be increased without increasing the package area. In addition, if multiple memory dies are vertically aligned instead of stacked in a stepped manner, wire bonding can be performed on all four sides of the memory die, as ​ shown. Thus, the semiconductor device can have a large capacity and much lower manufacturing cost. The semiconductor device 1300e may further include a power management integrated circuit PMIC 1330e. The power management integrated circuit PMIC may be disposed on the module substrate 1301e. In one embodiment, the power management integrated circuit PMIC may be disposed on the package substrate 1303e.

[0188] ​ is a diagram showing the configuration of a semiconductor device 1400 according to an embodiment of the present disclosure. Refer to ​, the semiconductor device 1400 can be a memory system, such as a CXL module or a CXL device. The semiconductor device 1400 can include a host 1410, a memory controller 1420, an interface circuit 1430, and a plurality of memory media MD1, MD2, MD3, MD4. The host 1410 can be electrically connected to an external device (such as ​ the main host 1211 shown) through the system bus 1401. The memory controller 1420 can be electrically connected to the host 1410 through the host bus 1450. The memory controller 1420 can include an enhanced error correction code (ECC) circuit. The memory controller 1420 can correct faulty bit errors in the data signals provided to the interface circuit 1430 through the enhanced ECC circuit 1480, and can correct faulty bit errors in the data signals received from the interface circuit 1430. If the memory controller 1420 includes the enhanced ECC circuit 1480, it can detect and correct a greater number of faulty bits generated by the memory media MD1, MD2, MD3, MD4. In one embodiment, the enhanced ECC circuit 1480 can correct faulty bit errors in the command signals and address signals provided from the memory controller 1420 to the interface circuit 1430 along with the data signals. In one embodiment, the enhanced ECC circuit 1480 can be provided outside the memory controller 1420. For example, the enhanced ECC circuit 1480 can be arranged to be electrically connected between the memory controller 1420 and the interface circuit 1430. The interface circuit 1430 can be electrically connected to the memory controller 1420 through the controller bus 1460, and can be electrically connected to the plurality of memory media MD1, MD2, MD3, MD4 through a plurality of memory buses 1471, 1472, 1473, 1474. In ​ , the semiconductor device 1400 is shown as including four memory media, but the number of memory media included in the semiconductor device 1400 can be less than four or more than four. The interface circuit 1430 can be electrically connected to the first memory media MD1 through the first memory bus 1471, to the second memory media MD2 through the second memory bus 1472, to the third memory media MD3 through the third memory bus 1473, and to the fourth memory media MD4 through the fourth memory bus 1474. The interface circuit 1430 can perform parallel data communication or partial parallel data communication with the memory controller 1420 through the controller bus 1460. The interface circuit 1430 can perform parallel data communication with the first to fourth memory media MD1, MD2, MD3, MD4 through the first to fourth memory buses 1471, 1472, 1473, 1474 respectively. The controller bus 1460 can have the same as ​The second bus 160 shown therein has substantially the same characteristics. Each of the first to fourth memory buses 1471, 1472, 1473, 1474 may have the same as ​ the third bus 170 shown therein.

[0189] Each of the first to fourth memory media MD1, MD2, MD3, MD4 may include a plurality of memory dies. Compared with a conventional memory die, the plurality of memory dies may have a simplified structure. In the plurality of memory dies, the number of memory cells may be increased, while the number of row address decoders and redundant units may be decreased. Therefore, the size of the plurality of memory dies may be smaller than that of a conventional memory die. In addition, since the plurality of memory dies can be stacked by wire bonding, a memory medium with a large data storage capacity can be realized at a low manufacturing cost. However, as the number of row address decoders and redundant units decreases, the number of faulty bit positions in the data signal stored in or output from the memory cell region may increase. Generally, a memory die and a memory controller have ECC logic for correcting faulty bit positions in the data signal. The memory controller 1420 may further include an enhanced ECC circuit 1480 (i.e., enhanced ECC performance) to further mitigate the increased faulty bit positions in the memory die through the ECC circuit 1480, thereby improving the reliability of the semiconductor device 1400. The host 1410, the memory controller 1420, and the interface circuit 1430 may be integrated into a controller device. Since the interface circuit 1430 performs parallel data communication with the memory controller 1420 and the plurality of memory media MD1, MD2, MD3, MD4 respectively, the memory controller 1420 may not have a SerDes or may have only a SerDes with a minimum size. Therefore, using part or all of the area allocated for the SerDes, the controller device can add the enhanced ECC circuit 1480 without increasing the total area of the controller device. Therefore, compared with a conventional semiconductor device, the semiconductor device 1400 may have a reduced total area and manufacturing cost while still providing a memory system with the same or improved performance as a conventional semiconductor device.

[0190] ​ is a diagram showing the configuration of a semiconductor device 1500 according to an embodiment of the present disclosure. Referring to ​ , the semiconductor device 1500 may be a memory system, such as a CXL module or a CXL device. The semiconductor device 1500 may include a first host 1511, a second host 1512, a memory controller 1520, an interface circuit 1530, and a plurality of memory media MD1, MD2, MD3, MD4. The first host 1511 and the second host 1512 may both be electrically connected to an external device (such as ​The main host shown in

[0191] The memory controller 1520 may be electrically connected to the first host 1511 through the first host bus 1541, and may be electrically connected to the second host 1512 through the second host bus 1542. The memory controller 1520 may generate command signals and address signals for accessing the plurality of memory media MD1, MD2, MD3, MD4 based on access requests provided by the first host 1511. The memory controller 1520 may generate command signals and address signals for instructing computational operations of the plurality of memory media MD1, MD2, MD3, MD4 based on computational requests provided from the second host 1512. The semiconductor device 1500 may further include a global buffer 1580. The global buffer 1580 may be electrically connected between the memory controller 1520 and the interface circuit 1530. The global buffer 1580 may store and output data corresponding to vectors such that the plurality of memory media MD1, MD2, MD3, MD4 can perform matrix operations. The global buffer 1580 may receive data corresponding to vectors from the memory controller 1520 and may store the data corresponding to vectors. The global buffer 1580 may output the data corresponding to vectors to the interface circuit 1530, and the interface circuit 1530 may provide the data corresponding to vectors to the plurality of memory media MD1, MD2, MD3, MD4. In one embodiment, the global buffer 1580 may be implemented with registers or static random access memory (SRAM). The interface circuit 1530 may be electrically connected to the memory controller 1520 through the controller bus 1560, and may be electrically connected to the plurality of memory media MD1, MD2, MD3, MD4 through the plurality of memory buses 1571, 1572, 1573, 1574. In FIG. 19, although the semiconductor device 1500 is shown as including four memory media, the number of memory media included by the semiconductor device 1500 may be less than four or more than four. The interface circuit 1530 may be electrically connected to the first memory media MD1 through the first memory bus 1571, to the second memory media MD2 through the second memory bus 1572, to the third memory media MD3 through the third memory bus 1573, and to the fourth memory media MD4 through the fourth memory bus 1574. The interface circuit 1530 may perform parallel data communication or partial parallel data communication with the memory controller 1520 through the controller bus 1560. The interface circuit 1530 may perform parallel data communication with the first to fourth memory media MD1, MD2, MD3, MD4 through the first to fourth memory buses 1571, 1572, 1573, 1574, respectively. The controller bus 1560 may have substantially the same characteristics as ​ the second bus 160 shown. Each of the first to fourth memory buses 1571, 1572, 1573, 1574 may have the same as​ substantially the same characteristics as the third bus 170 shown in

[0192] Each of the first to fourth memory media MD1, MD2, MD3, MD4 may include a plurality of memory dies. Since each of the plurality of memory dies performs parallel data communication with the interface circuit 1530, they may not include additional circuits such as SerDes. The area from which SerDes is removed may be provided with a processing unit PU. The processing unit PU may include a MAC (multiply-accumulate) unit. Each of the plurality of memory dies may include a memory cell array and a processing unit PU to perform a computing operation requested from the second host 1512. The first host 1511, the second host 1512, the memory controller 1520, the global buffer 1580, and the interface circuit 1530 may be integrated into a controller device. Since the interface circuit 1530 performs parallel data communication with the memory controller 1520 and the plurality of memory media MD1, MD2, MD3, MD4, respectively, the memory controller 1520 may not have SerDes or may have only a SerDes of a minimum size. Therefore, using part or all of the area allocated for SerDes, the controller device may add the second host 1512 and the global buffer 1580 without increasing the total area of the controller device. Therefore, the semiconductor device 1500 may implement a memory system that performs a PIM (processing-in-memory) function in substantially the same area as a conventional semiconductor device.

[0193] Those skilled in the art to which the present disclosure pertains can understand that the present disclosure can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims described below rather than the detailed description, and it should be understood that all variations or modifications derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the present disclosure.

Claims

1. A computing system comprising: Host; A memory controller electrically connected to the host via a host bus; an interface circuit electrically connected to the memory controller via a first data bus; as well as a memory device electrically connected to the interface circuit via a second data bus, Wherein, the width of the second data bus is greater than or equal to the width of the first data bus.

2. The computing system of claim 1, wherein: The clock rate of the second data bus is less than or equal to the clock rate of the first data bus.

3. The computing system of claim 1, wherein: The first data bus transmits n bits of data simultaneously, and the second data bus transmits m bits of data simultaneously, wherein n is a multiple of 2, and m is equal to n or a multiple of n.

4. The computing system of claim 1, wherein: A clock frequency ratio of the first data bus to the second data bus is set to one of 1:1, 2:1, and 4:

1.

5. The computing system of claim 1, wherein: The first data bus is one of a parallel bus and a partially parallel bus, and the second data bus is a parallel bus.

6. The computing system of claim 1, wherein: A data bandwidth of the first data bus is substantially the same as a data bandwidth of the second data bus.

7. The computing system of claim 1, wherein: The memory controller, the interface circuit, and the memory device are disposed on the same interposer, while the host is not disposed on the same interposer.

8. The computing system of claim 1, wherein: The memory controller, the interface circuit, and the memory device are disposed on the same substrate, while the host is not disposed on the same substrate.

9. The computing system of claim 1, wherein: The host, the memory controller, and the interface circuit are disposed on the same interposer, while the memory device is not disposed on the same interposer.

10. The computing system of claim 1, wherein: The host, the memory controller, and the interface circuit are disposed on the same substrate, while the memory device is not disposed on the same substrate.

11. The computing system of claim 1, wherein: The host, the memory controller, the interface circuit, and the memory device are disposed on the same interposer.

12. The computing system of claim 1, wherein: The host, the memory controller, the interface circuit, and the memory device are provided on the same substrate.

13. A computing system comprising: Host; A first memory controller electrically connected to the host via a first host bus; A first interface circuit electrically connected to the first memory controller via a first controller bus; as well as a first memory device electrically connected to the first interface circuit via a first memory bus, The clock rate of the first memory bus is less than or equal to the clock rate of the first controller bus.

14. The computing system of claim 13, wherein: The first controller bus includes a first data bus, the first memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

15. The computing system of claim 14, wherein: The first interface circuit includes an address control circuit, which: receives an address signal and a command signal from the first memory controller through the first controller bus; generates a row address signal and a column address signal based on the address signal and the command signal; and outputs the row address signal and the column address signal through the first memory bus.

16. The computing system of claim 14, wherein: The first data bus includes a write bus and a read bus, and wherein the first interface circuit includes a data input / output circuit, which: receives a write data signal from the first memory controller through the write bus and transmits a memory data signal generated based on the write data signal to the first memory bus; and receives the memory data signal from the first memory device through the first memory bus and outputs a read data signal generated based on the memory data signal to the read bus.

17. The computing system of claim 16, wherein: The first memory controller includes a clock frequency control circuit that generates a clock frequency control signal based on a frequency setting signal and outputs the clock frequency control signal to the first controller bus; And wherein the first interface circuit further comprises a clock control circuit, wherein the clock control circuit generates an interface clock signal and a memory clock signal from a system clock signal based on the frequency setting signal.

18. The computing system of claim 17, wherein: The frequency of the memory clock signal is less than or equal to the frequency of the interface clock signal.

19. The computing system of claim 17, wherein: The data input / output circuit comprises: a write control circuit that: latches the write data signal based on the interface clock signal, and outputs the latched write data signal as the memory data signal based on the memory clock signal; and A read control circuit latches the memory data signal based on the memory clock signal, and outputs the latched memory data signal as the read data signal based on the interface clock signal.

20. The computing system of claim 13, further comprising: a second interface circuit electrically connected to the first memory controller via a second controller bus; as well as The second memory device is electrically connected to the second interface circuit via a second memory bus.

21. The computing system of claim 20, wherein: The first controller bus includes a first data bus, the first memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

22. The computing system of claim 20, wherein: A clock rate of the second controller bus is greater than or equal to a clock rate of the second memory bus.

23. The computing system of claim 20, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

24. The computing system of claim 20, wherein: A clock rate of the second controller bus is lower than a clock rate of the second memory bus.

25. The computing system of claim 20, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the second data bus is smaller than a width of the first data bus.

26. The computing system of claim 13, further comprising: a second memory controller electrically connected to the host via a second host bus; a second interface circuit electrically connected to the second memory controller via a second controller bus; as well as The second memory device is electrically connected to the second interface circuit via a second memory bus.

27. The computing system of claim 26, wherein: The first controller bus includes a first data bus, the first memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

28. The computing system of claim 26, wherein: A clock rate of the second controller bus is greater than or equal to a clock rate of the second memory bus.

29. The computing system of claim 26, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

30. The computing system of claim 26, wherein: A clock rate of the second controller bus is lower than a clock rate of the second memory bus.

31. The computing system of claim 26, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the second data bus is smaller than a width of the first data bus.

32. A computing system comprising: Master host; a first memory controller electrically connected to the main host via a first host bus; A sub-host, which is electrically connected to the main host via a system bus; A second memory controller electrically connected to the sub-host via a second host bus; A first interface circuit electrically connected to the first memory controller via a first controller bus; a second interface circuit electrically connected to the second memory controller via a second controller bus; a first memory device electrically connected to the first interface circuit via a first memory bus; as well as a second memory device electrically connected to the second interface circuit via a second memory bus, Wherein, the clock rate of the first controller bus is greater than or equal to the clock rate of the first memory bus.

33. The computing system of claim 32, wherein: The first controller bus includes a first data bus, the first memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

34. The computing system of claim 32, wherein: A clock rate of the second controller bus is greater than or equal to a clock rate of the second memory bus.

35. The computing system of claim 32, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the first data bus is less than or equal to a width of the second data bus.

36. The computing system of claim 32, wherein: A clock rate of the second controller bus is lower than a clock rate of the second memory bus.

37. The computing system of claim 32, wherein: The second controller bus includes a first data bus, the second memory bus includes a second data bus, and a width of the second data bus is smaller than a width of the first data bus.

Images