AXI bus-based UART communication implementation method and system

Abstract

The invention provides a UART communication implementation method based on an AXI bus and a system thereof, which are applied to the technical field of integrated circuits and applied to an ARM host, an RAM slave, the AXI bus and a UART module, the UART module comprises the UART host, the UART slave, a UART sending module and a UART receiving module, and the method comprises the following steps: at a T5 rising edge moment, the UART slave completes data receiving, and at a T5 rising edge moment, the UART sending module sends data to the AXI bus; a BVALID write response effective signal is sent to the ARM host computer; meanwhile, UART output is executed on data to be written by the UART through a TXD pin of the UART sending module, and UART communication write operation and the like based on the AXI bus are completed; the ARM host realizes communication read operation with the UART module through the AXI bus, so that the use of a bridge is avoided, the hardware design is simplified, the unnecessary expenditure in the specific chip design is reduced, and the chip design area is saved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an implementation method and system for UART communication based on the AXI bus. Background Art

[0002] The AXI protocol is a high-performance and high-bandwidth on-chip interconnect protocol, which is widely used in SoC designs. It can effectively connect IP cores such as processors, memories, and various peripherals, enabling high-speed data transfer and communication between them, and improving data transfer efficiency and system performance. Usually, a bridge is required to implement communication between the AXI and APB protocols. The bridge has two interfaces, one connected to the AXI bus and the other connected to the APB bus. It is responsible for signal conversion, data format conversion, and protocol conversion between the two buses. This conversion process not only increases the complexity of the system but may also affect the stability and real-time performance of data transfer.

[0003] In some special customized fields, low-speed peripherals often do not require a variety of functional modules. When there is only one UART module, introducing an AXI to APB conversion bridge at this time seems redundant, increasing unnecessary functional expenses and the complexity of system design.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] To overcome the above problems, this application proposes an implementation method for UART communication based on the AXI bus. By directly implementing communication between UART modules under the AXI bus protocol, the complexity of using a bridge for protocol conversion is avoided, thereby improving the stability and real-time performance of data transfer, reducing unnecessary expenses in specific chip designs, and saving chip design area.

[0006] To achieve the above objects and other advantages of the present invention, the embodiments of this specification provide the following technical solutions:

[0007] The first object of the present invention is to provide an implementation method for UART communication based on the AXI bus, which specifically includes the following steps:

[0008] The ARM host outputs the operation address for writing to the UART to the AWADDR of the AXI bus at the rising edge of T0, and at the same time pulls up AWVALID to obtain a valid write address signal;

[0009] At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the UART slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the UART from the AXI bus.

[0010] At the rising edge of T2, the ARM master obtains the AWREADY write address handshake signal of the UART slave, and prepares to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data to be written to the UART; at the same time, it prepares the BREADY write response handshake signal.

[0011] At the rising edge of T3, the UART slave does not pull up the WREADY write data handshake signal, and the ARM master keeps the WDATA write data and the WVALID write data valid signal stable, waiting for the WREADY write data handshake signal to be valid.

[0012] At the rising edge of T4, when the UART slave sets the WREADY write data handshake signal to be valid, the UART slave receives the data to be written to the UART; the ARM master obtains the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus.

[0013] At the rising edge of T5, the UART slave completes data reception, sends the BVALID write response valid signal to the ARM master; at the same time, it executes UART output for the data to be written to the UART through the TXD pin of the UART sending module, completing the UART communication write operation based on the AXI bus.

[0014] Further, before the rising edge of T0, it further includes:

[0015] The ARM master sends a request to access the UART slave to the AXI bus; the UART slave responds to the request through the AXI bus, and then the ARM master obtains the permission to access the UART slave.

[0016] Further, preparing to output the WDATA write data further includes:

[0017] Judging whether the currently transmitted WDATA write data is the last data;

[0018] If so, when the ARM master outputs the WDATA write data, it pulls up the WLAST signal;

[0019] If not, it outputs the WDATA write data in sequence until all data is transmitted.

[0020] The second object of the present invention is to provide a method for implementing UART communication based on the AXI bus, specifically including the following steps:

[0021] At the rising edge of T7, the UART host outputs the operation address for writing to the RAM to the AWADDR of the AXI bus, and at the same time pulls up AWVALID to obtain the write address valid signal;

[0022] At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the RAM slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the RAM from the AXI bus;

[0023] At the rising edge of T9, the UART host obtains the AWREADY write address handshake signal of the RAM slave, and prepares to output WDATA write data and WVALID write data valid signal, where the WDATA write data is the data input by the UART; at the same time, it prepares the BREADY write response handshake signal;

[0024] At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to be valid, then the RAM slave receives the data to be written by the UART; the UART host obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus;

[0025] At the rising edge of T11, the RAM slave completes the data reception and sends a BVALID write response valid signal to the UART host; the data input by the UART is stored in the RAM slave; the ARM host reads the data input by the UART in the RAM slave through the AXI bus to complete the read operation of the UART communication based on the AXI bus.

[0026] Further, before the rising edge of T6, it further includes:

[0027] From the rising edge of T6 to the rising edge of T7, the RXD pin of the UART receiving module receives the input communication signal sent by the UART sending module; the UART host sends a request to occupy the bus to access the RAM slave through the AXI bus, and the RAM slave responds to the request through the AXI bus, then the UART host obtains the permission to access the RAM slave.

[0028] Further, preparing to output WDATA write data further includes:

[0029] Judging whether the currently transmitted WDATA write data is the last data;

[0030] If so, when the UART host outputs the WDATA write data, the WLAST signal is pulled high;

[0031] If not, the WDATA write data is output sequentially until all data transmissions are completed.

[0032] The third object of the present invention is to provide an implementation system for UART communication based on the AXI bus, specifically including:

[0033] A data writing unit for the ARM host to directly write data to the UART slave, specifically including:

[0034] At the rising edge of T0, the ARM host outputs the operation address for writing the UART to the AWADDR of the AXI bus, and at the same time pulls high the AWVALID to obtain the write address valid signal;

[0035] At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the UART slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing the UART from the AXI bus;

[0036] At the rising edge of T2, the ARM host obtains the AWREADY write address handshake signal of the UART slave, and is ready to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data to be written by the UART; at the same time, it is ready for the BREADY write response handshake signal;

[0037] At the rising edge of T3, since the UART slave does not pull high the WREADY write data handshake signal, the ARM host keeps the WDATA write data and the WVALID write data valid signal stable and waits for the WREADY write data handshake signal to be valid;

[0038] At the rising edge of T4, if the UART slave sets the WREADY write data handshake signal to be valid, then the UART slave receives the data to be written by the UART; the ARM host obtains the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus;

[0039] A data transmission unit for realizing the external transmission of the written data, specifically including:

[0040] At the rising edge of T5, the UART slave completes data reception and sends a BVALID write response valid signal to the ARM master; at the same time, the data to be written by the UART is output via the TXD pin of the UART transmission module to complete the UART communication write operation based on the AXI bus.

[0041] Further, before the rising edge of T0, it further includes:

[0042] The ARM master sends a request to access the UART slave to the AXI bus; the UART slave responds to the request via the AXI bus, and then the ARM master obtains the permission to access the UART slave;

[0043] Preparing to output WDATA write data further includes:

[0044] Determining whether the currently transmitted WDATA write data is the last data;

[0045] If so, the ARM master raises the WLAST signal while outputting the WDATA write data;

[0046] If not, the WDATA write data is output sequentially until all data is transmitted.

[0047] The fourth object of the present invention is to provide an implementation system for UART communication based on the AXI bus, specifically including:

[0048] A data storage unit for the UART master to store data in the RAM slave, specifically including:

[0049] At the rising edge of T7, the UART master outputs the operation address for writing to the RAM to the AWADDR of the AXI bus, and at the same time raises AWVALID to obtain a write address valid signal;

[0050] At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the RAM slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the RAM from the AXI bus;

[0051] At the rising edge of T9, the UART master obtains the AWREADY write address handshake signal of the RAM slave and prepares to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data input by the UART; at the same time, it prepares the BREADY write response handshake signal;

[0052] At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to valid, and then the RAM slave receives the data to be written by the UART; the UART master obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus.

[0053] A data reading unit, used for the ARM master to read data from the RAM slave, specifically including:

[0054] At the rising edge of T11, the RAM slave completes data reception and sends a BVALID write response valid signal to the UART master; the data input by the UART is stored in the RAM slave; the ARM master reads the data input by the UART in the RAM slave through the AXI bus, and completes the UART communication read operation based on the AXI bus.

[0055] Further, before the rising edge of T6, it also includes:

[0056] From the rising edge of T6 to the rising edge of T7, the RXD pin of the UART receiving module receives the input communication signal sent by the UART sending module; the UART master sends a request to occupy the bus to access the RAM slave to the AXI bus, and the RAM slave responds to the request through the AXI bus, then the UART master obtains the permission to access the RAM slave.

[0057] Preparing to output WDATA write data also includes:

[0058] Judging whether the currently transmitted WDATA write data is the last data;

[0059] If so, when the UART master outputs the WDATA write data, it raises the WLAST signal;

[0060] If not, output the WDATA write data in sequence until all data is transmitted.

[0061] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve at least the following beneficial effects:

[0062] The ARM master realizes the communication write operation and / or read operation with the UART module through the AXI bus, avoids using a bridge, simplifies the hardware design, reduces unnecessary expenses in specific chip designs, and saves chip design area;

[0063] The stability of the system and the reliability of data transmission are enhanced through timing design, reflecting a fine hardware cooperation mechanism; the host first obtains the access right, which ensures that the communication link has been established before data transmission and improves the communication efficiency; the added handshake signal mechanism further ensures that both the master and slave can exchange data correctly and reliably, reducing the communication error rate and improving the stability and efficiency of data exchange. In addition, this solution effectively reduces the data transmission delay and improves the system response speed by optimizing the data buffer mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0065] Figure 1 is a schematic structural diagram of an implementation method of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0066] Figure 2 is a flowchart of a communication write operation method in an implementation method of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0067] Figure 3 is a timing diagram of a communication write operation in an implementation method of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0068] Figure 4 is a flowchart of a communication read operation method in an implementation method of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0069] Figure 5 is a timing diagram of a communication read operation in an implementation method of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0070] Figure 6 is a schematic structural diagram of a communication write operation in an implementation system of UART communication based on the AXI bus provided by an embodiment of the present invention;

[0071] Figure 7 is a schematic structural diagram of a communication read operation in an implementation system of UART communication based on the AXI bus provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0072] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0073] The following describes the implementation modes of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0074] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0075] Figure 2 A method for implementing UART communication based on the AXI bus provided in Embodiment 1 of the present invention is applicable to a specific chip design. By directly implementing communication between the host and the UART module under the AXI bus protocol, it avoids using a bridge for complex protocol conversion, improves the stability and real-time performance of data transmission, reduces unnecessary expenses in the specific chip design, and saves chip design area. The UART module here includes, but is not limited to, low-speed device modules such as I2C modules and SPI modules. In this application, as Figure 1 shown, this method can be applied to an ARM host 100, a RAM slave 200, an AXI bus 300, and a UART module 400, where the UART module 400 includes a UART host 403, a UART slave 401, a UART transmission module 402, and a UART reception module 404.

[0076] Embodiment 1

[0077] This specification embodiment proposes a method for implementing UART communication based on the AXI bus, as Figure 2 shown, specifically including the following steps:

[0078] S10: At the rising edge of T0, the ARM host outputs the operation address for writing to the UART to the AWADDR of the AXI bus, and at the same time raises AWVALID to obtain the write address valid signal;

[0079] Among them, the rising edge of T0 refers to the instant when the clock signal changes from low level to high level, which is at the beginning of a timing diagram, as Figure 3 shown, marking the start of the write operation. AWADDR provides the target address for the write operation to ensure the accuracy of data transmission. In this embodiment, the AWADDR outputs the operation address for writing to the UART, including the address field. Raising the AWVALID signal indicates that the AWVALID signal is at a high level at this time, indicating that the write address is valid, that is, the write address AWADDR sent by the ARM host is valid, and the ARM host is ready to start the write operation.

[0080] S11: At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the UART slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and receives the operation address for writing to the UART from the AXI bus;

[0081] Among them, the rising edge of T1 marks that the UART slave confirms the validity of the operation address for writing to the UART through the AXI bus and performs function preparations to receive the operation address for writing to the UART. Function preparations need to ensure that there is enough space in the receive buffer inside the UART slave to avoid data overflow and facilitate receiving the upcoming UART data in the subsequent clock cycles.

[0082] Changing the AWREADY write address handshake signal on the AXI bus specifically means that the UART slave raises the AWREADY signal to make the AWREADY write address handshake signal valid, indicating that the UART slave is ready to receive the operation address for writing to the UART. If the AWREADY write address handshake signal is at a low level, indicating that the AWREADY write address handshake signal is invalid, the ARM host needs to wait until the signal becomes valid to ensure the accuracy and synchronization of data transmission. The rising edge of T1 and the rising edge of T0 are at least one clock cycle apart. In this embodiment, it is assumed that the waiting time is the shortest, that is, the rising edge of T1 and the rising edge of T0 are one clock cycle apart. T0 - T5 are all rising edge moments and there is one clock cycle between adjacent moments.

[0083] A write address is considered complete only when both the AWVALID and AWREADY signals are set high, and the ARM host can then proceed with subsequent write operations. Through the AWREADY write address handshake signal, the operation address for writing to the UART is successfully transferred between the ARM host and the UART slave. This AWREADY write address handshake signal gives the UART slave sufficient time to prepare to receive the operation address for writing to the UART, ensuring not only accurate data transmission but also correct storage locations, avoiding incorrect data writes, and improving overall performance.

[0084] S12: At the rising edge of T2, the ARM host obtains the AWREADY write address handshake signal from the UART slave and prepares to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data to be written to the UART; at the same time, it prepares the BREADY write response handshake signal.

[0085] Among them, the WDATA write data is a data transmission signal responsible for transmitting the data that the RAM host wants to write to the UART slave, which is specifically the data to be written to the UART in this embodiment. The WVALID write data valid signal is a key control signal used to indicate the validity of the WDATA write data. Only when WVALID is in a valid state can the UART slave recognize that the ADATA write data at this time is acceptable for reception and used for write operations. Preparing the BREADY write response handshake signal means that the ARM host is ready to receive the write response signal, ensuring that the UART slave can promptly feedback the status after completing the write operation, thereby achieving the efficiency and reliability of data transmission.

[0086] It should be noted that preparing to output the WDATA write data also includes:

[0087] S121: Determine whether the currently transmitted WDATA write data is the last data;

[0088] If so, execute S122; if not, execute S123.

[0089] S122: The ARM host raises the WLAST signal while outputting the WDATA write data;

[0090] S123: Output the WDATA write data sequentially until all data is transmitted.

[0091] In this way, the ARM host can precisely control the end of the data stream, thus avoiding data loss or misalignment. At the same time, the timely raising of the WLAST signal also provides a clear end flag for the UART slave, optimizing the efficiency of data reception and processing, and further enhancing the stability and reliability of the system.

[0092] S13: At the rising edge of T3, if the UART slave does not pull up the WREADY write data handshake signal, the ARM host needs to keep the WDATA write data and WVALID write data valid signals stable and wait for the WREADY write data handshake signal to be valid;

[0093] Among them, the WREADY write data handshake signal not being set to high level means that the UART slave is not ready to receive data. The ARM host needs to remain in a waiting state until the WREADY signal becomes valid to avoid incorrect data transmission. Although this waiting mechanism adds a little delay, it ensures that the UART slave is fully prepared, avoids data misalignment or loss, and improves the stability and reliability of data transmission.

[0094] S14: At the rising edge of T4, if the UART slave sets the WREADY write data handshake signal to be valid, then the UART slave receives the data to be written by the UART; the ARM host obtains the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus;

[0095] Among them, other signals include but are not limited to signals such as WDATA, WLAST, and WVALID. Releasing the occupation of other signals on the AXI bus is to avoid signal conflicts and ensure the singularity and accuracy of data transmission. At the same time, this step also marks the successful completion of the current write data, provides a clear starting point for subsequent data transmission, and further optimizes the overall operation efficiency of the system.

[0096] S15: At the rising edge of T5, the UART slave completes data reception, sends the BVALID write response valid signal to the ARM host; at the same time, the data to be written by the UART is output through the TXD pin of the UART transmission module to complete the UART communication write operation based on the AXI bus.

[0097] Among them, the rising edge moment of T5 is the key node for the UART slave to complete data reception confirmation. The UART slave will set BVALID to valid at an appropriate time, which is usually after the relevant processing of the write operation is completed and accurate write response information is generated. When the BVALID write response is valid, it is confirmed that the data has been successfully written to the UART slave, and the current write operation ends. When the ARM host detects that BVALID is valid, it judges whether the write operation is successful or what kind of error occurs according to the value of BRESP. Among them, BRESP is a signal specifically used for write response in the AXI bus protocol. It carries the response status of the UART slave to the write operation, including different statuses such as "OK" indicating that the write operation is successfully completed, "SLVERR" indicating an error in the slave device, and "DECERR" indicating an address decoding error. The ARM host obtains accurate information about the write operation by monitoring the BRESP signal to decide subsequent operations, such as whether to resend the write operation request or perform error handling. Through this mechanism, the system not only ensures the efficiency and security of data transmission, but also realizes the rapid response and handling of error statuses, thereby enhancing the stability and reliability of the entire communication process.

[0098] It should be noted that before the rising edge moment of T0, it also includes:

[0099] The ARM host sends a request to access the UART slave to the AXI bus; the UART slave responds to the request through the AXI bus, and then the ARM host obtains the permission to access the UART slave.

[0100] Before performing the write operation, an access request mechanism needs to be carried out to ensure the orderly control of permissions and data access.

[0101] In a preferred embodiment, if there are multiple hosts requesting the bus simultaneously, this process needs to be implemented through the arbitration mechanism of the AXI bus. The ARM host uses the bus request signal on the AHB bus to indicate to the bus arbiter that it hopes to obtain the bus usage right to access the UART slave. The bus arbiter decides whether to grant the bus usage right to the ARM host when multiple master devices request the bus simultaneously according to the preset arbitration algorithm. If the priority of the ARM host is higher or it is its turn to use the bus according to the arbitration rules, the arbiter will send a bus grant signal to the ARM host. After receiving the bus grant signal, the ARM host indicates that it has obtained the permission to access the UART slave and can start sending access requests to the UART slave on the bus. The arbitration mechanism ensures the reasonable allocation of bus resources, avoids conflicts, and improves the efficiency of system resources.

[0102] It can be understood that the ARM host in this embodiment can also be other processors with AXI bus interfaces, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism to further expand the application scenarios. The UART module can also be other low-speed devices such as I2C and SPI. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR and SRAM.

[0103] In this embodiment, the ARM host realizes the communication read operation with the UART module through the AXI bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. The added handshake signal mechanism further ensures that both the master and slave can correctly and reliably exchange data, reducing the communication error rate and improving the stability and efficiency of data exchange.

[0104] Embodiment 2

[0105] This embodiment of the specification proposes an implementation method for UART communication based on the AXI bus, such as Figure 4 , which specifically includes the following steps:

[0106] S20: At the rising edge of T7, the UART host outputs the operation address for writing to the RAM to the AWADDR of the AXI bus, and at the same time pulls up AWVALID to obtain the write address valid signal;

[0107] Among them, the rising edge of T7 refers to the moment when the clock signal changes from low level to high level, which is at the beginning of a timing diagram, as Figure 5 shown, marking the start of the read operation. AWADDR provides the target address to ensure the accuracy of data transmission. In this embodiment, the AWADDR outputs the operation address for writing to the RAM, including the address field. Pulling up the AWVALID signal indicates that the AWVALID signal is at a high level at this time, indicating that the write address is valid, that is, the write address AWADDR being sent by the UART host is valid, and the UART host is ready to start the write operation.

[0108] S21: At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding functional preparations; after the RAM slave completes the functional preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the RAM from the AXI bus;

[0109] Among them, the rising edge of T8 marks that the RAM slave confirms the validity of the operation address for writing to the RAM through the AXI bus and performs functional preparations to receive the operation address for writing to the RAM. The functional preparations need to ensure that there is enough space in the receive buffer inside the RAM slave to avoid data overflow, facilitating the reception of the upcoming RAM data in subsequent clock cycles.

[0110] The AWREADY write address handshake signal on the AXI bus is changed such that the RAM slave pulls up the AWREADY signal, making the AWREADY write address handshake signal valid, indicating that the RAM slave is ready to receive the operation address for writing to the RAM. If the AWREADY write address handshake signal is at a low level, indicating that the AWREADY write address handshake signal is invalid, the UART master needs to wait until the signal becomes valid to ensure the accuracy and synchronization of data transmission. The rising edge of T8 and the rising edge of T7 are separated by at least one clock cycle. In this embodiment, it is assumed that the waiting time is the shortest, that is, the rising edge of T8 and the rising edge of T7 are separated by one clock cycle. T6 - T11 are all rising edge moments and there is a one - clock - cycle separation between adjacent moments.

[0111] Only when both the AWVALID and AWREADY signals are set to a high level is a write address considered to be completed, and the UART master can then continue with subsequent write operations. Through the AWREADY write address handshake signal, the operation address for writing to the RAM is successfully transmitted between the UART master and the RAM slave. This AWREADY write address handshake signal provides the RAM slave with sufficient time to prepare to receive the operation address for writing to the RAM, not only ensuring the accuracy of data transmission but also ensuring the correct storage location, avoiding incorrect data writing, and improving the overall performance.

[0112] S22: At the rising edge of T9, the UART master obtains the AWREADY write address handshake signal of the RAM slave and prepares to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data input by the UART; at the same time, it prepares the BREADY write response handshake signal;

[0113] Among them, the WDATA write data is a data transmission signal responsible for transmitting the data that the UART master wants to write to the RAM slave. In this embodiment, it is specifically the data to be written to the RAM. The WVALID write data valid signal is a key control signal used to indicate the validity of the WDATA write data. Only when WVALID is in a valid state can the RAM slave recognize that the ADATA write data at this time can be received and used for the write operation. Preparing the BREADY write response handshake signal indicates that the UART master is ready to receive the write response signal, ensuring that the RAM slave can promptly feedback the status after completing the write operation, thereby achieving the efficiency and reliability of data transmission.

[0114] It should be noted that preparing to output the WDATA write data also includes:

[0115] S221: Determine whether the currently transmitted WDATA write data is the last data;

[0116] If so, the UART host raises the WLAST signal while outputting the WDATA write data; if not, the WDATA write data is output sequentially until all data is transmitted.

[0117] In this way, the UART host can accurately control the end of the data stream, thus avoiding data loss or misalignment. At the same time, the timely raising of the WLAST signal also provides a clear end flag for the RAM slave, optimizing the efficiency of data reception and processing, and further enhancing the stability and reliability of the system.

[0118] S23: At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to valid, then the RAM slave receives the data to be written by the UART; the UART host obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus;

[0119] Among them, other signals include but are not limited to signals such as WDATA, WLAST, and WVALID. Releasing the occupation of other signals on the AXI bus is to avoid signal conflicts and ensure the singularity and accuracy of data transmission. At the same time, this step also marks the successful completion of the current write data, providing a clear starting point for subsequent data transmission and further optimizing the overall operation efficiency of the system.

[0120] S24: At the rising edge of T11, the RAM slave completes data reception and sends a BVALID write response valid signal to the UART host; the data input by the UART is stored in the RAM slave; the ARM host reads the data input by the UART in the RAM slave through the AXI bus to complete the read operation of the UART communication based on the AXI bus.

[0121] In this embodiment, by first storing the data in the RAM slave and then directly reading it by the ARM host, the delay and interference in the data transmission process are effectively reduced, and the communication efficiency and data integrity are improved. At the same time, this mechanism simplifies the data processing flow, reduces the system complexity, and provides a reliable guarantee for efficient and stable UART communication.

[0122] It should be noted that before the rising edge of T6, it also includes:

[0123] From the rising edge of T6 to the rising edge of T7, the RXD pin of the UART receiving module receives the input communication sent by the UART transmitting module; the UART host sends a request to occupy the bus to access the RAM slave through the AXI bus, and the signal RAM slave responds to the request through the AXI bus, then the UART host obtains the permission to access the RAM slave.

[0124] There are multiple clock cycles between the rising edge of T6 and the rising edge of T7, and the RXD continuously receives data to ensure the integrity of the information. The UART host obtains the access permission first. This process ensures that the communication link is established and the data transmission is ready before the rising edge of T7, improving the communication efficiency.

[0125] It can be understood that the ARM host in this embodiment can also be other processors with an AXI bus interface, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism, further expanding the application scenarios. The UART module can also be other low-speed devices such as I2C, SPI, etc. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR, SRAM, etc.

[0126] In this embodiment, the ARM host realizes the communication read operation with the UART module through the AXI bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving the chip design area. The added handshake signal mechanism further ensures that both the master and slave can correctly and reliably exchange data, reducing the communication error rate and improving the stability and efficiency of data exchange.

[0127] Embodiment 3

[0128] An implementation system 500 for UART communication based on the AXI bus, as Figure 6 specifically includes:

[0129] A data writing unit 501, which is used for the ARM host to directly write data to the UART slave, specifically including:

[0130] At the rising edge of T0, the ARM host outputs the operation address for writing to the UART to the AWADDR of the AXI bus, and at the same time pulls up AWVALID to obtain the write address valid signal;

[0131] At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the UART slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the UART from the AXI bus;

[0132] At the rising edge of T2, the ARM host acquires the AWREADY write address handshake signal of the UART slave, and prepares to output the WDATA write data and the WVALID write data valid signal. Among them, the WDATA write data is the data to be written by the UART; at the same time, it prepares the BREADY write response handshake signal.

[0133] At the rising edge of T3, the UART slave does not pull up the WREADY write data handshake signal, and the ARM host keeps the WDATA write data and the WVALID write data valid signal stable, waiting for the WREADY write data handshake signal to be valid.

[0134] At the rising edge of T4, the UART slave sets the WREADY write data handshake signal to be valid, then the UART slave receives the data to be written by the UART; the ARM host acquires the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus.

[0135] The data transmission unit 502 is used to realize the external transmission of the written data, specifically including:

[0136] At the rising edge of T5, the UART slave completes the data reception, and sends the BVALID write response valid signal to the ARM host; at the same time, it executes the UART output of the data to be written by the UART through the TXD pin of the UART sending module, and completes the UART communication write operation based on the AXI bus.

[0137] It should be noted that before the rising edge of T0, it also includes:

[0138] The ARM host sends a request to access the UART slave to the AXI bus; the UART slave responds to the request through the AXI bus, then the ARM host acquires the permission to access the UART slave.

[0139] It should be noted that preparing to output the WDATA write data also includes:

[0140] Judging whether the currently transmitted WDATA write data is the last data.

[0141] If so, the ARM host pulls up the WLAST signal while outputting the WDATA write data.

[0142] If not, the WDATA write data is output sequentially until all data is transmitted.

[0143] It can be understood that the ARM host in this embodiment can also be other processors with AXI bus interfaces, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism to further expand the application scenarios. The UART module can also be other low-speed devices such as I2C and SPI. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR and SRAM.

[0144] In this embodiment, the ARM host realizes the communication write operation with the UART module through the AXI bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. The added handshake signal mechanism further ensures that both the master and slave can correctly and reliably exchange data, reducing the communication error rate and improving the stability and efficiency of data exchange.

[0145] Embodiment 4

[0146] An implementation system 600 for UART communication based on the AXI bus, as Figure 1 applied to an ARM host 100, a RAM slave 200, an AXI bus 300, and a UART module 400, where the UART module 400 includes a UART host 403, a UART slave 401, a UART transmission module 402, and a UART reception module 404, as Figure 7 specifically including:

[0147] A data storage unit 601 for the UART host to store data in the RAM slave, specifically including:

[0148] The UART host outputs the operation address for writing to the RAM to the AWADDR of the AXI bus at the rising edge of T7, and at the same time raises AWVALID to obtain the write address valid signal;

[0149] At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding function preparations; after the RAM slave completes the function preparations, it changes the AWREADY write address handshake signal on the AXI bus and obtains the operation address for writing to the RAM from the AXI bus;

[0150] At the rising edge of T9, the UART host obtains the AWREADY write address handshake signal of the RAM slave, prepares to output the WDATA write data and the WVALID write data valid signal, where the WDATA write data is the data input by the UART; at the same time, it prepares the BREADY write response handshake signal;

[0151] At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to valid, and then the RAM slave receives the data to be written by the UART; the UART master obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus.

[0152] The data reading unit 602 is used for the ARM master to read data from the RAM slave, and specifically includes:

[0153] At the rising edge of T11, the RAM slave completes data reception and sends a BVALID write response valid signal to the UART master; the data input by the UART is stored in the RAM slave; the ARM master reads the data input by the UART in the RAM slave through the AXI bus, and completes the UART communication read operation based on the AXI bus.

[0154] Before the rising edge of T6, it also includes:

[0155] From the rising edge of T6 to the rising edge of T7, the RXD pin of the UART receiving module receives the input communication signal sent by the UART sending module; the UART master sends a request to occupy the bus to access the RAM slave to the AXI bus, and the RAM slave responds to the request through the AXI bus, then the UART master obtains the permission to access the RAM slave.

[0156] Preparing to output WDATA write data also includes:

[0157] Determine whether the currently transmitted WDATA write data is the last data;

[0158] If so, when the UART master outputs the WDATA write data, it raises the WLAST signal;

[0159] If not, output the WDATA write data in sequence until all data is transmitted.

[0160] It can be understood that the ARM master in this embodiment can also be other processors with AXI bus interfaces, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism and further expand the application scenarios. The UART module can also be other low-speed devices such as I2C and SPI. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR and SRAM.

[0161] In this embodiment, the ARM host realizes the communication read operation with the UART module through the AXI bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. The added handshake signal mechanism further ensures that both the master and slave can correctly and reliably exchange data, reducing the communication error rate and enhancing the stability and efficiency of data exchange.

[0162] As described above, the above is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for implementing UART communication based on AXI bus, characterized in that: The specific steps include: The ARM host outputs the write UART operation address to the AWADDR of the AXI bus at the rising edge of T0, and pulls up AWVALID to obtain a valid write address signal. At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding functional preparation; the UART slave completes the functional preparation, changes the AWREADY write address handshake signal on the AXI bus, and obtains the operation address of the write UART from the AXI bus; At the rising edge of T2, the ARM host obtains the AWREADY write address handshake signal of the UART slave, and prepares to output WDATA write data and WVALID write data valid signals, wherein the WDATA write data is the data to be written by the UART; and prepares the BREADY write response handshake signal at the same time; At the rising edge of T3, the UART slave does not pull up the WREADY write data handshake signal, and the ARM host keeps the WDATA write data and WVALID write data valid signals stable, waiting for the WREADY write data handshake signal to be valid; At the rising edge of T4, the UART slave sets the WREADY write data handshake signal to be valid, and the UART slave receives the data to be written by the UART; the ARM host obtains the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus; At the rising edge of T5, the UART slave completes data reception and sends a BVALID write response valid signal to the ARM host; at the same time, the data to be written by the UART is output by the UART through the TXD pin of the UART sending module, completing the UART communication write operation based on the AXI bus.

2. The method for implementing UART communication based on AXI bus according to claim 1, characterized in that: The method further includes before the rising edge of T0: The ARM host sends a request to the AXI bus to access the UART slave; the UART slave responds to the request through the AXI bus, and the ARM host obtains permission to access the UART slave.

3. The method for implementing UART communication based on AXI bus according to claim 1, characterized in that: Preparation for outputting WDATA write data also includes: Determine whether the currently transmitted WDATA write data is the last data; If yes, the ARM host pulls up the WLAST signal while outputting WDATA write data; If not, the WDATA write data is output in sequence until all data transmission is completed.

4. A method for implementing UART communication based on AXI bus, characterized in that: The specific steps include: At the rising edge of T7, the UART host outputs the operation address of writing RAM to AWADDR of the AXI bus, and at the same time pulls up AWVALID to obtain the valid signal of writing address; At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding functional preparation; The RAM slave completes the functional preparation, changes the AWREADY write address handshake signal on the AXI bus, and obtains the operation address of the write RAM from the AXI bus; At the rising edge of T9, the UART host obtains the AWREADY write address handshake signal of the RAM slave, and prepares to output WDATA write data and WVALID write data valid signals, wherein the WDATA write data is the data input by the UART; and prepares the BREADY write response handshake signal at the same time; At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to be valid, and the RAM slave receives the data to be written by the UART; the UART host obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus; At the rising edge of T11, the RAM slave completes data reception and sends a BVALID write response valid signal to the UART host; the data input by UART is stored in the RAM slave; the ARM host reads the data input by UART in the RAM slave through the AXI bus, completing the UART communication read operation based on the AXI bus.

5. The method for implementing UART communication based on AXI bus according to claim 4, characterized in that: The method further includes before the rising edge of T6: From the rising edge time of T6 to the rising edge time of T7, the RXD pin of the UART receiving module receives the input communication signal sent by the UART sending module; the UART host sends a request to the AXI bus to occupy the bus to access the RAM slave, and the RAM slave responds to the request through the AXI bus, then the UART host obtains permission to access the RAM slave.

6. The method for implementing UART communication based on AXI bus according to claim 4, characterized in that: Preparation for outputting WDATA write data also includes: Determine whether the currently transmitted WDATA write data is the last data; If yes, the UART host pulls up the WLAST signal while outputting WDATA write data; If not, the WDATA write data is output in sequence until all data transmission is completed.

7. A UART communication implementation system based on AXI bus, characterized in that: Specifically include: The data writing unit is used by the ARM host to write data directly to the UART slave, including: The ARM host outputs the operation address of writing UART to AWADDR of the AXI bus at the rising edge of T0, and at the same time pulls up AWVALID to obtain a valid signal of writing address; At the rising edge of T1, the UART slave receives the write address valid signal on the AXI bus and performs corresponding functional preparation; the UART slave completes the functional preparation, changes the AWREADY write address handshake signal on the AXI bus, and obtains the operation address of the write UART from the AXI bus; At the rising edge of T2, the ARM host obtains the AWREADY write address handshake signal of the UART slave, and prepares to output WDATA write data and WVALID write data valid signals, wherein the WDATA write data is the data to be written by the UART; and prepares the BREADY write response handshake signal at the same time; At the rising edge of T3, the UART slave does not pull up the WREADY write data handshake signal, and the ARM host keeps the WDATA write data and WVALID write data valid signals stable, waiting for the WREADY write data handshake signal to be valid; At the rising edge of T4, the UART slave sets the WREADY write data handshake signal to be valid, and the UART slave receives the data to be written by the UART; the ARM host obtains the WREADY write data handshake signal of the UART slave and releases the occupation of other signals on the AXI bus; The data transmission unit is used to realize the external transmission of written data, specifically including: At the rising edge of T5, the UART slave completes data reception and sends a BVALID write response valid signal to the ARM host; at the same time, the data to be written by the UART is output by the UART through the TXD pin of the UART sending module, completing the UART communication write operation based on the AXI bus.

8. The system for implementing UART communication based on AXI bus according to claim 7, characterized in that: The method further includes before the rising edge of T0: The ARM host sends a request to the AXI bus to access the UART slave; the UART slave responds to the request through the AXI bus, and the ARM host obtains permission to access the UART slave; Preparation for outputting WDATA write data also includes: Determine whether the currently transmitted WDATA write data is the last data; If yes, the ARM host pulls up the WLAST signal while outputting WDATA write data; If not, the WDATA write data is output in sequence until all data transmission is completed.

9. A UART communication implementation system based on AXI bus, characterized in that: Specifically include: The data storage unit is used for the UART host to store data in the RAM slave, specifically including: The UART host outputs the operation address of writing RAM to AWADDR of the AXI bus at the rising edge of T7, and at the same time pulls up AWVALID to obtain a valid signal of writing address; At the rising edge of T8, the RAM slave receives the write address valid signal on the AXI bus and performs corresponding functional preparation; the RAM slave completes the functional preparation, changes the AWREADY write address handshake signal on the AXI bus, and obtains the operation address of the write RAM from the AXI bus; At the rising edge of T9, the UART host obtains the AWREADY write address handshake signal of the RAM slave, and prepares to output WDATA write data and WVALID write data valid signals, wherein the WDATA write data is the data input by the UART; and prepares the BREADY write response handshake signal at the same time; At the rising edge of T10, the RAM slave sets the WREADY write data handshake signal to be valid, and the RAM slave receives the data to be written by the UART; the UART host obtains the WREADY write data handshake signal of the RAM slave and releases the occupation of other signals on the AXI bus; The data reading unit is used by the ARM host to read data from the RAM slave, specifically including: At the rising edge of T11, the RAM slave completes data reception and sends a BVALID write response valid signal to the UART host; the data input by UART is stored in the RAM slave; the ARM host reads the data input by UART in the RAM slave through the AXI bus, completing the UART communication read operation based on the AXI bus.

10. The system for implementing UART communication based on AXI bus according to claim 9, characterized in that: The method further includes before the rising edge of T6: From the rising edge time of T6 to the rising edge time of T7, the RXD pin of the UART receiving module receives the input communication signal sent by the UART sending module; the UART host sends a request to the AXI bus to occupy the bus to access the RAM slave, and the RAM slave responds to the request through the AXI bus, then the UART host obtains permission to access the RAM slave; Preparation for outputting WDATA write data also includes: Determine whether the currently transmitted WDATA write data is the last data; If yes, the UART host pulls up the WLAST signal while outputting WDATA write data; If not, the WDATA write data is output in sequence until all data transmission is completed.

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