Multi-protocol communication control module and electronic equipment
By designing a multi-protocol communication control module, the limitations of the existing technology in processing speed, compatibility range and energy consumption control are solved, and compatible with multiple communication protocols under the same module topology is realized, which significantly reduces hardware costs and avoids CPU time consumption.
Patent Information
- Application Number
- CN202411951546.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-05-30
AI Technical Summary
Existing multi-protocol gateway products have limitations in terms of processing speed, compatibility range and energy consumption control, and cannot fully meet the growing demand for industrial and IoT applications.
A multi-protocol communication control module is designed, including a cache unit, a shift register unit, a counter unit and an input and output unit. The counter and shift register units can be flexibly configured through register operation, and are compatible with multiple serial communication protocols.
It realizes compatibility with multiple communication protocols under the same module topology, significantly reduces hardware costs, and does not take up CPU time after starting work, meeting the needs of industrial and Internet of Things applications.
Smart Images
Figure CN120067031A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to a multi - protocol communication control module and an electronic device. Background Art
[0002] Today, with the rapid development of Internet of Things and industrial automation technologies, the interconnection and interoperability between devices have become increasingly important. However, since different devices may adopt a variety of different communication protocols, this has led to complexity in data exchange and communication. The compatibility problem of communication protocols has become a key challenge for achieving seamless data sharing and exchange between devices. Although related technologies provide some multi - protocol gateway products that can, to a certain extent, achieve data conversion and forwarding between different protocols, there are still limitations in terms of processing speed, compatibility range, and energy consumption control, and they cannot fully meet the growing industrial and Internet of Things application requirements. Summary of the Invention
[0003] To solve the above - mentioned technical problems, the present disclosure provides a multi - protocol communication control module and an electronic device.
[0004] The present disclosure provides a multi - protocol communication control module, including a buffer unit, a shift register unit, a counter unit, and an input / output unit; the buffer unit is connected to the shift register unit and is used to buffer communication data between the buffer unit and the shift register unit; the shift register unit is also connected to the counter unit and is used to receive the counting signal provided by the counter unit, and the shift register unit is also used to transmit communication data based on the counting signal; the counter unit is also connected to the input / output unit and is used to generate the counting signal according to the input / output signal provided by the input / output unit; the input / output unit is also connected to the shift register unit and is used to provide the input / output signal to the shift register unit, and the shift register unit is also used to transmit serial communication data based on the input / output signal.
[0005] Optionally, the multi - protocol communication control module further includes a register configuration unit; the register configuration unit is connected to the shift register unit through the buffer unit and is used to control the shift register unit to transmit communication data.
[0006] Optionally, the buffer unit includes a transmit buffer unit and a receive buffer unit; both the transmit buffer unit and the receive buffer unit are connected to the shift register unit; the transmit buffer unit is used to buffer communication data sent to the shift register unit; the receive buffer unit is used to buffer communication data sent by the shift register unit.
[0007] Optionally, the shift register unit includes a transmit shift register and a receive shift register; the transmit shift register is configured to convert the transmitted communication data from parallel data into serial data; the receive shift register is configured to convert the received communication data from serial data into parallel data.
[0008] Optionally, the counter unit includes a plurality of counters, and each of the counters can be connected to the shift register unit.
[0009] Optionally, the multi-protocol communication control module further includes a first gating circuit; the shift register unit and the plurality of counters are connected through the first gating circuit, and any one of the counters can be connected to the shift register unit through the first gating circuit.
[0010] Optionally, the input / output unit includes a plurality of input / output interfaces, and each of the input / output interfaces can be connected to the counter unit and the counter unit.
[0011] Optionally, the multi-protocol communication control module further includes a second gating circuit; the shift register unit and the plurality of input / output interfaces are connected through the second gating circuit, and any one of the input / output interfaces can be connected to the shift register unit through the second gating circuit; the counter unit and the plurality of input / output interfaces are connected through the second gating circuit, and any one of the input / output interfaces can be connected to the counter unit through the second gating circuit.
[0012] Optionally, the counter unit includes a plurality of counters, and any one of the counters can be connected to any one of the input / output interfaces through the second gating circuit.
[0013] Based on the same inventive concept, the present disclosure also provides an electronic device including the multi-protocol communication control module.
[0014] The technical solution provided by the present disclosure has the following advantages compared with the prior art: The multi-protocol communication control module provided by the present disclosure can be compatible with multiple serial communication protocols under the same module topology, and through register operations, the counters and the shift register unit can be flexibly configured, with strong flexibility, significantly reducing the hardware cost, and after starting to work, it does not require CPU intervention in the middle and does not occupy CPU time. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.
[0016] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0017] Figure 1 Schematic diagram of the structure of a multi - protocol communication control module provided by an embodiment of the present disclosure;
[0018] Figure 2 Schematic diagram of the structure of another multi - protocol communication control module provided by an embodiment of the present disclosure;
[0019] Figure 3 Schematic diagram of the structure of another multi - protocol communication control module provided by an embodiment of the present disclosure. Detailed implementation manners
[0020] In order to more clearly understand the above - mentioned objects, features, and advantages of the embodiments of the present disclosure, the following will further describe the solutions of the embodiments of the present disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.
[0021] Many specific details are set forth in the following description to facilitate a thorough understanding of the embodiments of the present disclosure, but the embodiments of the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.
[0022] Related technologies usually use an MCU core + a dedicated interface controller circuit to implement the functions of each serial interface. The dedicated interface controller is responsible for ensuring the correctness of the communication timing and implementing the underlying hardware circuits of various configurable functions according to the published international standard protocol specifications. For example, SPI can be configured as a master or slave mode, and UART can be configured with 1 stop bit or 2 stop bits, etc.
[0023] For companies developing MCU (Microcontroller Unit) chips, the dedicated serial interface circuit will encounter the problem of the cost - effectiveness of silicon area during the chip design process. For example, for audio protocols, if all currently mainstream audio protocols need to be fully supported, chip designers need to design an application - specific integrated circuit using hardware design languages such as Verilog to implement all the functions specified in the protocols one by one, which will consume a significant amount of silicon area and manufacturing cost, and most of these fully implemented functions will not be fully utilized in most scenarios.
[0024] For users of MCU chips, it is common to encounter the problem that the serial interfaces are insufficient in the later stage of a project due to increased requirements. Based on experience, they can only reserve more serial interfaces than the actual demand during the chip selection in the early stage of the project, thus increasing the chip usage cost. If users try to simulate various serial interface protocols in software to reduce hardware costs, it will occupy the CPU (Central Processing Unit) time and may affect other already debugged software modules.
[0025] In view of this, embodiments of the present disclosure provide a multi-protocol communication control module, as Figure 1 shown, including a buffer unit 10, a shift register unit 20, a counter unit 30, and an input / output unit 40.
[0026] The buffer unit 10 is connected to the shift register unit 20 and is used to buffer the communication data between the buffer unit 10 and the shift register unit 20.
[0027] The buffer unit 10 is used to temporarily store the received data or the data to be sent. When processing multiple communication protocols, the buffer unit 10 can store data in different protocol formats, enabling the correct conversion and transmission of data between different protocols.
[0028] The shift register unit 20 can process data streams at different rates and can rearrange or format the data according to the requirements of different communication protocols.
[0029] The shift register unit 20 is also connected to the counter unit 30 and is used to receive the counting signal provided by the counter unit 30. The shift register unit 20 is also used to transmit communication data based on the counting signal.
[0030] The counter unit 30 can be used to control the data transmission rate and synchronization. In different communication protocols, the data transmission rates may be different. The counter unit 30 can help the module maintain the correct timing when switching between different protocols.
[0031] The counter unit 30 is also connected to the input / output unit 40 and is used to generate a counting signal according to the input / output signal provided by the input / output unit 40.
[0032] The input / output unit 40 is also connected to the shift register unit 20 and is used to provide the input / output signal to the shift register unit 20. The shift register unit 20 is also used to transmit serial communication data based on the input / output signal.
[0033] The input / output unit 40 reserves corresponding numbers of input / output interfaces for different communication protocols.
[0034] The multi-protocol communication control module provided by the embodiments of the present disclosure can be compatible with multiple communication protocols under the same module topology, including serial communication protocols such as UART, SPI, IIC, IIS, USART, PWM, etc., and common audio protocols such as Left Justified, Right Justified, Dsp / Pcm, etc. And through register operations, the counter and shift register unit can be flexibly configured, with strong flexibility, significantly reducing the hardware cost. And after starting to work, it does not require CPU intervention in the middle and does not occupy CPU time.
[0035] In some embodiments, as Figure 2 shown, the multi-protocol communication control module further includes a register configuration unit 50.
[0036] The register configuration unit 50 is connected to the shift register unit 20 through the buffer unit 10 and is used to control the shift register unit 20 to transmit communication data, so as to realize the read and write control of the internal register unit. Specifically, the register configuration unit 50 is communicatively connected to the AHB bus.
[0037] In some embodiments, as Figure 3 shown, the buffer unit 10 includes a transmit buffer unit 11 and a receive buffer unit 12; both the transmit buffer unit 11 and the receive buffer unit 12 are connected to the shift register unit 20.
[0038] The transmit buffer unit 11 is used to buffer the communication data sent to the shift register unit 20; the receive buffer unit 12 is used to buffer the communication data sent by the shift register unit 20.
[0039] Specifically, the above buffer unit 10 is a FIFO (First-In, First-Out) unit. The FIFO unit is a hardware or software component that processes data according to the first-in, first-out principle. It allows data items to be added (enqueued) at one end (the tail) and removed (dequeued) at the other end (the head). The key feature of the FIFO unit is its operation limitation, mainly including two operations: enqueue and dequeue, ensuring that the processing order of data items is the same as the order in which they are added.
[0040] The FIFO unit can be implemented as a memory block at the hardware level for buffering input / output operations, while at the software level it can be implemented by specific data structures such as arrays or linked lists. It may require a synchronization mechanism in a multi-threaded or multi-process environment to prevent data competition and inconsistency. The FIFO unit has a simple design, fast operation, can effectively manage the data stream, avoid data overflow and underflow problems, and ensure the orderliness and synchronization of data processing.
[0041] Specifically, the transmission buffer unit 11 realizes the buffering of transmitted data. The register configuration unit 50 writes the data to be transmitted into the transmission buffer unit 11 in advance through the AHB bus. When the shift register unit 20 is idle, it will automatically extract the new data to be transmitted from the transmission buffer unit 11 and send the data out in a set pattern. The reception buffer unit 12 realizes the buffering of the received data and waits for the shift register unit 20 to read it.
[0042] In specific implementation, both the above-mentioned transmission buffer unit 11 and reception buffer unit 12 are FIFO units with a bit width of 32 bits and a depth of 16.
[0043] In some embodiments, as Figure 3 shown, the shift register unit 20 includes a transmission shift register 21 and a reception shift register 22.
[0044] The transmission shift register 21 is used to convert the transmitted communication data from parallel data to serial data and is connected to the transmission buffer unit 11; the reception shift register 22 is used to convert the received communication data from serial data to parallel data and is connected to the reception buffer unit 12.
[0045] In specific implementation, both the transmission shift register 21 and the reception shift register 22 are 32-bit shift registers.
[0046] In specific implementation, the transmission shift register 21 also has the following characteristics: the shift clock is provided by the counter unit 30, and when the counter unit 30 is full, it will trigger the transmission shift register 21 to shift one bit; the transmission shift register 21 can output in big-endian or little-endian mode; it is possible to select whether to insert a start bit or an end bit in hardware; when idle, it can be configured to output a fixed value of 0 / 1 forcibly or the value of the last shift output; when idle, it can be configured to output high level or low level; the number of bits for a single transmission can be configured.
[0047] In specific implementation, the reception shift register 22 also has the following characteristics: the shift clock is provided by the counter unit 30, and when the counter unit 30 is full, it will trigger the reception shift register 22 to shift one bit; the reception shift register 22 can input in big-endian or little-endian mode; it is possible to select whether to check the start bit or the end bit in hardware; the number of bits for a single transmission can be configured.
[0048] In some embodiments, as Figure 3 shown, the counter unit 30 includes multiple counters 31, and each counter 31 can be connected to the shift register unit 20. Furthermore, the shift register unit 20 can freely select the connected counter 31 to support different communication protocols.
[0049] In a specific embodiment, the counter unit 30 includes 4 completely identical 24-bit counters 31, which are used for the shifting speed, starting and stopping of the shift register unit 20. Each counter 31 has the following characteristics: it can be in the 24-bit mode or the dual 12-bit mode. In the dual 12-bit mode, the 24-bit counter will be separated into 2 12-bit counters and both will be in the working state; it can enable the use of the highest bit of the counter 31 to directly output a PWM waveform; the trigger source can be selected from the input clock, the PWM waveform input of other counters, or the input signal provided by the input / output unit; the trigger polarity can be selected as the rising edge, the falling edge, or both edges simultaneously; the re-count signal source can be selected from the input signal provided by the input / output unit, the PWM waveform input of other counters, and the flag signal for the transmit shift register 21 to read the transmit buffer unit 11.
[0050] In some embodiments, as Figure 3 shown, the multi-protocol communication control module further includes a first gating circuit 61; the shift register unit 20 is connected to multiple counters 31 through the first gating circuit 61, and any counter 31 can be connected to the shift register unit 20 through the first gating circuit 61, further improving the flexibility of the circuit.
[0051] In some embodiments, as Figure 3 shown, the input / output unit 40 includes multiple input / output interfaces 41, and each input / output interface 41 can be connected to the counter unit 30 and the shift register unit 20. Setting multiple input / output interfaces 41 enables the multi-protocol communication control module provided by the embodiments of the present disclosure to support serial communication protocols with different numbers of interfaces.
[0052] Specifically, the above input / output interface 41 is a GPIO (General Purpose Input / Output) interface. GPIO is a digital interface that allows a microcontroller, microprocessor, or system-on-chip to transfer data with external devices such as sensors, displays, and switches. GPIO pins are multifunctional and can be dynamically configured as input or output modes through software programming to achieve two-way communication. These pins can output high or low level signals to control devices or indicate status, and can also be configured as interrupt sources to trigger a quick response of the microcontroller when the status of external devices changes.
[0053] In some embodiments, as Figure 3As shown, the multi - protocol communication control module further includes a second gating circuit 62; the shift register unit 20 is connected to multiple input / output interfaces 41 through a first gating circuit 61 and the second gating circuit 62. Any input / output interface 41 can be connected to the shift register unit 20 through the first gating circuit 61 and the second gating circuit 62. At this time, the first gating circuit 61 and the second gating circuit 62 can be regarded as multi - throw switches; the counter unit 30 is connected to multiple input / output interfaces 41 through the second gating circuit 62. Any input / output interface 41 can be connected to the counter unit 30 through the second gating circuit 62. At this time, the first gating circuit 61 and the second gating circuit 62 can be regarded as multi - throw switches, further improving the flexibility of the circuit.
[0054] In some embodiments, as Figure 3 shown, the counter unit 30 includes multiple counters 31. Any counter 31 can be connected to any input / output interface 41 through the second gating circuit 62, further improving the flexibility of the circuit.
[0055] In a specific embodiment, the above - mentioned multi - protocol communication control module of the present disclosure supports the UART communication protocol through the following method.
[0056] The multi - protocol communication control module simulates UART transmission and needs to use a counter, a transmit shift register, and an input / output interface associated with the multi - protocol communication control module.
[0057] To save a counter resource, the counter can be in a dual 12 - Bit mode; the lower 12 - bit counter comparison value determines the baud rate of the serial port transmission (when it counts up once, the transmit shift register shifts once); the comparison value of the higher 12 - bit counter determines the number of bits transmitted by the serial port. The restart trigger source of the counter is set to the event of reading the transmit buffer unit, that is, when reading the data to be transmitted once, the counter restarts; the addition - subtraction trigger source of the counter is set to the module main clock.
[0058] The transmit shift register is used to convert the parallel data to be transmitted fetched from the transmit buffer unit into a UART_TX serial signal, and it is necessary to enable the automatic insertion of the start bit and the stop bit. After configuring the counter and the transmit shift register, the software fills the data to be transmitted into the transmit buffer unit buffer. The transmit clock is divided from the multi - protocol communication control module main clock, and the user can calculate the optimal division ratio according to the baud rate and the module main clock.
[0059] The multi - protocol communication control module simulates UART reception and needs to use 1 counter, a receive shift register, and an input / output interface associated with the multi - protocol communication control module.
[0060] To save one counter resource, the counter can be set to the dual 12-bit mode; the change rate of the value of the high 12-bit counter should correspond to the baud rate of the serial port; the comparison value of the high 12-bit counter determines the number of bits received by the serial port. The restart trigger source of the counter is set to be associated with the multi-protocol communication control module, that is, the UART_RX signal; the addition and subtraction trigger source of the counter is set to the module main clock.
[0061] The receive shift register is used to convert the UART_RX signal input from the input / output interface of the associated multi-protocol communication control module into parallel data and then write it into the receive buffer unit. The receive shift register needs to enable stop bit detection. After configuring the counter and the receive shift register, the software reads the received serial port data through interrupt or polling.
[0062] In a specific embodiment, the above multi-protocol communication control module of the present disclosure supports the SPI MASTER communication protocol through the following method.
[0063] The multi-protocol communication control module needs to use a counter and an input / output interface associated with the multi-protocol communication control module to simulate the SPI CSN signal.
[0064] The counter needs to enable the PWM output function. The counter comparison value register is set to (total time of a single SPI transmission) / (module main clock cycle). The high and low level duty cycles of the CSN waveform can be set through the register. The restart trigger source of the counter is set to the event of reading the transmit buffer unit, that is, when reading the data to be transmitted once, the counter restarts. The addition and subtraction trigger source of the counter is set to the module main clock.
[0065] The multi-protocol communication control module needs to use a counter and an input / output interface associated with the multi-protocol communication control module to simulate the SPI SCK signal.
[0066] To save one counter resource, the counter can be set to the dual 12-bit mode; the counter needs to enable the PWM output function. The low 12-bit counter comparison value register is set to (SPI SCK clock cycle) / (module main clock cycle). The high 12-bit counter comparison value register is set to the number of bits of a single SPI transmission. The restart trigger source of the counter is set to the event of reading the transmit buffer unit, that is, when reading the data to be transmitted once, the counter restarts. The addition and subtraction trigger source of the counter is set to the module main clock.
[0067] The multi-protocol communication control module needs to use a counter, a transmit shift register and an input / output interface associated with the multi-protocol communication control module to simulate the SPI MOSI signal.
[0068] The key to MOSI signal output lies in the control of the MOSI counter. The transmission shift register is mainly responsible for parallel-to-serial conversion, and the timing control is mainly completed by the counter. The addition and subtraction trigger source of the MOSI counter is set to the PWM output signal of the SCK counter. The restart trigger source of the MOSI counter is set to the PWM output signal of the CSN counter. Through the above trigger source settings, the MOSI counter will be synchronized with CSN / SCK, and then combined with the 4 different modes of the SPI protocol to set the corresponding trigger source polarities (rising edge / falling edge). For example, for the SPI mode0 (CPOL == 0, CPHA == 0) mode, the restart trigger source polarity of the MOSI counter needs to be set to falling edge trigger, that is, when the CSN signal falls, the MOSI counter needs to be able to restart. The addition and subtraction trigger source polarity of the MOSI counter needs to be set to falling edge trigger, that is, when the SCK signal falls, the MOSI counter can update the count value.
[0069] The multi-protocol communication control module needs to use a counter, a receive shift register, and an input / output interface associated with the multi-protocol communication control module to simulate MISO.
[0070] The key to receiving the MISO signal lies in the control of the MISO counter. The receive shift register is mainly responsible for serial-to-parallel conversion, and the timing control is mainly completed by the counter. The addition and subtraction trigger source of the MISO counter is set to the PWM output signal of the SCK counter. The restart trigger source of the MOSI counter is set to the PWM output signal of the CSN counter. Through the above trigger source settings, the MOSI counter will be synchronized with CSN / SCK, and then combined with the 4 different modes of the SPI protocol to set the corresponding trigger source polarities (rising edge / falling edge). For example, for the SPI mode0 (CPOL == 0, CPHA == 0) mode, the restart trigger source polarity of the MISO counter needs to be set to falling edge trigger, that is, when the CSN signal falls, the MOSI counter needs to be able to restart. The addition and subtraction trigger source polarity of the MOSI counter needs to be set to rising edge trigger, that is, when the SCK signal rises, the MISO counter can update the count value.
[0071] Those skilled in the art can use the multi-protocol communication control module to implement other communication protocols according to the content disclosed in the above embodiments, and will not be elaborated here.
[0072] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides an electronic device including the multi-protocol communication control module in any of the above embodiments.
[0073] The multi-protocol communication control module in the electronic device provided by the embodiments of the present disclosure can be compatible with multiple communication protocols under the same module topology, including serial communication protocols such as UART, SPI, IIC, IIS, USART, PWM, etc., and common audio protocols such as LeftJustified, Right Justified, Dsp / Pcm, etc. Moreover, through register operations, the counter and shift register units can be flexibly configured, with strong flexibility, significantly reducing the hardware cost. After starting to work, it does not require CPU intervention in the middle and does not occupy CPU time.
[0074] The device of the above embodiment includes the corresponding multi-protocol communication control module in any of the foregoing embodiments, and has the beneficial effects of the corresponding embodiments, which will not be elaborated here.
[0075] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the above element.
[0076] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described above, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A multi-protocol communication control module, characterized in that: It includes a cache unit, a shift register unit, a counter unit and an input-output unit; The buffer unit is connected to the shift register unit and is used to buffer the communication data between the buffer unit and the shift register unit; The shift register unit is also connected to the counter unit and is used to receive a counting signal provided by the counter unit. The shift register unit is also used to transmit communication data based on the counting signal. The counter unit is also connected to the input-output unit and is used to generate the counting signal according to the input-output signal provided by the input-output unit; The input-output unit is also connected to the shift register unit and is used to provide the input-output signal to the shift register unit. The shift register unit is also used to transmit serial communication data based on the input-output signal.
2. The multi-protocol communication control module according to claim 1, characterized in that: Also included is a register configuration unit; The register configuration unit is connected to the shift register unit through the buffer unit and is used to control the shift register unit to transmit communication data.
3. The multi-protocol communication control module according to claim 1, characterized in that: The cache unit includes a sending cache unit and a receiving cache unit; The sending buffer unit and the receiving buffer unit are both connected to the shift register unit; The sending buffer unit is used to buffer the communication data sent to the shift register unit; The receiving buffer unit is used for buffering the communication data sent by the shift register unit.
4. The multi-protocol communication control module according to claim 1, characterized in that: The shift register unit includes a sending shift register and a receiving shift register; The transmission shift register is used to convert the transmitted communication data from parallel data to serial data; The receiving shift register is used to convert the received communication data from serial data to parallel data.
5. The multi-protocol communication control module according to claim 1, characterized in that: The counter unit includes a plurality of counters, and each of the counters can be connected to the shift register unit.
6. The multi-protocol communication control module according to claim 5, characterized in that: Also included is a first gating circuit; The shift register unit is connected to the plurality of counters via the first gating circuit, and any of the counters can be connected to the shift register unit via the first gating circuit.
7. The multi-protocol communication control module according to claim 1, characterized in that: The input-output unit includes a plurality of input-output interfaces, each of which can be connected to the counter unit and the counter unit.
8. The multi-protocol communication control module according to claim 7, characterized in that: Also included is a second gating circuit; The shift register unit is connected to the plurality of input and output interfaces via the second gating circuit, and any of the input and output interfaces can be connected to the shift register unit via the second gating circuit; The counter unit is connected to the plurality of input / output interfaces via the second selection circuit, and any one of the input / output interfaces can be connected to the counter unit via the second selection circuit.
9. The multi-protocol communication control module according to claim 8, characterized in that: The counter unit includes a plurality of counters, and any of the counters can be connected to any of the input / output interfaces through the second gating circuit.
10. An electronic device, characterized in that: It comprises the multi-protocol communication control module as described in any one of claims 1 to 9.