Chip communication method, device, system and equipment and readable storage medium

Abstract

The invention provides a chip communication method, device, system and equipment and a readable storage medium, and the method comprises the steps: controlling at least two signal transmitting ports of a first chip to transmit target level signals, so as to trigger a signal receiving port of a second chip to receive the target level signals; the second chip is used for sending a clock signal to the first chip under the condition that the signal receiving port receives the target level signal; and under the condition that the clock signal is received, sending a first message to the second chip so as to complete chip communication between the first chip and the second chip. According to the invention, the chip communication efficiency is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of chip communication systems, and in particular, to a chip communication method, apparatus, system, electronic device, and computer-readable storage medium. Background Art

[0002] In an embedded system or other systems, there may be multiple chips. According to specific functional requirements, the multiple chips can be divided into a master chip and slave chips. For example, the master chip is responsible for coordinating and controlling other chips, and the slave chips assist the master chip to complete specific tasks, and communication is required between chips.

[0003] In the related art, one chip sends a clock signal to another chip in a periodic or aperiodic manner, and the chips synchronize data transmission based on the clock signal to perform normal communication.

[0004] However, in the related art, a specific chip controls the sending of the clock signal, and this chip controls the communication process, resulting in large limitations in communication between chips and low communication efficiency. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure are proposed to provide a chip communication method, system, electronic device, and computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0006] In a first aspect, embodiments of the present disclosure disclose a chip communication method, the method including:

[0007] Controlling at least two signal sending ports of a first chip to respectively send target level signals to trigger a signal receiving port of a second chip to receive the target level signal; the second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signal;

[0008] When receiving the clock signal, sending a first message to the second chip to complete chip communication between the first chip and the second chip.

[0009] In a second aspect, embodiments of the present disclosure disclose a chip communication apparatus, the apparatus including:

[0010] An interrupt trigger module, configured to control at least two signal sending ports of a first chip to respectively send target level signals to trigger a signal receiving port of a second chip to receive the target level signal; the second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signal;

[0011] A message sending module, configured to send a first message to the second chip when receiving the clock signal, so as to complete chip communication between the first chip and the second chip.

[0012] In a third aspect, an embodiment of the present disclosure discloses a chip communication system, which includes a first chip, a second chip, and an AND logic circuit; the AND logic circuit is connected to at least two signal sending ports of the first chip, and the AND logic circuit is further connected to a signal receiving port of the second chip;

[0013] The first chip is configured to control at least two signal sending ports to respectively send target level signals, so as to trigger the signal receiving port to receive the target level signals;

[0014] The AND logic circuit is configured to send the target level signals to the signal receiving port when at least two signal sending ports respectively send target level signals;

[0015] The second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signals;

[0016] The first chip is configured to send a first message to the second chip when receiving the clock signal, so as to complete chip communication between the first chip and the second chip.

[0017] In a fourth aspect, an embodiment of the present disclosure further discloses an electronic device, including a processor and a memory, where the memory stores a program or instruction that can run on the processor, and when the program or instruction is executed by the processor, the steps of the chip communication method as described in the first aspect are implemented.

[0018] In a fifth aspect, an embodiment of the present disclosure further discloses a computer-readable storage medium, where a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the chip communication method as described in the first aspect are implemented.

[0019] In the embodiments of the present disclosure, by controlling at least two signal transmission ports of the first chip to respectively send target level signals, triggering the signal reception ports of the second chip to receive the target level signals, when the second chip receives the target level signals at the signal reception ports, the second chip sends a clock signal to the first chip, and when the first chip receives the clock signal, the first chip sends the first message to the second chip to complete the chip communication between the first chip and the second chip. On the one hand, by using at least two signal transmission ports to trigger the clock signal of the second chip, it can effectively reduce the problem of mis-triggering caused by electromagnetic interference in the special environment of complex multi-chip circuit layouts, and can effectively avoid generating incorrect chip communication; on the other hand, it enables the first chip to actively trigger the second chip to send a clock signal, avoiding the situation where only the second chip unilaterally controls the sending of the clock signal, thereby avoiding the restriction of the second chip on the chip communication process. When the first chip needs to communicate, it can actively trigger the clock signal of the second chip to send messages, improving the timeliness and flexibility of chip communication, and ultimately improving the efficiency of chip communication. Description of the Drawings

[0020] Figure 1 is a step diagram of a chip communication method provided by an embodiment of the present disclosure;

[0021] Figure 2 is a schematic diagram of the connection relationship between the master device and the slave device provided by an embodiment of the present disclosure;

[0022] Figure 3 is a step diagram of another chip communication method provided by an embodiment of the present disclosure;

[0023] Figure 4 is an interaction timing diagram of the first chip sending a data message provided by an embodiment of the present disclosure;

[0024] Figure 5 is a flowchart of the first chip sending a data message provided by an embodiment of the present disclosure;

[0025] Figure 6 is an interaction timing diagram of the second chip sending a data message provided by an embodiment of the present disclosure

[0026] Figure 7 is a flowchart of the second chip sending a data message provided by an embodiment of the present disclosure;

[0027] Figure 8 is a block diagram of a chip communication device provided by an embodiment of the present disclosure;

[0028] Figure 9 is a block diagram of a chip communication system provided by an embodiment of the present disclosure;

[0029] Figure 10It is a block diagram of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0030] Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.

[0031] Figure 1 It is a step diagram of a chip communication method provided by an embodiment of the present disclosure. The method includes:

[0032] Step 101: Control at least two signal transmission ports of the first chip to respectively send target level signals to trigger the signal receiving ports of the second chip to receive the target level signals; the second chip is configured to send a clock signal to the first chip when the target level signals are received at the signal receiving ports.

[0033] The application scenario of the chip communication method of the embodiment of the present disclosure can be applied to an embedded system or other systems with multiple chips. The multiple chips can be divided into a main chip and slave chips.

[0034] The main chip can be responsible for controlling and managing the operation of the entire system, has strong data processing capabilities and rich interface resources, and can be used to connect and coordinate other components in the system.

[0035] The slave chip is an auxiliary component in the system, which can be used to expand the functions of the main chip or provide additional interfaces. The slave chip can operate according to the instructions of the main chip to complete specific tasks or data processing work. In a multi-chip scenario, the slave chip is usually in a state of being managed by the main chip.

[0036] For example, for an electronic control unit (ECU), there can be at least one main chip and multiple slave chips in the embedded system of the ECU unit. Data communication can be carried out between the main chips or between the main chip and multiple slave chips.

[0037] The communication between chips can be based on the Serial Peripheral Interface (SPI). SPI is a short-distance inter-chip communication bus, and at the same time, it is a high-speed, full-duplex, synchronous communication bus. SPI can be applied to the communication between chips such as Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, Analog-to-Digital Converter (ADC), and Digital-to-Analog Converter (DAC).

[0038] When based on SPI, the full-duplex mode is usually adopted for communication transmission. The four wires used can be: Serial Clock (SCK), Chip Select (CS), Master Output, Slave Input (MOSI), and Master Input, Slave Output (MISO). When communicating based on SPI, different chips can have two modes: master and slave. The communication connection relationship usually consists of a master chip and one or more slave chips.

[0039] In an embedded system, the master chip usually acts as the master device and provides a clock signal to the slave device through the SPI controller. The slave chips connected to the master chip usually act as slave devices and receive the clock signal from the master device.

[0040] Figure 2 It is a schematic diagram of the connection relationship between the master device and the slave device provided by the embodiments of the present disclosure;

[0041] As Figure 2 shown. When the SPI bus performs read and write operations, first, the master device 210 (host) selects a slave device (slave) from the slave devices 221, 222, and 223 for enabling operation through the chip select information (CS). Then, the master device sends a clock signal to the selected slave device, and at the same time, full-duplex data communication is carried out on the MOSI and MISO lines. The clock signal can be periodic or aperiodic.

[0042] The first chip in the embodiments of the present disclosure can be a slave chip (slave device), such as a microcontroller unit (MCU), or a master chip. The second chip can be a master chip, such as a system-on-chip (SOC). The first chip needs to receive the clock signal sent by the second chip to perform data communication.

[0043] It can be understood that the first chip can be a master chip, which means that the first chip has strong data processing capabilities and rich interface resources, and can be used to connect and coordinate other components in the system and other characteristics of the master chip. However, when communicating between chips, it can still receive the clock signal sent by another master chip (i.e., the second chip).

[0044] The first chip can have at least two signal transmission ports, such as 2, 3, or other numbers of signal transmission ports. The at least two signal transmission ports respectively send target level signals, which means that each signal transmission port sends the same target level signal, such as a high-level signal or a low-level signal. There is no limitation here, and only at least two signal transmission ports need to respectively send the same target level signal.

[0045] When the at least two signal transmission ports of the first chip both send target level signals, the signal receiving port of the second chip can receive the target level signal. The implementation process can be based on an AND logic circuit. The input of the AND logic circuit corresponds to the number of signal transmission ports. The AND logic circuit can be designed to output a target level signal to the signal receiving port only when the target level signal is input to at least two signal transmission ports. It can also be based on software to implement the input and output of specific signals. There is no limitation here.

[0046] The signal transmission port and the signal receiving port can both be general-purpose input / output ports (GPIO). The target level signal received by the signal receiving port can be used as an interrupt signal to trigger the GPIO interrupt processing of the second chip. The GPIO interrupt service of the second chip can call the SCK port to send a clock signal to the MCU. The clock signal can help the chips stay synchronized during data transmission, so that data is transmitted and received at the correct time.

[0047] Step 102, when receiving the clock signal, send the first message to the second chip to complete the chip communication between the first chip and the second chip.

[0048] In an embodiment of the present disclosure, when the first chip receives a clock signal, it can start sending data, i.e., the first message, to the second chip. The data can be transmitted from the MISO of the first chip to the MISO of the second chip, thereby sending the first message to the second chip and completing the chip communication between the first chip and the second chip.

[0049] In summary, in the embodiment of the present disclosure, by controlling at least two signal sending ports of the first chip to respectively send target level signals, triggering the signal receiving port of the second chip to receive the target level signal, when the second chip receives the target level signal at the signal receiving port, it sends a clock signal to the first chip, and when the first chip receives the clock signal, it sends the first message to the second chip to complete the chip communication between the first chip and the second chip. On the one hand, triggering the clock signal of the second chip through at least two signal sending ports can effectively reduce the problem of mis-triggering caused by electromagnetic interference in the special environment of a multi-chip complex circuit layout, and can effectively avoid incorrect chip communication; on the other hand, it enables the first chip to actively trigger the second chip to send a clock signal, avoiding the situation where only the second chip unilaterally controls the sending of the clock signal, thereby avoiding the limitation of the second chip on the chip communication process. When the first chip needs to communicate, it can trigger the clock signal of the second chip to send messages, improving the timeliness and flexibility of chip communication, and ultimately improving the efficiency of chip communication.

[0050] Reference Figure 3 , which shows a step diagram of a chip communication method provided by an embodiment of the present disclosure. The method includes:

[0051] Step 301: Control at least two signal sending ports of the first chip to respectively send target level signals to trigger the signal receiving port of the second chip to receive the target level signal; the second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signal;

[0052] Step 302: When receiving the clock signal, send the first message to the second chip to complete the chip communication between the first chip and the second chip.

[0053] The above steps 301-302 can refer to the content of the above Figure 1 embodiment and will not be elaborated here.

[0054] In chip-to-chip communication, when the reliability of data is insufficient, it may affect the function or performance of the chip, resulting in abnormal application functions or poor performance, and ultimately may affect the function implementation of the entire multi-chip system. During the data transmission process of chip-to-chip communication, if errors or data loss occur, the data reliability will be reduced.

[0055] Optionally, the first message is a data message; the method further includes:

[0056] Step 303, receive a second message sent by the second chip, and determine the verification result carried in the second message; the second message is a response message carrying the verification result generated after the second chip verifies the data message;

[0057] Step 304, when the verification result includes first preset information, determine that the content of the data message received by the second chip is correct;

[0058] Step 305, when the verification result includes second preset information, determine that the content of the data message received by the second chip is incorrect.

[0059] In the embodiments of the present disclosure, the message type may include a data message and a response message. The data message contains actual data or request information, and the response message is a response or confirmation of the data message. The first message sent from the first chip to the second chip may be a data message.

[0060] After receiving the first message (data message), the second chip may verify the data content of the data message. Based on a preset verification algorithm, such as parity check, cyclic redundancy check (CRC), longitudinal redundancy check (LRC), etc., the data content is verified and a verification result is generated. The verification result may indicate whether the data in the data message is complete and accurate.

[0061] The second chip may generate a second message (response message) carrying the verification result and return the second message to the first chip. The first chip may determine whether the data message received by the second chip is complete and accurate based on the information included in the verification result in the second message.

[0062] The specific information included in the verification result may be determined by the second chip according to the verification situation. If the second chip determines that the content of the data message is complete and accurate, it may generate specific information, such as numbers or letters, to indicate that the content of the data message is complete and accurate. Similarly, the content error of the data message may be indicated by specific information.

[0063] The first preset information is, for example, "YES", which can be set to indicate that the content is complete and accurate. Then, when the verification result includes the first preset information, it is determined that the content of the data packet received by the second chip is correct. Similarly, the second preset information is, for example, "NO", which can be set to indicate that the content is incorrect. Then, when the verification result includes the second preset information, it is determined that the content of the data packet received by the second chip is incorrect.

[0064] By implementing the embodiments of the present disclosure, after receiving the response packet carrying the verification result generated by the second chip for verifying the data packet, when the verification result includes the first preset information, it is determined that the content of the data packet received by the second chip is correct; when the verification result includes the second preset information, it is determined that the content of the data packet received by the second chip is incorrect. It is possible to verify the data transmitted during chip communication, timely discover data problems, and improve the reliability of chip communication.

[0065] Figure 4 is the interaction timing diagram of the first chip sending a data packet provided by the embodiments of the present disclosure;

[0066] S401, the first chip sends a data packet;

[0067] S402, the second chip sends a data synchronization packet;

[0068] S403, the second chip performs packet verification;

[0069] S404, the second chip sends a response packet;

[0070] S405, the first chip sends a response synchronization packet;

[0071] S406, the first chip detects the response information.

[0072] Among them, the synchronization packet can be only used for supplementing the communication packet, and there can be no control or status information inside the synchronization packet.

[0073] During the data transmission process of chip - to - chip communication, if an error or data loss occurs, it may affect the function or performance of the chip, resulting in abnormal function or poor performance, and ultimately may affect the function realization of the entire multi - chip system.

[0074] Optionally, the method further includes:

[0075] When the verification result includes the second preset information, re - enter the step of controlling at least two signal sending ports of the first chip to emit target level signals;

[0076] Until the number of times that the verification result includes the second preset information reaches a preset number, or the verification result includes the first preset information.

[0077] In the embodiments of the present disclosure, when the verification result includes the second preset information, it indicates that the content of the data packet is incorrect. The first chip can re-control at least two signal sending ports to send target level signals, triggering the second chip to send a clock signal, so that data transmission can be performed again until the verification result includes the first preset information.

[0078] It can be understood that the re-sent data packet may still be incorrect. Therefore, a preset number of times can be set to limit the number of errors. If the data is still incorrect after re-transmission and the total number of errors reaches the preset number of times, it can be considered that there is a non-accidental problem, and then the meaningless loop re-transmission can be stopped, and it can be determined that the chip communication fails.

[0079] In addition, the result of chip communication failure can be returned to the first chip. For example, in the function called by the upper layer of the MCU for SPI transmission, the upper layer software of the MCU can perform subsequent problem location, error handling, and error correction operations. For example, it can specifically check the configuration parameters related to the clock, such as whether the clock frequency, polarity, phase, etc. are set correctly; it can also trigger other alternative operations, such as switching to another communication method; it can also report the fault to the upper layer system for system-level fault handling. The process of how to handle based on the chip communication failure result is not limited here.

[0080] Implementing the embodiments of the present disclosure, when the verification result includes the second preset information, re-enter the step of controlling at least two signal sending ports of the first chip to send target level signals until the number of times that the verification result includes the second preset information reaches the preset number of times, or the verification result includes the first preset information. It can correct data by loop re-transmission when data is incorrect, improving the data reliability of chip communication; at the same time, when there is a non-accidental problem, it can avoid a large number of loop transmission processes, thus avoiding additional losses to the chip.

[0081] During the data transmission process of chip communication, in addition to the problem that the data has been received by the data receiver but the data is incorrect, there may also be a problem that the data receiver has not received the data. Therefore, if only the received data is verified, data transmission problems cannot be completely avoided.

[0082] Optionally, the first packet is a data packet; the method further includes:

[0083] Step A1, when the data packet has been sent, start a timer and set a preset duration;

[0084] Step A2: When the preset duration has elapsed and the second message sent by the second chip has not been received, it is determined that the second chip has not received the data message; the second message is a response message carrying a verification result generated by the second chip after receiving and verifying the first message.

[0085] Step A3: When the response message is received within the preset duration, it is determined that the second chip has received the data message, and the timer is reset to the preset duration to start timing after the data message is sent to the second chip next time.

[0086] In the embodiments of the present disclosure, the first message may be a data message, that is, the first chip sends data to the second chip. When the first chip has sent the data message, the first chip may set a timer and set the timer to a preset duration. Among them, the timer may be a functional module in the first chip (such as an MCU).

[0087] By using the timer to determine that the preset duration has elapsed since the data message was sent and the second message sent by the second chip has not been received, the first chip may determine that the second chip has not received the data message. The second message is the message generated by the second chip after receiving and verifying the data, which will not be elaborated here.

[0088] Similarly, by using the timer to determine that the second message sent by the second chip is received within the preset duration since the data message was sent, the first chip may determine that the second chip has received the data message. At the same time, the timer may be reset to the preset duration to start timing after the data message is sent to the second chip next time.

[0089] In addition, if the preset duration has elapsed and the second message sent by the second chip has not been received, it may be considered that the processing mechanism of the second chip (such as an SOC) is abnormal, and it can be determined that the chip communication fails.

[0090] Implementing the embodiments of the present disclosure, when the first chip has sent the data message, it starts the timer and sets the preset duration. When the preset duration has elapsed and the response message from the second chip has not been received, it is determined that the second chip has not received the data message. When the response message is received within the preset duration, it is determined that the second chip has received the data message, and the timer is reset to the preset duration to start timing after the data message is sent to the second chip next time. It is possible to set a timer after the data is sent to determine whether the response message is received, so as to determine whether the second chip has successfully received the data message, and the problem location of data transmission can be clarified, thereby improving the discovery efficiency of chip communication problems.

[0091] Figure 5It is a flowchart for the first chip provided by an embodiment of the present disclosure to send a data packet;

[0092] Step 501, start;

[0093] Step 502, send a data packet;

[0094] Step 503, start a timer, set the timeout period T; wait for the response packet from the second chip;

[0095] Step 504, determine whether a timeout event occurs for the timer?

[0096] Step 505, if it occurs, assign the return value of the sending interface as FAIL, that is, determine that the communication fails;

[0097] Step 506, determine whether the response packet from the second chip is received?

[0098] Step 507, if yes, receive the response packet, send a response synchronization packet, and detect the verification result;

[0099] Step 508, determine whether the verification result passes;

[0100] Step 509, if it passes, assign the return value of the sending interface as ok, and determine that the communication is successful;

[0101] Step 510, if it does not pass, determine whether it fails continuously three times?

[0102] Step 511, if it is determined that it fails continuously three times, assign the return value of the sending interface as FAIL;

[0103] Step 512, end.

[0104] In chip communication, in addition to the first chip sending a data packet to the second chip, the second chip verifies the data packet. It is also possible that the second chip sends a data packet to the first chip. If there is an error in the data packet received by the first chip, it may also cause abnormal chip functions.

[0105] Optionally, the first packet is a response packet; the method further includes:

[0106] Receive a third packet sent by the second chip; the third packet is a data packet;

[0107] Verify the data packet and generate the response packet carrying the verification result.

[0108] In an embodiment of the present disclosure, the first message may be an acknowledgment message. The first chip will first obtain data, i.e., the third message (data message), from the second chip. Then, similar to the process in which the second chip obtains a data message from the first chip and performs verification, the first chip can also verify the third message (data message) and generate an acknowledgment message (the first message) carrying the verification result. Similarly, the first chip can send a target level signal to trigger the second chip to send a clock signal, and then the first chip can send the acknowledgment message to the second chip.

[0109] It can be understood that the first message, the second message, and the third message are only used to distinguish different messages, and there may be no fixed order among the first message, the second message, and the third message.

[0110] By implementing the embodiment of the present disclosure, by receiving the third message sent by the second chip; the third message is a data message; verifying the data message to generate an acknowledgment message carrying the verification result. When the second chip transmits data to the first chip, the first chip can verify the data transmitted during chip communication, timely discover data problems, improve the reliability of chip communication, and improve the stability of chip functions.

[0111] After receiving the data message, the first chip can only verify and process the data message it has obtained, but it cannot determine whether the data message received by the first chip is the same as the data message sent by the second chip. The first chip cannot determine whether the data message is complete and accurate by performing verification alone.

[0112] Optionally, the data message includes data content and first verification information;

[0113] The step of verifying the data message to generate the acknowledgment message carrying the verification result includes:

[0114] Performing information extraction processing on the data content in the data message to obtain second verification information;

[0115] Comparing the second verification information with the first verification information to obtain a verification result, and generating the acknowledgment message carrying the verification result.

[0116] In an embodiment of the present disclosure, the data message may include data content and first verification information. The first verification information may be information obtained by the second chip through a preset verification algorithm for verifying the data content. When the first chip performs verification, it can also perform similar verification processing based on the verification algorithm used by the second chip to obtain the second verification information.

[0117] The first chip can compare the second verification information with the first verification information to obtain a verification result. For example, if the second verification information is consistent with the first verification information, it means that the data received by the first chip is correct, and the verification result can be information carrying "YES" or "1"; if there is a difference between the second verification information and the first verification information, it means that the data received by the first chip is incorrect, and the verification result can be information carrying "NO" or "0". The specific content of the verification result is not specifically limited here.

[0118] In implementing the embodiments of the present disclosure, the first chip performs information extraction processing based on the data content in the data packet to obtain the second verification information. The first chip compares the second verification information with the first verification information to obtain a verification result, and generates a response packet carrying the verification result. It is possible to compare the verification information of the first chip with the verification information of the second chip, thereby conveniently determining whether the data is complete and correct, and improving the efficiency of data verification.

[0119] Figure 6 It is an interaction timing diagram for the second chip to send a data packet provided by the embodiments of the present disclosure;

[0120] S601, the second chip sends a data packet;

[0121] S602, the first chip sends a data synchronization packet;

[0122] S603, the first chip performs packet verification;

[0123] S604, the first chip sends a response packet;

[0124] S605, the second chip sends a response synchronization packet;

[0125] S606, the second chip detects the response information.

[0126] Figure 7 It is a flowchart for the second chip to send a data packet provided by the embodiments of the present disclosure;

[0127] Step 701, start;

[0128] Step 702, the second chip sends a data packet;

[0129] Step 703, start a timer, set T, and wait for the target level signal of the first chip;

[0130] Step 704, determine whether a timeout event occurs for the timer?

[0131] Step 705, if it times out, assign the return value of the sending interface as FAIL and determine that the communication fails;

[0132] Step 706, if not timed out, determine whether a target level signal is received?

[0133] Step 707, if there is a target level signal, the response message can be received, the response synchronization message can be sent, and the verification result can be detected;

[0134] Step 708, determine whether the verification result passes;

[0135] Step 709, if it passes, assign the return value of the sending interface as ok to determine successful communication;

[0136] Step 710, if it does not pass, determine whether the non-pass is continuous for 3 times?

[0137] Step 711, if it is not passed continuously for 3 times, assign the return value of the sending interface as FAIL;

[0138] Step 712, end.

[0139] In this application, by adopting an AND gate logic circuit, the real-time problem of communication between chips is solved, and at the same time, GPIO pin resources are saved. In addition, a response mechanism is added to the SPI communication stack to tell the sender whether the communication data is correctly received by the receiver, and the processing mechanism (retransmission mechanism and timeout mechanism) when it is abnormally received, which improves the reliability of SPI communication data.

[0140] Figure 8 A chip communication device 80 provided by an embodiment of the present disclosure includes:

[0141] An interrupt trigger module 801, configured to control at least two signal sending ports of the first chip to respectively send target level signals to trigger the signal receiving port of the second chip to receive the target level signal; the second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signal;

[0142] A message sending module 802, configured to send a first message to the second chip when receiving the clock signal to complete chip communication between the first chip and the second chip.

[0143] Optionally, the first message is a data message; the device further includes:

[0144] A first verification module, configured to receive a second message sent by the second chip and determine the verification result carried in the second message; the second message is a response message carrying the verification result generated by the second chip after verifying the data message;

[0145] A data correctness module, configured to determine that the content of the data packet received by the second chip is correct when the verification result includes first preset information;

[0146] A data error module, configured to determine that the content of the data packet received by the second chip is incorrect when the verification result includes second preset information.

[0147] Optionally, the apparatus further includes:

[0148] A loop sending module, configured to re-enter the step of controlling at least two signal sending ports of the first chip to send target level signals when the verification result includes the second preset information;

[0149] A loop stopping module, configured to continue until the number of times that the verification result includes the second preset information reaches a preset number of times, or the verification result includes the first preset information.

[0150] Optionally, the first packet is a data packet; the method further includes:

[0151] A timing module, configured to start a timer and set a preset duration when the data packet has been sent;

[0152] An unreceived packet module, configured to determine that the second chip has not received the data packet when the preset duration has elapsed and the second packet sent by the second chip has not been received; the second packet is a response packet carrying a verification result generated after the second chip receives the first packet and performs verification;

[0153] A received packet module, configured to determine that the second chip has received the data packet when the response packet has been received within the preset duration, and reset the timer to the preset duration for timing after the data packet is sent to the second chip next time.

[0154] Optionally, the first packet is a response packet; the apparatus further includes:

[0155] A data receiving module, configured to receive a third packet sent by the second chip; the third packet is a data packet;

[0156] A second verification module, configured to verify the data packet and generate the response packet carrying the verification result.

[0157] Optionally, the data packet includes data content and first verification information;

[0158] The second verification module includes:

[0159] A verification processing sub-module, which is used to perform information extraction processing on the data content in the data packet to obtain second verification information;

[0160] A verification generation sub-module, which is used to compare the second verification information with the first verification information to obtain a verification result, and generate the response packet carrying the verification result.

[0161] In the embodiment of the present disclosure, by controlling at least two signal transmission ports of the first chip to respectively send target level signals, triggering the signal receiving port of the second chip to receive the target level signal, when the second chip receives the target level signal at the signal receiving port, the second chip sends a clock signal to the first chip, and when the first chip receives the clock signal, the first chip sends the first packet to the second chip to complete the chip communication between the first chip and the second chip. On the one hand, by using at least two signal transmission ports to trigger the clock signal of the second chip, it can effectively reduce the problem of mis-triggering caused by electromagnetic interference in the special environment of complex multi-chip circuit layout, and can effectively avoid generating incorrect chip communication; on the other hand, it enables the first chip to actively trigger the second chip to send a clock signal, avoiding the situation where only the second chip unilaterally controls the sending of the clock signal, thereby avoiding the limitation of the second chip on the chip communication process. When the first chip needs to communicate, it can trigger the clock signal of the second chip to send a packet, improving the timeliness and flexibility of chip communication, and ultimately improving the efficiency of chip communication.

[0162] Figure 9 A chip communication system 90 provided by an embodiment of the present disclosure, the system 90 includes a first chip 901, a second chip 902, and an AND logic circuit 903; the AND logic circuit 903 is connected to at least two signal transmission ports 9011 of the first chip, and the AND logic circuit 903 is also connected to the signal receiving port 9021 of the second chip;

[0163] The first chip 901 is used to control at least two signal transmission ports to respectively send target level signals to trigger the signal receiving port to receive the target level signal;

[0164] The AND logic circuit 903 is used to send the target level signal to the signal receiving port when at least two signal transmission ports respectively send target level signals;

[0165] The second chip 902 is used to send a clock signal to the first chip when the signal receiving port receives the target level signal;

[0166] The first chip 901 is configured to send a first message to the second chip upon receiving a clock signal, so as to complete chip communication between the first chip and the second chip.

[0167] The chip communication system may be on a printed circuit board (PCB).

[0168] The first message is a data message; the first chip 901 is further configured to

[0169] receive a second message sent by the second chip and determine the verification result carried in the second message; the second message is a response message carrying the verification result generated by the second chip after verifying the data message.

[0170] When the verification result includes first preset information, it is determined that the content of the data message received by the second chip is correct.

[0171] When the verification result includes second preset information, it is determined that the content of the data message received by the second chip is incorrect.

[0172] The first chip 901 is further configured to

[0173] When the verification result includes the second preset information, re-enter the step of controlling at least two signal transmission ports of the first chip to emit target level signals.

[0174] Until the number of times the verification result includes the second preset information reaches a preset number of times, or the verification result includes the first preset information.

[0175] The first message is a data message; the first chip 901 is further configured to

[0176] When the data message has been sent, start a timer and set a preset duration.

[0177] When the preset duration has elapsed and the second message sent by the second chip has not been received, it is determined that the second chip has not received the data message; the second message is a response message carrying the verification result generated by the second chip after receiving and verifying the first message.

[0178] When the response message is received within the preset duration, it is determined that the second chip has received the data message, and the timer is reset to the preset duration for timing after the data message is sent to the second chip next time.

[0179] The first message is an acknowledgment message; the method further includes: the first chip 901 is further configured to receive a third message sent by the second chip; the third message is a data message;

[0180] Verify the data message to generate the acknowledgment message carrying the verification result.

[0181] The data message includes data content and first verification information; the first chip 901 is configured to

[0182] Perform information extraction processing on the data content in the data message to obtain second verification information;

[0183] Compare the second verification information with the first verification information to obtain a verification result, and generate the acknowledgment message carrying the verification result.

[0184] An embodiment of the present application further provides an electronic device, as Figure 10 shown, including a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. Among them, the processor 1001, the communication interface 1002, and the memory 1003 complete mutual communication through the communication bus 1004.

[0185] The memory 1003 is used to store a computer program.

[0186] When the processor 1001 is used to execute the program stored on the memory 1003, it implements the steps in the above chip communication method, which will not be elaborated here.

[0187] The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0188] The communication interface is used for communication between the above electronic device and other systems.

[0189] The memory may include a Random Access Memory (RAM), or may also include a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0190] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU for short), a Network Processor (NP for short), etc.; it may also be a Digital Signal Processor (DSP for short), an Application Specific Integrated Circuit (ASIC for short), a Field-Programmable Gate Array (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0191] In another embodiment provided by the present application, a computer-readable storage medium is further provided. Instructions are stored in the computer-readable storage medium. When it runs on a computer, the computer is caused to execute the chip communication method described in the above embodiment.

[0192] In another embodiment provided by the present application, a computer program product containing instructions is further provided. When it runs on a computer, the computer is caused to execute the chip communication method described in the above embodiment.

[0193] In the above embodiment, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, a computer, a server, or a data center to another website, a computer, a server, or a data center in a wired manner (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that the computer can access, or a data storage system such as a server or a data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a Solid State Disk (SSD)).

[0194] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or system comprising the said element.

[0195] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. For the embodiments of the apparatus, electronic device, computer-readable storage medium and computer program product containing instructions therein, since they are basically similar to the method embodiments, the description is relatively simple, and reference can be made to the partial description of the method embodiments for the relevant parts.

[0196] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip communication method, characterized in that: The method comprises: Controlling at least two signal sending ports of the first chip to send target level signals respectively, so as to trigger the signal receiving port of the second chip to receive the target level signal; the second chip is used to send a clock signal to the first chip when the signal receiving port receives the target level signal; When the clock signal is received, a first message is sent to the second chip to complete chip communication between the first chip and the second chip.

2. The method according to claim 1, characterized in that The first message is a data message; the method further includes: receiving a second message sent by the second chip, and determining a verification result carried in the second message; the second message is a response message carrying the verification result generated by the second chip after verifying the data message; In a case where the verification result includes the first preset information, determining that the content of the data message received by the second chip is correct; When the verification result includes the second preset information, it is determined that the content of the data message received by the second chip is incorrect.

3. The method according to claim 2, characterized in that The method further comprises: In a case where the verification result includes the second preset information, re-entering the step of controlling at least two signal sending ports of the first chip to send target level signals; Until the verification result includes the second preset information for a number of times reaching a preset number, or the verification result includes the first preset information.

4. The method according to claim 1, characterized in that: The first message is a data message; the method further includes: When the data message has been sent, start the timer and set a preset duration; When the preset time has passed and the second message sent by the second chip has not been received, it is determined that the second chip has not received the data message; the second message is a response message carrying a verification result generated by the second chip after receiving and verifying the first message; When the response message is received within the preset time period, it is determined that the second chip has received the data message, and the timer is reset to the preset time period to start timing after the data message is sent to the second chip next time.

5. The method according to claim 1, characterized in that The first message is a response message; the method further includes: receiving a third message sent by the second chip; the third message is a data message; The data message is verified, and the response message carrying the verification result is generated.

6. The method according to claim 5, characterized in that The data message includes data content and first verification information; The step of verifying the data message and generating the response message carrying the verification result includes: Performing information extraction processing on the data content in the data message to obtain second verification information; The second verification information is compared with the first verification information to obtain a verification result, and the response message carrying the verification result is generated.

7. A chip communication device, characterized in that: The device comprises: An interrupt trigger module, used for controlling at least two signal sending ports of the first chip to send target level signals respectively, so as to trigger the signal receiving port of the second chip to receive the target level signal; the second chip is used for sending a clock signal to the first chip when the signal receiving port receives the target level signal; The message sending module is used to send the first message to the second chip when the clock signal is received, so as to complete the chip communication between the first chip and the second chip.

8. A chip communication system, characterized in that: The system comprises a first chip, a second chip and an AND gate logic circuit; the AND gate logic circuit is connected to at least two signal sending ports of the first chip, and the AND gate logic circuit is also connected to a signal receiving port of the second chip; The first chip is used to control at least two signal sending ports to send target level signals respectively, so as to trigger the signal receiving port to receive the target level signals; The AND gate logic circuit is used to send the target level signal to the signal receiving port when at least two signal sending ports send target level signals respectively; The second chip is configured to send a clock signal to the first chip when the signal receiving port receives the target level signal; The first chip is used to send a first message to the second chip when receiving the clock signal, so as to complete the chip communication between the first chip and the second chip.

9. An electronic device, characterized in that: include: A processor, a communication interface, a memory and a communication bus; wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, configured to implement the steps of the chip communication method as claimed in any one of claims 1 to 6 when executing a program stored in a memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the chip communication method according to any one of claims 1 to 6 are implemented.

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