Semiconductor device and communication method between semiconductor devices

Abstract

The invention provides a semiconductor device and a communication method between semiconductor devices. A semiconductor device includes a plurality of pins, a semiconductor component, and a scalable digital interface circuit. The pins are divided into a plurality of data sending groups and a plurality of data receiving groups. The semiconductor component provides output data and receives input data. The extensible digital interface circuit is coupled to the data transmitting groups, the data receiving groups and the semiconductor component, and recombines the output data into parallel transmission data, so as to transmit the parallel transmission data to an external semiconductor device through parallel transmission. And receive the parallel reception data from the external semiconductor device via the parallel transmission to recombine the parallel reception data into the input data.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device using parallel transmission and a communication method between semiconductor devices. Background Art

[0002] For a long time, in order to increase the number of transistors in a chip to boost computing performance, the process of semiconductor manufacturing technology has been continuously improved, resulting in a gradual reduction in the gate length, which has gradually approached the currently known physical limit. However, with the rapid development of related applications such as Artificial Intelligence (AI) and AI Generated Content (AIGC), the device-side demand for the performance of core chips will be increasingly high. In the case where the improvement of process technology may encounter bottlenecks, it becomes a necessary choice to increase the number of transistors in the chip through advanced packaging technology of chip stacking. However, in view of the fact that the demand for computing resources may still continue to rise with the computing demand, improving the performance of the chip under the current packaging technology is still an important issue. Summary of the Invention

[0003] The present invention is directed to a semiconductor device and a communication method between semiconductor devices, which use multiple pins to transfer data through parallel transmission to improve transmission efficiency and reduce transmission frequency.

[0004] According to an embodiment of the present invention, a semiconductor device includes multiple pins, at least one semiconductor component, and an extensible digital interface circuit. These pins are divided into multiple data transmission groups and multiple data reception groups. At least one semiconductor component provides at least one output data and receives at least one input data. The extensible digital interface circuit is coupled to at least one of these data transmission groups, at least one of these data reception groups, and at least one semiconductor component, wherein the extensible digital interface circuit reorganizes at least one output data into at least one parallel transmission data to transmit at least one parallel transmission data to an external semiconductor device via parallel transmission, and receives at least one parallel reception data from the external semiconductor device via parallel transmission to reorganize at least one parallel reception data into at least one input data.

[0005] According to an embodiment of the present invention, a communication method between conductor devices includes the following steps. Recombine at least one output data provided by at least half of the conductor components into at least one parallel transmission data via an extensible digital interface circuit. Transmit at least one parallel transmission data to an external semiconductor device via parallel transmission through at least one of a plurality of data transmission groups of a plurality of pins. Receive at least one parallel received data from the external semiconductor device through at least one of a plurality of data reception groups of these pins. Recombine at least one parallel received data into at least one input data via the extensible digital interface circuit and then provide it to at least half of the conductor components.

[0006] Based on the above, in the semiconductor device and the communication method between semiconductor devices according to the embodiments of the present invention, data is transmitted between semiconductor devices through parallel transmission. Since the amount used by parallel transmission is large, the data transmission speed is increased, and the signal frequency can be at a low speed. Thereby, the transmission efficiency can be improved, and the transmission frequency can be reduced.

[0007] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and will be described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0008] Figure 1 It is a schematic diagram of a system encapsulating a plurality of semiconductor devices according to an embodiment of the present invention.

[0009] Figure 2 It is a coupling schematic diagram of pins connecting semiconductor devices according to an embodiment of the present invention.

[0010] Figure 3 It is a schematic diagram of a system of an extensible digital interface circuit according to an embodiment of the present invention.

[0011] Figure 4 It is a coupling schematic diagram of pins connecting semiconductor devices according to another embodiment of the present invention.

[0012] Figure 5 It is a schematic diagram of a system of an extensible digital interface circuit according to another embodiment of the present invention.

[0013] Figure 6 It is a stack schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 7 It is a stack schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0015] Figure 8 It is a circuit schematic diagram of a general-purpose input / output interface circuit according to an embodiment of the present invention.

[0016] Figure 9Flowchart of a communication method for multiple semiconductor devices according to an embodiment of the present invention. Detailed Description of the Invention

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 Schematic diagram of a system for encapsulating multiple semiconductor devices according to an embodiment of the present invention. Please refer to Figure 1 , in this embodiment, the integrated circuit 10 includes at least semiconductor devices 100 and 200. The semiconductor devices 100 and 200 can be, for example, chips, and the semiconductor devices 100 and 200 can be encapsulated into a single integrated circuit by using a three-dimensional (3D) chip packaging method or a chiplet packaging method. That is, the semiconductor devices 100 and 200 can be stacked adjacent to or close to each other in the integrated circuit in different ways, but the present invention is not limited thereto.

[0019] In this embodiment, the semiconductor device 100 includes, for example, a plurality of pins (such as a plurality of transmit pins GPTX1 and a plurality of receive pins GPRX1), at least one semiconductor component (such as memory cells 110_1 to 110_n and / or computing units 120_1 to 120_m, where n and m can be any positive integers, which depends on the circuit design), a signal bus 130, and an expandable digital interface circuit 140. Among them, these transmit pins GPTX1 can be divided into a plurality of data transmit groups (such as Figure 8 shown as GTX1 to GTX5), and the receive pins GPRX1 can be divided into a plurality of data receive groups (such as Figure 8 shown as GRX1 to GRX5). The expandable digital interface circuit 140 outputs data based on the data transmit groups (such as Figure 8 shown as GTX1 to GTX5), and inputs data based on the data receive groups (such as Figure 8 shown as GRX1 to GRX5).

[0020] The signal bus 130 is coupled to the memory cells 110_1 to 110_n, the computing units 120_1 to 120_m, and the expandable digital interface circuit 140. That is, the expandable digital interface circuit 140 is coupled to the memory cells 110_1 to 110_n and the computing units 120_1 to 120_m through the signal bus 130. In addition, the expandable digital interface circuit 140 is coupled to at least one data transmit group (such as Figure 8 shown as GTX1 to GTX5) among these transmit pins GPTX1, and is coupled to at least one data receive group (such as Figure 8as shown in GRX1 to GRX5).

[0021] When at least one of the storage units 110_1 to 110_n and the computing units 120_1 to 120_m provides the output data Dout, the scalable digital interface circuit 140 can receive at least one output data Dout via the signal bus 130, and then reorganize at least one output data Dout into at least one parallel transmission data Dpsent, so as to use the parallel transmission method to transmit at least one parallel transmission data Dpsent via the coupled data transmission group (such as Figure 8 as shown in GTX1 to GTX5) to another semiconductor device (such as 200) outside.

[0022] When the scalable digital interface circuit 140 receives at least one parallel received data Dprce from another semiconductor device (such as 200) outside via the coupled data receiving group (such as Figure 8 as shown in GRX1 to GRX5), the scalable digital interface circuit 140 will reorganize at least one parallel received data Dprce into at least one input data Din and then transmit it to the signal bus 130, where the input data Din will correspond to the data format of the received target (that is, one of the storage units 110_1 to 110_n and the computing units 120_1 to 120_m). Then, one or more of the storage units 110_1 to 110_n and the computing units 120_1 to 120_m receive the corresponding one in at least one input data Din via the signal bus 130.

[0023] According to the above, in the three-dimensional (3D) chip packaging method or the chiplet packaging method, the chips are stacked adjacent to or close to each other. Therefore, a large number of channels can be established between the semiconductor devices 100 and 200 (such as through-silicon via (TSV) or Redistribution Layer (RDL)). Through a large number of channels, the data transmission speed (such as bandwidth, bandwidth) can be increased, and the signal frequency does not necessarily need to be at a high speed. Thereby, the transmission efficiency can be improved under the settings of reducing power consumption and cost, and the transmission frequency can be reduced. And, through the scalable digital interface circuits 140 and 240, the semiconductor devices 100 and 200 transmit signals in a digital connection manner, so the manufacturing process of semiconductor components can be freely converted.

[0024] In the implementation of the present invention, the semiconductor device 200 includes, for example, a plurality of pins (such as a plurality of transmission pins GPTX2 and a plurality of reception pins GPRX2), at least one semiconductor component (such as memory cells 210_1 to 210_p and / or computing units 220_1 to 220_q, where p and q can be any positive integer or 0, depending on the circuit design), a signal bus 230, and an extensible digital interface circuit 240. The coupling structure and operation mode of the semiconductor device 200 can refer to the description of the semiconductor device 100, which will not be elaborated here.

[0025] In an embodiment of the present invention, the memory cells 110_1 to 110_n and / or the computing units 120_1 to 120_m can be integrated into at least one die. For example, the memory cells 110_1 to 110_n can be integrated into one or more dice, and the computing units 120_1 to 120_m can be integrated into one or more dice, depending on the circuit design. The embodiment of the present invention is not limited thereto. Similarly, the memory cells 210_1 to 210_p and / or the computing units 220_1 to 220_q can be integrated into at least one die.

[0026] In an embodiment of the present invention, in response to the circuit design of the memory cells 110_1 to 110_n and / or the computing units 120_1 to 120_m, the output data Dout and the input data Din can each include, for example, at least one of an Advanced High-performance Bus (AHB) signal, an Advanced eXtensible Interface (AXI) signal, a serial bus signal, and a parallel bus signal.

[0027] In an embodiment of the present invention, the computing units 120_1 to 120_m and 220_1 to 220_q include, for example, at least one of a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

[0028] In an embodiment of the present invention, the storage units 110_1 to 110_n and 210_1 to 210_p may include dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, thyristor random access memory (TRAM) devices, NAND flash devices, NOR flash devices, resistive random access memory (RRAM) devices, ferroelectric random access memory (FRAM) devices, phase change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, solid state drives (SSD), memory cards, universal flash memory devices (UFS), or similar devices.

[0029] Figure 2 FIG. is a coupling schematic diagram of pins connecting semiconductor devices according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , in this embodiment, the semiconductor devices 300 and 400 may refer to the embodiments of the semiconductor devices 100 and 200. In this embodiment, the number of transmit pins GPTX3 of the semiconductor device 300 may be different from the number of receive pins GPRX4 of the semiconductor device 400, and the number of receive pins GPRX3 of the semiconductor device 300 may be different from the number of transmit pins GPTX4 of the semiconductor device 400. However, the transmit pins GPTX3 of the semiconductor device 300 and the receive pins GPRX4 of the semiconductor device 400 may be grouped into a plurality of data transmit groups and a plurality of data receive groups based on the same pin base (e.g., 40 pins), such that the data transmit groups of the semiconductor device 300 and the data receive groups of the semiconductor device 400 can be coupled one-to-one, whereby the semiconductor device 300 and the semiconductor device 400 can transmit data from the semiconductor device 300 to the semiconductor device 400 through the coupled data transmit groups and data receive groups.

[0030] In this embodiment, the number of connections between the transmission pin GPTX3 of semiconductor device 300 and the reception pin GPRX4 of semiconductor device 400 is based on a pin base number (e.g., 40 pins) of a single data transmission group / single data reception group and is less than or equal to the smaller value between the number of transmission pins GPTX3 of semiconductor device 300 and the number of reception pins GPRX4 of semiconductor device 400. For example, the number of connections between the transmission pin GPTX3 (e.g., 640 pins) of semiconductor device 300 and the reception pin GPRX4 (e.g., 560 pins) of semiconductor device 400 can be 14 pairs of data transmission group - data reception group (i.e., 14 * 40 = 560 pins).

[0031] According to the above, through digital connection, semiconductor devices 300 and 400 can be connected without defining the same number of pins, that is, semiconductor devices with different numbers of pins are allowed to be connected, improving the flexibility of semiconductor device connection.

[0032] In this embodiment, when the transmission speed of the transmission pin GPTX3 of semiconductor device 300 is higher than the transmission speed of the reception pin GPRX4 of semiconductor device 400, the usage ratio of the connection part between the transmission pin GPTX3 of semiconductor device 300 and the reception pin GPRX4 of semiconductor device 400 can be increased to avoid signal transmission delay; relatively, when the transmission speed of the transmission pin GPTX3 of semiconductor device 300 is lower than the transmission speed of the reception pin GPRX4 of semiconductor device 400, the usage ratio of the connection part between the transmission pin GPTX3 of semiconductor device 300 and the reception pin GPRX4 of semiconductor device 400 can be decreased to reduce the waste of system performance without affecting signal transmission.

[0033] In this embodiment, when the transmission speeds of the output data Dout and the input data Din increase, the usage ratio of the connection part between the transmission pin GPTX3 of semiconductor device 300 and the reception pin GPRX4 of semiconductor device 400 can increase to reduce the pick-up idle rate (or pick-up idle time) of the scalable digital interface circuit (such as 140, 240) or the time that the signals to be transmitted accumulate in the scalable digital interface circuit (such as 140, 240); relatively, when the transmission speeds of the output data Dout and the input data Din decrease, the usage ratio of the connection part between the transmission pin GPTX3 of semiconductor device 300 and the reception pin GPRX4 of semiconductor device 400 can decrease.

[0034] Figure 3 It is a system schematic diagram of a scalable digital interface circuit according to an embodiment of the present invention. Please refer to Figures 1 to 3, in this embodiment, the semiconductor device 300 includes, for example, a scalable digital interface circuit 340. The scalable digital interface circuits 140 and 240 may refer to the scalable digital interface circuit 340. Moreover, the scalable digital interface circuit 340 includes a bus packaging circuit 341, an address / data recombination register 342, a transmit recombiner 343, a receive recombiner 344, a transmit buffer 345, an input / output controller 346, a receive buffer 347, and a general-purpose input / output interface circuit 348.

[0035] The bus packaging circuit 341 is coupled to the signal bus 130. The address / data recombination register 342 is coupled to the bus packaging circuit 341. The transmit recombiner 343 is coupled to the address / data recombination register 342. The receive recombiner 344 is coupled to the address / data recombination register 342. The transmit buffer 345 is coupled to the transmit recombiner 343. The receive buffer 347 is coupled to the receive recombiner 344. The general-purpose input / output interface circuit 348 is coupled to the transmit buffer 345 and the receive buffer 347. The input / output controller 346 is coupled to the transmit buffer 345 and the receive buffer 347.

[0036] The input / output controller 346 is used to control the transmit buffer 345 and the receive buffer 347. When the bus packaging circuit 341 receives output data (such as Dout) from the storage units (such as 110_1 to 110_n, 210_1 to 210_p) and / or the computing units (such as 120_1 to 120_m, 220_1 to 220_q) via the signal bus (such as 130, 230), the bus packaging circuit 341 temporarily stores the output data (such as Dout) in the address / data recombination register 342. Then, the transmit recombiner 343 recombines the output data (such as Dout) into parallel transmit data (such as Dpsent) for temporary storage in the transmit buffer 345. The transmit recombiner 343 is responsible for arranging the execution order of the read / write instructions into a small packet of continuous data to provide the parallel transmit data (such as Dpsent). Moreover, the general-purpose input / output interface circuit 348 transmits the parallel transmit data (such as Dpsent) temporarily stored in the transmit buffer 345 to another external semiconductor device (such as 400) via at least one of multiple data transmit groups in the transmit pin GPTX3.

[0037] On the other hand, when the general-purpose input / output interface circuit 348 receives another parallel reception data (such as Dprce) from another external semiconductor device (such as 400) via one less than the multiple data reception groups of the reception pin GPRX3, the general-purpose input / output interface circuit 348 temporarily stores the parallel reception data (such as Dprce) in the reception buffer 347. Then, the reception reorganizer 344 reorganizes the parallel reception data (such as Dprce) temporarily stored in the reception buffer 347 into input data (such as Din), and temporarily stores it in the address / data reorganization register 342. Among them, the reception reorganizer 344 is responsible for restoring a small packet of data (that is, the parallel reception data (such as Dprce)) back to an executable order that can be randomly written to provide the input data (such as Din). And, the bus encapsulation circuit 341 provides the input data (such as Din) temporarily stored in the address / data reorganization register 342 to the storage units (such as 110_1 to 110_n, 210_1 to 210_p) and / or the computing units (such as 120_1 to 120_m, 220_1 to 220_q) via the signal buses (such as 130, 140).

[0038] Figure 4 Schematic coupling diagram of pins between semiconductor devices according to another embodiment of the present invention. Please refer to Figure 1 、 Figure 2 and Figure 4 , in this embodiment, the semiconductor devices 500, 600, and 700 can refer to the embodiments of the semiconductor devices 100 and 200. In this embodiment, the transmission pins GPTX51 and GPTX52 of the semiconductor device 500 can be each grouped into multiple data transmission groups, and the reception pins GPRX51 and GPRX52 of the semiconductor device 500 can be each grouped into multiple data reception groups. Similarly, the transmission pin GPTX6 of the semiconductor device 600 and the transmission pin GPTX7 of the semiconductor device 700 can be each grouped into multiple data transmission groups, and the reception pins GPRX6 of the semiconductor device 600 and the reception pins GPRX7 of the semiconductor device 700 can be each grouped into multiple data reception groups.

[0039] In this embodiment, the data transmission groups of the transmission pins GPTX51 of the semiconductor device 500 can be coupled to the data reception groups of the reception pins GPRX6 of the semiconductor device 600 on a one-to-one basis. The data transmission groups of the transmission pins GPTX52 of the semiconductor device 500 can be coupled to the data reception groups of the reception pins GPRX7 of the semiconductor device 700 on a one-to-one basis. The data reception groups of the reception pins GPRX51 of the semiconductor device 500 can be coupled to the data transmission groups of the transmission pins GPTX6 of the semiconductor device 600 on a one-to-one basis. And the data reception groups of the reception pins GPRX52 of the semiconductor device 500 can be coupled to the data transmission groups of the transmission pins GPTX7 of the semiconductor device 700 on a one-to-one basis.

[0040] The ratio of the reception pins GPRX51 and GPRX52 of the semiconductor device 500 can be related to the ratio of the transmission speed of the transmission pin GPTX6 of the semiconductor device 600 to the transmission speed of the transmission pin GPTX7 of the semiconductor device 700, or related to the ratio of the transmission speed of the output data (such as Dout) and / or input data (such as Din) inside the semiconductor device 600 to the transmission speed of the output data (such as Dout) and / or input data (such as Din) inside the semiconductor device 700. That is, the higher the transmission speed, the higher the proportion.

[0041] On the other hand, the ratio of the transmission pins GPTX51 and GPTX52 of the semiconductor device 500 can be related to the ratio of the transmission speed of the reception pin GPRX6 of the semiconductor device 600 to the transmission speed of the reception pin GPRX7 of the semiconductor device 700. That is, the lower the transmission speed, the higher the proportion; or related to the ratio of the transmission speed of the output data (such as Dout) and / or input data (such as Din) inside the semiconductor device 600 to the transmission speed of the output data (such as Dout) and / or input data (such as Din) inside the semiconductor device 700. That is, the higher the transmission speed, the higher the proportion.

[0042] Figure 5 It is a system schematic diagram of a scalable digital interface circuit according to another embodiment of the present invention. Please refer to Figures 1 to 5, in this embodiment, the semiconductor device 500 includes, for example, a scalable digital interface circuit 540. The scalable digital interface circuits 140 and 240 can refer to the scalable digital interface circuit 540. Moreover, the scalable digital interface circuit 540 includes a bus packaging circuit 541, an address / data recombination register 542, transmit recombiners 543_1 to 543_x, receive recombiners 544_1 to 544_x, transmit buffers 545_1 to 545_x, input / output controllers 546_1 to 546_x, receive buffers 547_1 to 547_x, and general-purpose input / output interface circuits 548_1 to 548_x, where x can be any positive integer. The operation of the scalable digital interface circuit 540 can refer to the scalable digital interface circuit 340, which will not be elaborated here. Also, since a large number of connections are required for parallel transmission, semiconductor devices (such as 500 to 600) are not spaced too far apart. Therefore, usually x < 4. However, when long-distance transmission is required, other connection protocols may be adopted, such as the Peripheral Component Interconnect Express (PCIE), the Universal Chiplet Interconnect Express (UCIE), etc., but the embodiments of the present invention are not limited thereto.

[0043] Figure 6 Stack diagram of a semiconductor device according to an embodiment of the present invention. Please refer to Figure 1 and Figure 6 , in this embodiment, the semiconductor devices 100a and 200a are directly stacked, that is, the semiconductor devices 100a and 200a are packaged using a three-dimensional (3D) chip packaging method.

[0044] Figure 7 Stack diagram of a semiconductor device according to another embodiment of the present invention. Please refer to Figure 1 and Figure 7 , in this embodiment, the semiconductor devices 100b and 200b are stacked adjacent to each other on the same surface of an interposer or a substrate 800, that is, the semiconductor devices 100b and 200b are packaged using a chiplet packaging method. Among them, the semiconductor devices 100b and 200b are coupled to each other through a path formed by a redistribution layer (RDL) and / or through-silicon vias (TSVs) on the interposer or the substrate 800.

[0045] Figure 8 Circuit diagram of a general-purpose input / output interface circuit according to an embodiment of the present invention. Please refer to Figure 1 , Figure 3 and Figure 8, in this embodiment, the general-purpose input / output interface circuit 348 can be referred to as shown in the general-purpose input / output interface circuit 348a, where the general-purpose input / output interface circuit 348a includes a plurality of general-purpose input / output transmission circuits GPX1 to GPX5, a plurality of general-purpose input / output reception circuits GPE1 to GPE5, a plurality of transmission multiplexers TMX1 to TMX3, and a plurality of reception multiplexers RMX1 to RMX4.

[0046] In this embodiment, it is assumed that the parallel transmission data (such as Dpsent) stored in the transmission buffer 345a has 4 transmission data parts DPX1 to DPX4, and the received parallel reception data (such as Dprce) has 4 reception data parts DPE1 to DPE4 and is stored in the reception buffer 347a. At this time, the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output transmission circuits GPX1 to GPX5 to transmit the parallel transmission data (such as Dpsent), and the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output reception circuits GPE1 to GPE5 to receive the parallel reception data (such as Dprce).

[0047] In this embodiment, each of the plurality of transmission multiplexers TMX1 to TMX3 has a first input terminal for receiving one of the transmission data parts DPX1 to DPX4 (corresponding to the first transmission data part) from the transmission buffer 345a, a second input terminal for receiving another (corresponding to the second transmission data part) adjacent to the first transmission data part among the transmission data parts DPX1 to DPX4 from the transmission buffer 345a, and an output terminal coupled to one of these general-purpose input / output transmission circuits GPX1 to GPX5.

[0048] Furthermore, the transmission multiplexer TMX1 receives the transmission data parts DPX1 and DPX2 and is coupled to the general-purpose input / output transmission circuit GPX2, the transmission multiplexer TMX2 receives the transmission data parts DPX2 and DPX3 and is coupled to the general-purpose input / output transmission circuit GPX3, and the transmission multiplexer TMX3 receives the transmission data parts DPX3 and DPX4 and is coupled to the general-purpose input / output transmission circuit GPX4. Among them, the general-purpose input / output transmission circuit GPX1 directly receives the transmission data part DPX1, and the general-purpose input / output transmission circuit GPX5 directly receives the transmission data part DPX5. According to the above, the general-purpose input / output transmission circuits GPX1 to GPX5 are each used to receive one of the transmission data parts DPX1 to DPX4, and the data is allocated via the transmission multiplexers TMX1 to TMX3.

[0049] Each of the plurality of receive multiplexers RMX1 to RMX4 has a first input terminal coupled to one of these general-purpose input / output receive circuits GPE1 to GPE5 (corresponding to the first general-purpose input / output receive circuit), a second input terminal coupled to another one of these general-purpose input / output receive circuits GPE1 to GPE5 adjacent to the first general-purpose input / output receive circuit (corresponding to the second general-purpose input / output receive circuit), and an output terminal providing one of the receive data portions DPE1 to DPE4.

[0050] Furthermore, the receive multiplexer RMX1 is coupled to the general-purpose input / output receive circuits GPE1 and GPE2 and provides the data portion DPE1, the receive multiplexer RMX2 is coupled to the general-purpose input / output receive circuits GPE2 and GPE3 and provides the data portion DPE2, the receive multiplexer RMX3 is coupled to the general-purpose input / output receive circuits GPE3 and GPE4 and provides the data portion DPE3, and the receive multiplexer RMX4 is coupled to the general-purpose input / output receive circuits GPE4 and GPE5 and provides the data portion DPE4. According to the above, each of the general-purpose input / output receive circuits GPE1 to GPE5 is used to receive one of the data portions DPE1 to DPE4, and the data is allocated via the receive multiplexers RMX1 to RMX4.

[0051] According to the above, when one of the general-purpose input / output transmit circuits GPX1 to GPX5 presents a fault or error, the data can be transmitted via other general-purpose input / output transmit circuits, and when one of the general-purpose input / output receive circuits GPE1 to GPE5 presents a fault or error, the data can be received via other general-purpose input / output receive circuits.

[0052] In this embodiment, the general-purpose input / output interface circuit 348a further includes a plurality of transmit synchronization circuits T1 to T5 and a plurality of receive synchronization circuits R1 to R5. One of the general-purpose input / output transmit circuits GPX1 to GPX5 and one of the transmit synchronization circuits T1 to T5 are grouped to be coupled to the pins of the same data transmit group (such as GTX1 to GTX5). For example, the general-purpose input / output transmit circuit GPX1 and the transmit synchronization circuit T1 are grouped to be coupled to the pins of the data transmit group GTX1, the general-purpose input / output transmit circuit GPX2 and the transmit synchronization circuit T2 are grouped to be coupled to the pins of the data transmit group GTX2, and so on for the rest, and it can be referred to as shown in the drawings and will not be elaborated here.

[0053] One of the general-purpose input / output receiving circuits GPE1 to GPE5 is grouped with one of the receive synchronization circuits R1 to R5 to couple to the reception of the same data reception group (such as GRX1 to GRX5). For example, the general-purpose input / output receiving circuit GPE1 and the receive synchronization circuit R1 are grouped to couple to the pin of the data reception group GRX1, the general-purpose input / output receiving circuit GPE2 and the receive synchronization circuit R2 are grouped to couple to the pin of the data reception group GRX2, and so on for the rest. And it can be referred to as shown in the attached drawings, which will not be elaborated here.

[0054] The transmit synchronization circuits T1 to T5 are used to transmit transmit synchronization signals (usually frequency signals or data ready signals) and receive receive synchronization signals (usually frequency signals or receive ready signals of the receiving end). The receive synchronization circuits R1 to R5 are used to receive transmit synchronization signals (usually frequency signals or data ready signals of the transmitting end) and transmit receive synchronization signals (usually frequency signals or receive ready signals).

[0055] In an embodiment of the present invention, the semiconductor device (such as 100) further includes a channel controller 810. The channel controller 810 is coupled to these transmit multiplexers TMX1 to TMX3 and these receive multiplexers RMX1 to RMX4 to control, based on channel testing, the output ends of the respective transmit multiplexers TMX1 to TMX3 to be coupled to one of the first input end and the second input end, and control the output ends of the respective receive multiplexers RMX1 to RMX4 to be coupled to one of the first input end and the second input end. Further, before starting communication, the channel controller 810 will first test the channel (i.e., between the connected pins / data transmission group and data reception group), that is, test whether the channel is valid by transmitting and receiving data. If all channels are valid, data is transmitted and received through the preset conduction. If there are invalid channels and the error tolerance range is not exceeded, data is transmitted and received using the valid conduction. And, after communication, the channel controller 810 can perform data / channel handshake through the transmit synchronization circuits (such as T1 to T5) and the receive synchronization circuits (such as R1 to R5).

[0056] In an embodiment of the present invention, the channel controller 810 can be configured in the input / output controller 346, and the channel controllers 810 among the respective semiconductor devices (such as 100 to 700) can be communicatively connected to each other to test the channels.

[0057] Figure 9 It is a flowchart of a communication method for multiple semiconductor devices according to an embodiment of the present invention. Please refer to Figure 9, in the present embodiment, the communication method of the semiconductor device includes the following steps. In step S110, at least one output data provided by at least one semiconductor component is reorganized into at least one parallel transmission data via the scalable digital interface circuit. In step S120, at least one parallel transmission data is transmitted to an external semiconductor device via parallel transmission through at least one of a plurality of data transmission groups of a plurality of pins. In step S130, at least one parallel received data is received from the external semiconductor device through at least one of a plurality of data reception groups of these pins. In step S140, at least one parallel received data is reorganized into at least one input data via the scalable digital interface circuit and then provided to at least one semiconductor component. Among them, the order of steps S110, S120, S130, and S140 is for illustration, and the embodiments of the present invention are not limited thereto. Moreover, the details of steps S110, S120, S130, and S140 can be referred to Figures 1 to 8 as shown in the embodiment, which will not be described herein again.

[0058] In summary, for the semiconductor device and the communication method between semiconductor devices according to the embodiments of the present invention, data is transmitted between semiconductor devices through channels used for a large number of parallel transmissions. At this time, the signal frequency can be further reduced, the interface power consumption can be saved, the interface circuit complexity and manufacturing cost can be reduced, and the substantial transmission efficiency can be improved through a large number of parallel transmission methods, while achieving a low-power and high-efficiency data transmission interface. Moreover, signals are transmitted between semiconductor devices in a digital connection manner, so the manufacturing process of semiconductor components can be freely converted without affecting the connection method, and the number of pins for transmitting signals between semiconductor devices does not have to be equal to increase the flexibility of hybrid transmission between semiconductor devices.

[0059] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Multiple pins, divided into multiple data sending groups and multiple data receiving groups; At least one semiconductor device provides at least one output data and receives at least one input data; as well as An expandable digital interface circuit is coupled to at least one of the multiple data sending groups, at least one of the multiple data receiving groups, and the at least one semiconductor component, wherein the expandable digital interface circuit reorganizes the at least one output data into at least one parallel sending data to send the at least one parallel sending data to an external semiconductor device via parallel transmission, and receives at least one parallel receiving data from the external semiconductor device via parallel transmission to reorganize the at least one parallel receiving data into the at least one input data.

2. The semiconductor device according to claim 1, wherein: The at least one output data and the at least one input data each include at least one of an advanced high performance bus signal, an advanced extensible interface signal, a serial bus signal, and a parallel bus signal.

3. The semiconductor device according to claim 1, wherein: The number of connections between the multiple pins of the multiple data sending groups and the multiple data receiving pins of the external semiconductor device is based on the pin base number of a single data sending group and is less than or equal to the smaller value of the number of the multiple pins of the multiple data sending groups and the number of the multiple data receiving pins.

4. The semiconductor device according to claim 3, wherein: When the transmission speed of the multiple pins of the multiple data transmission groups is higher than the transmission speed of the multiple data transmission groups, the usage ratio of the connection parts of the multiple pins of the multiple data transmission groups and the multiple data receiving pins of the external semiconductor device is higher.

5. The semiconductor device according to claim 3, wherein: When the transmission speed of the at least one output data and the at least one input data increases, the usage ratio of the connection parts of the plurality of pins of the plurality of data transmission groups and the plurality of data receiving pins of the external semiconductor device increases.

6. The semiconductor device according to claim 1, wherein: The invention also includes a signal bus coupling the at least one semiconductor component and the expandable digital interface circuit.

7. The semiconductor device according to claim 6, wherein: The scalable digital interface circuit comprises: A bus coupled to the signal bus; An address data reorganization register coupled to the bus; a sending reassembler, coupled to the address data reassembly register; a receiving reorganizer, coupled to the address data reorganization register; a sending buffer, coupled to the sending reassembler; a receiving buffer coupled to the receiving reassembler; A universal input / output interface circuit, coupled to the sending buffer and the receiving buffer; and an input / output controller coupled to the sending buffer and the receiving buffer to control the sending buffer and the receiving buffer, wherein when the bus receives the at least one output data from the at least one semiconductor component via the signal bus, the at least one output data is temporarily stored in the address data reorganization register, and then the transmission reorganizer reorganizes the at least one output data into the at least one parallel transmission data to be temporarily stored in the transmission buffer, and the universal input / output interface circuit transmits the at least one parallel transmission data temporarily stored in the transmission buffer to the external semiconductor device via at least one of the plurality of data transmission groups; and When the universal input-output interface circuit receives the at least one parallel received data from the external semiconductor device via at least one of the multiple data receiving groups, the at least one parallel received data is temporarily stored in the receiving buffer, and then the receiving reorganizer reorganizes the at least one parallel received data into the at least one input data to be temporarily stored in the address data reorganization register, and the bus provides the at least one input data temporarily stored in the address data reorganization register to the at least one semiconductor component via the signal bus.

8. The semiconductor device according to claim 7, wherein: The universal input-output interface circuit comprises: a plurality of general purpose input and output transmission circuits, each for receiving one of at least one transmission data portion of the at least one parallel transmission data; A plurality of transmission synchronization circuits, used for transmitting transmission synchronization signals and receiving reception synchronization signals, wherein each of the plurality of transmission synchronization circuits and one of the plurality of general input and output transmission circuits are coupled to a plurality of pins of the same data transmission group in the plurality of data transmission groups; a plurality of general purpose input and output receiving circuits, each for receiving one of at least one receiving data portion of the at least one parallel receiving data via the plurality of pins; A plurality of receiving synchronization circuits, used for receiving the sending synchronization signal and sending the receiving synchronization signal, wherein each of the plurality of receiving synchronization circuits and one of the plurality of general input and output receiving circuits are coupled to a plurality of pins of the same data receiving group in the plurality of data receiving groups; a plurality of transmit multiplexers, each having a first input terminal for receiving a first transmit data portion of the at least one transmit data portion from the transmit buffer, a second input terminal for receiving a second transmit data portion of the at least one transmit data portion adjacent to the first transmit data portion from the transmit buffer, and an output terminal coupled to one of the plurality of general purpose input and output transmit circuits; and A plurality of receiving multiplexers each having a first input terminal coupled to a first universal input output receiving circuit among the plurality of universal input output receiving circuits, a second input terminal coupled to a second universal input output receiving circuit adjacent to the first universal input output receiving circuit among the plurality of universal input output receiving circuits, and an output terminal for providing the one of the at least one received data portion.

9. The semiconductor device according to claim 8, wherein: It also includes a channel controller, which is coupled to the multiple transmit multiplexers and the multiple receive multiplexers to control the output end of each of the multiple transmit multiplexers to be coupled to one of the first input end and the second input end based on a channel test, and to control the output end of each of the multiple receive multiplexers to be coupled to one of the first input end and the second input end.

10. The semiconductor device according to claim 1, wherein: The semiconductor device and the external semiconductor device include chips, and the at least one semiconductor component includes at least one die.

11. A communication method between semiconductor devices, comprising: Reorganize at least one output data provided by at least one semiconductor device into at least one parallel transmission data via an expandable digital interface circuit; Sending the at least one parallel transmission data to an external semiconductor device via parallel transmission via at least one of a plurality of data transmission groups of a plurality of pins; receiving at least one parallel receive data from the external semiconductor device via at least one of a plurality of data receive groups of the plurality of pins; as well as The at least one parallel received data is reorganized into at least one input data via the expandable digital interface circuit and then provided to the at least one semiconductor device.

12. The communication method according to claim 11, characterized in that: The at least one output data and the at least one input data each include at least one of an advanced high performance bus signal, an advanced extensible interface signal, a serial bus signal, and a parallel bus signal.

13. The communication method according to claim 11, characterized in that: The number of connections between the multiple pins of the multiple data sending groups and the multiple data receiving pins of the external semiconductor device is based on the pin base number of a single data sending group and is less than or equal to the smaller value of the number of the multiple pins of the multiple data sending groups and the number of the multiple data receiving pins.

14. The communication method according to claim 13, characterized in that: Also includes When the transmission speed of the multiple pins of the multiple data transmission groups is higher than the transmission speed of the multiple data transmission groups, the usage ratio of the connection parts of the multiple pins of the multiple data transmission groups and the multiple data receiving pins of the external semiconductor device is higher.

15. The communication method according to claim 13, characterized in that: Also includes When the transmission speed of the at least one output data and the at least one input data increases, the usage ratio of the connection parts of the plurality of pins of the plurality of data transmission groups and the plurality of data receiving pins of the external semiconductor device increases.

16. The communication method according to claim 11, characterized in that: The semiconductor device and the external semiconductor device include chips, and the at least one semiconductor component includes at least one die.

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