Simulation excitation generation method and device, electronic equipment and storage medium

Abstract

The invention discloses a simulation excitation generation method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the simulation excitation generation method comprises the steps that a first transmission transaction is acquired, and the first transmission transaction is used for simulating a host to store to-be-transmitted data in a host memory; determining M first half storage blocks in the plurality of half storage blocks according to the occupation state and the address expression mode of each half storage block; according to the M first half storage blocks, N address entries are generated, and the N address entries are bound with addresses of the M first half storage blocks; determining at least one address identifier according to the N and the addresses of the N address entries; and generating a simulation excitation comprising at least one address identifier, and sending the simulation excitation to the storage controller, the simulation excitation being used for testing the transmission function of the storage controller on the data to be transmitted. The problem that simulation excitation corresponding to data transmission in a discontinuous scene cannot be generated in the prior art can be solved, and the accuracy of testing the transmission function of the storage controller is improved.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a method, apparatus, electronic device, and storage medium for generating simulation stimuli. Background Art

[0002] With the rapid development of integrated circuit technologies, the complexity and integration level of integrated circuits have been continuously increasing, and the importance of front-end verification of integrated circuits has become increasingly prominent. In the design process of integrated circuits, front-end verification is an important link to ensure the correctness and reliability of the design. The front-end verification work can apply stimuli to the design in the form of software simulation during the hardware description language (HDL) code design stage to test the functional correctness of the design. In the storage field, as a key node connecting the user host and the storage medium, the storage controller (also known as the host controller) is specified with the Non-Volatile Memory Express (NVMe) protocol by the industry to better implement its functions. All data interaction actions between the storage controller and the host must comply with the NVMe protocol. For the front-end verification of the storage controller, it is necessary to simulate the host to apply simulation stimuli to the host controller.

[0003] In the related front-end verification process, only the host is simulated to forcibly divide different data structures matching different address representation forms on the continuous storage area after the specified address to generate simulation stimuli, so as to implement the scenario of describing the data location with address entries matching different address representation forms. However, this method of generating simulation stimuli cannot generate simulation stimuli corresponding to data transmission in a discontinuous scenario, resulting in low accuracy in testing the transmission function of the storage controller. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, and storage medium for generating simulation stimuli, so as to at least solve the problem in the related art that simulation stimuli corresponding to data transmission in a discontinuous scenario cannot be generated, resulting in low accuracy in testing the transmission function of the storage controller.

[0005] The present application provides a method for generating a simulation stimulus, including: obtaining a first transmission transaction, where the first transmission transaction is used to simulate the host storing data to be transmitted in the host memory. The first transmission transaction carries an address representation method, which is used to indicate the storage distribution method of the data to be transmitted in the host memory. The host memory is divided into multiple semi-storage blocks; determining M first semi-storage blocks from the multiple semi-storage blocks according to the occupancy status of each semi-storage block and the address representation method. The M first semi-storage blocks are used to store the data to be transmitted, and the distribution method of the M first semi-storage blocks matches the address representation method; generating N address entries according to the M first semi-storage blocks, where the N address entries bind the addresses of the M first semi-storage blocks, N ≤ M, and both N and M are positive integers; determining at least one address identifier according to N and the addresses of the N address entries, where the at least one address identifier is used to identify the addresses of the N address entries in the host memory; generating a simulation stimulus including the at least one address identifier, and sending the simulation stimulus to a storage controller, where the simulation stimulus is used to test the transmission function of the storage controller for the data to be transmitted.

[0006] The present application further provides a device for generating a simulation stimulus, including: an obtaining module, configured to obtain a first transmission transaction, where the first transmission transaction is used to simulate the host storing data to be transmitted in the host memory. The first transmission transaction carries an address representation method, which is used to indicate the storage distribution method of the data to be transmitted in the host memory. The host memory is divided into multiple semi-storage blocks.

[0007] A processing module, configured to determine M first semi-storage blocks from the multiple semi-storage blocks according to the occupancy status of each semi-storage block and the address representation method. The M first semi-storage blocks are used to store the data to be transmitted, and the distribution method of the M first semi-storage blocks matches the address representation method.

[0008] The processing module is further configured to generate N address entries according to the M first semi-storage blocks, where the N address entries bind the addresses of the M first semi-storage blocks, N ≤ M, and both N and M are positive integers.

[0009] The processing module is configured to determine at least one address identifier according to N and the addresses of the N address entries, where the at least one address identifier is used to identify the addresses of the N address entries in the host memory.

[0010] The processing module is configured to generate a simulation stimulus including the at least one address identifier, and send the simulation stimulus to a storage controller, where the simulation stimulus is used to test the transmission function of the storage controller for the data to be transmitted.

[0011] The present application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above methods for generating a simulation stimulus when executing the computer program.

[0012] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any one of the above-mentioned simulation excitation generation methods.

[0013] The present application also provides a computer program product including a computer program, which, when executed by a processor, implements the steps of any one of the above-mentioned simulation excitation generation methods.

[0014] Through the present application, a transmission transaction generator obtains a first transmission transaction, determines M first half storage blocks among a plurality of half storage blocks according to the occupancy status and address expression mode of each half storage block; generates N address entries according to the M first half storage blocks; determines at least one address identifier according to N and the addresses of the N address entries; generates a simulation excitation including at least one address identifier, and sends the simulation excitation to a storage controller.

[0015] Since the host memory can be divided into multiple half storage blocks, the host memory space can be allocated for the transmission transactions required by the user, and the data to be stored can be stored and multiple address entries can be generated according to the distribution range of these memory spaces, the occupancy status of the space, and the selected address expression mode. Furthermore, based on the multiple address entries, simulation excitations corresponding to data transmission in a discontinuous scenario are generated, improving the accuracy of testing the transmission function of the storage controller. In addition, the present application saves the time for allocating the address range corresponding to the half storage blocks for the data to be transmitted, groups and spatially plans the address entries according to different address expression modes, controls the distribution of the data to be transmitted and the generation quantity and distribution of the corresponding address entries, and provides the flexibility and richness of the simulation excitation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0017] Figure 1 It is a topological structure diagram of a simulation excitation generation system provided by an embodiment of the present application; Figure 2 It is a flowchart of a simulation excitation generation method provided by an embodiment of the present application; Figure 3 It is a schematic diagram of dividing a host memory into multiple HKBs provided by an embodiment of the present application; Figure 4 It is a schematic diagram of the distribution of address entries in the host memory provided by an embodiment of the present application; Figure 5 Schematic diagram of PRP-List entry distribution provided by an embodiment of the present application; Figure 6 Schematic diagram of SGL entry distribution provided by an embodiment of the present application; Figure 7 Block diagram of a structure of a simulation excitation generation device provided by an embodiment of the present application; Figure 8 Schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0019] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0021] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the simulation excitation generation method depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0022] The embodiments of the present application are applied to the front-end verification of a storage controller (also referred to as a host controller / master control integrated circuit), and it is necessary to simulate the scenario where a user host applies simulation excitation to the storage controller.

[0023] In the NVMe protocol, data transmission may be discontinuous. This protocol usually uses data pointers in the form of Physical Region Page (PRP) or Scatter / Gather List (SGL) to represent discontinuous or chunked data distributions. This requires the model simulating the user host to place the data to be transmitted in a discontinuous or chunked form in the host memory and generate PRP and SGL address entries.

[0024] Among them, PRP is a physical page-based data transmission method used in the NVMe protocol to describe the data transmission between the host memory and storage devices (e.g., solid-state drives), mainly used to describe continuous memory spaces.

[0025] SGL is a more flexible data transmission method in NVMe, which can describe memory spaces of any size and discontinuity.

[0026] In the related art, by simulating the host to forcibly divide different data structures matching the address expression forms on the continuous storage area after the specified address to generate simulation stimuli, on the one hand, it is impossible to generate simulation stimuli corresponding to data transmission in discontinuous scenarios, and on the other hand, there is a risk of data overlap when multiple transmission transactions are initiated in parallel, which is not conducive to the parallel execution of multiple stimuli.

[0027] To solve the above technical problems, the embodiments of the present application provide a method for generating simulation stimuli. The user memory is divided into several minimum space units. According to the total amount of data to be transmitted and the selected address expression form, a sufficient number of minimum space units are selected. Utilizing the characteristics of the simulation-enabled backdoor read / write memory, these minimum space unit sets are read and written. According to the selection results, simulation stimuli corresponding to several PRP and SGL entries are generated and sent to the storage controller to transmit the address information of the minimum space unit sets to the storage controller, thereby testing the transmission function of the storage controller for the data to be transmitted. This method can generate simulation stimuli corresponding to data transmission in discontinuous scenarios to improve the accuracy of testing the transmission function of the storage controller.

[0028] Next, taking Figure 1 the simulation stimulus generation system shown as an example, the method provided by the embodiments of the present application will be described.

[0029] As Figure 1 shown, Figure 1 is the topology diagram of a simulation stimulus generation system provided by the embodiments of the present application. Figure 1 In it, the simulation stimulus generation system 100 includes a transmission transaction generator 101, a storage controller 102, a host memory 103, and a controller memory 104.

[0030] The Transaction Generator 101 in the embodiments of this application can be any device with communication and computing functions, abbreviated as Trans-Gen. The transaction generator is an important programming paradigm (SystemVerilog Object-Oriented Programming, SV-OOP) based on hardware verification and design, and is established using syntax structures such as classes, attributes, and methods. The transaction generator can also be called a simulation stimulus generation device.

[0031] The storage controller 102 in the embodiments of this application can manage data transmission between the host memory and the controller memory to ensure data storage reliability and read / write performance.

[0032] The host memory 103 can be the random access memory (RAM) in the host, which is a component used to temporarily store data and program instructions when the computer is running.

[0033] The controller memory 104 can be the memory equipped with the main controller / storage controller itself, which is used to assist the main controller in completing specific tasks.

[0034] Figure 1 The shown simulation stimulus generation system is only for illustration and is not used to limit the technical solutions of this application. Those skilled in the art should understand that in the specific implementation process, the simulation stimulus generation system can also include more devices, which are not limited.

[0035] The embodiments of this application provide a method for generating simulation stimuli, which is applied to a transaction generator, as Figure 2 shown, Figure 2 is a schematic flowchart of a method for generating simulation stimuli provided by the embodiments of this application. The method for generating simulation stimuli includes the following steps: S201: Obtain a first transmission transaction.

[0036] Among them, the first transmission transaction is used to simulate the host storing the data to be transmitted in the host memory. The first transmission transaction carries an address expression method, the data length of the data to be transmitted, and the data to be transmitted.

[0037] Among them, the address expression method is used to indicate the storage distribution method of the data to be transmitted in the host memory. The address expression includes a physical region page expression method (Physical Region Page, PRP) and a scatter / gather list expression method (Scatter / Gather List, SGL).

[0038] The host memory (also known as Host-mem) is divided into multiple half-kilobyte blocks. A half-kilobyte block (HKB) is also known as the smallest storage unit. The size of each half-kilobyte block can be 512 Bytes. Each half-kilobyte block corresponds to an index or number, which is used to identify each HKB.

[0039] It can be understood that in the NVMe protocol, the smallest unit of data transmission is a logical block, and a logical block is at least 512 Bytes. Therefore, in this application, the Host-mem space is divided into multiple half-kilobyte blocks with a size and boundary of 512 Bytes. For example, when the host memory is 1024KB, it can be divided into 2048 HKBs.

[0040] S202: Determine M first half-kilobyte blocks among the multiple half-kilobyte blocks according to the occupancy status and address representation of each half-kilobyte block.

[0041] Among them, the M first half-kilobyte blocks are used to store the data to be transmitted. The distribution method of the M first half-kilobyte blocks matches the address representation.

[0042] In some alternative embodiments, the transmission transaction generator obtains the multi-bit static attribute corresponding to the host memory and the size of each half-kilobyte block; calculates the sum of the data length and the size of each half-kilobyte block to obtain the total number M of half-kilobyte blocks required for the data to be transmitted; determines M first half-kilobyte blocks among the multiple half-kilobyte blocks based on the address representation, static attribute, and total number M. The occupancy status of each first half-kilobyte block in the M first half-kilobyte blocks is the unoccupied status.

[0043] Among them, the static attribute includes multiple bits. Each bit is used to indicate the occupancy status of each half-kilobyte block. The static attribute is named allocated_hkb. Each bit of the static attribute represents the occupancy status of each HKB in the host memory.

[0044] Among them, when the bit is set to a preset value, it indicates that the HKB corresponding to the index of this bit is in the occupied state. The preset value is used to indicate that the occupancy status of the half-kilobyte block corresponding to each bit is the occupied state. For example, the preset value can be 1. Correspondingly, when the bit is set to 0, it indicates that the HKB corresponding to the index of this bit is in the unoccupied state or the idle state.

[0045] It can be understood that the static attribute can ensure the intercommunication of the space management information of multiple Trans-Gen objects (i.e., multiple transmission transactions), that is, this static attribute is shared by all Trans-Gen objects. This static attribute enables the occupancy information among all transmission transactions to be shared with each other, ensuring that there is no data overlap among multiple transmission transactions.

[0046] In one example, when the address expression is in the physical page expression, the transmission transaction generator determines M first half storage blocks that match the physical page expression from multiple half storage blocks based on the static attribute and the total quantity M. Among them, the M first half storage blocks are distributed on N storage pages.

[0047] In another example, when the address expression is in the scatter-gather list expression, the transmission transaction generator determines M first half storage blocks that match the scatter-gather list expression from multiple half storage blocks based on the static attribute and the total quantity M. Among them, the M first half storage blocks correspond to N storage segments.

[0048] Exemplarily, taking Figure 3 as an example, Figure 3 is a schematic diagram of dividing a host memory into multiple HKBs provided by an embodiment of the present application. In Figure 3 , the shaded HKBs in the figure indicate that they have been occupied by other ongoing transmission transactions and are in the occupied state. The size of each storage page (Memory Page) corresponding to this host memory is 4KB (so the aligned address should be 0x1000), that is, it means that the maximum storage space that a PRP entry can represent is 4KB. Figure 3 Each row in

[0049] represents a MemoryPage. Taking the data length of the data to be transmitted as 12 * 512 Bytes and 12 HBKs required for the data to be transmitted as an example, the transmission transaction generator determines 12 first half storage blocks in multiple half storage blocks under different address expressions, including: Example 1: When the address expression is PRP, the Transmission Transaction Generator (Trans-Gen) looks for idle HKBs in the host memory based on static attributes. First, it finds HKB4 in the first row. However, since the address expression is PRP, if the starting address 0x0800 of HKB4 is used as the first PRP entry, according to the definition of PRP in the NVMe protocol, it will cover the address space from 0x0800 to 0x0fff. In the figure, the address space from 0x0a00 to 0x0fff is occupied by other transmission transactions, so HKB4 cannot be used as the first half storage block. Then, it finds HKB14 and HKB15 in the second row. If the starting address 0x1c00 of HKB14 is used as the first PRP entry, according to the definition of PRP in the NVMe protocol, it will cover 0x1c00 to 0x1fff, and the HKBs corresponding to 0x1c00 to 0x1fff are all in the unoccupied state, that is, this storage space is available. Therefore, 2 HKBs, namely HKB14 and HKB15, can be used as the first half storage block. Then, it continues to query 8 HKBs, namely HKB16 to HKB23, in the third row. These 8 HKBs happen to be a storage page and are all not occupied by other transmission transactions (all in the unoccupied state). Therefore, 8 HKBs, namely HKB16 to HKB23, can be used as the first half storage block. Finally, it finds 2 HKBs, namely HKB32 and HKB33, in the fifth row. So far, 12 first half storage blocks that match the physical page expression are determined from multiple half storage blocks, including: HKB14, HKB15, HKB16 to HKB23, HKB32 and HKB33.

[0050] Example 2: When the address expression is SGL, the Transmission Transaction Generator (Trans-Gen) looks for idle HKBs in the host memory based on static attributes. First, it finds HKB4. Since the address expression is SGL, according to the definition of SGL in the NVMe protocol, it can accurately express the space of HKB4 without worrying about covering other spaces. Therefore, HKB4 can be used as the first half storage block. Then, it continues to find HKB14 to HKB23 and HKB32, all of which are in the unoccupied state. Therefore, HKB14 to HKB23 and HKB32 can be used as the first half storage block. So far, 12 first half storage blocks that match the scatter-gather list expression are determined from multiple half storage blocks, including: HKB4, HKB14 to HKB23 and HKB32.

[0051] In some alternative embodiments, after determining M first half storage blocks in multiple half storage blocks, the transmission transaction generator may also look up M bit positions corresponding to the M first half storage blocks in the static attributes; update each of the M bit positions in the static attributes to a preset value to obtain the first static attribute. For example, the transmission transaction generator may update each of the M bit positions in the static attributes to 1 to indicate locking of the M first HKBs.

[0052] Optionally, the transmission transaction generator may record the indices of the M first HKBs into a queue variable (udata_hkb_q).

[0053] In one example, when the transmission transaction generator first locks the M HKBs through allocated_hkb, it may set a semaphore in the class definition of the transmission transaction generator and set the semaphore as a static attribute. This semaphore is also referred to as alloc_chg_sema.

[0054] Exemplarily, before modifying allocated_hkb, the transmission transaction generator needs to apply for the right to modify to the semaphore (alloc_chg_sema), and after obtaining the right to modify, modify allocated_hkb; and after the modification is completed, return the right to modify.

[0055] It can be understood that setting the semaphore as a static attribute by the transmission transaction generator can ensure that any transmission transaction applies for the same semaphore. In addition, since the allocated_hkb variable is a static attribute and multiple transmission transactions modify the same variable, to avoid read-write conflicts between multiple parallel transmission transactions.

[0056] S203: Generate N address entries according to the M first half storage blocks.

[0057] Among them, the N address entries are bound to the addresses of the M first half storage blocks, N ≤ M, and both N and M are positive integers.

[0058] In some alternative embodiments, when the address expression is in the physical page expression, the transmission transaction generator generates N address entries based on the starting address corresponding to the first first half storage block distributed on each of the N storage pages corresponding to the M first half storage blocks.

[0059] Exemplarily, when the address expression is in the physical page expression, the transmission transaction generator generates N PRP address entries based on the starting address of the first first HKB in udata_hkb_q (the first first HKB corresponding to the first storage page distribution of the M first half storage blocks) and the starting addresses of the first first HKBs of the other storage pages except the first storage page among the N storage pages.

[0060] Example 3, taking Example 1 as an example, the M first half storage blocks are HKB14~15, HKB16~23, and HKB32~33 respectively. The transmission transaction generator creates a PRP address entry using the starting address 0x1c00 of the first first HKB in the first row, i.e., HKB14; creates a PRP address entry using the starting address 0x2000 of the first first HKB in the third row, and creates a PRP address entry using the starting address 0x400 of the first first HKB in the fifth row, that is, generates three PRP address entries. It can be understood that three PRP entries can represent all the data positions of the data to be transmitted.

[0061] Optionally, the transmission transaction generator can write the N PRP address entries into a queue (prp_list).

[0062] In some alternative embodiments, when the address expression is in the scatter-gather list expression, the transmission transaction generator generates N address entries based on the starting address corresponding to the first first half storage block in each of the N storage segments corresponding to the M first half storage blocks, and the data lengths of at least one first half storage block included in each storage segment. Among them, each address entry is also called an SGL Data Block descriptor.

[0063] Exemplarily, when the address expression is in the scatter-gather list expression, the transmission transaction generator generates N SGL Data Block descriptors based on the consecutive N storage segments corresponding to the M first half storage blocks in udata_hkb_q.

[0064] Example 4. Taking Example 2 as an example, the M first half storage blocks are HKB4, HKB14 to 23, and HKB32 respectively. The M first half storage blocks are distributed in three consecutive memory spaces, that is, the M first half storage blocks correspond to 3 storage segments. The transmission transaction generator uses the starting address 0x0800 of HKB4 and the data length 512B of one first half storage block to establish an SGL Data Block descriptor; uses the starting address 0x1c00 of HKB14 to 23 and the data length 5120B of ten first half storage blocks to establish an SGL Data Block descriptor; uses the starting address 0x4000 of HKB32 and the data length 512B of one first half storage block to establish an SGL Data Block descriptor, that is, three SGL Data Block descriptors (i.e., three SGL address entries) are generated. It can be understood that the three SGL Data Block descriptors can express all the data positions of the data to be transmitted.

[0065] Optionally, the transmission transaction generator can write N SGL address entries into a queue (sgl_dscrps).

[0066] S204: Determine at least one address identifier according to N and the addresses of N address entries.

[0067] Wherein, at least one address identifier is used to identify the addresses of N address entries in the host memory.

[0068] In some alternative embodiments, when the address expression is a physical page expression and N is greater than a first value, the transmission transaction generator obtains the entry size of each address entry and the storage page size of each storage page; calculates the ratio between the storage page size and the entry size to obtain the maximum number of entries that each storage page allows to store; calculates the ratio between N and the maximum number, and performs a ceiling operation on the ratio to obtain the first number of storage pages required for N - 1 address entries; calculates the sum of the first number and N - 2 to obtain the second number L of the second half storage blocks required for N address entries; determines L second half storage blocks from multiple half storage blocks based on the first static attribute and L; determines at least one address identifier based on the starting addresses of the L second half storage blocks and the first address corresponding to the first address entry.

[0069] Wherein, N - 1 address entries are the other N - 1 address entries except the first address entry.

[0070] The L second half storage blocks are used to store N address entries. The L second half storage blocks are the remaining and unoccupied half storage blocks among multiple half storage blocks after the M first half storage blocks, and L≥N and is a positive integer.

[0071] The occupancy status of each of the L second half storage blocks is the unoccupied status.

[0072] When N is greater than the first value, at least one address identifier includes the start address and the first address.

[0073] The first value can be set according to the storage protocol between the host and the storage controller. For example, when the storage protocol is the NVMe protocol, the first value is 2.

[0074] It can be understood that when there are more than 2 PRP address entries, it is necessary to organize the other PRP address entries after the first address entry in the form of a PRP-List. Among them, the PRP-List is divided into blocks by memory pages (Memory Page). For example, in the 4KB Memory Page memory space shown in Example 1, one memory page can store 512 PRP entries with a length of 8B. When N is greater than the number of address entries that can be stored in one memory page (PRP-List Page), the remaining PRP address entries need to be stored in another memory page (PRP-List Page), and the last PRP entry in the previous PRP-List Page should be the start address of the next PRP-List Page. This makes it necessary to store not only the N PRP address entries that describe the location of all data, but also the entries that point to the PRP-List Page when the N address entries are stored in different PRP-List Pages in Host-mem. Therefore, the transmission transaction generator needs to judge how many Memory Pages are required according to the total number of PRP entries N, combined with the number of entries pointing to the PRP-List Page that may need to be inserted, select a sufficient amount of HKB from Host-mem, and generate entries pointing to the PRP-List Page.

[0075] Exemplarily, taking N address entries as 521 PRP address entries as an example, as Figure 4 shown, Figure 4Schematic diagram of the distribution of address entries in the host memory provided by the embodiment of the present application; the transmission transaction generator obtains that the entry size of each address entry is 8B and the storage page size of each storage page is 4KB; calculates the ratio between the storage page size and the entry size, and obtains the maximum number of entries that each storage page allows to store as 512; calculates the ratio between N and the maximum number, and performs a ceiling operation on the ratio, and obtains that the first number of storage pages required for N - 1 address entries is 2 (that is, it is determined that 2 PRP-List Pages are required to store 520 PRP address entries); calculates the sum of the first number and N - 2, and obtains that the second number L of the second half storage blocks required for N address entries is 521, that is, it indicates that 1 entry pointing to the PRP-List Page needs to be inserted, and there are a total of 521 PRP address entries with a size of 8B.

[0076] The transmission transaction generator searches for free HBKs in the host memory, finds HBK40~47 in the 6th row, and HBK40 and HBK48 in the 7th row, and records the indexes of HBK40~47, HBK40 and HBK48 into a queue variable (udptr_hkb_q). Optionally, the transmission transaction generator sets the bit corresponding to the indexes of HBK40~47, HBK40 and HBK48 in allocated_hkb to 1 to indicate that HBK40~47, HBK40 and HBK48 are locked.

[0077] Further, as Figure 5 shown, Figure 5 Schematic diagram of the distribution of PRP-List entries provided by the embodiment of the present application; the transmission transaction generator traverses all HBK indexes in udptr_hkb_q. When it is found that the current HBK index and the next HBK index are not within the same PRP-List Page range, it is considered that the PRP-List Page needs to be switched at this time. Then, a blank PRP address entry (blank entry) is inserted at the end of the entries that the first PRP-ListPage can carry, and the position of the PRP address entry is recorded. When traversing to the beginning of the next PRP-List Page, the previously inserted blank PRP entry is assigned a value, and the assigned content is the starting address of the current new PRP-List Page.

[0078] Optionally, when the address expression is the physical page expression and N is less than or equal to the first value, the transmission transaction generator determines at least one address identifier based on the address corresponding to each address entry in the N address entries. At this time, at least one address identifier includes the address corresponding to each address entry in the N address entries.

[0079] In some alternative embodiments, when the address expression mode is the scattered-gathered list expression mode and N is greater than the second value, the transmission transaction generator determines the first storage segment among multiple half storage blocks based on the first static attribute; if the first storage segment can store N address entries, the starting address corresponding to the first storage segment is determined as at least one address identifier; if the first storage segment cannot store N address entries, the second storage segment is determined among multiple half storage blocks based on the first static attribute; if the second storage segment can store N address entries and the starting address corresponding to the first storage segment, the starting address corresponding to the second storage segment is inserted into the last address entry of the first storage segment, and the starting address corresponding to the first storage segment is determined as at least one address identifier; if the second storage segment cannot store N address entries, the starting address corresponding to the first storage segment is determined as at least one address identifier, and multiple storage segments are determined among multiple half storage blocks based on the first static attribute until the multiple storage segments can store N address entries and the starting address of the subsequent storage segment is stored in the previous storage segment.

[0080] The second value can be set according to the storage protocol between the host and the storage controller. For example, when the storage protocol is the NVMe protocol, the second value is 1.

[0081] It can be understood that when there are more than 1 SGL Data Block descriptors, N SGL Data Block descriptors need to be organized in the form of SGL segments (also known as storage segments). An SGL segment is a continuous storage space. When the first SGL segment is not sufficient to hold N SGL Data Block descriptors, the second SGL segment needs to be determined in the next continuous space, and the last SGL address entry of the previous SGL segment should indicate the SGL segment descriptor or the last segment descriptor of the next SGL segment. This requires not only storing N SGL Data Block descriptors that describe all data positions, but also storing the SGL segment descriptors that point to multiple SGL segments when N SGL Data Block descriptors are stored in different storage segments in Host-mem.

[0082] Among them, the SGL segment descriptor includes the size of each storage segment and the starting address of multiple SGL Data Block descriptors included in the storage segment.

[0083] In one example, when the address expression is in the form of a scattered aggregation list expression and N is greater than the second value, the transmission transaction generator obtains the entry size of each address entry; calculates the product of N and the entry size of each address entry to obtain the amount of memory space required for N address entries; calculates the ratio between the amount of memory space and the size of each half storage block, adds 1 to the ratio and rounds it up to obtain the number of half storage blocks required for N address entries. Based on the number of half storage blocks required for N address entries, the number of storage segments required for N address entries is determined.

[0084] Exemplarily, taking 64 SGL Data Block descriptors as N address entries and each SGL Data Block descriptor being 16B as an example, the transmission transaction generator calculates the product of N and the entry size of each address entry to obtain the amount of memory space required for N address entries (16 * 64 = 1024B); calculates the ratio between the amount of memory space and the size of each half storage block (1024B / 512B = 2), adds 1 to the ratio and rounds it up to obtain the number of half storage blocks required for N address entries as 3, that is, 3 HKB storages are required. Therefore, 1 SGL segment descriptor and 1 SGL end segment descriptor need to be inserted, with a total of 66 SGL entries of 16B size. As Figure 4 shown, the transmission transaction generator searches for free HBKs in the host memory, finds HKB34, HKB37, and HKB40, and records the indexes of HKB34, HKB37, and HKB40 into a queue variable (udptr_hkb_q). Optionally, the transmission transaction generator sets the bit positions corresponding to the indexes of HKB34, HKB37, and HKB40 in allocated_hkb to 1 to indicate that HKB34, HKB37, and HKB40 are locked.

[0085] Furthermore, as Figure 6 shown, Figure 6 is a schematic diagram of SGL entry distribution provided by an embodiment of the present application; the transmission transaction generator traverses all HKB indexes in udptr_hkb_q. When it is found that the current HKB index is not continuous with the next HKB index, it is considered that an SGL segment needs to be switched at this time. Then, a blank SGL segment descriptor (i.e., a blank entry) is inserted at the end of the address entries that can be carried by the first SGL segment, and the position of the SGL segment descriptor is recorded. When traversing to the HKB at the beginning of the next SGL segment, the address (i.e., the start address) part included in the previously inserted blank SGL segment descriptor is assigned a value. When traversing to the HKB at the beginning of the second SGL segment judged or the last HKB, the length (i.e., the size of each storage segment) part of the previously inserted blank SGL segment descriptor is assigned a value.

[0086] In some alternative embodiments, when the address expression is the scattered-gathered list expression and N is less than or equal to the second value, the transmission transaction generator determines at least one address identifier based on the address corresponding to each address entry among the N address entries. At this time, the at least one address identifier includes the address corresponding to each address entry among the N address entries.

[0087] Optionally, the transmission transaction generator uses the static attribute allocated_hkb as the storage unit lock. In addition to modifying the value of the lock when allocating the host memory space for the data to be transmitted and the corresponding address entries, the lock information can also be independently modified by the user to achieve customized data distribution. For example, in a continuous available HKB0 to HKB15, taking the N address entries with a size of 3KB as an example, if directly allocating a range for the N address entries in HKB0 to 15, only one SGL Data Block descriptor with an address of 0x0 and a length of 3KB, containing HKB0 to 5, will be obtained. However, if more address entries are to be used, before allocation, the user can modify allocated_hkb to lock HKB2 and HKB5, and finally the allocated HKBs will be HKB0, HKB1, HKB3, HKB4, HKB6, HKB7, that is, 3 SGL Data Block descriptors can be generated. Similarly, taking N address entries as 40 SGL Data Block descriptors as an example, if directly allocating a range for the N address entries in HKB0 to 15, HKB0 and HKB1 will be allocated, and finally an SGL segment with a starting address of 0x0 and a length of 40 SGL Data Block descriptors will be obtained. However, if more SGL segments are to be used, before allocation, the user can actively modify allocated_hkb to lock HKB1, and finally HKB0 and HKB2 will be allocated, forming an SGL segment containing 31 SGL Data Block descriptors and an SGL end segment containing 9 SGL Data Block descriptors.

[0088] It can be understood that when the number of PRP entries is more than 2 or the number of SGL entries (SGL Data Block descriptors) is more than 1, since the simulation stimulus (IO command of the NVMe protocol) cannot accommodate more address entries, therefore, each entry needs to be placed in the host memory, and only the starting position of these entries in the host memory (i.e., at least one address identifier) is transmitted in the simulation stimulus.

[0089] S205: Generate a simulation stimulus containing at least one address identifier and send the simulation stimulus to the storage controller.

[0090] Among them, the simulation stimulus is used to test the transmission function of the storage controller for the data to be transmitted.

[0091] In one example, after the transmission transaction generator determines the required half storage blocks for the data to be transmitted and the corresponding address entries in the host memory, it backdoors the data to be transmitted and the corresponding address entries into the host memory in sequence according to the recorded HKB indexes. Among them, the backdoor writing method is implemented through the deposit system task of the SystemVerilog language.

[0092] In one example, the transmission transaction generator generates a simulation stimulus containing at least one address identifier based on at least one address identifier and an address expression, and sends the simulation stimulus to the storage controller so that the storage controller transmits the data to be transmitted based on at least one address identifier.

[0093] It can be understood that after receiving the simulation stimulus, the storage controller transfers the data to be transmitted from the host memory to the controller memory based on at least one address identifier and an address expression. If the storage controller can successfully transfer the data to be transmitted from the host memory to the controller memory, it indicates that the transmission function of the storage controller is normal.

[0094] Optionally, after the first transmission transaction is completed, the half storage blocks occupied by the first transmission transaction are released, and the bit positions corresponding to the half storage blocks occupied by the first transmission transaction are updated.

[0095] It can be understood that after the first transmission transaction is completed, the HKB occupied and locked by the first transmission transaction can be released through the udata_hkb_q and udptr_hkb_q queues recording the HKB indexes occupied by the first transmission transaction. When releasing the HKB occupied by the first transmission transaction, only need to traverse each index value in these two queues and reset the corresponding bit position in the attribute allocated_hkb to 0 to unlock.

[0096] Based on Figure 2 For the method shown, the transmission transaction generator obtains the first transmission transaction, determines M first half storage blocks among multiple half storage blocks according to the occupancy status and address expression of each half storage block; generates N address entries according to the M first half storage blocks; determines at least one address identifier according to N and the addresses of the N address entries; generates a simulation stimulus containing at least one address identifier, and sends the simulation stimulus to the storage controller.

[0097] Since the host memory can be divided into multiple semi-storage blocks, the host memory space can be allocated for the required transfer transactions of the user. According to the distribution range of these memory spaces, the data to be stored can be stored and multiple address entries can be generated according to the space occupancy status and the selected address expression method. Furthermore, based on multiple address entries, the simulation stimuli corresponding to data transfer in a discontinuous scenario can be generated, improving the accuracy of testing the transfer function of the storage controller. In addition, this application saves the time for allocating the address range corresponding to the semi-storage block for the data to be transferred, groups and spatially plans the address entries according to different address expression methods, controls the distribution of the data to be transferred and the generation quantity and distribution of the corresponding address entries, and improves the flexibility and richness of the simulation stimuli.

[0098] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0099] An embodiment of this application also provides a device for generating simulation stimuli, as Figure 7 shown, Figure 7 is a structural block diagram of a device for generating simulation stimuli provided by an embodiment of this application; the device includes: an acquisition module 701, configured to acquire a first transfer transaction, where the first transfer transaction is used to simulate the host storing the data to be transferred in the host memory, the first transfer transaction carries an address expression method, and the address expression method is used to indicate the storage distribution method of the data to be transferred in the host memory, and the host memory is divided into multiple semi-storage blocks.

[0100] A processing module 702, configured to determine M first semi-storage blocks in the multiple semi-storage blocks according to the occupancy status of each semi-storage block and the address expression method, where the M first semi-storage blocks are used to store the data to be transferred, and the distribution method of the M first semi-storage blocks matches the address expression method.

[0101] The processing module 702 is configured to generate N address entries according to the M first semi-storage blocks, where the N address entries bind the addresses of the M first semi-storage blocks, N≤M, and both N and M are positive integers.

[0102] The processing module 702 is configured to determine at least one address identifier according to N and the addresses of the N address entries, where the at least one address identifier is used to identify the addresses of the N address entries in the host memory.

[0103] The processing module 702 is configured to generate a simulation stimulus including at least one address identifier, and send the simulation stimulus to the storage controller, where the simulation stimulus is used to test the transfer function of the storage controller for the data to be transferred.

[0104] In some alternative embodiments, the first transmission transaction further carries the data length of the data to be transmitted; the processing module 702 is specifically configured to obtain the static attributes of multiple bits corresponding to the host memory and the size of each half storage block, where the static attributes include multiple bits, and each bit is used to indicate the occupancy status of each half storage block; calculate the sum of the data length and the size of each half storage block to obtain the total number M of half storage blocks required for the data to be transmitted; based on the address expression, the static attributes, and the total number M, determine M first half storage blocks among the multiple half storage blocks, and the occupancy status of each first half storage block among the M first half storage blocks is the unoccupied status.

[0105] In some alternative embodiments, after determining M first half storage blocks among the multiple half storage blocks, the processing module 702 is further configured to find M bits corresponding to the M first half storage blocks in the static attributes; update each of the M bits in the static attributes to a preset value to obtain the first static attribute, where the preset value is used to indicate that the occupancy status of the half storage block corresponding to each bit is the occupied status.

[0106] In some alternative embodiments, the processing module 702 is configured to, when the address expression is the physical page expression, based on the static attributes and the total number M, determine M first half storage blocks that match the physical page expression among the multiple half storage blocks, and the M first half storage blocks are distributed on N storage pages.

[0107] In some alternative embodiments, the processing module 702 is further configured to, when the address expression is the scatter-gather list expression, based on the static attributes and the total number M, determine M first half storage blocks that match the scatter-gather list expression among the multiple half storage blocks, and the M first half storage blocks correspond to N storage segments.

[0108] In some alternative embodiments, the processing module 702 is further configured to, when the address expression is the physical page expression, generate N address entries based on the start addresses of the first first half storage blocks distributed on each of the N storage pages corresponding to the M first half storage blocks.

[0109] In some alternative embodiments, the processing module 702 is further configured to, when the address expression is the scatter-gather list expression, generate N address entries based on the start addresses of the first first half storage blocks in each of the N storage segments corresponding to the M first half storage blocks and the data lengths of at least one first half storage block included in each storage segment.

[0110] In some alternative embodiments, the processing module 702 is further configured to, when the address representation is a physical page representation and N is greater than a first value, obtain the entry size of each address entry and the storage page size of each storage page. Calculate the ratio between the storage page size and the entry size to obtain the maximum number of storage entries allowed for each storage page; calculate the ratio between N and the maximum number, and perform a ceiling operation on the ratio to obtain the first number of storage pages required for N - 1 address entries, where the N - 1 address entries are the other N - 1 address entries except the first address entry; calculate the sum of the first number and N - 2 to obtain the second number L of second half - storage blocks required for N address entries. The L second half - storage blocks are used to store N address entries, and the L second half - storage blocks are the remaining and unoccupied half - storage blocks among the multiple half - storage blocks after M first half - storage blocks, where L≥N and L is a positive integer; based on the first static attribute and L, determine L second half - storage blocks among the multiple half - storage blocks, and the occupancy status of each of the L second half - storage blocks is unoccupied; based on the start address corresponding to the L second half - storage blocks and the first address corresponding to the first address entry, determine at least one address identifier, where the at least one address identifier includes the start address and the first address.

[0111] In some alternative embodiments, the processing module 702 is further configured to, when the address representation is a physical page representation and N is less than or equal to the first value, determine at least one address identifier based on the address corresponding to each address entry among the N address entries, where the at least one address identifier includes the address corresponding to each address entry among the N address entries.

[0112] In some alternative embodiments, the processing module 702 is further configured to, when the address representation is a scatter - gather list representation and N is greater than a second value, determine a first storage segment among the multiple half - storage blocks based on the first static attribute; if the first storage segment can store N address entries, determine the start address corresponding to the first storage segment as at least one address identifier; if the first storage segment cannot store N address entries, determine a second storage segment among the multiple half - storage blocks based on the first static attribute; if the second storage segment can store N address entries and the start address corresponding to the first storage segment, then insert the start address corresponding to the second storage segment into the last address entry of the first storage segment, and determine the start address corresponding to the first storage segment as at least one address identifier; if the second storage segment cannot store N address entries, determine the start address corresponding to the first storage segment as at least one address identifier, and determine multiple storage segments among the multiple half - storage blocks based on the first static attribute until the multiple storage segments can store N address entries and the start address of the subsequent storage segment is stored in the previous storage segment.

[0113] In some alternative embodiments, the processing module 702 is further configured to, when the address expression is a scatter-gather list expression and N is less than or equal to a second value, determine at least one address identifier based on the address corresponding to each address entry among the N address entries, where the at least one address identifier includes the address corresponding to each address entry among the N address entries.

[0114] In some alternative embodiments, the processing module 702 is further configured to, after the execution of the first transmission transaction is completed, release the half storage block occupied by the first transmission transaction and update the bit corresponding to the half storage block occupied by the first transmission transaction.

[0115] For the description of the features in the corresponding embodiments of the simulation stimulus generation device, reference may be made to the relevant description in the corresponding embodiments of the simulation stimulus generation method, which will not be elaborated here one by one.

[0116] Embodiments of the present application further provide an electronic device, such as Figure 8 shown Figure 8 is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application. The electronic device may be Figure 1 the transmission transaction generator 101 shown; the electronic device includes a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above-described embodiments of the simulation stimulus generation method.

[0117] Embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the simulation stimulus generation method when running.

[0118] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc, and other various media that can store computer programs.

[0119] Embodiments of the present application further provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the simulation stimulus generation method are implemented.

[0120] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the simulation stimulus generation method are implemented.

[0121] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0122] The above has introduced in detail a method, apparatus, electronic device, and storage medium for generating a simulation excitation provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating a simulation stimulus, characterized in that: The method comprises: Acquire a first transmission transaction, where the first transmission transaction is used to simulate a host storing data to be transmitted in a host memory, where the first transmission transaction carries an address expression mode, where the address expression mode is used to indicate a storage distribution mode of the data to be transmitted in the host memory, where the host memory is divided into a plurality of half storage blocks; According to the occupation state of each half storage block and the address expression mode, determining M first half storage blocks from the multiple half storage blocks, the M first half storage blocks are used to store the data to be transmitted, and the distribution mode of the M first half storage blocks matches the address expression mode; Generate N address entries according to the M first half storage blocks, wherein the N address entries are bound to addresses of the M first half storage blocks, where N≤M, and both N and M are positive integers; Determine at least one address identifier according to N and the addresses of the N address entries, wherein the at least one address identifier is used to identify the addresses of the N address entries in the host memory; A simulation stimulus including the at least one address identifier is generated, and the simulation stimulus is sent to a storage controller, wherein the simulation stimulus is used to test a transmission function of the storage controller for data to be transmitted.

2. The method according to claim 1, characterized in that The first transmission transaction also carries the data length of the data to be transmitted; and determining M first half storage blocks from the plurality of half storage blocks according to the occupation state of each half storage block and the address expression method, comprises: Obtaining a static attribute of multiple bits corresponding to the host memory and the size of each half storage block, wherein the static attribute includes multiple bits, each bit is used to indicate the occupation status of each half storage block; Calculating the sum of the data length and the size of each half storage block to obtain the total number M of half storage blocks required for the data to be transmitted; Based on the address expression mode, the static attribute and the total number M, the M first half storage blocks are determined from the multiple half storage blocks, and the occupied state of each first half storage block in the M first half storage blocks is an unoccupied state.

3. The method according to claim 2, characterized in that After determining M first half storage blocks from the plurality of half storage blocks, the method further includes: Searching the static attributes for M bits corresponding to the M first half storage blocks; Each of the M bits in the static attribute is updated to be set to a preset value to obtain a first static attribute, wherein the preset value is used to indicate that the occupation state of the half storage block corresponding to each bit is an occupied state.

4. The method according to claim 3, characterized in that The determining the M first half storage blocks from the plurality of half storage blocks based on the address expression mode, the static attribute and the total number M comprises: When the address expression is a physical page expression, based on the static attribute and the total number M, the M first half storage blocks matching the physical page expression are determined from the multiple half storage blocks, and the M first half storage blocks are distributed on N storage pages.

5. The method according to claim 3, characterized in that: The determining the M first half storage blocks from the plurality of half storage blocks based on the address expression mode, the static attribute and the total number M comprises: When the address expression is a scatter-gather list expression, based on the static attribute and the total number M, the M first half storage blocks matching the scatter-gather list expression are determined from the multiple half storage blocks, and the M first half storage blocks correspond to N storage segments.

6. The method according to claim 4, characterized in that The step of generating N address entries according to the M first half storage blocks comprises: When the address expression is the physical page expression, the N address entries are generated based on the first address corresponding to the first first half storage block distributed on each of the N storage pages corresponding to the M first half storage blocks.

7. The method according to claim 5, characterized in that The step of generating N address entries according to the M first half storage blocks comprises: When the address expression is the scatter-gather list expression, the N address entries are generated based on the first address corresponding to the first first half storage block in each storage segment of the N storage segments corresponding to the M first half storage blocks, and the data length of at least one first half storage block included in each storage segment.

8. The method according to claim 6, characterized in that The determining at least one address identifier according to the N and the addresses of the N address entries includes: When the address expression is the physical page expression and N is greater than a first value, obtaining an entry size of each address entry and a storage page size of each storage page; Calculating a ratio between the storage page size and the entry size to obtain a maximum number of entries allowed to be stored in each storage page; Calculating a ratio between the N and the maximum number, and performing an upward rounding operation on the ratio to obtain a first number of storage pages required for the N-1 address entries, where the N-1 address entries are other N-1 address entries except the first address entry; Calculate the sum of the first number and N-2 to obtain a second number L of second half storage blocks required for the N address entries, the L second half storage blocks are used to store the N address entries, the L second half storage blocks are the remaining half storage blocks in the plurality of half storage blocks except the M first half storage blocks and are in the unoccupied state, and L ≥ N is a positive integer; Based on the first static attribute and L, determining the L second half storage blocks from the plurality of half storage blocks, the occupied state of each second half storage block in the L second half storage blocks being the unoccupied state; Based on the first addresses corresponding to the L second half storage blocks and the first address corresponding to the first address entry, the at least one address identifier is determined, and the at least one address identifier includes the first address and the first address.

9. The method according to claim 8, characterized in that The determining at least one address identifier according to the N and the addresses of the N address entries includes: When the address expression is the physical page expression and N is less than or equal to the first value, the at least one address identifier is determined based on the address corresponding to each address entry in the N address entries, and the at least one address identifier includes the address corresponding to each address entry in the N address entries.

10. The method according to claim 7, characterized in that The determining at least one address identifier according to the N and the addresses of the N address entries includes: When the address expression is the scatter-gather list expression and N is greater than a second value, determining a first storage segment in the plurality of half storage blocks based on the first static attribute; If the first storage segment can store the N address entries, determining the first address corresponding to the first storage segment as the at least one address identifier; If the first storage segment cannot store the N address entries, determining a second storage segment in the plurality of half storage blocks based on the first static attribute; If the second storage segment can store the N address entries and the first address corresponding to the first storage segment, insert the first address corresponding to the second storage segment into the last address entry of the first storage segment, and determine the first address corresponding to the first storage segment as the at least one address identifier; If the second storage segment cannot store the N address entries, the starting address corresponding to the first storage segment is determined as the at least one address identifier, and based on the first static attribute, multiple storage segments are determined in the multiple half storage blocks until the multiple storage segments can store the N address entries and the starting address of the next storage segment is stored in the previous storage segment.

11. The method according to claim 10, characterized in that The determining at least one address identifier according to the N and the addresses of the N address entries includes: When the address expression is the scatter-gather list expression and N is less than or equal to the second value, the at least one address identifier is determined based on the address corresponding to each address entry in the N address entries, and the at least one address identifier includes the address corresponding to each address entry in the N address entries.

12. The method according to claim 1, characterized in that The method further comprises: After the first transmission transaction is executed, the half storage block occupied by the first transmission transaction is released, and the bit corresponding to the half storage block occupied by the first transmission transaction is updated.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for generating simulation stimuli as claimed in any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for generating simulation stimuli according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for generating simulation stimuli according to any one of claims 1 to 12 are implemented.

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