Clock gating method, system and device and storage medium

Abstract

The invention discloses a clock gating method, system and device and a storage medium. The method comprises the following steps: acquiring an inter-module clock dependency relationship, an inter-module time sequence relationship and an inter-module data dependency relationship in the system; based on the time sequence relation between the modules, the data dependence relation between the modules and a topological sorting method, a time sequence relation graph between the modules in the system is constructed; acquiring real-time load data of each module in the system, performing dynamic simulation by using the real-time load data and the clock dependency relationship between the modules, and constructing a clock domain relational graph between the modules in the system based on a dynamic simulation result; and dividing modules in the system into a plurality of clock domains based on the clock domain relation graph and the time sequence relation graph, and adjusting a clock control mode of the clock domains based on module load data in the clock domains. The embodiment of the invention can improve the management precision of the clock module in the system, reduce the power consumption of the system and improve the resource utilization efficiency of the system, and can be widely applied to the technical field of clock gating.

Description

Technical Field

[0001] The present invention relates to clock gating technology, and in particular, to a clock gating method, system, device, and storage medium. Background Art

[0002] The distribution network chip in the power system is a key component for the intelligence and automation of the distribution network, responsible for data acquisition, transmission, and processing, and supporting the stable operation of the distribution system. And the clock gating technology, as a low-power design strategy, plays an important role in the design of the distribution network chip.

[0003] The clock gating technology dynamically controls the opening and closing of the clock signal, isolates the clock signal for those circuit parts that do not require clock driving at the current moment, thereby effectively reducing unnecessary power consumption. In the distribution network chip, the clock gating technology can be applied to each functional module, such as the data acquisition module, communication module, processing module, etc. When a certain module is in an idle state or does not require real-time data processing, the clock gating technology can turn off the clock signal of the module to avoid waste of power consumption. And when the module needs to work, the clock gating technology can quickly turn on the clock signal to ensure that the module can operate normally and efficiently.

[0004] However, most of the existing clock gating strategies use static or coarse-grained clock management methods, which cannot accurately, quickly, and flexibly control the load and state of the clock, resulting in low management accuracy of the clock module in the system, high system power consumption, and low system resource utilization efficiency. Summary of the Invention

[0005] In view of this, to solve one of the above problems, an object of the embodiments of the present invention is to provide a clock gating method, system, device, and storage medium, which can improve the management accuracy of the clock module in the system, reduce the system power consumption, and improve the system resource utilization efficiency.

[0006] In a first aspect, an embodiment of the present invention provides a clock gating method, including:

[0007] Performing static analysis based on the circuit netlist of the system to obtain the clock dependency relationship, timing relationship, and data dependency relationship between modules in the system;

[0008] Based on the timing relationship between modules, the data dependency relationship between modules, and the topological sorting method, constructing a timing relationship graph between each module in the system;

[0009] Obtaining the real-time load data of each module in the system, performing dynamic simulation using the real-time load data and the clock dependency relationship between modules, and constructing a clock domain relationship graph between each module in the system based on the results of the dynamic simulation;

[0010] Based on the clock domain relationship diagram and the timing relationship diagram, divide the modules in the system into several clock domains;

[0011] Obtain the module load data in several clock domains, and adjust the clock control modes of several clock domains based on the module load data.

[0012] Specifically, constructing the timing relationship diagram between each module in the system based on the inter-module timing relationship, the inter-module data dependency relationship, and the topological sorting method includes

[0013] Construct a directed acyclic graph according to the topological sorting method and the inter-module data dependency relationship;

[0014] Based on the inter-module timing relationship and the directed acyclic graph, construct the timing relationship diagram between each module in the system.

[0015] Specifically, the dynamic simulation using the real-time load data and the inter-module clock dependency relationship includes:

[0016] Perform calculations based on the real-time load data to obtain the activity frequency and load fluctuation of each module in the system;

[0017] Generate a dynamic simulation model based on the inter-module dependency relationship;

[0018] Input the activity frequency and load fluctuation of each module into the dynamic simulation model and perform dynamic simulation to obtain the results of the dynamic simulation.

[0019] Specifically, the results of the dynamic simulation include the clock requirements of each module under different load conditions; constructing the clock domain relationship diagram between each module in the system based on the results of the dynamic simulation includes:

[0020] Based on the clock requirements of each module under different load conditions and the load fluctuation, use the minimum cut algorithm to group the modules in the system to obtain several first module groups that meet the first preset conditions for clock requirements and load fluctuation;

[0021] Based on several first module groups, constitute the clock domain relationship diagram between each module in the system.

[0022] Specifically, dividing the modules in the system into several clock domains based on the clock domain relationship diagram and the timing relationship diagram includes:

[0023] Based on the timing relationship diagram, determine the clock signal sharing situation between each module in the system;

[0024] Based on the sharing situation of clock signals between each of the said modules, obtain several second module groups whose timing conflict situation satisfies the second preset condition;

[0025] Based on several of the said second module groups, divide the modules within the system into several clock domains.

[0026] Specifically, the construction method of the said clock domain relationship diagram is the same as that of the timing relationship diagram; the timing relationship diagram is constructed by the following method:

[0027] Represent the module, the clock characteristics or timing characteristics of the module as nodes;

[0028] Represent the timing dependency or control signal transmission between modules as edges;

[0029] Represent the delay or timing requirement of signal transmission between modules as the weight of the said edge.

[0030] Specifically, the said obtaining the module load data within several of the said clock domains and adjusting the clock control modes of several of the said clock domains based on the module load data includes:

[0031] Obtain the real-time load data and historical load data of each module within several of the said clock domains;

[0032] Perform load prediction based on the real-time load data and historical load data of each of the said modules;

[0033] Adjust the clock control modes of several of the said clock domains based on the real-time load data of each of the said modules and the result of the said load prediction.

[0034] On the other hand, an embodiment of the present invention also provides a clock gating system, including:

[0035] A first module, configured to perform static analysis based on the circuit netlist of the system, and obtain the clock dependency relationship, timing relationship, and data dependency relationship between the modules within the system;

[0036] A second module, based on the said timing relationship between modules, the said data dependency relationship between modules, and the topological sorting method, constructs a timing relationship diagram between each of the said modules within the system;

[0037] A third module, obtains the real-time load data of each module within the system, performs dynamic simulation using the real-time load data and the said clock dependency relationship between modules, and constructs a clock domain relationship diagram between each of the said modules within the system based on the result of the said dynamic simulation;

[0038] The fourth module divides the modules in the system into several clock domains based on the clock domain relationship diagram and the timing relationship diagram;

[0039] The fifth module obtains the module load data in several clock domains and adjusts the clock control modes of several clock domains based on the module load data.

[0040] On the other hand, an embodiment of the present invention further provides a clock gating device, including:

[0041] At least one processor;

[0042] At least one memory for storing at least one program;

[0043] When the at least one program is executed by the at least one processor, the at least one processor implements the method as described above.

[0044] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored, and the program executable by the processor is used to execute the method as described above when executed by the processor.

[0045] In summary, the beneficial effects that can be achieved by implementing the embodiments of the present invention are as follows:

[0046] The embodiments of the present invention provide a clock gating method, system, device and storage medium. The method constructs a timing relationship diagram and a clock domain relationship diagram of the modules in the system by performing static analysis on the system, combining the results of the static analysis and the real-time load data of the modules in the system, divides the system into several clock domains based on the constructed relationship diagrams, and finally adjusts the clock control mode of each clock domain according to the module load data in the clock domain, which can improve the management accuracy of the clock modules in the system, reduce the system power consumption, and improve the system resource utilization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic flowchart of the steps of a clock gating method provided by an embodiment of the present invention;

[0048] Figure 2 is a schematic flowchart of the steps of adjusting the clock control mode of a clock domain provided by an embodiment of the present invention;

[0049] Figure 3 is a structural block diagram of a clock gating system provided by an embodiment of the present invention;

[0050] Figure 4 is a structural block diagram of a clock gating device provided by an embodiment of the present invention;

[0051] Figure 5is a structural block diagram of a fine-grained clock gating unit provided by an embodiment of the present invention;

[0052] Figure 6 It is a structural block diagram of an integrated adaptive control unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0054] Several terms involved in this application are explained as follows:

[0055] Clock gating technology: A low-power design strategy that, in digital integrated circuits, intelligently controls the transmission of clock signals and shuts down the clocks of circuit parts that are idle or do not need to work, thereby effectively reducing unnecessary clock flipping activities and significantly reducing dynamic power consumption.

[0056] Directed Acyclic Graph (DAG): A special graph structure consisting of vertices and edges. Each edge has a clear direction and the entire graph is acyclic, that is, there is no path that can start from a vertex and return to the vertex through a series of edges.

[0057] Topological sorting method: It is a vertex linear sorting method for directed acyclic graphs (DAGs), which makes vertex u appear before vertex v in the sorting for each directed edge (u, v) in the graph. This algorithm is widely used to solve dependency problems such as task scheduling and course scheduling. By continuously selecting vertices with in-degree 0 to add to the result sequence, a linear sequence of vertices that satisfies all dependencies is finally obtained.

[0058] Temporal relationship: A special graph structure consisting of vertices (or nodes) and directed edges. There is no path in the graph that starts from a vertex, passes through several edges and then returns to the vertex, that is, there is no cycle. DAG is widely used to represent the connection between events, tasks or concepts with a clear sequence or dependency, such as task scheduling, compilation optimization, Bayesian networks and other fields.

[0059] Clock domain relationship: In integrated circuit design, the regional division formed when different functional modules or circuit parts are controlled by different clock signals. There may be data interaction between these clock domains, and synchronization mechanisms are required to ensure the correctness and stability of data when it is transmitted across clock domains to avoid problems such as metastability.

[0060] Timing Characteristics: In clock gating technology, the timing characteristics of modules focus on the signal propagation delay of each functional module, the time from the clock edge to data validity, and the timing constraints for data interaction between modules after enabling clock gating.

[0061] Clock Dependency: It is reflected in clock gating technology that each module dynamically connects or disconnects the clock signal according to its working requirements to reduce unnecessary power consumption.

[0062] Data Dependency: In clock gating technology, the data dependency relationship between modules refers to the dependence of the data input, output, and transmission processes of different modules on the clock signal state under the control of clock gating logic, as well as the timing constraints that need to be satisfied for data interaction between modules.

[0063] Clock Requirements: It refers to the requirements of a module for the frequency, phase, duty cycle of the clock signal, and the clock enable signal, etc. under a specific working state. These requirements ensure that the module can sample, process, and transmit data under the correct timing conditions to maintain the stability and performance of the system.

[0064] Timing Requirements: It refers to a series of timing conditions that a module needs to satisfy to ensure correct data transmission and processing under the action of clock gating, including parameters such as the frequency, phase, and duty cycle of the clock signal, as well as the timing constraints of the data sampling window and data interaction between modules.

[0065] Fine-grained Clock Gating Technology: A fine control method used in digital circuit design to reduce power consumption. It achieves independent clock control for individual flip-flops or small logic units, enabling the activation of the corresponding part of the clock signal only when needed, thus significantly reducing unnecessary clock switching activities and further reducing dynamic power consumption.

[0066] Activity Monitoring Unit (AMU): A non-intrusive component mainly used to finely monitor and count various activities of the processor (such as the number of instruction executions, cache hits / misses, number of interrupts, branch prediction errors, etc.) through a set of 64-bit counters.

[0067] Minimum Cut Algorithm: Used to solve the minimum cut problem. The minimum cut problem can be described as: in a weighted directed graph or undirected graph, find a "cutting" method such that the sum of the weights of the edges across the cutting line is the smallest among all possible cutting methods. This smallest sum of weights is called the minimum cut.

[0068] Fine-Grained Clock Gating Unit (FGCGU): A power management technique that significantly reduces dynamic power consumption by independently clocking each flip-flop or smaller logic block and turning off its clock signal when not needed, while maintaining system synchronization and stability. This technique is applicable to digital system designs with strict power requirements, such as mobile devices, Internet of Things devices, etc.

[0069] RTL Level: That is, Register Transfer Level, which is a level of hardware description language (HDL) modeling used to define the abstraction level of the digital part in a design description. At the RTL level, designers construct circuits by describing data transfer and logical functions between registers. It lies between the behavioral level and the gate level, having a certain degree of abstraction while accurately reflecting the working principle of the circuit. RTL-level designs are usually carried out using HDL languages such as Verilog or VHDL.

[0070] SPICE Simulation (Simulation Program with Integrated Circuit Emphasis): A circuit simulation program widely used in the field of electronic engineering. Based on the mathematical model of the circuit and circuit analysis methods, it simulates the performance and behavior of the circuit under different conditions by solving a set of linear or nonlinear algebraic and differential equations, providing designers with accurate circuit behavior information to help them optimize and improve circuit performance.

[0071] Adaptive Control Unit (ACU): A powerful programmable controller system that mainly receives data from multiple sensors and input devices, processes it according to the set control strategy, and then outputs control signals to achieve centralized control, real-time monitoring, and multi-machine coordination of multiple devices or systems.

[0072] Clock Tree Optimization: A technique for improving the performance and reliability of digital circuit designs. It mainly optimizes the distribution and timing of clock signals by adjusting the layout and parameters of clock buffers and clock lines, ensuring that the clock signals have the same arrival time at different circuit nodes, thereby improving the working speed, stability, and energy efficiency of the circuit.

[0073] Design Compiler: An advanced digital integrated circuit synthesis tool developed by Synopsys. It can convert high-level hardware description language (HDL) code into an optimized gate-level netlist and supports various optimization algorithms, such as logic optimization, area optimization, and timing optimization, to meet specific design goals and constraints.

[0074] PrimeTime: A high-precision static timing analysis tool developed by Synopsys. It can comprehensively perform timing analysis and optimization on large-scale, synchronous digital designs, ensuring that the design can operate correctly and meet timing requirements at the specified operating frequency. PrimeTime supports multiple analysis modes, including full-chip analysis, multi-corner analysis, clock tree analysis, etc., and provides detailed timing reports and automated repair functions to help designers quickly locate and solve timing problems, improving design efficiency and quality.

[0075] ARIMA algorithm: Autoregressive Integrated Moving Average Model, a classic and widely used time series analysis and prediction method. It effectively captures trends, seasonality, and random fluctuations in time series data by combining three techniques: autoregressive (AR), differencing (I), and moving average (MA), thus enabling accurate prediction of future data.

[0076] VHDL: Very-High-Speed Integrated Circuit Hardware Description Language, a high-level language used for circuit design. It is mainly used to describe the structure, behavior, function, and interface of digital systems, and has the characteristics of powerful function, flexible design, wide support, and easy modification.

[0077] FPGA: Field-Programmable Gate Array, an advanced programmable logic device. It allows users to program and configure the device after it is deployed in the final environment, thus realizing specific logic functions.

[0078] As Figure 1 shown, an embodiment of the present invention provides a clock gating method, and the steps included therein are as follows.

[0079] S100: Perform static analysis based on the circuit netlist of the system to obtain the clock dependency relationship, timing relationship, and data dependency relationship between modules within the system.

[0080] Analyze the netlist structure of the circuit through a timing analysis tool. Based on factors such as clock period, module delay, and signal transmission delay, calculate the input-output relationship of each module, and generate timing constraint information to clarify the working priority, timing requirements, and data dependency of the module. Finally, obtain the clock dependency relationship, timing relationship, and data dependency relationship between modules within the system.

[0081] Optionally, the timing analysis tool includes PrimeTime;

[0082] S200: Based on the inter-module timing relationship, the inter-module data dependency relationship, and the topological sorting method, construct a timing relationship graph between each module within the system.

[0083] The inter-module timing relationship and the inter-module data dependency relationship obtained through detailed analysis of the circuit functional modules by static analysis, combined with the topological sorting method, are used to construct the module timing relationship graph;

[0084] Specifically, in the static analysis stage, Design Compiler is used to parse the RTL code of the circuit, analyze the timing characteristics of each module. Design Compiler will synthesize the VHDL code of the circuit, generate the netlist of the circuit, and extract the timing constraints of the modules, including the clock frequency of each module, the timing relationship between the input and output, and the information of the critical path, to obtain the inter-module timing relationship and the inter-module data dependency relationship.

[0085] In some embodiments, the timing relationship graph in step S200 can be constructed by the following method:

[0086] S210: Based on the topological sorting method and the inter-module data dependency relationship, construct a directed acyclic graph;

[0087] Through static timing analysis, Design Compiler can identify the timing bottlenecks in the circuit and calculate the timing characteristics such as the delay of each module and the signal transmission time, so as to generate a timing report. Based on the generated timing report, the topological sorting method is used for the data dependency relationship between modules to ensure the correct module execution order. Further, the topological sorting method constructs a directed acyclic graph (DAG) according to the inter-module data dependency relationship and the determined module execution order.

[0088] S220: Based on the inter-module timing relationship and the directed acyclic graph, construct a timing relationship graph between each module within the system.

[0089] Through the directed acyclic graph, the timing between modules can be determined and the execution order of each module can be clarified. Based on the directed acyclic graph generated by the inter-module timing relationship and the topological sorting method, the graph theory method is used to construct the module timing relationship graph.

[0090] S300: Obtain the real-time load data of each module within the system, perform dynamic simulation using the real-time load data and the inter-module clock dependency relationship, and construct a clock domain relationship graph between each module within the system based on the results of the dynamic simulation.

[0091] The load detection unit measures the real-time load data of each module in the system, and the dynamic calculation tool calculates the real-time load data of each module; the dynamic simulation is carried out by combining the calculation results and the clock dependence relationship between modules obtained by static analysis, and the clock domain relationship diagram between each module in the system is constructed based on the results of the dynamic simulation.

[0092] In some embodiments, the process of performing dynamic simulation using the real-time load data and the clock dependence relationship between modules in step S300 can be implemented by the following method:

[0093] S311: Calculate based on the real-time load data to obtain the activity frequency and load fluctuation of each module in the system;

[0094] The load detection unit measures the real-time load data of each module in the system, and the dynamic calculation tool dynamically generates the activity frequency and load fluctuation of each module based on the actual signal activity and module calculation load.

[0095] Optionally, the load detection unit can use the activity monitoring unit AMU;

[0096] S312: Generate a dynamic simulation model based on the clock dependence relationship between modules;

[0097] Through the clock dependence relationship between modules, the connection status and work requirement data between modules during system task execution are obtained, and further based on the obtained data, a dynamic simulation model is generated.

[0098] S313: Input the activity frequency and load fluctuation of each module into the dynamic simulation model and perform dynamic simulation to obtain the results of the dynamic simulation.

[0099] The real-time load detection unit inputs the calculated activity frequency and load fluctuation of each module into the dynamic simulation model and performs dynamic simulation to obtain the results of the dynamic simulation. The results of the dynamic simulation include the clock requirements of each module in the system under different load conditions;

[0100] In some embodiments, the process of constructing the clock domain relationship diagram between each module in the system based on the results of the dynamic simulation in step S300 can be implemented by the following method:

[0101] S321: Based on the clock requirements and load fluctuation of each module under different load conditions, use the minimum cut algorithm to group the modules in the system to obtain several first module groups that meet the first preset conditions for both clock requirements and load fluctuation;

[0102] The minimum cut algorithm is used to group the modules, and multiple module groups are divided. The modules within each module group have similar timing requirements and load fluctuations.

[0103] Specifically, when grouping and partitioning modules, minimizing signal transmission across clock domains and clock synchronization issues can effectively reduce the clock latency and power consumption of the modules. Secondly, the modules within the divided module groups have similar timing requirements and load fluctuations and can share the same clock signal.

[0104] S322: Based on several first module groups, construct a clock domain relationship diagram for each module within the system.

[0105] Based on the grouping situation of several first module groups within the system, construct a clock domain relationship diagram for each module within the system through graph theory methods.

[0106] Specifically, the construction method of the clock domain relationship diagram is the same as that of the timing relationship diagram; both are constructed using graph theory methods; the graph theory method includes the following specific steps:

[0107] Represent the module, the clock characteristics or timing characteristics of the module as nodes;

[0108] Represent the timing dependencies or control signal transmissions between modules as edges;

[0109] Represent the delay or timing requirements of the signal transmissions between modules as the weights of the edges.

[0110] S400: Based on the clock domain relationship diagram and the timing relationship diagram, partition the modules within the system into several clock domains.

[0111] Through the timing relationship diagram, the sharing situation of the modules within the system can be determined. The several first module groups divided by the clock domain are further subdivided to obtain several second module groups whose timing conflict situations meet the preset conditions.

[0112] According to the grouping situation of the several second module groups, partition the modules within the system into several clock domains.

[0113] S500: Obtain the module load data within several clock domains and adjust the clock control methods of the several clock domains based on the module load data.

[0114] Obtain the module load data within the divided several clock domains and perform calculations. Use the calculation results as the clock gating reference for the several clock domains, start or stop the module clocks within the clock domains or set the clock schedule, and adjust the clock control methods of the several clock domains.

[0115] In some embodiments, as Figure 2 shown, the process of adjusting the clock control methods of the several clock domains based on the module load data in S500 can be implemented by the following method:

[0116] S510: Obtain the real-time load data and historical load data of each module within a number of clock domains;

[0117] Monitor the real-time load data and historical load data of each module within the clock domain through the Activity Monitoring Unit (AMU), which serves as a reference for subsequent adjustment of the clock control method of the clock domain.

[0118] S520: Perform load prediction based on the real-time load data and historical load data of each module;

[0119] Integrate an algorithm on the Activity Monitoring Unit (AMU) so that it can process based on real-time data and historical data to predict future loads;

[0120] Optionally, the integrated algorithm can select the ARIMA algorithm.

[0121] Specifically, based on the real-time load monitoring data, store these data in the form of a time series to form the input of the prediction model. The algorithm is embedded in the AMU through a hardware acceleration unit and the autoregressive (AR), differencing (I), and moving average (MA) parts are implemented on the FPGA using the VHDL language. In the FPGA, the calculation process of ARIMA includes differencing the historical load data to eliminate the trend component in the data, and predicting the load changes in the next few cycles through the autoregressive model and the moving average model.

[0122] S530: Adjust the clock control methods of a number of clock domains based on the real-time load data of each module and the results of the load prediction.

[0123] Execute corresponding judgments based on the real-time load data and the results of the load prediction, and adjust the clock control method of the clock domain by starting and stopping the clock signal in real time, dynamically adjusting the clock, and adjusting the clock start / stop plan.

[0124] Specifically, based on the comparison between the prediction result and the real-time load, the AMU can turn off the clocks of inactive modules when the load is low, thereby reducing power consumption; when the predicted load is high, the AMU resumes the clock in advance to ensure computing performance. Secondly, utilize the dynamic clock gating decision mechanism based on load prediction to predict the working state in the next few cycles through real-time load changes, thereby making clock control adjustments in advance, further optimizing the timing of clock start / stop, and reducing the delay and power consumption caused by clock switching.

[0125] Implementing the embodiments of the present invention includes the following beneficial effects:

[0126] The clock gating method provided by the embodiments of the present invention constructs a timing relationship diagram and a clock domain relationship diagram through static analysis and dynamic simulation, divides the modules in the system into several clock domains, and enables the clock control of the modules within each clock domain to be independent, thereby improving the efficiency and accuracy of clock management. Secondly, the functional modules are divided into multiple clock domains, and the clock state is dynamically adjusted according to the task characteristics, greatly improving the flexibility of power consumption control. It not only optimizes the delay of clock domain switching, but also reduces power consumption and improves resource utilization efficiency while ensuring the stability of the system.

[0127] As Figure 3 shown, the embodiments of the present invention also provide a clock gating system, including:

[0128] The first module is used to perform static analysis based on the circuit netlist of the system to obtain the clock dependency relationship, timing relationship, and data dependency relationship between the modules in the system;

[0129] The second module constructs a timing relationship diagram between each module in the system based on the timing relationship between modules, the data dependency relationship between modules, and the topological sorting method;

[0130] The third module obtains the real-time load data of each module in the system, performs dynamic simulation using the real-time load data and the clock dependency relationship between modules, and constructs a clock domain relationship diagram between each module in the system based on the results of the dynamic simulation;

[0131] The fourth module divides the modules in the system into several clock domains based on the clock domain relationship diagram and the timing relationship diagram;

[0132] The fifth module obtains the module load data in several clock domains and adjusts the clock control modes of the several clock domains based on the module load data.

[0133] It can be seen that the content in the above method embodiments is applicable to the system embodiments of the present invention. The functions specifically implemented by the system embodiments of the present invention are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0134] As Figure 4 shown, the embodiments of the present invention also provide a clock gating device, including:

[0135] At least one processor;

[0136] At least one memory for storing at least one program;

[0137] When the at least one program is executed by the at least one processor, the at least one processor implements the steps of the clock gating method described in the above method embodiments.

[0138] Among them, the memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. The memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a remote memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0139] It can be seen that the content in the above method embodiments is applicable to the device embodiments herein. The functions specifically implemented in the device embodiments are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0140] As Figure 5 shown, the embodiment of the present invention also designs a fine-grained clock gating unit (FGCGU) to implement independent clock management for each sub-module in the chip. During operation, the chip first initializes the clock states of each sub-module. The FGCGU generates dynamic clock control decisions through static analysis and dynamic simulation, divides the clock domain according to task requirements, determines the task-specific clock domain, divides the functional modules into multiple clock domains, and dynamically adjusts the clock state according to the task characteristics and execution frequency.

[0141] Specifically, the fine-grained clock gating unit (FGCGU) includes a clock domain division module, a control logic, a clock selector, a task scheduler, and a status register, specifically as follows:

[0142] The clock domain division module is used to divide the clock domain according to task requirements and generate clock control decisions based on the sub-module clock state data;

[0143] Specifically, the clock domain division module generates dynamic clock control decisions through static analysis and dynamic simulation, divides the clock domain according to task requirements, determines the task-specific clock domain, and divides the functional modules into multiple clock domains.

[0144] The task scheduler is responsible for generating a clock control decision scheduling task according to the clock control decision;

[0145] The control logic is used to monitor and periodically check the sub-module scheduling task signal and the clock state data, and schedule the clock control and adjustment process;

[0146] The clock selector is used to respond to the clock control decision scheduling task signal and perform clock control methods such as clock switching, clock signal selection, clock domain selection, and signal routing selection;

[0147] The status register is used to record and update clock status data; the clock status data includes clock status consistency, clock frequency, clock start / stop data, clock delay, and clock cycle.

[0148] Specifically, in the fine-grained clock gating unit (FGCGU), the clock domain switching delay is optimized to within 5 ns, the update interval of the status register is 50 ns, and the power consumption of the control logic is lower than 1 μW, ensuring that the system is lightweight and efficient.

[0149] Specifically, during the process of inserting the fine-grained clock gating unit into the circuit, first, based on the activity frequency and power consumption contribution of the module, the insertion position of the clock gating unit is accurately calculated to ensure that the impact on the critical path delay is less than 5%. After the gating insertion, the clock tree layout is optimized by combining SPICE simulation. By adding buffers and adjusting the driving strength, the clock signal propagation delay is optimized to within 2 ns.

[0150] As Figure 6 shown, the embodiment of the present invention also provides an integrated adaptive control unit (ACU) to dynamically adjust the clock frequency of the system, thereby optimizing the balance between power consumption and performance.

[0151] The integrated adaptive control unit (ACU) includes a hardware design module, a real-time load monitoring module, a load prediction module, a decision-making module, a clock control module, and a clock tree optimization module, specifically:

[0152] The hardware design module is used to divide each module of the circuit into multiple clock domains according to functions and loads;

[0153] The real-time load monitoring module is used to collect load data and transmit it to the decision-making module; the load data includes real-time load data and historical load data;

[0154] The load prediction module is used to analyze the data trends of historical load data and real-time load data to predict the load fluctuations in the next period of time.

[0155] The decision-making module is used to accurately determine which modules are in a low-load state based on the real-time load data and make decisions on clock start / stop on this basis; at the same time, according to the load prediction, corresponding clock control decisions are generated before the load changes to ensure that the clock frequency is always consistent with the system requirements.

[0156] The clock control module is used to control the clock start / stop according to various decisions issued by the decision-making module;

[0157] Specifically, when the system load is low, the ACU can effectively turn off the clocks of inactive modules to avoid unnecessary energy consumption; when the system load is expected to rise, the ACU can restore the clocks of the corresponding modules in advance to ensure the timely provision of the required computing resources.

[0158] The clock tree optimization module is used to adjust the layout and parameters of clock buffers and clock lines according to the module timing relationship and module function distribution.

[0159] Specifically, to ensure the efficient transmission of the clock, the ACU is closely integrated with the clock tree design. The design of the clock tree is optimized to minimize the signal propagation delay, and techniques such as buffers are used to reduce the delay of the clock signal. The ACU will adjust the frequency and start / stop state of the clock signal according to the topology of the clock tree, combined with real-time load data, to ensure the stability and timing accuracy of the clock signal. By optimizing the clock tree and clock domain, the ACU can reduce the delay in the clock signal propagation without sacrificing performance, thereby improving the overall efficiency of the system. The ACU also ensures the timing coordination between different clock domains and avoids timing conflicts caused by clock frequency adjustment.

[0160] Specifically, to ensure the stability and performance of the system under different operating conditions, when the ACU adjusts the clock gating, the delay of the gating decision is controlled within 5 ns, and the power consumption is optimized to 20%-30%. In terms of hardware implementation, the feedback control signal of the ACU ensures the best balance between the clock frequency and power consumption in various environments by dynamically adjusting the on / off cycle of the clock gating switch.

[0161] In addition, the embodiments of the present application also disclose a computer program product or a computer program. The computer program product or the computer program is stored in a computer-readable storage medium. The processor of the computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above method.

[0162] The embodiments of the present invention also provide a computer-readable storage medium. The computer-readable storage medium stores a program executable by a processor. The program executable by the processor is used to implement the above method when executed by the processor. Similarly, the content in the above method embodiments is applicable to the embodiments of this storage medium. The functions specifically implemented by the embodiments of this storage medium are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0163] It will be understood that all or some of the steps and systems disclosed in the above methods may be implemented as software, firmware, hardware and their appropriate combinations. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules or other data. Computer storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0164] The above is a specific description of the preferred embodiments of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A clock gating method, characterized in that: include: Perform static analysis based on the circuit netlist of the system to obtain the clock dependency, timing relationship and data dependency between modules in the system; Based on the inter-module timing relationship, the inter-module data dependency and the topological sorting method, construct a timing relationship diagram between each of the modules in the system; Acquire real-time load data of each module in the system, perform dynamic simulation using the real-time load data and the clock dependency relationship between the modules, and construct a clock domain relationship diagram between each module in the system based on the result of the dynamic simulation; Based on the clock domain relationship diagram and the timing relationship diagram, dividing the modules in the system into a plurality of clock domains; Module load data in a plurality of the clock domains is obtained, and clock control modes of the plurality of the clock domains are adjusted based on the module load data.

2. The method according to claim 1, characterized in that The timing relationship diagram between each module in the system is constructed based on the timing relationship between the modules, the data dependency relationship between the modules and the topological sorting method, including: Constructing a directed acyclic graph according to a topological sorting method and data dependencies between the modules; Based on the inter-module timing relationship and the directed acyclic graph, a timing relationship graph between each of the modules in the system is constructed.

3. The method according to claim 1, characterized in that The dynamic simulation using the real-time load data and the inter-module clock dependency relationship includes: Calculate based on the real-time load data to obtain the activity frequency and load fluctuation of each module in the system; Based on the clock dependency relationship between the modules, a dynamic simulation model is generated; The activity frequency and the load fluctuation of each module are input into the dynamic simulation model and dynamic simulation is performed to obtain the result of the dynamic simulation.

4. The method according to claim 3, characterized in that The result of the dynamic simulation includes the clock requirements of each module under different load conditions; and constructing a clock domain relationship diagram between each module in the system based on the result of the dynamic simulation includes: Based on the clock requirements and the load fluctuation conditions of each module under different load conditions, the modules in the system are grouped using a minimum cut algorithm to obtain a plurality of first module groups whose clock requirements and load fluctuation conditions both meet a first preset condition; Based on a plurality of the first module groups, a clock domain relationship diagram between each of the modules in the system is constructed.

5. The method according to claim 4, characterized in that Based on the clock domain relationship diagram and the timing relationship diagram, the modules in the system are divided into several clock domains, including: Based on the timing relationship diagram, determining the clock signal sharing situation between each of the modules in the system; Based on the clock signal sharing situation between each of the modules, a plurality of second module groups whose timing conflict situation meets the second preset condition are obtained; Based on a plurality of the second module groups, the modules in the system are divided into a plurality of clock domains.

6. The method according to claim 1, characterized in that The clock domain relationship diagram and the timing relationship diagram are constructed in the same manner; the timing relationship diagram is constructed by the following method: Representing modules, clock characteristics or timing characteristics of modules as nodes; Represent the timing dependencies or control signal transmission between modules as edges; The delay or timing requirement of signal transmission between modules is represented as the weight of the edge.

7. The method according to claim 1, characterized in that The acquiring module load data in the plurality of clock domains and adjusting the clock control modes of the plurality of clock domains based on the module load data comprises: Acquire real-time load data and historical load data of each module in the plurality of clock domains; Perform load forecasting based on real-time load data and historical load data of each module; Based on the real-time load data of each module and the result of the load prediction, the clock control modes of several clock domains are adjusted.

8. A clock gating system, characterized in that: include: The first module is used to perform static analysis based on the circuit netlist of the system to obtain the clock dependency, timing relationship and data dependency between modules in the system; The second module constructs a timing relationship diagram between each of the modules in the system based on the timing relationship between the modules, the data dependency relationship between the modules and the topological sorting method; The third module obtains the real-time load data of each module in the system, performs dynamic simulation using the real-time load data and the clock dependency relationship between the modules, and constructs a clock domain relationship diagram between each module in the system based on the result of the dynamic simulation; A fourth module, based on the clock domain relationship diagram and the timing relationship diagram, divides the modules in the system into a plurality of clock domains; The fifth module obtains module load data in several of the clock domains, and adjusts the clock control methods of the several clock domains based on the module load data.

9. A clock gating device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

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