Superconducting fast single magnetic flux quantum circuit and design method thereof

Abstract

The invention provides a superconducting fast single-magnetic flux sub-circuit and a design method thereof, the circuit comprises a plurality of stages of logic gates, each logic gate and a plurality of sub-stages of logic gates connected with the door of the logic gate form a basic network; wherein each basic network comprises a source point and a plurality of sink points, the source point is a logic gate, and each sink point is a sub-level logic gate; and each basic network is additionally provided with at least one superconducting trigger to meet a path balance requirement, and is additionally provided with at least one superconducting separation unit to meet a multi-fan-out requirement. The circuit minimizes the number of the superconductive triggers and the superconductive separation units added to the basic networks while ensuring that each basic network meets the path balance of the superconductive RSFQ circuit and meets the fan-out requirement, and is also beneficial to reducing the depth of the circuit, improving the performance of the superconductive RSFQ circuit and reducing the power consumption and the area of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of logic synthesis of circuits, and particularly relates to a superconducting rapid single flux quantum circuit and a design method thereof. Background Art

[0002] Superconducting Rapid Single Flux Quantum (RSFQ) circuit is a digital circuit technology based on Josephson junctions and superconducting loops, which has advantages such as high speed, low power consumption, and high sensitivity. In an RSFQ circuit, information is stored and transmitted in the form of flux quanta, and logical operations are realized through the switching states of Josephson junctions. Since the operating frequency of the RSFQ circuit is extremely high (up to hundreds of GHz), even minor differences in the signal transmission path can lead to significant timing deviations. Therefore, path balance is crucial for ensuring the correctness and stability of the circuit. In addition, the basic unit in the RSFQ circuit is the Josephson junction, and their connections are realized through superconducting transmission lines. Due to the extremely low impedance of the superconducting transmission line, the fan-out ability in the RSFQ circuit is strictly limited. Fan-out limitation means that an RSFQ logic gate cannot directly drive multiple logic gates. Therefore, superconducting RSFQ circuits need to consider meeting the limitations of path balance and fan-out. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention proposes a superconducting rapid single flux quantum circuit and a design method thereof. The number of superconducting flip-flops and superconducting separation units inserted in the circuit is minimized while meeting the requirements of path balance and fan-out, so as to improve the performance of the superconducting RSFQ circuit, reduce the power consumption and area of the circuit.

[0004] To achieve the above object, on the one hand, the present invention provides a superconducting rapid single flux quantum circuit, comprising: multiple levels of logic gates, and each logic gate and a plurality of sub-level logic gates connected to the fan-out of the logic gate form a basic network; wherein, each of the basic networks includes a source point and several sink points, the source point is a logic gate, and each of the sink points is a sub-level logic gate;

[0005] And at least one superconducting flip-flop is added to each of the basic networks to meet the path balance requirement, and at least one superconducting separation unit is added to meet the multi-fan-out requirement.

[0006] In an embodiment of the present invention, for each of the basic networks, according to the number of the superconducting flip-flops to be inserted in the basic network, the superconducting flip-flops are inserted between the source point and at least one of the sink points.

[0007] In an embodiment of the present invention, for each basic network, given the logical depth of the source point, calculate the logical depth of each sink point. The logical depth of each sink point is the sum of the number of logic gates passed from the source point to this sink point and the logical depth of the source point.

[0008] Statistical the logical depth of all sink points in this basic network to obtain the maximum logical depth.

[0009] Calculate the difference between the maximum logical depth and the logical depth of the source point to obtain a maximum logical depth difference, and determine that the number of the superconducting flip-flops to be inserted in this basic network is the maximum logical depth difference minus one.

[0010] In an embodiment of the present invention, preferentially insert superconducting flip-flops between the sink point corresponding to the maximum logical depth and the source point, and the maximum number of inserted superconducting flip-flops is the number of the superconducting flip-flops to be inserted in this basic network.

[0011] In an embodiment of the present invention, insert one superconducting separation unit between the source point and a superconducting flip-flop adjacent to the source point, and between adjacent superconducting flip-flops; and each superconducting separation unit is also connected to at least one sink point of the remaining sink points except the sink point corresponding to the maximum logical depth.

[0012] In an embodiment of the present invention, if this basic network includes three or more logic gates, the superconducting separation unit adopts SPL3 or SPL tree to meet the multi-fan-out requirements, where the preset fan-out requirements include this fan-out requirement.

[0013] In an embodiment of the present invention, accumulate the number of superconducting flip-flops corresponding to all the basic networks to obtain the total number of superconducting flip-flops to be added to this superconducting rapid single-flux quantum circuit.

[0014] Construct an objective function according to the total number of superconducting flip-flops, solve this objective function, and determine the optimal logical depth of each logic gate of this superconducting rapid single-flux quantum circuit.

[0015] For each basic network, correct the number of the superconducting flip-flops to be inserted in this basic network according to this optimal logical depth.

[0016] In an embodiment of the present invention, the objective function is to minimize the total number of superconducting flip-flops and satisfy the following constraints:

[0017] For each basic network, the difference between the logical depth of each sink point and the logical depth of the source point minus one is greater than or equal to the number of superconducting flip-flops to be inserted in this basic network, and the difference between the logical depth of each sink point and the logical depth of the source point minus one is greater than or equal to zero.

[0018] On the other hand, the present invention also provides a design method for a superconducting rapid single-flux quantum circuit, the method comprising:

[0019] Dividing the superconducting rapid single-flux quantum circuit into several basic networks, wherein each logic gate of the superconducting rapid single-flux quantum circuit and a plurality of sub-logic gates connected to the fan-out of the logic gate form one of the basic networks; each of the basic networks includes a source point and several sink points, the source point is a logic gate, and each of the sink points is a sub-logic gate;

[0020] For each of the basic networks, superconducting triggers are inserted between the source point and at least one of the sink points according to the number of the superconducting triggers required to be inserted in the basic network.

[0021] In an embodiment of the present invention, for each of the basic networks, the method for calculating the number of the superconducting triggers required to be inserted in the basic network is:

[0022] For each basic network, given the logic depth of the source point, calculate the logic depth of each sink point. For the logic depth of each sink point, it is the sum value of the number of logic gates passed from the source point to the sink point and the logic depth of the source point;

[0023] Statistical the logic depths of all sink points in the basic network to obtain the maximum logic depth;

[0024] Calculate the difference between the maximum logic depth and the logic depth of the source point to obtain a maximum logic depth difference, and determine that the number of the superconducting triggers required to be inserted in the basic network is the maximum logic depth difference minus one.

[0025] In an embodiment of the present invention, the method for calculating the number of the superconducting triggers required to be inserted in the basic network further includes:

[0026] Accumulate the numbers of the superconducting triggers corresponding to all the basic networks to obtain the total number of the superconducting triggers to be added to the superconducting rapid single-flux quantum circuit;

[0027] Construct an objective function according to the total number of the superconducting triggers, solve the objective function, and determine the optimal logic depth of each logic gate of the superconducting rapid single-flux quantum circuit; wherein, the objective function is to minimize the total number of the superconducting triggers, and satisfies the constraint conditions: for each basic network, the difference between the logic depth of each sink point and the logic depth of the source point minus one is greater than or equal to the number of the superconducting triggers required to be inserted in the basic network, and the difference between the logic depth of each sink point and the logic depth of the source point minus one is greater than or equal to zero;

[0028] For each basic network, the number of the superconducting flip-flops to be inserted for the basic network is corrected according to the optimal logic depth.

[0029] In an embodiment of the present invention, it is preferred to insert superconducting flip-flops between the sink corresponding to the maximum logic depth and the source, and the maximum number of the inserted superconducting flip-flops is the number of the superconducting flip-flops to be inserted for the basic network;

[0030] A superconducting separation unit is inserted between the source and a superconducting flip-flop adjacent to the source, and between adjacent superconducting flip-flops; and each superconducting separation unit is also connected to at least one sink of the remaining sinks except the sink corresponding to the maximum logic depth.

[0031] As can be seen from the above solutions, the advantages of the present invention are as follows:

[0032] The superconducting rapid single flux quantum circuit disclosed by the present invention is composed of a plurality of basic networks divided from the RSFQ circuit, and then superconducting flip-flops and superconducting separation units are inserted into the basic networks, so that each basic network satisfies the path balance of the superconducting RSFQ circuit and meets the fan-out requirement. Finally, the entire circuit can meet the path balance and meet the fan-out requirement. The insertion operations of superconducting flip-flops and superconducting separation units for the circuit can be carried out simply and quickly. At the same time, while ensuring that each basic network satisfies the path balance of the superconducting RSFQ circuit and meets the fan-out requirement, the number of the inserted superconducting flip-flops and superconducting separation units for the basic network is minimized, which helps to reduce the circuit depth, improve the performance of the superconducting RSFQ circuit, and reduce the power consumption and area of the circuit. Description of the Drawings

[0033] Figure 1 The block diagram of the superconducting rapid single flux quantum circuit provided by an embodiment of the present invention is shown;

[0034] FIG. 2(a) and FIG. 2(b) show the results of two DFF and SPL insertion methods in the same basic network;

[0035] Figures 3(a) to 3(d) An example of inserting DFF and SPL into a basic network is shown;

[0036] Figure 4 The flow schematic diagram of the design method of the superconducting rapid single flux quantum circuit provided by an embodiment of the present invention is shown.

[0037] Among them, the reference numerals are:

[0038] 100: superconducting rapid single flux quantum circuit;

[0039] 10: basic network;

[0040] 11: Source point;

[0041] 12, 12_1... 12_n: Sink points;

[0042] 13, 13_1... 13_n: Superconducting flip-flops;

[0043] 14, 14_1... 14_n: Superconducting splitting units. Detailed implementation manners

[0044] To make the above features and effects of the present invention more clearly and understandably described, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings of the specification as follows.

[0045] Refer to Figure 1 as shown in Figure 1 which shows a structural block diagram of a superconducting rapid single-flux quantum circuit provided by an embodiment of the present invention. The superconducting rapid single-flux quantum circuit 100 includes: a multi-stage logic gate, and each logic gate and a plurality of sub-level logic gates connected to the fan-out of the logic gate form a basic network 10; wherein, each of the basic networks includes a source point 11 and several sink points 12, the source point is a logic gate, and each of the sink points is a sub-level logic gate. And at least one superconducting flip-flop (such as a D flip-flop, DFF) 13 is added to each of the basic networks 10 to meet the path balance requirement, and at least one superconducting splitting unit (Splitter, SPL) 14 is added to meet the multi-fan-out requirement. In the RSFQ circuit, since the output of a superconducting logic gate can only drive one logic gate (i.e., the fan-out ability is 1), when multi-fan-out needs to be realized, the multi-fan-out requirement usually appears in the case where a signal needs to be transmitted to multiple logic units simultaneously. To meet the multi-fan-out requirement, a superconducting splitting unit is introduced in the RSFQ circuit to reasonably distribute a single input signal to multiple output terminals. The SPL unit is a logic gate that does not require a clock input. It receives an SFQ pulse and generates two or three output pulses after a certain delay. The types of SPL units include SPL2 (generating two output pulses) and SPL3 (generating three output pulses), etc.

[0046] In this embodiment, the superconducting rapid single-flux quantum (RSFQ) circuit is abstracted as an overall network, which can be composed of several basic networks, and each basic network is defined by a source point and several sink points. To ensure the path balance of the superconducting RSFQ circuit and meet the fan-out requirement, it is necessary to insert additional superconducting flip-flops and superconducting separation units into the circuit. However, inserting superconducting flip-flops and superconducting separation units into the network formed by the entire circuit is too complex. Therefore, in this embodiment, the overall network is divided into several basic networks, and then superconducting flip-flops and superconducting separation units are added to the basic networks, so that each basic network meets the path balance of the superconducting RSFQ circuit and meets the fan-out requirement. Finally, the entire circuit can meet the path balance and meet the fan-out requirement. Using this method, the insertion operation of superconducting flip-flops and superconducting separation units can be carried out on the circuit simply and quickly.

[0047] Specifically, referring to Figure 1 as shown, for each of the basic networks, according to the number of the superconducting flip-flops to be inserted into the basic network, the superconducting flip-flops 13 are inserted between the source point 11 and at least one of the sink points 12. For calculating the number of the superconducting flip-flops to be inserted, according to the logical depth of the given source point, calculate the logical depth of each sink point. The logical depth of each sink point is the sum of the number of logic gates passed from the source point to this sink point and the logical depth of the source point; then count the logical depths of all sink points in the basic network to obtain the maximum logical depth; calculate the difference between the maximum logical depth and the logical depth of the source point to obtain a maximum logical depth difference, and determine that the number of the superconducting flip-flops to be inserted into the basic network is the maximum logical depth difference minus one.

[0048] In one embodiment, when inserting the superconducting flip-flops between the source point and at least one of the sink points, preferably insert the superconducting flip-flops between the sink point corresponding to the maximum logical depth and the source point, and the maximum number of the inserted superconducting flip-flops is the number of the superconducting flip-flops to be inserted into the basic network. However, the present invention is not limited to this.

[0049] In one embodiment, a superconducting separation unit 14 is inserted between the source point 11 and a superconducting flip-flop 13 adjacent to the source point 11, and between adjacent superconducting flip-flops 13, and each superconducting separation unit 14 is also connected to at least one of the sink points of the remaining sink points except the sink point corresponding to the maximum logical depth. However, the present invention is not limited to this. In one embodiment, if the basic network includes three or more logic gates, the superconducting separation unit adopts SPL3 or SPL tree to meet the multi-fan-out requirement.

[0050] However, different methods of inserting superconducting flip-flops and superconducting splitter units will seriously affect the number of superconducting flip-flops and superconducting splitter units inserted into the RSFQ circuit. Figures 2(a) and 2(b) show the results of using two methods of inserting superconducting flip-flops and superconducting splitter units in the same basic network. Although they both achieve the same function and meet the requirements of path balance and fan-out, the basic network shown in Figure 2(a) only requires inserting 3 DFFs, 2 SPL2s (generating two output pulses), and one SPL3 (generating three output pulses), while the basic network shown in Figure 2(b) requires inserting 8 DFFs and 5 SPLs. The G in the figure 0 →{G 1 ,G 2 ,G 3 ,G 4 ,G 5} is a network composed of five connections, where G 0 is the source point 11, {G 1 ,G 2 ,G 3 ,G 4 ,G 5} is the sink set 12_1...12_n, and G 0 →G 1 is a connection.

[0051] However, the RSFQ circuit needs to minimize the circuit area and power consumption as much as possible. Therefore, it is necessary to minimize the number of inserted superconducting flip-flops and superconducting splitter units. In one embodiment, consider allocating the optimal logic depth to each logic gate in the circuit, so as to minimize the number of inserted superconducting flip-flops, and at the same time, it also helps to reduce the circuit depth and speed up the realization of the circuit function. Specifically, for the problem of the number of superconducting flip-flops inserted in the overall network abstracted from the circuit, it can be converted into the minimum value of the sum of the number of superconducting flip-flops inserted in all basic networks in the network to construct an objective function. By solving this objective function through several constraints, the optimal logic depth of each logic gate in the circuit can be obtained, and then the minimum value of the number of superconducting flip-flops to be inserted in each basic network can be determined. Add superconducting flip-flops to each basic network according to the minimum value of the number of superconducting flip-flops, so that the number of inserted superconducting flip-flops and superconducting splitter units in the circuit is the least under the condition of meeting the path balance and the fan-out requirements.

[0052] Specifically, accumulate the number of superconducting flip-flops corresponding to all the basic networks to obtain the total number of superconducting flip-flops to be added to the superconducting rapid single-flux quantum circuit; construct an objective function based on the total number of superconducting flip-flops, and the objective function is to minimize the total number of superconducting flip-flops, that is where d eThe number of superconducting triggers to be inserted for each basic network. The objective function is subject to the following constraints: for each basic network, for each sink e ti The logical depth L[e ti minus the logical depth L[e s of the source point e s minus one is greater than or equal to the number d e of superconducting triggers to be inserted for this basic network, that is L represents the logical depth; and for each sink e ti The logical depth L[e ti minus the logical depth L[e s of the source point e s minus one is greater than or equal to zero, that is That is, this constraint ensures that the logical depth of the source point in each basic network must be strictly less than the logical depth of all its sink points. At the same time, for the entire network of the RSFQ circuit, it is also necessary to satisfy that the logical depth of all input nodes is zero, that is where Pi is the i-th input node, and PI is the set of input nodes; and the logical depths of all output nodes are the same, that is where u and v are output nodes, and PO is the set of output nodes. That is, the following optimization problem is obtained:

[0053]

[0054] Solve this objective function to determine the optimal logical depth of each logic gate of the superconducting rapid single flux quantum circuit. Then, for each basic network, modify the number of superconducting triggers to be inserted for this basic network according to the optimal logical depth, that is, obtain the optimal number of superconducting triggers, and then superconducting triggers can be inserted into this basic network according to the optimal number of superconducting triggers. For example, preferentially insert superconducting triggers between the sink point corresponding to the maximum logical depth and the source point, and the number of inserted superconducting triggers is the number of superconducting triggers to be inserted for this basic network. At the same time, insert a superconducting separation unit 14 between the source point 11 and a superconducting trigger 13 adjacent to the source point 11, and between adjacent superconducting triggers 13, and each superconducting separation unit 14 is also connected to at least one sink point of the remaining sink points except the sink point corresponding to the maximum logical depth. As Figures 3(a) to 3(d) shown, an example of adding superconducting triggers and superconducting separation units to a basic network is shown. As shown in Fig. 3(a), it is a basic network in an RSFQ circuit, where the logical depth of sink G 5 is 1, G 1 , G 2 , G 3 , G 4and G 5 The logical depths of 5 are 4, 3, 3, 2, and 1 respectively. Then, as shown in Fig. 3(b), first select the sink corresponding to the maximum logical depth difference and insert a DFF, that is, first insert a DFF for the edge G 0 →G 1 As shown in Fig. 3(c), after inserting 3 DFFs, G 1 achieves path balance. At this time, only SPL needs to be inserted between the DFFs, and no additional DFFs need to be inserted to meet the path balance of all gates. Specifically, as shown in Fig. 3(d), insert a superconducting separation unit between the source point G 0 and a superconducting trigger adjacent to this source point G 0 , and between adjacent superconducting triggers. And each superconducting separation unit is also connected to at least one sink of the remaining sinks except the sink G 1 corresponding to the maximum logical depth. That is, as shown in Fig. 3(d), the superconducting separation unit 14_1 is connected to the source point G 0 , the superconducting trigger 13_1, and the sink G 5 . The superconducting separation unit 14_2 is connected to the superconducting trigger 13_1, the superconducting trigger 13_2, and the sink G 4 . The superconducting separation unit 14_3 is connected to the superconducting trigger 13_2, the superconducting trigger 13_3, the sink G 2 , and G 3 . Compared with Fig. 2(b), the same function can be achieved, and both the path balance and fan-out requirements are met, and the number of inserted DFFs and SPLs is the least. Furthermore, it helps to reduce the circuit depth, so as to improve the performance of the superconducting RSFQ circuit, reduce the power consumption and area of the circuit.

[0055] In addition, it should be noted that in the superconducting RSFQ circuit, the SPL does not require clock driving, so the SPL does not need to be considered when calculating the logical depth.

[0056] Refer to Figure 4 As shown in, in an embodiment of the present invention, a design method for a superconducting rapid single flux quantum circuit is further provided. The method specifically includes the following steps:

[0057] Step S1: Divide the superconducting rapid single flux quantum circuit into several basic networks, where each logic gate of the superconducting rapid single flux quantum circuit and the multiple sub-logic gates connected to the fan-out of this logic gate form a basic network; each basic network includes a source point and several sinks, the source point is a logic gate, and each sink is a sub-logic gate;

[0058] Step S2: For each basic network, insert superconducting triggers between the source point and at least one sink according to the number of superconducting triggers required to be inserted in this basic network.

[0059] In one embodiment, for each of the basic networks, the method for calculating the number of superconducting flip-flops to be inserted into the basic network is as follows: for each basic network, given the logical depth of the source point, calculate the logical depth of each sink point. The logical depth of each sink point is the sum of the number of logic gates passed from the source point to this sink point and the logical depth of the source point; count the logical depths of all sink points in this basic network to obtain the maximum logical depth; calculate the difference between the maximum logical depth and the logical depth of the source point to obtain a maximum logical depth difference, and determine that the number of superconducting flip-flops to be inserted into this basic network is the maximum logical depth difference minus one.

[0060] In one embodiment, accumulate the numbers of superconducting flip-flops corresponding to all the basic networks to obtain the total number of superconducting flip-flops to be added to the superconducting rapid single flux quantum circuit; construct an objective function based on the total number of superconducting flip-flops, solve the objective function, and determine the optimal logical depth of each logic gate of the superconducting rapid single flux quantum circuit; wherein, the objective function is to minimize the total number of superconducting flip-flops, and satisfies the constraint conditions: for each basic network, the difference between the logical depth of each sink point and the logical depth of the source point minus one is greater than or equal to the number of superconducting flip-flops to be inserted into this basic network, and the difference between the logical depth of each sink point and the logical depth of the source point minus one is greater than or equal to zero; and, the logical depths of all input nodes are zero, and the logical depths of all output nodes are the same. For each basic network, correct the number of superconducting flip-flops to be inserted into this basic network according to the optimal logical depth.

[0061] In one embodiment, preferentially insert a superconducting flip-flop between the sink point corresponding to the maximum logical depth and the source point, and the maximum number of inserted superconducting flip-flops is the number of superconducting flip-flops to be inserted into this basic network.

[0062] In one embodiment, insert a superconducting separation unit between the source point and a superconducting flip-flop adjacent to the source point, and between adjacent superconducting flip-flops; and each superconducting separation unit is also connected to at least one sink point of the remaining sink points except the sink point corresponding to the maximum logical depth.

[0063] In summary, the superconducting rapid single flux quantum circuit and its design method disclosed by the present invention, while ensuring that each basic network satisfies the path balance of the superconducting RSFQ circuit and meets the fan-out requirements, minimize the number of superconducting flip-flops and superconducting separation units added to the basic network, and also help to reduce the circuit depth, improve the performance of the superconducting RSFQ circuit, and reduce the power consumption and area of the circuit. Specifically:

[0064] First, the RSFQ circuit is divided into several basic networks, and then superconducting flip-flops and superconducting separation units are inserted into the basic networks so that each basic network meets the path balance of the superconducting RSFQ circuit and meets the fan-out requirements. Finally, the entire circuit can meet the path balance and meet the fan-out requirements. The insertion operations of superconducting flip-flops and superconducting separation units can be carried out simply and quickly for the circuit.

[0065] Second, in order to minimize the circuit area and power consumption while making the basic network meet the path balance of the superconducting RSFQ circuit and meet the fan-out requirements, the number of inserted superconducting flip-flops and superconducting separation units is minimized. Specifically, by constructing the problem of the minimum sum of the number of DFFs inserted into all basic networks, the optimal logical depth of each logic gate in the circuit is obtained, and then the optimal number of superconducting flip-flops to be inserted into each basic network is determined, so that the number of DFFs and SPLs inserted in the circuit is the least under the requirements of meeting the path balance and meeting the fan-out.

[0066] The above specific implementation manners do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A superconducting fast single flux quantum circuit, characterized in that: It comprises: a multi-level logic gate, each logic gate and a plurality of sub-level logic gates fanned out from the logic gate form a basic network; wherein each of the basic networks comprises a source point and a plurality of sink points, the source point is a logic gate, and each of the sink points is a sub-level logic gate; Each of the basic networks is added with at least one superconducting trigger to meet the path balance requirement, and is added with at least one superconducting separation unit to meet the multi-fan-out requirement.

2. The superconducting fast single flux quantum circuit according to claim 1, characterized in that: For each of the basic networks, the superconducting triggers are inserted between the source point and at least one of the sink points according to the number of the superconducting triggers required to be inserted into the basic network.

3. The superconducting fast single flux quantum circuit according to claim 2, characterized in that: For each basic network, given the logic depth of the source point, the logic depth of each sink point is calculated, and the logic depth of each sink point is the sum of the number of logic gates from the source point to the sink point and the logic depth of the source point; Count the logic depths of all sinks in the basic network and obtain the maximum logic depth; The difference between the maximum logic depth and the logic depth of the source point is calculated to obtain a maximum logic depth difference, and the number of the superconducting triggers required to be inserted into the basic network is determined to be the maximum logic depth difference minus one.

4. The superconducting fast single flux quantum circuit according to claim 3, characterized in that: The superconducting trigger is preferably inserted between the sink corresponding to the maximum logic depth and the source point, and the maximum number of the inserted superconducting triggers is the number of the superconducting triggers required to be inserted into the basic network.

5. The superconducting fast single flux quantum circuit according to claim 4, characterized in that: Inserting the superconducting separation unit between the source point and a superconducting trigger adjacent to the source point, and between adjacent superconducting triggers; Each superconducting separation unit is also simultaneously connected to at least one sink point of the remaining sink points except the sink point corresponding to the maximum logic depth.

6. The superconducting fast single flux quantum circuit according to claim 5, characterized in that: If the basic network includes three or more logic gates, the superconducting separation unit adopts SPL3 or SPL tree to meet the multi-fan-out requirement.

7. The superconducting fast single flux quantum circuit according to claim 3, characterized in that: Accumulating the number of superconducting triggers corresponding to all the basic networks to obtain the total number of superconducting triggers that need to be added to the superconducting fast single flux quantum circuit; Constructing an objective function according to the total number of the superconducting triggers, solving the objective function, and determining the optimal logic depth of each logic gate of the superconducting fast single flux quantum circuit; For each basic network, the number of superconducting flip-flops required to be inserted into the basic network is modified according to the optimal logic depth.

8. The superconducting fast single flux quantum circuit according to claim 7, characterized in that: The objective function is to minimize the total number of superconducting triggers and satisfy the following constraints: For each basic network, the difference between the logic depth of each sink and the logic depth of the source point minus one is greater than or equal to the number of superconducting triggers required to be inserted into the basic network, and the difference between the logic depth of each sink and the logic depth of the source point minus one is greater than or equal to zero.

9. A method for designing a superconducting fast single flux quantum circuit, characterized in that: The superconducting fast single magnetic flux quantum circuit is divided into a plurality of basic networks, wherein each logic gate of the superconducting fast single magnetic flux quantum circuit and a plurality of sub-level logic gates fanned out from the logic gate constitute a basic network; each of the basic networks comprises a source point and a plurality of sink points, the source point is a logic gate, and each of the sink points is a sub-level logic gate; For each of the basic networks, superconducting triggers are inserted between the source point and at least one of the sink points according to the number of the superconducting triggers required to be inserted into the basic network.

10. The method according to claim 9, characterized in that For each of the basic networks, the method for calculating the number of the superconducting triggers that need to be inserted into the basic network is: For each basic network, given the logic depth of the source point, the logic depth of each sink point is calculated, and the logic depth of each sink point is the sum of the number of logic gates from the source point to the sink point and the logic depth of the source point; Count the logic depths of all sinks in the basic network and obtain the maximum logic depth; The difference between the maximum logic depth and the logic depth of the source point is calculated to obtain a maximum logic depth difference, and the number of the superconducting triggers required to be inserted into the basic network is determined to be the maximum logic depth difference minus one.

11. The method according to claim 10, characterized in that The method for calculating the number of superconducting triggers required to be inserted into the basic network further comprises: Accumulating the number of superconducting triggers corresponding to all the basic networks to obtain the total number of superconducting triggers that need to be added to the superconducting fast single flux quantum circuit; Constructing an objective function according to the total number of the superconducting triggers, solving the objective function, and determining the optimal logic depth of each logic gate of the superconducting fast single flux quantum circuit; wherein the objective function is to minimize the total number of the superconducting triggers and satisfy the constraint conditions: for each basic network, the difference between the logic depth of each sink and the logic depth of the source point minus one is greater than or equal to the number of superconducting triggers required to be inserted into the basic network, and the difference between the logic depth of each sink and the logic depth of the source point minus one is greater than or equal to zero; For each basic network, the number of superconducting flip-flops required to be inserted into the basic network is modified according to the optimal logic depth.

12. The method according to claim 10, characterized in that Preferentially inserting a superconducting trigger between the sink point corresponding to the maximum logic depth and the source point, and the maximum number of superconducting triggers inserted is the number of superconducting triggers required to be inserted in the basic network; Inserting a superconducting separation unit between the source point and a superconducting trigger adjacent to the source point, and between adjacent superconducting triggers; Each superconducting separation unit is also simultaneously connected to at least one sink point of the remaining sink points except the sink point corresponding to the maximum logic depth.

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