Sampling point rearrangement method, device, equipment and storage medium

Abstract

The present application discloses a method, apparatus, device, and storage medium for rearranging sampling points, which belongs to the field of image data processing. The method includes: reading m sampling points arranged in a first arrangement from a storage unit, wherein the m sampling points are sampling points in at least one pixel, and the first arrangement is an arrangement based on the sampling point index of the m sampling points, where m is a positive integer; rearranging the m sampling points to obtain m sampling points arranged in a second arrangement, wherein the second arrangement is an arrangement based on the positions of the m sampling points in the at least one pixel; and storing the m sampling points arranged in the second arrangement in the storage unit. For the m sampling points stored in the storage unit, the position information of the sampling points is restored, which facilitates the subsequent execution of various algorithms based on the position information of the sampling points.

Description

Technical Field

[0001] The present application relates to the field of image data processing, and in particular to a sampling point rearrangement method, apparatus, device and storage medium. Background Art

[0002] Multi-Sampling Anti-Aliasing (MSAA) is an anti-aliasing method that performs multiple sampling and calculations on a pixel point and finally summarizes the pixel information of the pixel point. This method can make the edges of the drawn image smoother.

[0003] When using MSAA, when storing an image in a memory cell, instead of storing the pixel information corresponding to each pixel, the sampling point information of each sampling point must be stored in the memory cell. However, related technologies do not adapt to the storage method of sampling points in memory cells, resulting in the storage of sampling points in the memory cell only being based on the sampling point index.

[0004] However, the storage method based on the sampling point index is not friendly to some algorithms that need to be applied to the location information of the sampling points. Summary of the Invention

[0005] This application provides a sampling point rearrangement method, apparatus, device, and storage medium. The technical solution is as follows:

[0006] According to one aspect of the present application, a method for rearranging sampling points is provided, the method comprising:

[0007] Reading m sampling points arranged according to a first arrangement from a storage unit, where the m sampling points are sampling points in at least one pixel, the first arrangement is an arrangement based on sampling point indexes of the m sampling points, and m is a positive integer greater than 1;

[0008] Rearranging the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is an arrangement based on positions of the m sampling points in the at least one pixel;

[0009] The m sampling points arranged in the second arrangement manner are stored in the storage unit.

[0010] According to one aspect of the present application, a sampling point rearrangement device is provided, the device comprising:

[0011] an acquisition module, configured to read from a storage unit m sampling points arranged in a first arrangement, where the m sampling points are sampling points in at least one pixel, and the first arrangement is an arrangement based on sampling point indexes of the m sampling points, where m is a positive integer greater than 1;

[0012] a rearrangement module, configured to rearrange the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is an arrangement based on positions of the m sampling points in the at least one pixel;

[0013] A storage module is used to store the m sampling points arranged in the second arrangement manner in the storage unit.

[0014] According to one aspect of the present application, a computer device is provided, comprising: a processor and a memory, wherein the memory stores at least one program; and the processor is configured to execute the at least one program in the memory to implement the above-mentioned sampling point rearrangement method.

[0015] According to one aspect of the present application, a computer-readable storage medium is provided, wherein executable instructions are stored in the computer-readable storage medium. The executable instructions are loaded and executed by a processor to implement the above-mentioned sampling point rearrangement method.

[0016] According to one aspect of the present application, a computer program product is provided. The computer program product includes computer instructions. The computer instructions are stored in a computer-readable storage medium. A processor reads and executes the computer instructions from the computer-readable storage medium to implement the above-mentioned sampling point rearrangement method.

[0017] The beneficial effects of the technical solution provided by this application include at least:

[0018] The m sampling points originally stored in a storage unit according to a first arrangement (i.e., based on sampling point indexes) are rearranged to be stored according to a second arrangement (i.e., based on the position of each of the m sampling points within at least one pixel). The storage of the sampling points incorporates position information of the sampling points within at least one pixel (or image or image block), enabling the m sampling points arranged in the second arrangement to support various algorithms requiring position information, such as image compression algorithms. This avoids loss of position information during the storage of the m sampling points, improving the storage flexibility of the m sampling points. Furthermore, the second arrangement based on the positions of the m sampling points within at least one pixel is more user-friendly for data access based on position information, improving access efficiency and query performance for the m sampling points in the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 shows a schematic diagram of an image compression process;

[0021] Figure 2 A schematic diagram showing an arrangement of images in a storage unit;

[0022] Figure 3 A schematic diagram showing another arrangement of images in a storage unit;

[0023] Figure 4 An architectural diagram of a computer system provided by an exemplary embodiment of the present application is shown;

[0024] Figure 5 A flow chart showing a method for rearranging sampling points provided by an exemplary embodiment of the present application is shown;

[0025] Figure 6 A flow chart showing a method for rearranging sampling points provided by another exemplary embodiment of the present application is shown;

[0026] Figure 7 A schematic diagram of a standard sampling position provided by an exemplary embodiment of the present application is shown;

[0027] Figure 8A schematic diagram showing a method for rearranging sampling points provided by an exemplary embodiment of the present application is shown;

[0028] Figure 9 A schematic diagram illustrating a method for determining a pixel index provided by an exemplary embodiment of the present application is shown;

[0029] Figure 10 A schematic diagram showing a method for rearranging sampling points provided by another exemplary embodiment of the present application is shown;

[0030] Figure 11 A schematic diagram showing an arrangement of sampling points provided by an exemplary embodiment of the present application is shown;

[0031] Figure 12 A schematic diagram showing a method for rearranging sampling points provided by yet another exemplary embodiment of the present application is shown;

[0032] Figure 13 A schematic diagram showing a method for rearranging sampling points provided by yet another exemplary embodiment of the present application is shown;

[0033] Figure 14 A structural block diagram of a sampling point rearrangement device provided by an exemplary embodiment of the present application is shown;

[0034] Figure 15 A schematic structural diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0036] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0037] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the information such as the settings operations involved in this application is obtained with full authorization.

[0039] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter without departing from the scope of this disclosure. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0040] First, the relevant terms involved in this application are introduced.

[0041] Image Compressions: is a technique for reducing the size of image files. Image compression can be achieved by reducing the amount of data in the image while maintaining the visual quality of the image as much as possible. In hardware, especially in GPUs (Graphics Processing Units), image compression is a common technical means to reduce bandwidth transmission requirements. Generally speaking, image compression requires the use of position information between pixels in order to achieve a higher compression rate. For example, in Figure 1In the illustrated image compression technology, for a frame image 10 extracted from a video or animation, a compression unit 11 (a hardware or software component within a GPU) performs data compression and decompression operations. Compression unit 11 reads an image block 12 from frame image 10 and processes image block 12 within compression unit 11 using a wavelet frequency domain transform, generating four components of information: a low-frequency information component 13 in the upper left corner, a high-frequency horizontal information component 14 in the lower left corner, a high-frequency vertical information component 15 in the upper right corner, and a high-frequency diagonal information component 16 in the lower right corner. After performing the wavelet frequency domain transform, each pixel in these four components can be encoded to achieve data compression. For example, encoding is performed for each 2×2 pixel block. For example, 2×2 pixel blocks are extracted from the low-frequency information component 13 in the upper left corner. The pixel information at each pixel indicates the color information, such as the grayscale value, of that pixel. The extracted 2×2 pixel information, i.e., pixel information 17 for four pixels, consists of 8 bits per pixel, resulting in a total of 32 bits. Data compression is performed on these four pixels, which can be understood as extracting the common portion of the pixel information 17. Since each of the four pixels contains three zeros before the pixel information, compression can be performed on both the common and non-common portions, resulting in compressed pixel information 18. The compressed pixel information consists of five parts. The first part represents the common portion of the four pixels, consisting of "011 (i.e., 3)" zeros. The second through fifth parts represent the non-common portions of the four pixels, respectively. This achieves compression of 32 bits of pixel information to 23 bits. The image compression method described above first requires a wavelet frequency domain transform, which essentially converts the original image information into the frequency domain, preserving high-frequency and low-frequency signals separately. This requires the hardware to be able to restore the position information between consecutive pixel information stored in memory to their original position information in the original image.

[0042] In the GPU, the original image is usually arranged in memory in two modes: linear layout (Linear Layout) and staggered layout (Twiddle Layout).

[0043] Linear arrangement: The pixel information of the same row of an image or image block is placed at consecutive addresses in the memory, and each row of pixel information is followed by the pixel information of the next row. In other words, the addresses of adjacent pixel information of the same row of an image or image block in the memory are consecutive, such as Figure 2As shown, among the pixel information of image block 19 stored in memory 20, virtual addresses 0x80000000 to 0x8000 0003 store the pixel information of the first row of image block 19, that is, the pixel information of the pixel points in the coordinates (0, 0) to (0, 3); virtual addresses 0x8000 0004 to 0x8000 0007 store the pixel information of the second row of image block 19, that is, the pixel information of the pixel points in the coordinates (1, 0) to (1, 3); virtual addresses 0x8000 0008 to 0x8000 000B store the pixel information of the third row of image block 19, that is, the pixel information of the pixel points in the coordinates (2, 0) to (2, 3); virtual addresses 0x8000 000C to 0x8000 000F stores the pixel information of the 4th row in image block 19, that is, the pixel information of the pixel points between coordinates (3, 0) and (3, 3).

[0044] Staggered layout: It can also be called tile layout. The pixels in an image or image block are divided into multiple groups of pixels. Each group of pixels is located in a rectangle or a tile. Each group of pixels is stored in memory in a fixed order. The fixed order can be a Z-order curve. For example Figure 3 As shown, the image block 19 is divided into 4 tiles, each tile includes 2×2 pixels, and the pixels in each tile are stored in the memory 20 in a z-sequence arrangement. At the same time, the tiles are also stored in the memory 20 in a z-sequence arrangement. The virtual addresses 0x8000 0000 to 0x8000 0003 store the pixel information of the first tile, that is, the pixel information of the pixel points at coordinates (0, 0), (1, 0), (0, 1), and (1, 1); the virtual addresses 0x8000 0004 to 0x8000 0007 store the pixel information of the second tile, that is, the pixel information of the pixel points at coordinates (2, 0), (3, 0), (2, 1), and (3, 1); the virtual addresses 0x8000 0008 to 0x8000 000B store the pixel information of the third tile, that is, the pixel information of the pixel points at coordinates (0, 2), (1, 2), (0, 3), and (1, 3); the virtual addresses 0x8000 000C to 0x8000 000F stores the pixel information in the fourth tile, that is, the pixel information of the pixel points at coordinates (2, 2), (3, 2), (2, 3), and (3, 3).

[0045] When the compression unit gets a memory address that stores the original image information, it will first restore the relationship between the original pixels according to the arrangement of the compression unit. Figure 2As shown in the figure, under Linear Layout, the pixel information stored at 0x8000 0000 and 0x8000 0003 is restored to the pixel information with coordinates of (0, 0) and (0, 2), while under Twiddle Layout, Figure 3 As shown, the pixel information at these two addresses will be restored to pixel information with coordinates of (0, 0) and (0, 1).

[0046] MSAA (Multi-Sample Anti-Alias) is an anti-aliasing technology that performs multiple sampling and calculations on a single pixel and finally aggregates the pixel information for that pixel, thereby making the edges of the drawn image smoother. In other words, a single pixel is further subdivided to obtain multiple sampling points. In this way, the multiple sampling points in each pixel can be independently interpolated and fragment shaded to calculate independent color and depth values. The arithmetic mean of all the sampling points for the same pixel is then calculated to obtain the final color of that pixel. In this way, the edges of the graphics are drawn more finely and smoothly. Of course, for a 1920×1280 grid, MSAA4 is equivalent to processing 1920×1280×4 grids, and the amount of calculation is also doubled.

[0047] Physical address: An address in actual physical memory that directly points to a specific location on a memory stick. Physical addresses are hardware-level addresses that the CPU (Central Processing Unit), memory controller, and other hardware directly use to access data in memory. Physical addresses are real, directly accessible memory addresses, typically translated from virtual addresses by the Memory Management Unit (MMU).

[0048] A virtual address is an address in the address space provided by the operating system for each process. It is the address from the process's perspective and is used to access memory. The virtual address space is created for each process by the operating system through virtual memory management technology. This allows each process to have an independent address space, thereby achieving memory protection and isolation. In a virtual memory system, virtual addresses must be converted to physical addresses by the MMU, a process called address translation.

[0049] Figure 4 FIG. 1 shows an architecture diagram of a computer system provided by an exemplary embodiment of the present application. The computer system includes: a computer device 110 .

[0050] Optionally, the computer device 110 may be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. The AI ​​computing cluster may also be referred to as an intelligent computing cluster or a smart computing cluster.

[0051] For images using MSAA technology, each pixel contains multiple sampling points. The location of sampling points within a pixel is generally specified by the graphics standard, but it also allows users to customize the location of sampling points using the Programmable Sample Location technology. In related technologies, the storage method of the relevant information of the sampling points does not distinguish between the two sampling point location definitions mentioned above, and both are based on Figure 4 The first arrangement shown is to store the relevant information of the sampling points in the memory 20 in the order of the sampling point index. That is, for the pixel 21 of MSAA8X, for sampling points 0 to 7 (i.e. S0-S7), although the up-down and left-right position relationships between the sampling points are different, they are all stored in the memory 20 in the order of the sampling point index from 0 to 7. If the compression unit is interleaved and restored based on the interleaved arrangement, it will be parsed as follows Figure 4 As shown in the case of the pixel point 22 in FIG, the first arrangement 23 stored in the memory 20 in the order of the sampling point index is not conducive to the compression unit or the GPU to restore the position information of the sampling point inside the pixel point.

[0052] The method provided in the embodiment of the present application rearranges the sampling points in the memory so that the position information of the sampling points can be restored in the compression unit or GPU. The specific process is as follows.

[0053] (1) Obtain m sampling points and m first storage addresses.

[0054] Optionally, the m first storage addresses refer to virtual addresses of the m sampling points when they are stored in the memory 20 according to the sampling point index.

[0055] (2) Rearrange m sampling points to obtain m second storage addresses.

[0056] Optionally, based on the order of the m sampling points indicated by the m first storage addresses, the storage address of each of the m sampling points is changed so that the m sampling points stored in the resulting m second storage addresses are arranged according to their positions in the pixel, for example, from left to right and from top to bottom, thereby obtaining m second storage addresses storing the m sampling points in the order of "S3 → S7 → S5 → S0 → S1 → S2 → S4 → S6." The storage order is related to the application scenario of the m sampling points. For example, in an image compression scenario, the storage order is related to a mapping rule of a compression unit. The mapping rule of a compression unit refers to the rule by which the compression unit maps multiple sampling points to different positions of their corresponding pixels after reading them from the storage unit; or, the mapping rule of a compression unit refers to the rule by which the compression unit maps multiple sampling points to different positions in an image or image block after reading them from the storage unit.

[0057] That is, for the m sampling points corresponding to the m second storage addresses, after using interleaving recovery, the following is obtained: Figure 4 As shown in the effect of the pixel points 24 in FIG, the pixel points 24 arranged according to the second arrangement manner 25 retain the position information of each sampling point compared to the pixel points 22 arranged according to the first arrangement manner 23.

[0058] (3) Store back into memory 20.

[0059] Optionally, the m sampling points arranged according to the second arrangement manner 25 are stored back into the memory 20 so that other units such as the compression unit can subsequently directly read the relevant information of the sampling points with position information from the memory 20 .

[0060] Figure 5 The flowchart of the method for rearranging sampling points provided by an embodiment of the present application is shown. The method is executed by a computer device, which may be the computer device described above. Figure 4 The computer device shown in the figure includes the following steps.

[0061] Step 210: Read m sampling points arranged in a first arrangement from a storage unit, where the m sampling points are sampling points in at least one pixel. The first arrangement is an arrangement based on sampling point indexes of the m sampling points, where m is a positive integer greater than 1.

[0062] Reading m sampling points arranged in a first arrangement from a storage unit; or reading at least one pixel from a storage unit, where the at least one pixel includes m sampling points, and the m sampling points are arranged in the first arrangement; or reading m sampling points corresponding to the at least one pixel from a storage unit, where the m sampling points are arranged in the first arrangement.

[0063] Optionally, each pixel point in the at least one pixel point includes m sampling points; the sampling point indexes of the m sampling points included in each pixel point are different or the sampling point indexes of the m sampling points included in each pixel point are the same.

[0064] Exemplarily, the sampling point indexes of the m sampling points included in each pixel are the same. The sampling point index is used to indicate the index of the sampling point in the pixel where it is located. For example, each pixel includes 2 sampling points; for pixel 0, the sampling point indexes of the two sampling points included are 0 and 1 respectively; for pixel 1, the sampling point indexes of the two sampling points included are also 0 and 1 respectively; for pixel 2, the sampling point indexes of the two sampling points included are also 0 and 1 respectively; for pixel 3, the sampling point indexes of the two sampling points included are also 0 and 1 respectively.

[0065] Exemplarily, the sampling point indexes of the m sampling points included in each pixel are different. For example, the sampling point index is used to indicate the index of the sampling point in the image or image block. If each pixel includes 2 sampling points, the sampling point index of each sampling point is determined based on the index of the sampling point in the pixel point where it is located and the index of the pixel point in the image or image block. For pixel point 0, the sampling point indexes of the two sampling points it includes can be expressed as P0S0 and P0S1, where P0 represents the index of the pixel point in the image or image block, and S0 and S1 represent the index of the sampling point in the pixel point where it is located; for pixel point 1, the sampling point indexes of the two sampling points it includes can be expressed as P1S0 and P1S1; for pixel point 2, the sampling point indexes of the two sampling points it includes can be expressed as P2S0 and P2S1; for pixel point 3, the sampling point indexes of the two sampling points it includes can be expressed as P3S0 and P3S1.

[0066] It should be noted that in the embodiment of the present application, the sampling point indexes of the m sampling points included in each pixel are the same. That is, the sampling point index is used to indicate the index of the sampling point in the pixel where it is located, or in other words, the sampling point index of the sampling point is used to indicate the index of the pixel corresponding to the sampling point. However, the embodiment of the present application is not limited to this.

[0067] Step 220: rearrange the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is based on the positions of the m sampling points in at least one pixel.

[0068] The m sampling points are rearranged to obtain m sampling points arranged in the second arrangement; or, according to the indication information, the m sampling points are rearranged to obtain m sampling points arranged in the second arrangement, where the indication information is used to indicate that the arrangement after rearrangement is the second arrangement.

[0069] Optionally, at least one pixel point is located in an image or an image block, and the second arrangement method is an arrangement method based on the position arrangement of the m sampling points in the image, or the second arrangement method is an arrangement method based on the position arrangement of the m sampling points in the image block.

[0070] Alternatively, the arrangement can be understood as the order of storage in the storage unit, or the order of the m sampling points in the storage unit, or the order of the storage addresses corresponding to the m sampling points in the storage unit. That is, the first arrangement and the second arrangement are used to indicate the order of storage of the m sampling points in the storage unit; or the first arrangement and the second arrangement are used to indicate the order of storage of the m sampling points in the storage unit; or the first arrangement and the second arrangement are used to indicate the order of storage addresses corresponding to the m sampling points in the storage unit.

[0071] Optionally, in the field of image compression, the first arrangement is an arrangement that is unrelated to the mapping rule of the compression unit, and the second arrangement is an arrangement that is related to the mapping rule of the compression unit. Alternatively, the first arrangement is an arrangement based on the sampling point indices of the m sampling points, and the sampling point indices of the m sampling points are unrelated to the mapping rule of the compression unit. The second arrangement is an arrangement based on the mapping rule of the compression unit and the positions of the m sampling points in at least one pixel. Alternatively, the first arrangement is not an arrangement that is arranged in the mapping order of the compression unit, and the second arrangement is an arrangement that is arranged in the mapping order of the compression unit. A compression unit is a unit for executing a compression algorithm on an image or image block. The mapping rule of a compression unit refers to the rule by which the compression unit maps multiple sampling points to different positions of their corresponding pixels after reading multiple sampling points from a storage unit; or, the mapping rule of a compression unit refers to the rule by which the compression unit maps multiple sampling points to different positions of an image or image block after reading multiple sampling points from a storage unit. Being unrelated to the mapping rule of the compression unit means that the first arrangement mode or the sampling point index is not set according to the mapping rule, but is based on other rules, such as the sampling point index is determined based on the standard sampling position formulated by the graphic standard, or the sampling point index is determined based on the programmable sampling position set by the user.

[0072] Exemplarily, each pixel point in at least one pixel point includes 8 sampling points. For the first arrangement, the 8 sampling points of each pixel point are stored sequentially in the storage unit according to the sampling point index, but for different pixel points in at least one pixel point, each pixel point can be stored in the order of the pixel point index, or can be stored according to the position of the pixel point in the image or image block. For the second arrangement, the m sampling points are regarded as independent points in the image or image block, and the order of each pixel point in the m sampling points is determined according to the actual position of the m sampling points in the image or image block. That is, the storage positions of the sampling points belonging to the same pixel point can be adjacent or non-adjacent at this time, which depends on the mapping rules of the storage unit or compression unit for different storage positions. For example, the above Figure 2 and Figure 3 Shown are two different mapping rules for pixels.

[0073] Step 230: Store the m sampling points arranged in the second arrangement manner into a storage unit.

[0074] The m sampling points arranged according to the second arrangement are stored again in the storage unit to obtain m sampling points stored according to the second arrangement.

[0075] Optionally, the m sampling points shown above may also be understood as related information of the m sampling points, or sampling point information of the m sampling points, or pixel information (color value, depth value, transparency, etc.) of the m sampling points, and so on.

[0076] In summary, the method provided in the embodiments of the present application rearranges m sampling points originally stored in a storage unit according to a first arrangement (i.e., m sampling points stored based on sampling point indexes) into m sampling points stored according to a second arrangement (i.e., m sampling points stored based on the position of each of the m sampling points in at least one pixel). The storage of the sampling points incorporates the position information of the sampling points in at least one pixel (or image or image block), enabling the m sampling points arranged in the second arrangement to support various algorithms requiring position information, such as image compression algorithms. This avoids the loss of position information during the storage of the m sampling points, thereby increasing the flexibility of the storage of the m sampling points. Furthermore, the storage of the m sampling points in the second arrangement based on the positions of the m sampling points in at least one pixel is more user-friendly for data access based on position information, thereby improving access efficiency and query performance for the m sampling points in the storage unit.

[0077] Next, the rearrangement method will be further explained.

[0078] Based on Figure 5In an optional embodiment, as Figure 6 As shown, the above step 220 can be implemented as steps 221 to 223.

[0079] Step 221: Obtain m first storage addresses of the m sampling points in the storage unit, where the m first storage addresses correspond one-to-one to the m sampling points.

[0080] Optionally, the m first storage addresses are virtual addresses or physical addresses. The embodiment of the present application is described by taking the first storage address and the second storage address as virtual addresses as an example, but the protection scope of the embodiment of the present application is not limited thereto.

[0081] Optionally, obtaining m first storage addresses of the m sampling points in the storage unit can be understood as obtaining the first storage address of each of the m sampling points in the storage unit, wherein the first storage address of each sampling point is used to indicate the storage location of each sampling point in the storage unit.

[0082] In some embodiments, step 221 may be performed simultaneously with step 210 or in a swapped order, that is, the first storage address of each sampling point in the storage unit is obtained while reading m sampling points; or, after reading the m first storage addresses of the m sampling points in the storage unit, the m sampling points are read; or, after reading the m sampling points, the m first storage addresses of the m sampling points in the storage unit are read.

[0083] Step 222: Based on the m first storage addresses, determine m second storage addresses, where the second storage addresses correspond to the m sampling points one-to-one, and the m second storage addresses are different from the m first storage addresses.

[0084] Optionally, based on the first storage address of each of the m sampling points, the second storage address of each sampling point is determined to obtain m second storage addresses. That is, by changing the storage address of each of the m sampling points, the m sampling points are rearranged.

[0085] Optionally, m second storage addresses are determined based on a mapping rule between the m first storage addresses and the compression unit.

[0086] Step 223: Based on the m second storage addresses, determine m sampling points arranged in a second arrangement manner.

[0087] Optionally, based on the m second storage addresses, m sampling points arranged in the second arrangement are determined; or, based on the m second storage addresses, storage positions of the m sampling points in the storage unit are determined, and based on the storage positions of the m sampling points in the storage unit, the m sampling points are rearranged to obtain m sampling points arranged in the second arrangement.

[0088] It should be noted that the first storage address refers to the original storage address of the m sampling points in the storage unit, while the second storage address is the storage address where the m sampling points will be stored, determined based on the rearrangement method illustrated in the embodiment of the present application. However, only after executing step 230 to store the m sampling points in the storage unit do the m second storage addresses become the actual storage addresses corresponding to the rearranged m sampling points. That is, the second storage address can be understood as a simulated storage address. When storing the m sampling points in step 230, the m sampling points may be stored according to the m second storage addresses, or rather, the m sampling points arranged in the second arrangement determined based on the m second storage addresses may be stored in the storage unit. That is, the m sampling points arranged in the second arrangement correspond to m third storage addresses in the storage unit. The m third storage addresses are different from the m second storage addresses, but the m sampling points corresponding to the m third storage addresses and the m second storage addresses are both arranged in the second arrangement.

[0089] Optionally, the sampling point positions of the m sampling points included in each pixel of the at least one pixel are standard sampling positions; or programmable sampling positions. A standard sampling position refers to a sampling point position determined according to a graphics standard. A programmable sampling position refers to a sampling point position set by a user or developer.

[0090] Among them, standard sampling position and programmable sampling position both refer to the sampling method of a pixel. Standard sampling position means that the sampling point positions of multiple sampling points within a pixel are pre-agreed by the graphics standard. Programmable sampling position means that the sampling point positions of multiple sampling points within a pixel are set by the user or developer. Standard sampling position is as follows Figure 7 As shown, when a pixel point includes 2 sampling points, the standard sampling position is as follows Figure 7 As shown in part (1) of this article, this situation can also be called the use of MSAA2 technology; when a pixel point includes 4 sampling points, the standard sampling position is as follows Figure 7 As shown in part (2) of the above, this situation can also be called the use of MSAA4 technology; when a pixel point includes 8 sampling points, the standard sampling position is as follows Figure 7 As shown in part (3) of the above, this situation can also be called the use of MSAA8 technology. For programmable positions, users or developers are supported to set the number of sampling points and the sampling point positions (or sampling positions) included in a pixel.

[0091] Optionally, the mapping rule of the compression unit is set based on a standard sampling position, or the mapping rule of the compression unit is set based on a programmable sampling position.

[0092] In summary, the method shown in the embodiment of the present application shows a method for rearranging m sampling points, by changing the m first storage addresses of the m sampling points in the storage unit to obtain m second storage addresses, wherein the first storage address corresponding to each sampling point can reflect the order in which each sampling point is located among the m sampling points when arranged according to the first arrangement, that is, the m first storage addresses can reflect the first arrangement, and the second storage addresses can reflect the second arrangement.

[0093] Furthermore, the sampling point positions of each sampling point within at least one pixel support both standard sampling positions and programmable sampling positions, improving the scalability of the sampling point rearrangement method provided in the embodiments of the present application. Furthermore, for standard sampling positions, the method provided in the embodiments of the present application can effectively restore the positional information between sampling points, reducing the probability of high-frequency signals and improving the compression ratio. For programmable sampling positions, the method provided in the embodiments of the present application provides the driver with a more flexible means of recovering sampling point position information.

[0094] The method for determining the m second storage addresses is as follows.

[0095] Determination method 1: Address Swizzle.

[0096] Determination method 2: Look Up Table (LUT).

[0097] Next, the two determination methods shown above are introduced one by one (the order of introduction does not represent the advantages or disadvantages of the determination methods).

[0098] Determination method 1: address rearrangement.

[0099] In some embodiments, the above step 222 can be implemented as follows: for the i-th first storage address among the m first storage addresses, obtain the last n bits of the i-th first storage address, where the last bit of the last n bits is used to indicate the sampling point index of the sampling point corresponding to the i-th first storage address, and the first n-1 bits of the last n bits are used to indicate the pixel point index of the pixel point corresponding to the i-th first storage address, where both i and n are positive integers; adjust the order of the bits in the last n bits to determine the second storage address corresponding to the i-th first storage address; set i=i+1, and re-enter the step of obtaining the last n bits of the i-th first storage address and start executing until m second storage addresses are determined.

[0100] Optionally, n is related to the number of sampling points corresponding to m sampling points. For example, ,or, .

[0101] Optionally, the sampling point index is used to indicate the index of the sampling point in its corresponding pixel point. The pixel point index is used to indicate the index of the pixel point in the image or image block. The sampling point index has nothing to do with the position of the sampling point in the pixel point; in other words, there is no strong correlation between the sampling point index and the position of the sampling point in the pixel point. Figure 7 The three types of sampling point positions and sampling point indexes within a pixel are shown in FIG. Figure 7 Part (1) shows the case of using MSAA2 technology and Figure 7 For the case of using MSAA8 as shown in part (3), if the mapping rule of the compression unit is based on standard sampling position mapping, then for Figure 7 Part (1) and Figure 7 In the case shown in part (2), if the sampling point index is arranged in the storage unit, Figure 5 In the situation shown in FIG, that is, due to the loss of the sampling point position, the compression unit will not be able to correctly restore the sampling point in the image or image block, so it is necessary to rearrange the m sampling points already stored in the storage unit.

[0102] Optionally, since the first storage address has a large number of addresses, usually greater than or much greater than n, only the last n bits of the first storage address are extracted. Since m first storage addresses can indicate the first arrangement, the first part of these last n bits (i.e., the first n-1 bits) represents the index of each pixel in the image or image block, i.e., the pixel index; and the second part of these last n bits (i.e., the nth bit, or the last bit) represents the index of the sampling point in the pixel, i.e., the sampling point index.

[0103] Optionally, adjusting the order of the bits in the n bits to determine the second storage address corresponding to the i-th first storage address includes: adjusting the order of the bits in the n bits to determine the last n bits of the second storage address corresponding to the i-th first storage address; and determining the i-th second storage address based on the last n bits of the i-th second storage address. Optionally, the second storage address is a simulated storage address, i.e., the second storage address is primarily used to indicate the position of its corresponding sampling point among the m sampling points. Therefore, the address bits of the second storage address may be different from the address bits of the first storage address. For example, if the i-th second storage address only includes n bits, then adjusting the order of the bits in the n bits to determine the last n bits of the second storage address corresponding to the i-th first storage address (i.e., determining the i-th second storage address). Alternatively, if the second storage address is an actual storage address, i.e., the i-th sampling point will be stored at the storage location corresponding to the second storage address after rearrangement, then determining the i-th second storage address based on the last n bits of the i-th second storage address and the i-th first storage address. For example, if both the first and second storage addresses include m bits, the first mn bits of the i-th first storage address are concatenated with the last n bits of the i-th second storage address to obtain the i-th second storage address. That is, the i-th second storage address is the first mn bits of the i-th first storage address + the last n bits of the i-th second storage address. The "+" is a connector. For example, if m is 32, n is 4, the i-th first storage address is 0x8000 0001, the last 4 bits of the i-th first storage address are 0x1, i.e., 0b0001, and the last 4 bits of the i-th second storage address are determined to be 0x0, i.e., 0b0000. In this case, the first mn (i.e., 32-4=28) bits of the i-th first storage address are 0x8000000, and the resulting i-th second storage address after concatenation is 0x8000 0000. In this case, the m sampling points within a continuous storage location in the storage unit are removed, rearranged, and then stored back into the continuous storage location. However, in actual implementation, the rearranged m sampling points can also be stored in another continuous storage location. In this case, after determining the last n bits of the i-th second storage address, the i-th second storage address should be determined based on the storage address corresponding to the storage location to be stored. It should be noted that the embodiments of the present application use the example of removing m sampling points from a continuous storage location in the storage unit, rearranging them, and then storing them back into the continuous storage location as an example, but the scope of protection of the embodiments of the present application is not limited to this.

[0104] Exemplarily, for the i-th sampling point among the m sampling points, it corresponds to the i-th first storage address. Assume that the first storage address has 32 bits, such as the i-th first storage address is 0x8000 0001, and assume that n is 4. Since 1 hexadecimal bit can be represented by 4 binary bits, the last 4 bits of the i-th first storage address are 0x1, that is, 0b0001, where the first 3 bits "000" indicate that the pixel index of the pixel corresponding to the i-th sampling point is "000", that is, 0b000=0, that is, the pixel index is 0; the fourth bit "1" indicates that the sampling point index corresponding to the i-th sampling point is "1", that is, 0b1=1, that is, the sampling point index is 1. The i-th second storage address is obtained by adjusting the last 4 bits of the i-th first storage address, so that the i-th second storage address can be mapped to the correct position of the i-th sampling point in the image block according to the mapping rule. For example, the correct position of the i-th sampling point in the image block is (0, 0). If the mapping rule is that (0, 0) in the image block is mapped to the position 0b0000 of the storage unit, then the last 4 bits of the i-th second storage address are 0b0000.

[0105] Optionally, the order of the bits in the last n bits is adjusted to determine the second storage address corresponding to the i-th first storage address; or, in other words, the order of the bits in the last n bits is adjusted so that the last n bits are used to indicate the position of the sampling point in the image or image block; or, the order of the bits in the last n bits is adjusted so that the last n bits are used to indicate the position of the sampling point in at least one pixel.

[0106] Next, the method of adjusting each bit in the n bits is described.

[0107] In some embodiments, adjusting the order of each bit in the last n bits to determine the second storage address corresponding to the i-th first storage address includes: inverting the last bit in the last n bits; starting numbering from the last bit to obtain multiple odd bits and multiple even bits; swapping the j-th odd bit and the j-th even bit, the j-th odd bit is the j-th odd bit from right to left in the last n bits, and the j-th even bit is the j-th even bit from right to left in the last n bits, where j is a positive integer; determining the second storage address corresponding to the i-th first storage address based on the last n bits after swapping the order of the bits.

[0108] Optionally, numbering begins with the last digit to obtain a plurality of odd digits and a plurality of even digits; this can be understood as numbering from right to left to obtain a plurality of odd digits and a plurality of even digits. Optionally, numbering begins at 0, or, numbering begins at 1. If numbering begins at 0, the plurality of even digits may include or exclude the bit numbered 0.

[0109] Optionally, the order of the bits in the n bits is adjusted to determine the second storage address corresponding to the i-th first storage address. From the perspective of the image block, the m sampling points in the image block are regarded as basic elements and the m sampling points in the image block are re-encoded using Morton coding.

[0110] Optionally, the last bit of the last n bits is inverted because the embodiment of the present application is based on Figure 7 Part (1) shows that a pixel point includes 2 sampling points, and the sampling point index is also as follows Figure 7 In the method shown in part (1), the sampling point index of the sampling point located at the top is 1, and the sampling point index of the sampling point located at the bottom is 0. After inversion, it can be converted to the sampling point located at the top corresponding to 0 and the sampling point located at the bottom corresponding to 1. In other words, the original sampling point index is as follows Figure 7 Part (1) shows that the sampling point index of the sampling point on the left is 1, and the sampling point index of the sampling point on the right is 0. After negation, it can be converted to the sampling point index of the sampling point on the left is 0, and the sampling point index of the sampling point on the right is 1.

[0111] Exemplarily, n is 4, and the last four bits of the i-th first storage address are, from right to left, the first bit, the second bit, the third bit, and the fourth bit, respectively. The second bit, the third bit, and the fourth bit are used to indicate the pixel point index of the sampling point corresponding to the i-th storage address, and the first bit is used to indicate the sampling point index of the sampling point corresponding to the i-th first storage address; inverting the last bit of the last n bits includes: inverting the first bit to obtain the inverted first bit; swapping the j-th odd bit and the j-th even bit includes: swapping the fourth bit and the third bit, and swapping the second bit and the inverted first bit.

[0112] For example, Figure 8 As shown, for the image block 50, it includes 8 pixels, each pixel includes 2 sampling points, and the sampling point index is based on the above Figure 7 In the image block 50, the two sampling points in one pixel are regarded as upper and lower, but these two sampling points are actually Figure 7 The diagonal relationship shown in Figure 8 In the related art, at least one pixel included in the image block 50 is arranged in an interlaced manner, that is, for the pixel in the memory 20, the pixel index is designed according to the interlaced arrangement, that is, the pixel index can determine the position information of the pixel in the image block 50 according to the mapping rule, but for the two sampling points included in the pixel, they are stored according to the sampling point index. The sampling points are arranged according to the first arrangement method, such as Figure 8As shown in the storage relationship 51 shown in memory 20 (i.e., storage unit), each pixel corresponds to two storage locations. The eight pixels are stored according to the mapping rule satisfied by the pixel in image block 50. The two sampling points included in each pixel are sequentially stored in the two storage locations corresponding to the pixel according to the sampling point index of the sampling point. The storage location of a pixel, or the pixel index of the pixel, is obtained by performing Morton coding based on the pixel's position in image block 50.

[0113] Among them, Morton coding is an encoding method that converts multidimensional data into one-dimensional data. Morton coding defines a Z-shaped space-filling curve, so Morton coding is often also called a Z-order curve. In N-dimensional space, coordinates close to each other have close Morton codes, which can be used to generate a unique index for an integer pair. For example, the Morton code generated by Morton coding for a coordinate point in a coordinate system can uniquely index the corresponding point. Figure 9 As shown, for the 8 pixels in the image or image block, place them in a two-dimensional plane coordinate system, first convert the row and column numbers into binary, Figure 9 Where is the converted binary row and column number, which is numbered starting from 0. Since the image block is arranged in 2×4, 1 bit is required to represent the row number and 2 bits are required to represent the column number. The row number Y takes values ​​0 and 1, while the column number X takes values ​​00, 01, 10, and 11. For ease of representation, the binary row and column numbers can be split from right to left, such as the first row number is represented as Y0, the first column number is represented as X0, and the second column number is represented as X1. Then, when the row and column numbers corresponding to each pixel point are known, the index of each pixel point can be obtained. Specifically, the row and column numbers corresponding to each pixel point are interleaved in the order of YX, such as Figure 9 The pixel index of each pixel in is X1Y0X0. For example, the pixel on (0, 0) has X1 as 0, X0 as 0, and Y0 as 0, so its corresponding sampling point index is 0b000=0. For another example, the sampling point on (3, 1) has X1 as 1, X0 as 1, and Y0 as 1, so its corresponding sampling point index is 0b111=7.

[0114] The adjustment operation for the last n bits of the first storage address shown in the embodiment of the present application is to convert the m sampling points arranged in the first arrangement into an arrangement according to their positions in the image or image block. Figure 8The storage relationship 51 in the figure shows the storage relationship of m sampling points arranged according to the sampling point index in the memory 20 in the related art. P0 to P7 represent pixel point indices, which are obtained based on Morton coding, but S0 and S1 represent sampling point indices, which are determined in standard sampling positions or programmable sampling positions and are not obtained according to Morton coding. That is, the pixel index can represent the position of the pixel point in the image or image block, but the sampling point index cannot represent the position of the sampling point in the pixel point or image or image block. In the first storage address of the sampling point indicated by splicing the pixel point index and the sampling point index, the position of the sampling point in the image or image block cannot be represented. Therefore, it is necessary to use the method shown in the embodiment of the present application to re-execute Morton coding on the sampling point based on the known first storage address of the sampling point (pixel point index and sampling point index) to obtain a new second storage address (the actual index of the sampling point in the image or image block). The re-encoded second storage address is as shown in FIG. Figure 8 Storage relationship 52 is shown in FIG. For storage relationships 51 and 52, if a compression unit performs interleaved recovery on the m sampling points corresponding to storage relationship 51, image block 53 will be obtained. Comparing image blocks 50 and 53, it can be seen that storage relationship 51 destroys or loses the position information of the m sampling points. Moreover, due to the arrangement based on the first arrangement method and the interleaved recovery, high-frequency information (dramatic changes in grayscale values) is generated in image block 53, which is not conducive to image compression by the compression unit. However, after adopting the address rearrangement shown in the embodiment of the present application, image block 54 corresponding to storage relationship 52 well retains the low-frequency information in image block 54.

[0115] For example, the address reordering process is as follows: Figure 10As shown, it should be noted that in this example, two sampling points within a pixel are considered to be in a top-to-bottom relationship. For the case of the first arrangement, it is equivalent to performing Morton encoding on at least one pixel and obtaining a first storage address based on the pixel index and the sampling point index. The address rearrangement process is to generate a second storage address for m sampling points. This second storage address will be able to reflect the position information of the sampling point in the image or image block. In other words, it can be understood as re-performing Morton encoding based on the known pixel index and sampling point index to obtain the second storage address of the sampling point or the last n bits of the second storage address. Since the sampling points within a pixel are considered to be in a top-to-bottom relationship, that is, for a 2×4 pixel, the image block needs to be treated as a 4×4 sampling point during the Morton encoding process. In the first arrangement, the first storage address can be expressed as X1Y0X0S0, where X1Y0X0 represents the pixel index and S0 represents the sampling point index, that is, Address_Origin[3:0] = X1Y0X0S0. Since the sampling points within a pixel are regarded as upper and lower relationships, during the Morton encoding process, Y is expanded from one bit to two bits, and the expanded row number can be represented based on the original row number Y0 and the sampling point index S0. The expanded row number can be represented as Y0 ( S0), where ( S0) indicates that the sampling point index is inverted. This is because the sampling point index specified by the standard sampling position is 1 for the upper sampling point and 0 for the lower sampling point, which does not match the actual position of the sampling point in the image block. After the row number is expanded, Morton encoding can be performed based on the expanded row number and the original column number to obtain the second storage address of each sampling point or the last n bits of the second storage address. That is, Address_Remap[3:0]=Y0X1( S0)X0.

[0116] It should be noted that the value of n is related to the number of sampling points included in the image block, or in other words, the value of n is related to the number of binary bits representing the number of rows and columns of the image block. In addition, the above example uses the sampling points included in a pixel as arranged vertically, and the row number Y is expanded as an example; however, in actual implementation, the sampling points included in the pixel can also be regarded as arranged horizontally, and the column number X is expanded. In other words, the embodiment of the present application does not limit the method of determining the second storage address based on the first storage address during the address reordering process, but the scope of protection of the embodiment of the present application is not limited to this.

[0117] In addition, the above example uses 2×4 pixels, each pixel including 2 sampling points, thus expanding to a 4×4 Morton code. However, it can also be used in scenarios such as 1×2 pixels, 2×2 pixels, and 4×4 pixels, and the embodiments of the present application are not limited to this. For scenarios with different numbers of pixels, the main difference lies in the row and column numbers when re-encoding the Morton code. It is only necessary to ensure that the row and column numbers are interleaved. In the case where the binary bit corresponding to the row number is greater than the binary bit corresponding to the column number, or the binary bit corresponding to the column number is greater than the binary bit corresponding to the row number, such as when the row number has 1 bit (Y0) and the column number has 3 bits (X2X1X0), the interleaved order is still used, such as X2X1Y0X0, to obtain the pixel index.

[0118] In some embodiments, when the sampling points in a pixel are regarded as arranged vertically, multiple even bits are used to indicate the rearranged row number, multiple odd bits are used to indicate the rearranged column number, and the multiple even bits include the last bit numbered 0; adjusting the order of each bit in the n bits to determine the second storage address corresponding to the i-th first storage address includes: adjusting the order of each bit in the n bits to obtain the last n bits of the second storage address corresponding to the i-th first storage address, so that the last n bits of the i-th second storage address are the Morton code corresponding to the position information of the i-th sampling point in the image block.

[0119] In some embodiments, when the sampling points in a pixel are considered to be arranged left and right, multiple even-numbered bits are used to indicate the rearranged row number, and multiple odd-numbered bits are used to indicate the rearranged column number. The multiple even-numbered bits do not include the last bit numbered 0, that is, the first odd-numbered bit is numbered 1, the first even-numbered bit is numbered 2, and so on. Adjusting the order of the bits in the n bits to determine the second storage address corresponding to the i-th first storage address includes: adjusting the order of the bits in the n bits to obtain the last n bits of the second storage address corresponding to the i-th first storage address, so that the last n bits of the i-th second storage address are the Morton code corresponding to the position information of the i-th sampling point in the image block.

[0120] In summary, the method provided in the embodiments of the present application illustrates a method for determining m second storage addresses based on address rearrangement. After address rearrangement, a second storage address or the last n bits of the second storage address is obtained, which can represent the positions of the m sampling points in an image or image block. This allows the position information of the m sampling points to be recovered and preserved. In image compression applications, this method can avoid the loss of high-frequency information introduced by the loss of sampling point position information, thereby improving the image compression ratio.

[0121] The specific address rearrangement process is also shown. Based on the pixel index and sampling point index in the last n bits of the first storage address, the known pixel index and sampling point index are re-based on the known pixel index and sampling point index. Morton coding is used, with the sampling point as the basic element in the image block as the encoding condition. The Morton code (i.e., the second storage address or the last n bits of the second storage address) for each sampling point in the image block is obtained, which implicitly contains the position information of each sampling point. This achieves the rearrangement of m sampling points. The address rearrangement process for a 2×4 pixel array is also shown, clarifying the specific steps of the address rearrangement process and how to obtain the Morton code for each sampling point based on the known pixel index and sampling point index. This maintains spatial locality in the image block and improves efficiency in applications that require processing local information in space, such as rendering of detailed areas. Furthermore, multidimensional information is converted to one-dimensional information, optimizing information storage. A unique index associated with the position information of each sampling point is generated, facilitating efficient search and read operations for this unique index.

[0122] Determination method 2: Lookup table.

[0123] In some embodiments, the above step 222 can be implemented as: obtaining a lookup table, the lookup table is used to indicate the mapping relationship between m first storage addresses and m second storage addresses; based on the lookup table, searching for the second storage address corresponding to each first storage address in the m first storage addresses to determine the m second storage addresses.

[0124] Optionally, the lookup table is stored in the terminal device and is preset by a user or a developer.

[0125] Optionally, the terminal device stores at least one lookup table, each containing a different mapping relationship and number of mapping relationships. For example, for standard sampling locations, there are three lookup tables: one for a 2×4 pixel scenario with two sampling points per pixel; one for a 1×2 pixel scenario with eight sampling points per pixel; another for a 2×2 pixel scenario with eight sampling points per pixel; and so on. For programmable sampling locations, there are three lookup tables: one for programming mode 1, one for programming mode 2, and one for programming mode 3, and so on.

[0126] Optionally, the terminal device obtains a lookup table corresponding to the compression unit based on the compression unit.

[0127] Optionally, based on a lookup table, the second storage address corresponding to each first storage address in the m first storage addresses is searched to determine the m second storage addresses, including: for the i-th first storage address in the m first storage addresses, querying the i-th second storage address corresponding to the i-th first storage address from the lookup table; setting i=i+1, re-entering the step of querying the i-th second storage address corresponding to the i-th first storage address from the lookup table and starting execution until m second storage addresses are determined, where i is a positive integer.

[0128] In some embodiments, a lookup table is used to indicate a mapping relationship between the last n bits of m first storage addresses and the last n bits of m second storage addresses; based on the lookup table, the second storage address corresponding to each first storage address in the m first storage addresses is searched to determine the m second storage addresses, including: obtaining the last n bits of the m first storage addresses; based on the last n bits of the m first storage addresses, searching for the last n bits of the second storage address corresponding to the m first storage addresses; based on the last n bits of the second storage address corresponding to the m first storage addresses, determining the m second storage addresses.

[0129] Optionally, the last n bits of the first storage address are used to indicate at least one of a sampling point index and a pixel index of the sampling point corresponding to the first storage address. For example, among the last n bits of the first storage address, the first ns bits represent the pixel index, and the last s bits represent the sampling point index, where s is a positive integer.

[0130] Optionally, the m second storage addresses are determined based on the last n bits of the second storage addresses corresponding to the m first storage addresses, i.e., the last n bits of the m second storage addresses. Optionally, the second storage addresses are simulated storage addresses, i.e., the second storage addresses are primarily used to indicate the position of the corresponding sampling point among the m sampling points. Therefore, the address bits of the second storage addresses may be different from the address bits of the first storage addresses. Alternatively, the second storage addresses are actual storage addresses, i.e., the i-th sampling point will be stored at the storage location corresponding to the second storage address after rearrangement. Then, the i-th second storage address is determined based on the last n bits of the i-th second storage address and the i-th first storage address. For a detailed description of the second storage addresses, please refer to the description in "Determination Method 1: Address Rearrangement" above, which will not be repeated here.

[0131] In some embodiments, the sampling point positions of the m sampling points included in each of the at least one pixel are standard sampling positions; or the sampling point positions of the m sampling points included in each of the at least one pixel are programmable sampling positions.

[0132] Therefore, the following describes a process of determining the second storage address using a lookup table for a standard sampling position and a programmable sampling position.

[0133] (1) Standard sampling position.

[0134] Standard sampling locations such as Figure 7 As shown, the following is an example of a pixel point including 8 sampling points and an image block including 1×2 pixels. For the 8 sampling points in a pixel point, the corresponding second arrangement is as follows Figure 11 That is, the storage order of the eight sampling points S0 to S7 in a pixel in the storage unit should be S3 → S7 → S5 → S0 → S1 → S2 → S4 → S6, that is, they should be stored in accordance with the mapping relationship in the Morton encoding process.

[0135] For example, Figure 12 As shown, for the image block 60, if the m sampling points in the image block 60 are arranged in the first arrangement mode, the storage relationship 61 in the memory 20 is as follows: Figure 12 As shown, if interleaved recovery is performed on the storage relationship 61, an image block 63 will be recovered. Compared with the image block 60, the image block 63 introduces high-frequency information that is not conducive to image compression. If the lookup table shown in Table 1 is used to rearrange the m sampling points to obtain m sampling points arranged in the second arrangement, the following can be obtained: Figure 12 The storage relationship 62 shown in FIG. 1 can be used to restore the image block 64 retaining the low-frequency information in the image block 60 by performing interleaved restoration on the storage relationship 62 .

[0136] Table 1 Lookup table

[0137]

[0138] For example, for m first storage addresses, the last 4 bits of the m first storage addresses are obtained. The first bit of the last 4 bits is used to represent the pixel index, and the last 3 bits are used to represent the sampling point index. That is, the last 4 bits of the first storage address can be expressed as Address_Origin[3:0]=X0S2S1S0. In the process of determining the last 4 bits of the m second storage addresses based on the lookup table, the last 4 bits of the second storage address can be expressed as Address_Remap[3:0]=LUT(Address_Origin[3:0]). That is, based on the last 4 bits of the first storage address, the last 4 bits of the second storage address corresponding to the last 4 bits are retrieved from the lookup table. The above Table 1 is expressed using one hexadecimal digit (equivalent to 4 binary bits) as an example. For example, when the last 4 bits of the first storage address are 0x1, that is, 0b0001, according to Table 1, the last 4 bits of the corresponding second storage address are 0x8, that is, 0b1000. The method of determining other first storage addresses is similar to this, and no examples are given here.

[0139] (2) Programmable sampling position.

[0140] For example, in the case of using programmable sampling positions, if a pixel is set to include 8 sampling points and an image block includes 1×2 pixels, the sampling point positions included in the image block can refer to Figure 13 The sampling point positions in image block 70 are shown in FIG. At this point, the eight sampling points S0 to S7 within a pixel should be stored in the order S7 → S3 → S6 → S2 → S5 → S1 → S4 → S0, that is, they should be stored in the order that satisfies the mapping relationship in the Morton encoding process. For MSAA2X, MSAA4X, and MSAA8X, the hardware will rearrange the 16 sampling points according to the LUT table configured by the driver.

[0141] For example, Figure 13 As shown, for the image block 70, if the m sampling points in the image block 70 are arranged in the first arrangement mode, the storage relationship 71 in the memory 20 is as follows: Figure 13 As shown, if interleaved recovery is performed on the storage relationship 71, an image block 73 will be recovered. Compared with the image block 70, the image block 73 introduces high-frequency information that is not conducive to image compression. If the lookup table shown in Table 2 is used to rearrange the m sampling points to obtain m sampling points arranged in the second arrangement, the following can be obtained: Figure 13 The storage relationship 72 shown in FIG. 7 can be restored by performing interleaving restoration on the storage relationship 72 to restore an image block 74 that retains the low-frequency information in the image block 70 .

[0142] Table 2 Lookup table

[0143]

[0144] For example, for m first storage addresses, the last 4 bits of the m first storage addresses are obtained. The first bit of the last 4 bits is used to represent the pixel index, and the last 3 bits are used to represent the sampling point index. That is, the last 4 bits of the first storage address can be expressed as Address_Origin[3:0]=X0S2S1S0. In the process of determining the last 4 bits of the m second storage addresses based on the lookup table, the last 4 bits of the second storage address can be expressed as Address_Remap[3:0]=LUT_PROG(Address_Origin[3:0]). That is, based on the last 4 bits of the first storage address, the last 4 bits of the second storage address corresponding to the last 4 bits are retrieved from the lookup table. The above Table 1 is expressed using 1 hexadecimal digit (equivalent to 4 binary bits) as an example. For example, when the last 4 bits of the first storage address are 0x1, that is, 0b0001, according to Table 1, the last 4 bits of the corresponding second storage address are 0x8, that is, 0b1000. The method of determining other first storage addresses is similar to this, and no examples are given here.

[0145] In summary, the method provided in the embodiment of the present application directly queries a lookup table when determining the m second storage addresses. This improves the efficiency of determining the second storage addresses compared to determination method 1. Furthermore, the method of determining the second storage addresses based on the lookup table has a wider range of applicable scenarios, improving the usability of the sampling point reordering method based on the lookup table.

[0146] In addition, the lookup table only includes the mapping relationship between the last n bits of the first storage address and the last n bits of the second storage address. Compared with the lookup table including the mapping relationship between m first storage addresses and m second storage addresses, the amount of data in the lookup table is reduced, thereby improving the search efficiency of searching for the second storage address based on the lookup table.

[0147] Furthermore, for standard sampling positions, the method provided by the embodiments of the present application can better restore the position information between sampling points, reducing the probability of high-frequency signals and improving the compression rate. For programmable sampling positions, the method provided by the embodiments of the present application provides the driver with a more flexible means of recovering the position information of the sampling points.

[0148] It should be noted that the above-mentioned "Determination Method 1: Address Rearrangement" and "Determination Method 2: Lookup Table" can be implemented as independent embodiments or as a combined embodiment. For example, for a scenario where a pixel includes two sampling points, the method shown in the above-mentioned "Determination Method 1: Address Rearrangement" can be used for rearrangement. For a scenario where a pixel includes more sampling points, such as four or eight sampling points, and the use of "Determination Method 1: Address Rearrangement" may result in excessive computational complexity, then the "Determination Method 2: Lookup Table" can be used for rearrangement. This embodiment of the present application is not limited to this.

[0149] In some embodiments, the method further includes: acquiring configuration information of an image block, the image block including at least one pixel point, the configuration information of the image block being used to indicate the number of sampling points corresponding to each pixel point in the at least one pixel point.

[0150] Optionally, based on the configuration information of the image block, a determination method of determining the m second storage addresses based on the m first storage addresses (ie, the above-mentioned determination method 1 or determination method 2) is selected.

[0151] Optionally, the configuration information is further used to indicate whether the sampling point position in each pixel is a standard sampling position or a programmable sampling position. Based on the configuration information, a lookup table corresponding to the sampling point position of each pixel is obtained.

[0152] The configuration information is used to indicate information such as the number of sampling points in the pixel, so that the rearrangement method to be used is determined based on the information such as the number of sampling points, thereby improving the diversity and flexibility of the rearrangement method.

[0153] Next, the application of the above rearrangement method in the field of image compression is taken as an example to illustrate the above rearrangement method of sampling points applied in the image compression process.

[0154] Step 1: Read m sampling points arranged in a first arrangement from a storage unit based on a compression unit, where the m sampling points are sampling points in at least one pixel in the compression unit. The first arrangement is an arrangement based on a sampling point index of the m sampling points, where m is a positive integer greater than 1.

[0155] Optionally, the first arrangement is unrelated to a mapping rule of the compression unit. The mapping rule of the compression unit refers to a rule for mapping each sampling point to a different position of its corresponding pixel point after the compression unit reads multiple sampling points from the storage unit; or the mapping rule of the compression unit refers to a rule for mapping each sampling point to a different position of the image or image block after the compression unit reads multiple sampling points from the storage unit.

[0156] Step 2: rearrange the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is based on the positions of the m sampling points in at least one pixel.

[0157] Optionally, the second arrangement is related to a mapping rule of the compression unit.

[0158] In some embodiments, rearranging the m sampling points to obtain the m sampling points arranged in a second arrangement includes: obtaining m first storage addresses of the m sampling points in a storage unit, the m first storage addresses corresponding one-to-one to the m sampling points; determining m second storage addresses based on the m first storage addresses, the second storage addresses corresponding one-to-one to the m sampling points, the m second storage addresses being different from the m first storage addresses; and determining the m sampling points arranged in the second arrangement based on the m second storage addresses.

[0159] In some embodiments, the method for determining the m second storage addresses based on the m first storage addresses can refer to the above-mentioned “determination method one: address reordering” and “determination method two: lookup table”, which will not be repeated here.

[0160] Step 3: Store the m sampling points arranged in the second arrangement mode into a storage unit.

[0161] In step 4, the compression unit retrieves m sampling points arranged in the second arrangement from the storage unit; and restores the image block based on the retrieved m sampling points and the mapping rule of the compression unit.

[0162] Optionally, the sampling point positions of the respective sampling points in the image block restored by the compression unit are the same as or similar to the sampling point positions of the sampling points of the image block before being stored in the storage unit.

[0163] In some embodiments, the sampling point positions of the m sampling points included in each of the at least one pixel are standard sampling positions; or the sampling point positions of the m sampling points included in each of the at least one pixel are programmable sampling positions.

[0164] In some embodiments, the method further includes: obtaining configuration information of an image block, the image block including at least one pixel, the configuration information of the image block indicating the number of sampling points corresponding to each of the at least one pixel. Optionally, the configuration information of the image block indicates at least one of a size of a compression unit, a mapping rule for the compression unit, and a location of a sampling point in each pixel.

[0165] In summary, the methods provided in the embodiments of the present application illustrate an example of applying the methods of the embodiments to the field of image compression. By rearranging the m sampling points originally stored in a storage unit according to a first arrangement (i.e., based on the sampling point index), they are re-arranged into m sampling points stored according to a second arrangement (i.e., based on the position of each of the m sampling points within at least one pixel). The storage of the sampling points incorporates the position information of the sampling points within at least one pixel (or image or image block), enabling the m sampling points arranged in the second arrangement to support various algorithms requiring position information, such as image compression algorithms. This avoids the loss of position information during the storage of the m sampling points, thereby increasing the flexibility of the storage of the m sampling points. Furthermore, the storage of the m sampling points in the second arrangement based on the positions of the m sampling points within at least one pixel is more user-friendly for data access based on position information, thereby improving access efficiency and query performance for the m sampling points in the storage unit. In particular, for image compression algorithms designed for low-frequency information, performing image compression based on m sampling points arranged in the second arrangement rather than performing image compression based on m sampling points arranged in the first arrangement can improve the image compression rate, such as improving the compression rate of an image compression algorithm based on wavelet transform. This is because the first arrangement may introduce high-frequency information that does not exist in the original image or image block, resulting in a decrease in the compression rate.

[0166] Please refer to Figure 14 , which shows a structural block diagram of a sampling point rearrangement device provided by an exemplary embodiment of the present application. The device has the function of implementing the above-mentioned sampling point rearrangement method example, and the function can be implemented by hardware or by hardware executing corresponding software. The device can be the computer device described above, or it can be set in a computer device. Figure 14 As shown, the apparatus may include: an acquisition module 410 , a rearrangement module 420 and a storage module 430 .

[0167] An acquisition module 410 is configured to read, from a storage unit, m sampling points arranged in a first arrangement, where the m sampling points are sampling points in at least one pixel. The first arrangement is an arrangement based on a sampling point index of the m sampling points, where m is a positive integer greater than 1.

[0168] The rearrangement module 420 is configured to rearrange the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is an arrangement based on positions of the m sampling points in the at least one pixel.

[0169] The storage module 430 is configured to store the m sampling points arranged in the second arrangement manner in the storage unit.

[0170] In some embodiments, the rearrangement module 420 is further configured to obtain m first storage addresses of the m sampling points in the storage unit, where the m first storage addresses correspond one-to-one to the m sampling points; determine m second storage addresses based on the m first storage addresses, where the second storage addresses correspond one-to-one to the m sampling points, and the m second storage addresses are different from the m first storage addresses; and determine, based on the m second storage addresses, the m sampling points arranged in a second arrangement.

[0171] In some embodiments, the rearrangement module 420 is further configured to obtain, for an i-th first storage address among the m first storage addresses, the last n bits of the i-th first storage address, where the last bit of the last n bits is used to indicate the sampling point index of the sampling point corresponding to the i-th first storage address, and the first n-1 bits of the last n bits are used to indicate the pixel point index of the pixel point corresponding to the i-th first storage address, where both i and n are positive integers; adjust the order of the bits in the last n bits to determine the second storage address corresponding to the i-th first storage address; set i=i+1, and re-enter the step of obtaining the last n bits of the i-th first storage address and start executing until the m second storage addresses are determined.

[0172] In some embodiments, the rearrangement module 420 is further used to invert the last bit of the last n bits; start numbering from the last bit to obtain multiple odd bits and multiple even bits; exchange the jth odd bit and the jth even bit, the jth odd bit is the jth odd bit from right to left in the last n bits, and the jth even bit is the jth even bit from right to left in the last n bits, and j is a positive integer; based on the last n bits after exchanging the order of the bits, determine the second storage address corresponding to the i-th first storage address.

[0173] In some embodiments, n is 4, and the last four bits of the i-th first storage address are, from right to left, the first bit, the second bit, the third bit, and the fourth bit, respectively. The second bit, the third bit, and the fourth bit are used to indicate the pixel point index of the sampling point corresponding to the i-th storage address, and the first bit is used to indicate the sampling point index of the sampling point corresponding to the i-th first storage address. The rearrangement module 420 is further used to invert the first bit to obtain the inverted first bit; swap the fourth bit with the third bit, and swap the second bit with the inverted first bit.

[0174] In some embodiments, the rearrangement module 420 is further used to obtain a lookup table, which is used to indicate the mapping relationship between the m first storage addresses and the m second storage addresses; based on the lookup table, the second storage address corresponding to each first storage address in the m first storage addresses is searched to determine the m second storage addresses.

[0175] In some embodiments, the lookup table is used to indicate the mapping relationship between the last n bits of the m first storage addresses and the last n bits of the m second storage addresses; the rearrangement module 420 is also used to obtain the last n bits of the m first storage addresses; based on the last n bits of the m first storage addresses, search for the last n bits of the second storage addresses corresponding to the m first storage addresses; based on the last n bits of the second storage addresses corresponding to the m first storage addresses, determine the m second storage addresses.

[0176] In some embodiments, the sampling point positions of the m sampling points included in each of the at least one pixel are standard sampling positions; or the sampling point positions of the m sampling points included in each of the at least one pixel are programmable sampling positions.

[0177] In some embodiments, the acquisition module 410 is further used to acquire configuration information of an image block, where the image block includes at least one pixel point, and the configuration information of the image block is used to indicate the number of sampling points corresponding to each pixel point in the at least one pixel point.

[0178] In summary, the apparatus provided by the embodiments of the present application illustrates an example of applying the methods described in the embodiments to the field of image compression. By rearranging m sampling points originally stored in a storage unit according to a first arrangement (i.e., based on sampling point indexes), the apparatus rearranges the m sampling points to be stored according to a second arrangement (i.e., based on the position of each of the m sampling points within at least one pixel). The storage of the sampling points incorporates the position information of the sampling points within at least one pixel (or image or image block), enabling the m sampling points arranged in the second arrangement to support various algorithms requiring position information, such as image compression algorithms. This avoids the loss of position information during the storage of the m sampling points, thereby increasing the flexibility of the storage of the m sampling points. Furthermore, the storage of the m sampling points in the second arrangement based on the positions of the m sampling points within at least one pixel is more user-friendly for data access based on position information, thereby improving access efficiency and query performance for the m sampling points in the storage unit.

[0179] It should be noted that the apparatus provided in the above embodiments is merely illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0180] Figure 15 A schematic structural diagram of a computer device provided by an exemplary embodiment of the present application is shown.

[0181] The computer device 800 includes a central processing unit (CPU) 801, a system memory 804 including a random access memory (RAM) 802 and a read-only memory (ROM) 803, and a system bus 805 connecting the system memory 804 and the CPU 801. The computer device 800 also includes a basic input / output system (I / O system) 806 that facilitates information transmission between various components within the computer device, and a mass storage device 807 for storing an operating system 813, application programs 814, and other program modules 815.

[0182] The basic input / output system 806 includes a display 808 for displaying information and an input device 809 such as a mouse and keyboard for user input. The display 808 and the input device 809 are connected to the central processing unit 801 via an input / output controller 810 connected to the system bus 805. The basic input / output system 806 may also include an input / output controller 810 for receiving and processing input from a variety of other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 810 also provides output to a display screen, printer, or other types of output devices.

[0183] The mass storage device 807 is connected to the central processing unit 801 via a mass storage controller (not shown) connected to the system bus 805. The mass storage device 807 and its associated computer-readable storage medium provide non-volatile storage for the computer device 800. In other words, the mass storage device 807 may include a computer-readable storage medium (not shown) such as a hard disk or a compact disc read-only memory (CD-ROM) drive.

[0184] Without loss of generality, the computer-readable storage medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable storage instructions, data structures, program modules, or other data. Computer storage media include RAM, ROM, Erasable Programmable Read-Only Memory (EPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other solid-state storage technologies, CD-ROM, Digital Versatile Disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices. Of course, those skilled in the art will appreciate that computer storage media are not limited to the aforementioned types. The aforementioned system memory 804 and mass storage device 807 may be collectively referred to as memory.

[0185] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 801. The one or more programs contain instructions for implementing the above-mentioned method embodiments. The central processing unit 801 executes the one or more programs to implement the methods provided by the above-mentioned method embodiments.

[0186] According to various embodiments of the present application, the computer device 800 may also be connected to a remote computer device on a network, such as the Internet, for operation. Specifically, the computer device 800 may be connected to a network 812 via a network interface unit 811 connected to the system bus 805. Alternatively, the network interface unit 811 may be used to connect to other types of networks or remote computer device systems (not shown).

[0187] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0188] In an exemplary embodiment, a non-transitory computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the computer program implements the above-mentioned sampling point rearrangement method.

[0189] In an exemplary embodiment, a computer program product is further provided. When the computer program product is executed by a processor, it is used to implement the above-mentioned sampling point rearrangement method.

[0190] On the other hand, an embodiment of the present application provides a graphics card, which includes the compression unit described in the above embodiments.

[0191] It should be understood that the "multiple" mentioned in this article refers to two or more. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution order between the steps. In some other embodiments, the above steps may also be executed in a non-numbered order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the opposite order to that shown in the figure. This embodiment of the application is not limited to this.

[0192] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for rearranging sampling points, characterized in that: The method comprises: Reading m sampling points arranged according to a first arrangement from a storage unit, where the m sampling points are sampling points in at least one pixel, the first arrangement is an arrangement based on a sampling point index of the m sampling points, m is a positive integer greater than 1, and sampling point positions of the m sampling points included in each pixel of the at least one pixel are standard sampling positions, or sampling point positions of the m sampling points included in each pixel of the at least one pixel are programmable sampling positions; Rearranging the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is an arrangement based on positions of the m sampling points in the at least one pixel; Storing the m sampling points arranged in the second arrangement manner in the storage unit; The rearranging of the m sampling points to obtain m sampling points arranged in a second arrangement manner includes: Obtaining m first storage addresses of the m sampling points in the storage unit, where the m first storage addresses correspond one-to-one to the m sampling points; Determine m second storage addresses based on the m first storage addresses, where the second storage addresses correspond one-to-one to the m sampling points, the m second storage addresses are different from the m first storage addresses, and the m second storage addresses are obtained by adjusting the last n bits of the m first storage addresses, where the last n bits of each of the m first storage addresses are used to indicate at least one of a sampling point index and a pixel point index of the sampling point corresponding to the first storage address; Based on the m second storage addresses, the m sampling points arranged in the second arrangement manner are determined.

2. The method according to claim 1, characterized in that The determining m second storage addresses based on the m first storage addresses includes: For an i-th first storage address among the m first storage addresses, obtain last n bits of the i-th first storage address, where the last bit of the last n bits is used to indicate a sampling point index of a sampling point corresponding to the i-th first storage address, and first n-1 bits of the last n bits are used to indicate a pixel point index of a pixel corresponding to the i-th first storage address, where i and n are both positive integers; Adjusting the order of the bits in the last n bits to determine the second storage address corresponding to the i-th first storage address; Let i=i+1, and re-enter the step of obtaining the last n bits of the i-th first storage address and start executing until the m second storage addresses are determined.

3. The method according to claim 2, characterized in that The adjusting the order of the bits in the last n bits to determine the second storage address corresponding to the i-th first storage address includes: Invert the last bit of the last n bits; Starting from the last digit, numbering is performed to obtain a plurality of odd digits and a plurality of even digits; Swap the jth odd bit and the jth even bit, where the jth odd bit is the jth odd bit from right to left in the last n bits, and the jth even bit is the jth even bit from right to left in the last n bits, where j is a positive integer; Based on the last n bits after the order of the bits is swapped, the second storage address corresponding to the i-th first storage address is determined.

4. The method according to claim 3, characterized in that Where n is 4, the last four bits of the i-th first storage address are respectively the first bit, the second bit, the third bit, and the fourth bit from right to left, the second bit, the third bit, and the fourth bit are used to indicate the pixel point index of the sampling point corresponding to the i-th storage address, and the first bit is used to indicate the sampling point index of the sampling point corresponding to the i-th first storage address; The step of inverting the last bit of the last n bits includes: inverting the first bit to obtain an inverted first bit; The exchanging of the j-th odd bit and the j-th even bit comprises: The fourth bit and the third bit are swapped, and the second bit and the inverted first bit are swapped.

5. The method according to claim 1, characterized in that The determining m second storage addresses based on the m first storage addresses includes: Obtaining a lookup table, where the lookup table is used to indicate a mapping relationship between the m first storage addresses and the m second storage addresses; Based on the lookup table, the second storage address corresponding to each of the m first storage addresses is searched to determine the m second storage addresses.

6. The method according to claim 5, characterized in that The lookup table is used to indicate a mapping relationship between the last n bits of the m first storage addresses and the last n bits of the m second storage addresses; The step of searching, based on the lookup table, for a second storage address corresponding to each of the m first storage addresses to determine the m second storage addresses comprises: Obtaining the last n bits of the m first storage addresses; Based on the last n bits of the m first storage addresses, searching for the last n bits of the second storage addresses corresponding to the m first storage addresses; The m second storage addresses are determined based on the last n bits of the second storage addresses corresponding to the m first storage addresses.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Configuration information of an image block is acquired, where the image block includes at least one pixel point, and the configuration information of the image block is used to indicate the number of sampling points corresponding to each pixel point in the at least one pixel point.

8. A sampling point rearrangement device, characterized in that: The device comprises: an acquisition module, configured to read from a storage unit m sampling points arranged according to a first arrangement, wherein the m sampling points are sampling points in at least one pixel, the first arrangement being an arrangement based on a sampling point index of the m sampling points, m being a positive integer greater than 1, and the sampling point positions of the m sampling points included in each pixel of the at least one pixel being standard sampling positions, or the sampling point positions of the m sampling points included in each pixel of the at least one pixel being programmable sampling positions; a rearrangement module, configured to rearrange the m sampling points to obtain m sampling points arranged in a second arrangement, where the second arrangement is an arrangement based on positions of the m sampling points in the at least one pixel; A storage module, configured to store the m sampling points arranged in the second arrangement manner in the storage unit; The rearrangement module is further configured to obtain m first storage addresses of the m sampling points in the storage unit, the m first storage addresses corresponding one-to-one to the m sampling points; determine m second storage addresses based on the m first storage addresses, the second storage addresses corresponding one-to-one to the m sampling points, the m second storage addresses being different from the m first storage addresses, the m second storage addresses being obtained by adjusting the last n bits of the m first storage addresses, the last n bits of each of the m first storage addresses being used to indicate at least one of a sampling point index and a pixel point index of the sampling point corresponding to the first storage address; and determine the m sampling points arranged in the second arrangement based on the m second storage addresses.

9. A computer device, characterized in that: The computer device includes: a processor and a memory, wherein the memory stores at least one program; the processor is configured to execute the at least one program in the memory to implement the sampling point rearrangement method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores executable instructions, which are loaded and executed by a processor to implement the sampling point rearrangement method according to any one of claims 1 to 7.

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