Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof. The pixel driving circuit in the display device comprises a driving transistor connected between a first voltage line and a light-emitting element, a first reset transistor and a data writing transistor which are electrically connected to a grid electrode of the driving transistor, and a second reset transistor electrically connected to a source electrode of the driving transistor, the first switch transistor is electrically connected between the first voltage line and the drain electrode of the driving transistor, when the first reset transistor and the data write-in transistor are conducted in sequence, the driving transistor is conducted, and the first switch transistor is conducted and cut off; the compensation effect on the threshold voltage of the driving transistors in the pixel driving circuits is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display device and a driving method thereof. Background Art

[0002] In current self-luminous display products, when the pixel driving circuit operates in the data writing stage, the driving transistor is in the on state, resulting in electrical conduction between the high-voltage signal line and the source electrode of the driving transistor. As a result, the potential of the source electrode of the driving transistor is continuously charged by the high-voltage signal, causing the gate-source voltage of the driving transistor to include a distortion voltage caused by the elevation of its source electrode potential in the data writing stage. This distortion voltage is related to the threshold voltage of the driving transistor, weakening the compensation effect for the threshold voltage of the driving transistor in the pixel driving circuit. Summary of the Invention

[0003] An object of the present invention is to provide a display device and a driving method thereof to improve the problem of weakened compensation effect for the threshold voltage of the pixel driving circuit in existing self-luminous display products.

[0004] An embodiment of the present invention provides a display device, including a plurality of sub-pixels. The sub-pixels include a light-emitting element and a pixel driving circuit electrically connected thereto. The pixel driving circuit includes:

[0005] A driving transistor, one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element;

[0006] A first reset transistor, electrically connected to the gate of the driving transistor, for transmitting a first reset signal to the gate of the driving transistor according to a first control signal;

[0007] A second reset transistor, electrically connected to the other of the source and drain of the driving transistor, for transmitting a second reset signal to the other of the source and drain of the driving transistor according to a second control signal;

[0008] A first switching transistor, electrically connected between the first voltage line and one of the source and drain of the driving transistor, for controlling the formation of a current path between the first voltage line and one of the source and drain of the driving transistor according to a third control signal;

[0009] A data writing transistor, electrically connected to the gate of the driving transistor, for transmitting a data signal to the gate of the driving transistor according to a fourth control signal;

[0010] When the first reset transistor is turned on in response to the first control signal, the driving transistor is turned on, and the first switching transistor is turned on in response to the third control signal;

[0011] When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal.

[0012] In some embodiments, before the first reset transistor is turned on in response to the first control signal, the second reset transistor is turned on in response to the second control signal.

[0013] In some embodiments, the period of the pulse of the first control signal is the same as the period of the pulse corresponding to the third control signal.

[0014] In some embodiments, after the data writing transistor is turned on in response to the fourth control signal, the first switching transistor is turned on in response to the third control signal.

[0015] In some embodiments, the pixel driving circuit further includes:

[0016] A second switching transistor, electrically connected between the first voltage line and one of the source and drain of the driving transistor, for controlling a current path to be formed between the first voltage line and one of the source and drain of the driving transistor according to a fifth control signal;

[0017] When the first switching transistor is turned off and the data writing transistor is turned on, the second switching transistor is turned off in response to the fifth control signal;

[0018] After the data writing transistor is turned on in response to the fourth control signal, the second switching transistor is turned on in response to the fifth control signal.

[0019] In some embodiments, the pixel driving circuit further includes:

[0020] A third switching transistor, electrically connected between the light emitting element and the other of the source and drain of the driving transistor, for controlling a current path to be formed between the light emitting element and the other of the source and drain of the driving transistor according to the fifth control signal;

[0021] When the second reset transistor is turned on in response to the second control signal, the third switching transistor is turned off in response to the fifth control signal.

[0022] In some embodiments, one of the anode and cathode of the light emitting element is electrically connected to the second voltage line, and the other is electrically connected to the other of the source and drain of the driving transistor;

[0023] The pixel driving circuit further includes:

[0024] A third reset transistor is electrically connected to the other one of the anode and the cathode of the light-emitting element, and is configured to transmit a third reset signal to the other one of the anode and the cathode of the light-emitting element according to the second control signal.

[0025] In some embodiments, the data signal includes a plurality of data voltages corresponding to a plurality of the light-emitting elements, and the fourth control signal includes a first gate pulse for controlling conduction of the corresponding data writing transistor;

[0026] Wherein, a start time of the first gate pulse is ahead of a start time of a period in which the corresponding data voltage is located.

[0027] In some embodiments, the third control signal includes a second gate pulse for controlling conduction of the corresponding first switching transistor;

[0028] Wherein, an interval between an end time of the second gate pulse and a start time of the first gate pulse is greater than or equal to 0.1×H, and the H is a driving period of one row of sub-pixels of the display device within one frame.

[0029] In some embodiments, pulse widths of the first gate pulses at different refresh rates are different.

[0030] An embodiment of the present invention provides a driving method for a display device, which is applied to a pixel driving circuit and a light-emitting element electrically connected in the display device. The pixel driving circuit includes:

[0031] A driving transistor, one of a source and a drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element;

[0032] A first reset transistor, which is electrically connected to a gate of the driving transistor;

[0033] A second reset transistor, which is electrically connected to the other one of the source and the drain of the driving transistor;

[0034] A first switching transistor, which is electrically connected between the first voltage line and one of the source and the drain of the driving transistor;

[0035] A data writing transistor, which is electrically connected to a gate of the driving transistor;

[0036] The driving method of the display device includes:

[0037] In a first stage, the first reset transistor is turned on in response to the first control signal to transmit a first reset signal to the gate of the driving transistor, so that the driving transistor is turned on, and the first switching transistor is turned on in response to the third control signal;

[0038] In a second stage after the first stage, the data writing transistor is turned on in response to the fourth control signal so that a data signal is transmitted to the driving transistor.

[0039] The present invention provides a display device and a driving method thereof. By providing a first switching transistor electrically connected between a first voltage line and the drain of a driving transistor, and when a first reset transistor and a data writing transistor are turned on in sequence, the driving transistor is always turned on, and the first switching transistor is turned on and off respectively, the potential of the source of the driving transistor can rise to "Vref - Vth" and then remain unchanged when a data voltage is written, preventing the source of the driving transistor from being continuously charged by the first voltage signal and causing its potential to rise. When a light-emitting element emits light, the potential of the source of the driving transistor can compensate for the threshold voltage of the driving transistor, improving the compensation effect for the threshold voltages of driving transistors in multiple pixel driving circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of the architecture of a display device provided by an embodiment of the present invention.

[0041] Figure 2 and Figure 3 They are respectively a circuit diagram of a sub-pixel provided by a comparative example of the present invention and a corresponding timing diagram.

[0042] Figure 4 and Figure 5 They are respectively a circuit diagram of a sub-pixel provided by an embodiment of the present invention and a corresponding timing diagram.

[0043] Figure 6 and Figure 7 They are respectively a circuit diagram of a sub-pixel provided by another embodiment of the present invention and a corresponding timing diagram.

[0044] Figure 8 It is a flowchart of a driving method of a display device provided by an embodiment of the present invention.

[0045] Figure 9 It is a curve diagram of the potential of the source of a driving transistor corresponding to multiple sub-pixels provided by a comparative example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0047] In the description of the present invention, it should be understood that terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined. "Electrically connected" means that there is conduction between the two, and it does not limit whether it is a direct connection or an indirect connection.

[0048] In addition, it should also be noted that the drawings only provide structures and steps that are relatively closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the inventive points clear at a glance, rather than indicating that the actual device is exactly the same as the drawings, and it is not a limitation of the actual device. Figure 1 As such, it is not a limitation of the actual device.

[0049] The present invention provides a display device, and the display device may include, but is not limited to, the following embodiments and combinations between the following embodiments.

[0050] In some embodiments, in combination with Figure 1 、 Figure 4 and Figure 6 as shown, the display device 100 includes a plurality of sub-pixels 10. The sub-pixels 10 include a light-emitting element 101 and a pixel driving circuit 102 that are electrically connected. The pixel driving circuit 102 includes: a driving transistor T1, one of the source s and the drain d of the driving transistor T1 is electrically connected to a first voltage line (for transmitting a first voltage signal VDD), and the other is electrically connected to the light-emitting element 101; a first reset transistor T2, electrically connected to the gate g of the driving transistor T1, for transmitting a first reset signal Vref to the gate g of the driving transistor T1 according to a first control signal REF; a second reset transistor T3, electrically connected to the other of the source s and the drain g of the driving transistor T1, for transmitting a second reset signal Vini to the other of the source s and the drain g of the driving transistor T1 according to a second control signal INI; a first switching transistor T4, electrically connected between the first voltage line and one of the source s and the drain d of the driving transistor T1, for controlling a current path to be formed between the first voltage line and one of the source s and the drain d of the driving transistor T1 according to a third control signal REF'; a data writing transistor T5, electrically connected to the gate g of the driving transistor T1, for transmitting a data signal Vdata to the gate g of the driving transistor T1 according to a fourth control signal Gn; as Figure 5 and Figure 6As shown, when the first reset transistor T2 is turned on in response to the first control signal REF, the driving transistor T1 is turned on, and the first switching transistor T4 is turned on in response to the third control signal REF'; when the data writing transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switching transistor T4 is turned off in response to the third control signal REF'.

[0051] Among them, the display device 100 is but not limited to an organic self-luminous display device or an inorganic self-luminous direct display device. As Figure 1 shown, taking the example of the arrangement of a plurality of sub-pixels 10 in the display panel 20 of the display device 100, the display device 100 may further include a plurality of gate lines 30, a plurality of data lines 40, a source driver 50 electrically connected to the plurality of data lines 40, and a gate driver 60 electrically connected to the plurality of gate lines 30. Among them, the plurality of gate lines 30, the plurality of data lines 40, and the plurality of sub-pixels 10 may also be located on the substrate of the display panel 20. The gate driver 60 may be a gate driving circuit located on the substrate of the display panel 20 or a chip provided independently of the display panel 20 ( Figure 1 only the former case is shown as an example).

[0052] Specifically, each gate line 30 is electrically connected to a plurality of pixel driving circuits 102 in a plurality of sub-pixels 10 in the corresponding row to output at least the corresponding fourth control signal Gn as described above to them. In each frame, the fourth control signal Gn includes a first gate pulse p1 for controlling the corresponding plurality of pixel driving circuits 102 to turn on. The pixel driving circuits 102 in multiple rows of sub-pixels 10 are sequentially turned on under the control of the plurality of first gate pulses p1 in the plurality of fourth control signals Gn; each data line 40 is connected to a plurality of pixel driving circuits 102 in a plurality of sub-pixels 10 in the corresponding column to output the corresponding data signal Vdata as described above to them. The data signal Vdata includes a plurality of data voltages Vd1 corresponding to the corresponding plurality of sub-pixels 10 and an invalid voltage Vd2 between two adjacent data voltages Vd1. The plurality of data signals Vdata corresponding to multiple columns of sub-pixels 10 are set to transmit the corresponding plurality of data voltages Vd1 to the plurality of sub-pixels 10 in the corresponding row through the plurality of data lines 40 respectively when each row of sub-pixels 10 is turned on. Among them, the invalid voltage Vd2 is used to separate the plurality of data voltages Vd1 to reduce the risk of mischarging of the data voltage Vd1.

[0053] Specifically, the gate driver 60 may include a multi-level gate driving module corresponding to multiple rows of sub-pixels 10. Each gate driving module includes multiple gate driving units respectively used for generating multiple gate signals. The multiple gate signals may include, but are not limited to, the above-mentioned first control signal REF, second control signal INI, third control signal REF', and fourth control signal Gn. That is, the multiple sub-pixels 10 in the same row are controlled by the multiple gate signals output by the same gate driving module. The multiple gate signals can respectively control the turn-on periods of multiple transistors in the multiple pixel driving circuits 102 of this row, and cooperate with the multiple data signals Vdata output by the source driver 50 to realize the light emission of the light-emitting elements 101 in this row. And so on, the multiple pixel driving circuits 102 work in sequence under the control of the corresponding multiple gate driving modules and are sequentially loaded with the corresponding multiple data voltages Vd1 in the multiple data signals Vdata, so as to display a frame of picture.

[0054] It should be noted that, as Figure 2 and Figure 3 shown, compared with the pixel circuit 1-2 in the comparative example provided by the present invention and the above Figure 4 shown embodiment, the above-mentioned first switching transistor T4 is not provided between the first voltage line and one of the source s and drain d of the driving transistor T1, that is, they are electrically connected by a wire. Each sub-pixel 10 at least includes the following working stages:

[0055] The first comparison period t1': the second control signal INI is at the corresponding high potential, the second reset transistor T3 is turned on, and the second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it;

[0056] The second comparison period t2' (including the above-mentioned first stage): the second control signal INI and the first control signal REF are both at the corresponding high potential. The second reset transistor T3 remains turned on, and the first reset transistor T2 is turned on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is turned on, and the first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the driving transistor T1 to raise its potential until the driving transistor T1 is turned off, and the potential of the source s of the driving transistor T1 is "Vref - Vth";

[0057] During the third comparison period t3', the fourth control signal Gn is at the corresponding high potential, the data writing transistor T5 is turned on, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 remains turned on. However, since there is an electrical connection between the first voltage line and the driving transistor T1, the first voltage signal VDD has been raising the potential of the source s of the driving transistor T1, resulting in a distortion of the final gate-source voltage Vgs of the driving transistor T1, including a ΔV increase in the potential of the source s of the driving transistor T1 being lifted, causing Vgs to be approximately Vdata - (Vref - Vth + ΔV);

[0058] During the fourth comparison period t4', the fourth control signal Gn is at the corresponding low potential, the data writing transistor T5 is turned off, and the driving transistor T1 is turned on to form a current path between the first voltage line and the second voltage line. The driving transistor T1 generates a driving current flowing through the light-emitting element 101, and the light-emitting element 101 emits light. The magnitude of the driving current is approximately k × {[Vdata - (Vref - Vth)] - Vth} 2 ≈k × (Vdata - Vref - ΔV) 2 , where k is a constant.

[0059] Therefore, as Figure 9 shown, it schematically shows a curve graph of the potential Vs of the source s of the driving transistor T1 in multiple sub-pixels 10 of the same display panel 20 in the comparative example. The abscissa is the time when the sub-pixel 10 operates, and the ordinate is the potential Vs of the source s of the driving transistor T1.

[0060] Combined with the above analysis of the working stages of the comparative example, during the third comparison period t3', since the first switching transistor T4 is not set to be turned off to form a current break between the first voltage line and the source s of the driving transistor T1, that is, there is a current path between the first voltage line and the source s of the driving transistor T1 during the third comparison period t3' of the comparative example, resulting in the potential Vs of the source s of the driving transistor T1 of each sub-pixel 10 being charged by the first voltage signal VDD and its potential being lifted, and the degree of lifting is related to the threshold voltage Vth of its respective driving transistor T1. For example, L1 to L5 are the curve graphs of the potential Vs of the source s of the driving transistor T1 of 5 sub-pixels 10. Since each of the threshold voltages Vth of the 5 driving transistors T1 corresponding to L1 to L5 is different from the former, there are differences of ΔV1, ΔV2, ΔV3, ΔV4 between the potential Vs of the source s of the driving transistor T1 of each of L1 to L5 during the third comparison period t3 and the former, resulting in differences still existing in the potential Vs of the source s of the 5 driving transistors T1 in the fourth period t4, and finally resulting in differences in the values of the corresponding 5 driving currents, and it is impossible to effectively compensate for the threshold voltages Vth of all the driving transistors T1.

[0061] Among them, as Figures 4 to 7 shown, for the convenience of description, in the specification, it is taken as an example that the source s of the driving transistor T1 is directly electrically connected to the second reset transistor T3, the drain d of the driving transistor T1 is directly electrically connected to the first switching transistor T4, and the multiple transistors in the pixel driving circuit 102 are all N-type transistors, and the first voltage signal VDD, the first reset signal Vref, and the second reset signal Vini are constant voltage signals. Each sub-pixel 10 at least includes the following working stages:

[0062] When the first reset transistor T2 is turned on in response to the first control signal REF, the driving transistor T1 is turned on, and the first switching transistor T4 is turned on in response to the third control signal REF';

[0063] That is to say, when the first reset transistor T2 is turned on in response to the first control signal REF and transmits the first reset signal Vref to the gate g of the driving transistor T1 to reset its potential, at this time, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to make it turn on. At the same time, the first switching transistor T4 is turned on in response to the potential of the third control signal REF' at this time. The first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switching transistor T4 and the driving transistor T1 to charge it until the gate-source voltage Vgs of the driving transistor T1 is less than or equal to its threshold voltage Vth, and then the driving transistor T1 is turned off. Therefore, the potential of the source s of the driving transistor T1 is "Vref - Vth";

[0064] When the data writing transistor T5 is turned on in response to the fourth control signal Gn, the driving transistor T1 is turned on, and the first switching transistor T4 is turned off in response to the third control signal REF';

[0065] That is to say, when the data writing transistor T5 is turned on in response to the fourth control signal Gn and transmits the corresponding data voltage Vd1 in the data signal Vdata to the gate g of the driving transistor T1 to write the data voltage Vd1, at this time, the gate-source voltage Vgs of the driving transistor T1 is also greater than its threshold voltage Vth to make it turn on. However, at this time, the first switching transistor T4 is turned off in response to the potential of the third control signal REF' at this time. At this time, the first voltage signal VDD will not be transmitted to the source s of the driving transistor T1 to charge it, that is, the potential of the source s of the driving transistor T1 is maintained at "Vref - Vth". Therefore, the gate-source voltage Vgs of the driving transistor T1 is "Vd1 - Vref + Vth".

[0066] It can be understood that the second reset transistor T3 in this embodiment is turned on in response to the corresponding potential in the second control signal INI and resets the source s of the driving transistor T1 through the second reset signal Vini. Moreover, when the first reset transistor T2 is turned on in sequence in response to the corresponding potential in the first control signal REF and resets the gate g of the driving transistor T1 through the first reset signal Vref, and is turned on in response to the corresponding potential in the fourth control signal Gn and writes the data voltage Vd1 to the gate g of the driving transistor T1 through the data voltage Vd1, the first switching transistor T4 is controlled to be turned on and off in sequence, so that the potential of the source s of the driving transistor T1 can remain unchanged after rising to "Vref - Vth", avoiding the potential of the source s of the driving transistor T1 being continuously charged by the first voltage signal VDD and causing its potential to rise, such that the potential of the source s of the driving transistor T1 can compensate for the threshold voltage Vth of the driving transistor T1 when the light-emitting element 101 emits light, improving the compensation effect for the threshold voltage of the driving transistor T1 in multiple pixel driving circuits 102.

[0067] In some embodiments, as Figures 4 to 7 shown, before the first reset transistor T2 is turned on in response to the first control signal REF, the second reset transistor T3 is turned on in response to the second control signal INI. That is, before the first reset signal Vref resets the gate g of the driving transistor T1 through the first reset transistor T2, the second reset transistor T3 can be turned on in response to the second control signal INI, so that the second reset signal Vini resets the source s of the driving transistor T1. Furthermore, it can be considered that when the first reset transistor T2 is turned on in response to the first control signal REF, the gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on.

[0068] Particularly, after the multiple light-emitting elements 101 emit light stably in the previous frame, due to differences such as the conduction voltage drop of the light-emitting elements 101 of different colors, the potentials of the sources s of different driving transistors T1 are also different. Therefore, it is necessary to reset the potentials of the sources s of all the driving transistors T1 through the same second reset signal Vini. Moreover, since the potentials of the sources s of all the driving transistors T1 may affect the potential of the anode or cathode of the light-emitting element 101, resetting the potentials of the sources s of all the driving transistors T1 first can ensure that the multiple light-emitting elements 101 are turned off, avoiding the mis-emission of the light-emitting element 101 when the gate g of the driving transistor T1 is reset later.

[0069] Among them, the pixel driving circuit 102 may further include a storage capacitor Cst electrically connected between the gate g and the source s of the driving transistor T1. The storage capacitor Cst is used to maintain the voltage difference between the gate g and the source s of the driving transistor T1, so as to achieve functions including but not limited to storing the threshold voltage Vth of the driving transistor T1.

[0070] In some embodiments, as Figure 4 and Figure 5 shown, the period in which the pulse of the first control signal REF is located is included in the period corresponding to the pulse of the third control signal REF', or as Figure 6 and Figure 7 shown, the period in which the pulse of the first control signal REF is located is the same as the period corresponding to the pulse of the third control signal REF'. Among them, Figure 4 and Figure 6 the potential corresponding to the pulse of the first control signal REF can turn on the first reset transistor T2 to reset the gate g of the driving transistor T1, and the potential corresponding to the pulse of the third control signal REF' can turn on the first switching transistor T4 to raise the potential of the source s of the driving transistor T1.

[0071] Combined with the above discussion, as Figure 4 and Figure 5 shown, in this embodiment, by setting the period in which the pulse of the first control signal REF is located to be included in the period corresponding to the pulse of the third control signal REF', during the period of resetting the gate g of the driving transistor T1, it is included in the stage of raising the potential of the source s of the driving transistor T1, so that the potential of the source s of the driving transistor T1 can rise to "Vref - Vth".

[0072] Furthermore, Figure 6 and Figure 7 shown, in order to save signal types, by reasonably setting the electrical characteristics of the first reset transistor T2 and the first switching transistor T4, the first control signal REF and the third control signal REF' can be the same signal, that is, their waveforms can be the same. At this time, the period in which the pulse of the first control signal REF is located and the period corresponding to the pulse of the third control signal REF' can be the same, and the above functions can also be achieved.

[0073] It should be noted that, Figure 4 in the corresponding circuit diagram, the period in which the pulse of the first control signal REF is located and the period corresponding to the pulse of the third control signal REF' can also be set to be the same, and the above functions can also be achieved at this time.

[0074] In some embodiments, as Figure 4 andFigure 5 As shown, after the data writing transistor T5 is turned on in response to the fourth control signal Gn, the first switching transistor T4 is turned on in response to the third control signal REF'. It can be understood that when only the first switching transistor T4 is connected in series between the first voltage line and the drain d of the driving transistor T1, after the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the first switching transistor T4 needs to be turned on to form a current path between the first voltage line and the drain d of the driving transistor, so as to prepare for forming a driving current. Thus, the first switching transistor T4 can also implement the function of forming a current path for the driving current in the pixel driving circuit 102.

[0075] In some embodiments, as Figure 6 shown, the pixel driving circuit 102 further includes: a second switching transistor T6, electrically connected between the first voltage line and one of the source s and the drain d of the driving transistor T1, for controlling a current path to be formed between the first voltage line and one of the source s and the drain d of the driving transistor according to the fifth control signal EM; as Figure 7 shown, when the first switching transistor T4 (responding to the third control signal REF') is turned off and the data writing transistor T5 (responding to the fourth control signal Gn) is turned on, the second switching transistor T6 is turned off in response to the fifth control signal EM; after the data writing transistor T5 is turned on in response to the fourth control signal Gn, the second switching transistor T6 is turned on in response to the fifth control signal EM.

[0076] Combined with the above discussion, the first switching transistor T4 is turned on and off in sequence when the first reset signal Vref and the data voltage Vd1 corresponding to the data signal Vdata are written to the gate g of the driving transistor T1 in sequence. On this basis, in this embodiment, by also electrically connecting the second switching transistor T6 between the first voltage line and one of the source s and the drain d of the driving transistor T1, and after the data voltage Vd1 corresponding to the data signal Vdata is written to the gate g of the driving transistor T1, the second switching transistor T6 is turned on to form a current path between the first voltage line and the drain d of the driving transistor, so as to prepare for forming a driving current. Thus, by providing the above second switching transistor T6, the function of the current path for providing the driving current in the pixel driving circuit 102 can be retained.

[0077] Specifically, in order to ensure that a current break is formed between the first voltage line and the drain d of the driving transistor T1 when the above data voltage Vd1 is written, the second switching transistor T6 also needs to be turned off in response to the potential corresponding to the fifth control signal EM at this time.

[0078] Further, as Figure 6 shown, the pixel driving circuit 102 further includes: a third switching transistor T7, electrically connected between the light-emitting element 101 and the other of the source s and the drain d of the driving transistor T1, for controlling a current path to be formed between the light-emitting element 101 and the other of the source s and the drain d of the driving transistor T1 according to the fifth control signal EM; as Figure 7 shown, when the second reset transistor T3 is turned on in response to the second control signal INI, the third switching transistor T7 is turned off in response to the fifth control signal EM.

[0079] Combined with the above discussion, both the third switching transistor T7 and the second switching transistor T6 are controlled by the fifth control signal EM to be turned on or off, that is, both are turned off when the data voltage Vd1 is written to the first switching transistor T4 as described above, and both are turned on after the data voltage Vd1 is written as described above to form the current path of the driving current. At the same time, since the third switching transistor T7 is electrically connected between the light-emitting element 101 and the source s of the driving transistor T1, in order to avoid the potential of the anode or cathode of the light-emitting element 101 being affected when the second reset signal Vini resets the source s of the driving transistor T1 and causing the light-emitting element 101 to emit light erroneously, the third switching transistor T7 can be turned off at this time.

[0080] In some embodiments, as Figure 6 shown, one of the anode and the cathode of the light-emitting element 101 is electrically connected to a second voltage line (for transmitting a second voltage signal VSS), and the other is electrically connected to the other of the source s and the drain d of the driving transistor T1; the pixel driving circuit 102 further includes: a third reset transistor T8, electrically connected to the other of the anode and the cathode of the light-emitting element 101, for transmitting a third reset signal Viano to the other of the anode and the cathode of the light-emitting element 101 according to the second control signal INI.

[0081] For the convenience of description, in the specification, it is taken as an example that the anode of the light-emitting element 101 is at least electrically connected to the second reset transistor T3 (further, it can also be electrically connected to the third reset transistor T8 and the third switching transistor T7), the cathode of the light-emitting element 101 is electrically connected to the second voltage line, and the third reset signal Viano and the second voltage signal VSS are also constant voltage signals.

[0082] As described above, both the third reset transistor T8 and the second reset transistor T3 are controlled by the second control signal INI to conduct or cut off, that is, both conduct simultaneously before the first reset signal Vref resets the gate g of the driving transistor T1, so that the second reset signal Vini and the third reset signal Viano respectively reset the source s of the driving transistor T1 and the anode of the light-emitting element 101.

[0083] It should be noted that since the first reset signal Vref resets the gate g of the driving transistor T1 and the second reset signal Vini resets the source s of the driving transistor T1, it is necessary to turn on the driving transistor T1, that is, the gate-source voltage Vgss = Vref - Vini of the driving transistor T1 needs to be greater than its threshold voltage Vth. Therefore, the difference degree between the amplitudes of the second reset signal Vini and the first reset signal Vref is limited by the threshold voltage Vth. At the same time, since the third reset signal Viano resets the anode of the light-emitting element 101, it is necessary to ensure that the light-emitting element 101 is turned off. Therefore, Viano < VSS + Vth_oled, where Vth_oled is the turn-on voltage of the light-emitting element 101.

[0084] Therefore, in this embodiment, by setting the above-mentioned second reset transistor T3, third reset transistor T8, and third switching transistor T7, the source s of the driving transistor T1 and the anode of the light-emitting element 101 can be respectively reset. And when resetting the two, due to the third switching transistor T7, the interference of the potentials of the two can be avoided. At the same time, the second reset transistor T3 and the third reset transistor T8 are both controlled by the second control signal INI, which can effectively reduce the types of signals.

[0085] In some embodiments, as Figure 1 、 Figures 4 to 7 shown, the data signal Vdata includes a plurality of the above-mentioned data voltages Vd1 corresponding to the plurality of light-emitting elements 101, and the fourth control signal Gn includes the above-mentioned first gate pulse p1 for controlling the corresponding data writing transistor T5 to conduct; wherein, the starting moment of the first gate pulse p1 is ahead of the starting moment of the time period where the corresponding data voltage Vd1 is located.

[0086] As Figure 5 and Figure 7As shown, the pulses drawn in solid lines in the fourth control signal Gn can be understood as the first comparison gate pulse p1' in the comparative example, and the pulses drawn in dashed lines can be understood as the first gate pulse p1 in the embodiment. It can be observed that the start time of the first comparison gate pulse p1' in the comparative example lags behind the start time of the period corresponding to the data voltage Vd1. In this embodiment, since the first switching transistor T4 and the second switching transistor T6 are both cut off during the period of the first gate pulse p1, the conduction of the driving transistor T1 will not cause the potential of its source s to be charged by the first voltage signal VDD and increase its potential.

[0087] Therefore, compared with the comparative example, in this embodiment, the start time of the first gate pulse p1 is advanced to be ahead of the start time of the period corresponding to the data voltage Vd1. While avoiding the potential of the source s of the driving transistor T1 being charged by the first voltage signal VDD and increasing its potential, it can also increase the overlapping duration between the first gate pulse p1 and the period corresponding to the data voltage Vd1, so that the corresponding sub-pixel 10 has a longer charging duration, which is beneficial to the charging rate of the sub-pixel 10 especially under high refresh rates, especially for heavy-load images. At the same resolution, it can support a higher refresh rate, or at the same refresh rate, it can support a higher resolution.

[0088] Furthermore, as shown in Figure 1 、 Figures 4 to 7 , the third control signal REF' includes a second gate pulse p2 for controlling the conduction of the corresponding first switching transistor T4; wherein, the interval between the end time of the second gate pulse p2 and the start time of the first gate pulse p1 is greater than or equal to 0.1×H, and H is the driving period of one row of the sub-pixels 10 of the display device 100 within one frame.

[0089] Among them, the driving period of one row of the sub-pixels 10 of the display device 100 within one frame can be understood as the duration required for one row of the pixel driving circuit 102 to be turned on within one frame to at least write the corresponding data voltage Vd. There can be the following calculation method: 1H = 1 / (refresh rate × number of vertical lines). The number of vertical lines can include the number of rows of the multiple sub-pixels 10 in the display area of the display panel 20 and the sum of the number of virtual rows in the non-display area. For example, for a display device 100 with a resolution of 1080p operating at a refresh rate of 60Hz, the corresponding 1H duration is approximately 15.6 microseconds.

[0090] Of course, considering that generally, time needs to be reserved for the system to perform operations such as caching between the data voltages Vd1 of two adjacent frames, it can be considered that 1H is slightly less than 1 / (refresh rate × number of vertical lines).

[0091] It can be understood that in this embodiment, on the basis that the start time of the first gate pulse p1 is ahead of the start time of the period in which the corresponding data voltage Vd1 is located, the interval between the start time of the first gate pulse p1 and the end time of the second gate pulse p2 is set to be greater than or equal to 0.1×H, so as to avoid an overlapping period between the first gate pulse p1 and the corresponding second gate pulse p2, which may cause the data voltage Vd1 to be written to the gate g of the driving transistor T1 before the potential of the source s of the driving transistor T1 reaches "Vref - Vth", resulting in insufficient compensation of the threshold voltage Vth.

[0092] Based on the above explanation of 1H, Figure 5 and Figure 7 H is also used to indicate the pulse widths of the pulses of multiple signals and the intervals between different pulses, but the above markings do not limit the waveforms of the above signals of the present invention.

[0093] Furthermore, in combination with Figure 1 , Figure 4 and up to Figure 7 As shown, the pulse widths of the first gate pulse p1 at different refresh rates are different. Combining the above discussion, for the same display device 100, since the time reserved for the pixel driving circuit 102 in a row within one frame to be turned on to at least write the corresponding data voltage Vd is different at different refresh rates, for a high refresh rate, it can be considered that Figure 4 and Figure 6 As shown, the pulse widths of the pulses of different signals are all reduced compared to the low refresh rate. The short time for scanning one row of sub-pixels 10 is likely to have a problem of insufficient charging.

[0094] It can be understood that since this embodiment can make the start time of the first gate pulse p1 ahead of the start time of the period in which the corresponding data voltage Vd1 is located, and as Figure 5 and Figure 7 shown, to avoid the problem of mischarging of the data voltage Vd1, the end time of the first gate pulse p1 needs to be earlier than the end time of the corresponding data voltage Vd1 by a certain duration. Therefore, it can be considered that the intervals between the end times of the corresponding data voltages Vd1 of different first gate pulses p1 are the same. Thus, this embodiment can differentially set the start time of the first gate pulse p1 at different refresh rates, that is, differentially set the pulse width of the first gate pulse p1. For example, compared with the low refresh rate, the pulse width of the first gate pulse p1 can be set larger at the high refresh rate, so that when both the pulse width of the first gate pulse p1 and the duration of the period in which the corresponding data voltage Vd1 is located are small, by maximizing the overlapping duration between the two, the overlapping duration between the first gate pulse p1 and the period in which the corresponding data voltage Vd1 is located at different refresh rates can tend to be consistent, thereby improving the uniformity of the display of the display device 100 at different refresh rates.

[0095] The present invention provides a driving method for a display device, which is applied to a pixel driving circuit and a light-emitting element that are electrically connected in the display device. The pixel driving circuit includes: a driving transistor, one of the source and drain of the driving transistor is electrically connected to a first voltage line, and the other is electrically connected to the light-emitting element; a first reset transistor, electrically connected to the gate of the driving transistor; a second reset transistor, electrically connected to the other of the source and drain of the driving transistor; a first switching transistor, electrically connected between the first voltage line and one of the source and drain of the driving transistor; and a data writing transistor, electrically connected to the gate of the driving transistor. The specific circuit of this pixel driving circuit and its connection manner with the light-emitting element can refer to the relevant discussion above. Figure 1 、 Figures 4 to 7 related discussion.

[0096] Such as Figure 8 shown, the driving method of the display device includes but is not limited to the following steps and combinations between the following steps.

[0097] S1, in the first stage, the first reset transistor is turned on in response to a first control signal to transmit a first reset signal to the gate of the driving transistor, so that the driving transistor is turned on, and the first switching transistor is turned on in response to a third control signal;

[0098] Combined with the above discussion, in the first stage, the potential of the first control signal REF controls the first reset transistor T2 to turn on, and the first reset signal Vref is transmitted to the gate g of the driving transistor T1. The gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on. At the same time, the potential of the third control signal REF' controls the first switching transistor T4 to turn on, and the first voltage signal VDD is transmitted to the source s of the driving transistor T1 until the driving transistor T1 is turned off. At this time, the potential of the source s of the driving transistor T1 is "Vref - Vth";

[0099] S2, in the second stage after the first stage, the data writing transistor is turned on in response to a fourth control signal to transmit a data signal to the gate of the driving transistor, so that the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal;

[0100] As described above, in the second stage, the potential of the fourth control signal Gn controls the data writing transistor T5 to turn on, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. The gate-source voltage Vgs of the driving transistor T1 is greater than its threshold voltage Vth to turn it on. However, at this time, the potential of the third control signal REF’ controls the first switching transistor T4 to turn off, and at this time, the first voltage signal VDD does not transmit to the source s of the driving transistor T1. That is, the potential of the source s of the driving transistor T1 is maintained at "Vref - Vth", so the gate-source voltage Vgs of the driving transistor T1 is "Vd1 - Vref + Vth".

[0101] To better illustrate the display device and its driving method provided by the present invention, in combination with Figure 7 the timing diagram shown in Figure 6 the working period of the sub-pixel 10 shown in is described as follows:

[0102] In the first period t1, the second control signal INI is at the corresponding high potential, and both the second reset transistor T3 and the third reset transistor T8 are turned on. The second reset signal Vini is transmitted to the source s of the driving transistor T1 to reset it, and the third reset signal Viano is transmitted to the anode of the light-emitting element 101 to reset it;

[0103] In the second period t2 (including the above-mentioned first stage), the second control signal INI, the first control signal REF, and the third control signal REF’ are all at the corresponding high potential. The second reset transistor T3 and the third reset transistor T8 remain turned on, and both the first reset transistor T2 and the first switching transistor T4 are turned on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is turned on, and the first voltage signal VDD is transmitted to the source s of the driving transistor T1 through the first switching transistor T4 and the driving transistor T1 to raise its potential until the driving transistor T1 is turned off. The potential of the source s of the driving transistor T1 is "Vref - Vth";

[0104] In the third period t3 (including the above-mentioned second stage), the fourth control signal Gn is at the corresponding high potential, the data writing transistor T5 is turned on, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. The driving transistor T1 is still turned on, but both the first switching transistor T4 and the second switching transistor T6 are turned off. The potential of the source s of the driving transistor T1 is maintained at "Vref - Vth", so the gate-source voltage Vgs of the driving transistor T1 is "Vd1 - Vref + Vth";

[0105] In the fourth period t4, the fifth control signal EM is at the corresponding high potential, and the second switching transistor T6, the third switching transistor T7, and the driving transistor T1 are all turned on to form a current path between the first voltage line and the second voltage line. The driving transistor T1 generates a driving current flowing through the light-emitting element 101, and the light-emitting element 101 emits light. The magnitude of the driving current is approximately k×{[Vdata-(Vref-Vth)]-Vth} 2 ≈k×(Vdata-Vref) 2 , where k is a constant.

[0106] Referring to the above description of the first period t1 to the fourth period t4 as shown in Figure 6 and Figure 7 , it may also include the following working stages: Figure 4 and Figure 5 as shown in

[0107] In the first period t1, the second control signal INI and the third control signal REF’ are at the corresponding high potentials. On the basis of resetting the source s of the driving transistor T1, the first voltage signal VDD is transmitted to the drain d of the driving transistor T1 to reset it;

[0108] In the second period t2 (including the above-mentioned first stage), the second control signal INI, the first control signal REF, and the third control signal REF’ are at the corresponding high potentials. The second reset transistor T3 and the first switching transistor T4 remain turned on, and the first reset transistor T2 is turned on. The first reset signal Vref is transmitted to the gate g of the driving transistor T1 to reset it. The driving transistor T1 is turned on, and the first voltage signal VDD further transmits through the driving transistor T1 to the source s of the driving transistor T1 to raise its potential until the driving transistor T1 is turned off, and the potential of the source s of the driving transistor T1 is "Vref-Vth";

[0109] In the third period t3 (including the above-mentioned second stage), the fourth control signal Gn is at the corresponding high potential, and the corresponding data voltage Vd1 in the data signal Vdata is transmitted to the gate g of the driving transistor T1. Similarly to the third period t3 in the above Figure 7 , finally, the gate-source voltage Vgs of the driving transistor T1 is also "Vd1-Vref+Vth";

[0110] During the fourth time period t4, the fourth control signal Gn and the third control signal REF' are both at their corresponding high potentials. The data writing transistor T5 is turned off, and the driving transistor T1 and the first switching transistor T4 are both turned on to form a current path between the first voltage line and the second voltage line. The driving transistor T1 generates a driving current flowing through the light-emitting element 101, and the light-emitting element 101 emits light. The magnitude of the driving current is approximately k × {[Vdata - (Vref - Vth)] - Vth} 2 ≈k × (Vdata - Vref) 2 , where k is a constant.

[0111] It should be noted that, as can be seen from the above discussion, since Figure 4 when only the first switching transistor T4 is connected in series between the first voltage line and the drain d of the driving transistor T1, in Figure 5 the fourth time period t4, the third control signal REF' needs to be set to its corresponding high potential to form a current path between the first voltage line and the second voltage line.

[0112] The above has introduced in detail the structure of the display device and its driving method provided by the embodiments of the present invention. Specific examples are used herein to illustrate the principle and implementation manner of the present invention. The description of the above embodiments is only for helping to understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: The invention comprises a plurality of sub-pixels, wherein the sub-pixels include a light-emitting element and a pixel driving circuit electrically connected, and the pixel driving circuit includes: a driving transistor, wherein one of a source and a drain of the driving transistor is electrically connected to the first voltage line, and the other is electrically connected to the light emitting element; a first reset transistor, electrically connected to the gate of the driving transistor, and configured to transmit a first reset signal to the gate of the driving transistor according to a first control signal; a second reset transistor electrically connected to the other of the source and the drain of the driving transistor, and configured to transmit a second reset signal to the other of the source and the drain of the driving transistor according to a second control signal; a first switch transistor, electrically connected between the first voltage line and one of the source and the drain of the driving transistor, and configured to control the formation of a current path between the first voltage line and one of the source and the drain of the driving transistor according to a third control signal; a data writing transistor, electrically connected to the gate of the driving transistor, and configured to transmit a data signal to the gate of the driving transistor according to a fourth control signal; When the first reset transistor is turned on in response to the first control signal, the driving transistor is turned on, and the first switch transistor is turned on in response to the third control signal; When the data writing transistor is turned on in response to the fourth control signal, the driving transistor is turned on, and the first switching transistor is turned off in response to the third control signal.

2. The display device according to claim 1, wherein: The second reset transistor is turned on in response to the second control signal before the first reset transistor is turned on in response to the first control signal.

3. The display device according to claim 1, wherein: The time period of the pulse of the first control signal is the same as the time period of the pulse corresponding to the third control signal.

4. The display device according to claim 1, wherein: After the data writing transistor is turned on in response to the fourth control signal, the first switching transistor is turned on in response to the third control signal.

5. The display device according to claim 1, wherein: The pixel driving circuit further includes: a second switch transistor, electrically connected between the first voltage line and one of the source and the drain of the driving transistor, and configured to control the formation of a current path between the first voltage line and one of the source and the drain of the driving transistor according to a fifth control signal; When the first switch transistor is turned off and the data writing transistor is turned on, the second switch transistor is turned off in response to the fifth control signal; After the data write transistor is turned on in response to the fourth control signal, the second switch transistor is turned on in response to the fifth control signal.

6. The display device according to claim 5, characterized in that The pixel driving circuit further includes: a third switch transistor, electrically connected between the light emitting element and the other of the source and the drain of the driving transistor, and configured to control the formation of a current path between the light emitting element and the other of the source and the drain of the driving transistor according to the fifth control signal; When the second reset transistor is turned on in response to the second control signal, the third switch transistor is turned off in response to the fifth control signal.

7. The display device according to claim 6, wherein: One of the anode and cathode of the light emitting element is electrically connected to the second voltage line, and the other is electrically connected to the other of the source and drain of the driving transistor; The pixel driving circuit further includes: The third reset transistor is electrically connected to the other of the anode and the cathode of the light emitting element, and is used to transmit a third reset signal to the other of the anode and the cathode of the light emitting element according to the second control signal.

8. The display device according to any one of claims 1 to 7, characterized in that: The data signal includes a plurality of data voltages corresponding to the plurality of light emitting elements, and the fourth control signal includes a first gate pulse for controlling the corresponding data writing transistor to be turned on; The starting time of the first gate pulse is earlier than the starting time of the corresponding time period of the data voltage.

9. The display device according to claim 8, wherein: The third control signal comprises a second gate pulse for controlling the corresponding first switch transistor to be turned on; The interval between the end time of the second gate pulse and the start time of the first gate pulse is greater than or equal to 0.1×H, where H is a driving period of a row of sub-pixels of the display device within a frame.

10. The display device according to claim 8, wherein: The pulse width of the first gate pulse is different at different refresh rates.

11. A method for driving a display device, characterized in that: A pixel driving circuit and a light-emitting element electrically connected to the display device, wherein the pixel driving circuit comprises: a driving transistor, wherein one of a source and a drain of the driving transistor is electrically connected to the first voltage line, and the other is electrically connected to the light emitting element; A first reset transistor electrically connected to the gate of the driving transistor; A second reset transistor electrically connected to the other of the source and the drain of the driving transistor; A first switch transistor electrically connected between the first voltage line and one of the source and the drain of the driving transistor; A data writing transistor electrically connected to the gate of the driving transistor; The driving method of the display device comprises: In the first stage, the first reset transistor is turned on in response to the first control signal so that the first reset signal is transmitted to the gate of the driving transistor so that the driving transistor is turned on, and the first switch transistor is turned on in response to the third control signal; In a second phase after the first phase, the data writing transistor is turned on in response to the fourth control signal to transmit the data signal to the gate of the driving transistor to turn on the driving transistor, and the first switching transistor is turned off in response to the third control signal.

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