Method of operating a memory controller, method of controlling a memory device, and memory controller

Abstract

Methods of operating a memory controller, methods of controlling a memory device, and a memory controller are provided. A method of operating a memory controller includes receiving first information of a MRS of a memory device, the first information of the MRS including a control parameter indicating that the memory device supports a DFE amount operation of DQ pins of the memory device; sending a CAS command synchronized with a clock signal to the memory device; sending a write command to the memory device; sending a write clock signal synchronized with the clock signal to the memory device after a predetermined time elapses from the CAS command; sending write data to the memory device through data lines; and sending second information to the MRS of the memory device. The data lines are pre-driven to a logical low for a predetermined pre-drive time based on the control parameter. The second information of the MRS includes global operation parameters and per-pin operation parameters of the DFE amount operation, the global operation parameters being associated with the DQ pins, and the per-pin operation parameters being associated with respective DQ pins.

Description

[0001] This application is a divisional application of the invention patent application filed on October 22, 2021, with application number "202111231244.7" and invention title "Apparatus, memory device and method for storing multiple parameter codes of operation parameters". Technical Field

[0002] This disclosure relates to a device, a memory device, and a method of operating such a device for storing a plurality of parameter codes for an operation parameter. Background Technology

[0003] To support high-speed interfacing with the memory device, the controller (or central processing unit (CPU)) can provide a clock signal to the memory device. The memory device can process signals received from the controller in response to the clock signal and synchronize signals sent to the controller with the clock signal. Depending on the operating frequency of the clock signal, the memory device can support various data rates (e.g., 1600 Mbps, 2400 Mbps, 6400 Mbps, etc.). Due to the demand for high data rates, accurately capturing signals transmitted between the controller and the memory device at high clock frequencies is crucial.

[0004] Typically, memory devices include a mode register, which provides various operational and control parameters for setting the operating conditions of the memory device. Examples of operational and control parameters include parameters associated with burst length, read / write latency, preamble / postamble length, on-die termination (ODT) calibration, impedance regulation (ZQ) calibration, and reference voltage setting.

[0005] The memory device sends and receives data from the controller via data lines. Because the physical characteristics of the data lines differ, the characteristics of the signals carried through the respective data lines can also differ. When operating at a high clock frequency, the data sent to the memory device has a data eye diagram state. The data eye diagram is shown as a superposition of multiple data transitions representing jitter caused by noise. Depending on the environment of the respective data line, the data can exhibit data eye diagrams with different distorted waveforms.

[0006] When facilitating the reception of data based on the signal characteristics of the corresponding data line when sending data to the memory device, it is possible to find a state where the eye opening region of the data eye diagram of the corresponding data line is symmetrical and maximized, thereby promoting the improvement of the signal integrity (SI) characteristics of the data. Summary of the Invention

[0007] Example embodiments provide a device, a memory device, and a method for operating a plurality of codes for storing an operation parameter.

[0008] According to one aspect of an example embodiment, a device is provided, the device comprising: a plurality of signal pins connected to a plurality of signal lines, wherein each of the plurality of signal pins is connected to a signal line of the plurality of signal lines, and each signal line carries a signal; and a mode register configured to store a first parameter code and a second parameter code of an operation parameter of the device in a first register and a second register, respectively, wherein the first parameter code includes a global operation parameter code associated with an operation condition of the signal pin associated with the operation parameter, and the second parameter code includes a per-pin operation parameter code associated with an operation condition of the corresponding signal pin associated with the operation parameter, the per-pin operation parameter code being represented as an offset value from the global operation parameter code.

[0009] According to one aspect of an example embodiment, a memory device configured to be set as a current operating condition is provided, the memory device comprising: a mode register configured to store a first parameter code and a second parameter code for setting a first operating condition and a second operating condition of an operating parameter of the memory device; and control logic circuitry configured to: set a first operating condition as the current operating condition by using the first parameter code of the operating parameter based on a first control code stored in the mode register, and set a second operating condition as the current operating condition by using the first parameter code and the second parameter code of the operating parameter based on a second control code stored in the mode register, wherein the second parameter code is represented as an offset value from the first parameter code.

[0010] According to one aspect of an example embodiment, a method for setting current operating conditions of a memory device is provided, the method comprising: storing a first parameter code of an operating parameter for setting a first operating condition in a first register of a mode register; storing a second parameter code of the operating parameter for setting a second operating condition in a second register of the mode register, wherein the second parameter code is represented as an offset value from the first parameter code; setting a first operating condition as the current operating condition by using the first parameter code of the operating parameter; and setting a second operating condition as the current operating condition by using the first parameter code and the second parameter code of the operating parameter. Attached Figure Description

[0011] The above and / or other aspects will be more clearly understood from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an example embodiment.

[0013] Figure 2 This is a block diagram of a memory device according to an example embodiment.

[0014] Figure 3 It is shown Figure 1 A flowchart of the operation of the memory system.

[0015] Figure 4 This is a conceptual diagram used to describe a data manipulation circuit system according to an example embodiment.

[0016] Figure 5A , Figure 5B and Figure 5C It is used to describe Figure 4 A diagram showing the reference voltage of the data line.

[0017] Figure 6 This is a diagram illustrating a portion of the Mode Register Configuration (MRS) according to an example embodiment.

[0018] Figure 7 This is a diagram illustrating a portion of the MRS according to an example embodiment.

[0019] Figure 8 This is a diagram illustrating the effect of a decision feedback equalizer (DFE) on a data line according to an example embodiment.

[0020] Figure 9 It is used to describe Figure 8 A diagram of the DFE.

[0021] Figure 10 This is a diagram illustrating a portion of the MRS according to an example embodiment.

[0022] Figures 11 to 13 This is an illustration used to describe an example of the operation of a memory device according to an example embodiment.

[0023] Figure 14 This is a diagram used to describe the oscillation width calibration of a data line according to an example embodiment.

[0024] Figure 15 This is a diagram used to describe the pre-emphasis operation of data rows according to an example embodiment. Detailed Implementation

[0025] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an example embodiment.

[0026] Reference Figure 1The memory system 10 may include a memory controller 100 and a memory device 120. The memory system 10 may represent an integrated circuit, electronic device or system, smartphone, tablet PC, computer, server, workstation, portable communication terminal, personal digital assistant (PDA), portable multimedia player (PMP), computing device (such as other suitable computers), virtual machine, or virtual computing device thereof. Optionally, the memory system 10 may be one of the components included in a computing system (e.g., a graphics card). According to example embodiments, the memory system 10 may be implemented as an unbuffered dual in-line memory module (UDIMM), a register-equipped DIMM (RDIMM), a low-load DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small-size DIMM (SODIMM), etc.

[0027] The memory controller 100 can be connected to and communicate with the memory device 120 via the memory bus 110. The memory controller 100 may include a register control word (RCW) 102, a training circuit system 104, and a memory physical layer (PHY) 106.

[0028] RCW 102 may be provided to control memory device 120 based on initialization and / or operational characteristics. RCW 102 may include various algorithms for configuring memory controller 100 so that memory controller 100 can interact normally with memory device 120. For example, codes indicating the frequency, timing, drive, and detailed operating parameters of memory device 120 may be set to RCW 102. Memory training of memory device 120 may be performed based on the codes set to RCW 102.

[0029] The training circuitry system 104, under the control of the memory controller 100, can perform memory core parameter training associated with the memory core of the memory device 120 and / or peripheral circuit parameter training for peripheral circuits other than the memory core. The training circuitry system 104 can determine the optimal parameters for the memory core parameters and / or peripheral circuit parameters of the memory device 120. The training circuitry system 104 can perform memory training of the memory device 120 through the memory controller 100. In this example embodiment, although the training circuitry system 104 is described as being included in the memory controller 100, the training circuitry system 104 can be included in the memory device 120, such that the memory device 120 can be a memory device performing memory training.

[0030] The memory PHY 106 is a physical or electrical and logic layer that provides the signals, frequencies, timings, drive signals, detailed operating parameters, and functionality required for effective communication between the memory controller 100 and the memory device 120. The memory PHY 106 can support the features of the Joint Electronic Equipment Committee (JEDEC) standard Double Data Rate (DDR) protocol and / or Low Power Double Data Rate (LPDDR) protocol.

[0031] The memory PHY 106 connects the memory controller 100 to the memory device 120 via the memory bus 110. For simplicity, the diagram shows a clock signal CLK, command / address signal CA, and data DQ provided between the memory controller 100 and the memory device 120 via a single signal line; however, in practice, these signals can be provided via multiple signal lines. The signal lines between the memory controller 100 and the memory device 120 can be connected via connectors. Connectors can be implemented as pins, balls, signal lines, or other hardware components.

[0032] The clock signal CLK can be transmitted from the memory controller 100 to the memory device 120 via the clock signal line of the memory bus 110. The command / address signal CA can be transmitted from the memory controller 100 to the memory device 120 via the command / address bus of the memory bus 110. The chip select signal CS can be transmitted from the memory controller 100 to the memory device 120 via the chip select line of the memory bus 110. Figure 11 As shown, the chip select signal CS, activated as logic high, can indicate that the command / address signal CA sent via the command / address bus is a command. Data DQ can be sent from memory controller 100 to memory device 120 or from memory device 120 to memory controller 100 via the data bus of memory bus 110, which includes bidirectional signal lines.

[0033] The memory device 120 can write or read data DQ under the control of the memory controller 100. The memory device 120 may include a memory cell array 200, a mode register configuration (MRS) 210, and control logic circuitry 220.

[0034] The memory cell array 200 may include multiple word lines, multiple bit lines, and multiple memory cells formed at the intersections of the word lines and bit lines. The memory cells of the memory cell array 200 may include volatile memory cells (e.g., dynamic random access memory (DRAM) cells, static RAM (SRAM) cells, etc.), non-volatile memory cells (e.g., flash memory cells, resistive RAM (ReRAM) cells, phase-change RAM (PRAM) cells, magnetic RAM (MRAM) cells, etc.), or some other type of memory cells.

[0035] MRS 210 can be programmed to set various operating parameters, options, functions, characteristics, and modes of memory device 120. When an MRS command is issued by memory controller 100, MRS 210 can store parameter codes including appropriate bit values ​​for the command / address bus to be provided to memory bus 110.

[0036] For example, the MRS 210 can be used to control burst length, read / write latency, preamble / postamble length, write equalization enable / disable, decision feedback equalization (DFE) amount, pull-down / on-die termination (ODT), pull-up / output high-level voltage (Voh) calibration, pre-emphasis, reference voltage setting, etc.

[0037] Burst length can be provided to set the maximum number of column positions that can be accessed for read and / or write commands. Read / write latency can be provided to define the clock cycle delay between a read and / or write command and the first bit of valid output and / or input data. Write equalization can be provided to enable or disable skew compensation between the clock signal and the data strobe signal during a write operation.

[0038] The DFE value can be provided to subtract the bit residual of the previously read data DQ to determine the current data bit. Pull-down / ODT calibration and pull-up / Voh calibration can be provided to improve signal integrity (SI) by adjusting the swing width and / or drive strength of signals received through the command / address bus and / or data bus.

[0039] A pre-emphasis function can be provided to improve SI by increasing the data eye aperture area of ​​the signal transmitted via the data bus. A reference voltage setting can be provided to determine a logic value by comparing it with the logic value of the received signal. The voltage used for comparison with the received signal may be referred to as the decision level. For example, in some embodiments, in Figure 9The received signal observed at the input of the sampler 920, as a first value higher than the decision level, will cause the sampler to output a high voltage ("1") as the value SDQ0. The input level can be changed using the VREF operating parameters. In contrast, at Figure 9 The received signal observed at the input of the sampler 920, as a first value lower than the decision level, will cause the sampler to output a low voltage (“0”) as the value SDQ0. See also... Figure 9 .

[0040] In addition, the MRS 210 can be used to control DRAM-related Delay Locked Loop (DLL) reset, DLL enable / disable, output drive strength, additional delay, Terminal Data Strobe (TDQS) enable / disable, input / output buffer enable / disable, CAS (Column Address Strobe) write delay, dynamic termination, write cyclic redundancy check (CRC), multipurpose register (MPR) position function, MPR operation function, gear down mode, MPR read format, power-down mode, Vref monitoring, read preamble training mode, read preamble function, write preamble function, command and address (CA) parity function, CRC error status, CA parity error status, ODT function, data mask function, write data bus inversion (DBI) function, read DBI function, error detection code (EDC) hold mode, etc.

[0041] Control logic circuit 220 can receive clock signal CLK via the clock signal line of memory bus 110 and control the operation timing of memory device 120. In addition to the clock signal CLK, the operation timing of memory device 120 can also be provided based on signals (e.g., strobe signals) provided to memory device 120. Control logic circuit 220 can receive commands received via command / address bus and can generate control signals for performing various memory operations in memory device 120 in response to commands.

[0042] Figure 2 This is a block diagram of a memory device according to an example embodiment.

[0043] Reference Figure 1 and Figure 2 The memory device 120 may include a memory cell array (MCA) 200, a row decoder 202, a word line driver 204, a column decoder 206, an input / output gating circuit 208, an MRS 210, a control logic circuit 220, an address buffer 230, an ODT circuit 240, a reference voltage generation circuit 250, a data input buffer 260, and a data output buffer 270.

[0044] The memory cell array 200 includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array 200 includes multiple word lines WL and multiple bit lines BL connected to the memory cells. The word lines WL can be connected to memory cells in rows, and the multiple bit lines BL can be connected to memory cells in columns.

[0045] Row decoder 202 can select any word line WL connected to memory cell array 200. Row decoder 202 can decode the row address ROW_ADDR received from address buffer 230, select any word line corresponding to the row address ROW_ADDR, and connect the selected word line to the word line driver 204 that activates the selected word line. Column decoder 206 can select predetermined bit lines among the bit lines BL of memory cell array 200. Column decoder 206 can generate a column selection signal CSL by decoding the column address COL_ADDR received from address buffer 230, and connect the bit line selected by column selection signal CSL to input / output gating circuit 208. Input / output gating circuit 208 may include a read data latch for storing read data of the bit line selected by column selection signal CSL and a write driver for writing write data to memory cell array 200. Read data stored in the read data latch of input / output gating circuit 208 can be provided to the data bus through data output buffer 270. Write data can be applied to the memory cell array 200 through the data input buffer 260 connected to the data bus and through the write driver of the input / output gating circuit 208.

[0046] The control logic circuit 220 can receive a clock signal CLK and a command CMD, and generate a control signal CTRLS for controlling the operating timing and / or memory operations of the memory device 120. The control logic circuit 220 can use the control signal CTRLS to read data from the memory cell array 200 and write data to the memory cell array 200.

[0047] MRS 210 may store information used by control logic circuitry 220 to configure the operation of memory device 120 to set the operating conditions of memory device 120. MRS 210 may include a register storing parameter codes for various operating parameters and control parameters used to set the operating conditions of memory device 120. Parameter codes may be received by memory device 120 via a command / address bus. Control logic circuitry 220 provides control signals CTRLS to the circuitry of memory device 120 to operate as set by the operating parameters and control parameters stored in MRS 210. Generally, the term "parameter" refers to a variable, and the term "parameter code" refers to the pattern of bits on the command / address bus used to execute commands associated with the variable.

[0048] To minimize the transmission time of signals sent to / received from memory device 120, the signal swipe width is reduced. As the signal swipe width decreases, the impact of external noise on memory device 120 increases, and signal reflections caused by impedance mismatch at the interface become more severe. To address impedance mismatch, memory device 120 controls impedance matching by performing a ZQ calibration operation.

[0049] Pull-down / ODT calibration can be provided to switch the termination resistance of the target memory device on / off and / or fix the termination resistance of non-target memory devices. Pull-up / Voh calibration can be provided to meet the VOH specification SPEC by adjusting the pull-up strength during read operations. Pull-down / ODT calibration and pull-up / Voh calibration can be referred to as impedance regulation operations, ZQ calibration, or offset removal operations for continuously adjusting the output and / or termination resistance of memory device 120.

[0050] The ODT circuit 240, when enabled, provides termination resistors for the command / address bus and / or data bus. The termination resistors improve the signal integrity (SI) of signals received through the bus. The enablement of the ODT circuit 240 and the magnitude of the termination resistors provided to the bus can be set by storing the appropriate parameter code in the MRS 210.

[0051] The reference voltage generation circuit 250 provides a reference voltage VREF for use by the circuitry of the memory device 120. For example, the reference voltage VREF can be used by the control logic circuit 220 to compare it with the voltage of a signal received from the command bus to determine the logic value of the signal. The reference voltage VREF and / or the range of the reference voltage VREF can be set by storing the reference voltage operation parameter code in the MRS 210.

[0052] Figure 3 It is shown Figure 1 A flowchart of the operation of the memory system.

[0053] Reference Figure 1 , Figure 2 and Figure 3 During operation S310, the memory system 10 can perform initialization. When the memory system 10 is powered on, the memory controller 100 and the memory device 120 can perform initial setup operations according to a preset method. Default operating parameters can be set during the initialization of the memory device 120.

[0054] In operation S320, the memory system 10 can perform a command address training operation. The memory controller 100 and the memory device 120 can perform the command address training operation to improve the timing margin of the command CMD and the address ADDR.

[0055] In operation S330, the memory system 10 can perform a read training operation. The memory controller 100 can adjust the operating parameter code of the memory device 120 to have an optimal SI and data eye diagram for the data read from the memory device 120.

[0056] In operation S340, memory system 10 can perform a write training operation. Memory controller 100 can send data to memory device 120 and adjust the operating parameter codes of memory device 120 so that the sent data has optimal SI and data eye diagram.

[0057] In operation S350, after the initialization and training operations are performed in operations S310 to S340, the memory system 10 can perform normal operation.

[0058] Figure 4 This is a conceptual diagram used to describe a data manipulation circuit system according to an example embodiment. In the following example embodiments, for ease of explanation, the terms data DQ and DQ are used interchangeably.

[0059] Reference Figure 2 and Figure 4 Multiple DQ lines can transmit and receive internal data DIO (hereinafter referred to as "DIO data") through multiple DQ operation circuit systems 400 to 407, 408, 409 to 415. Each of the DQ operation circuit systems 400 to 408 and 408 to 415 can be an ODT circuit 240, a reference voltage generation circuit 250, a data input buffer 260, a data output buffer 270, or a DFE.

[0060] Typically, the signal pins connected to the DQ line are referred to as DQ pins. The collection of these signal pins is referred to as multiple DQ pins.

[0061] The DQ0 line can send and receive DIO0 data via the DQ0 operating circuit system 400. The DQ1 to DQ7 lines can send and receive DIO1 to DIO7 data via the DQ1 operating circuit system 401 to the DQ7 operating circuit system 407. Similarly, the DQ8 to DQ15 lines can send and receive DIO8 to DIO15 data via the DQ8 operating circuit system 408 to the DQ15 operating circuit system 415. DQ0 to DQ7 can be referred to as the low DQ bytes DQ[7:0], and DQ8 to DQ15 can be referred to as the high DQ bytes DQ[15:8].

[0062] Figures 5A to 5C It is used to describe Figure 4 A diagram showing the reference voltage VREF of the data line.

[0063] Figure 5AThe diagram shows the signal integrity (SI) of the DQ0 line when the reference voltage VREF is set to VREF1, VREF2, and VREF3. SI represents the size, vertical height, or width of the data eye diagram of the signal received through the DQ line. A larger SI indicates a more accurate identification of the DQ line. When the reference voltage VREF is set to VREF1, the DQ0 line can have SI1 signal integrity. When the reference voltage VREF is set to VREF2 or VREF3, the DQ0 line can have SI2 or SI3 signal integrity. It can be seen that SI2 or SI3 signal integrity is less than SI1 signal integrity. In other words, when the reference voltage VREF is set to VREF1, the DQ0 line has optimal SI.

[0064] Reference Figure 5B When the reference voltage VREF for lines DQ0, DQ1, and DQ2 is set to VREF1, lines DQ0, DQ1, and DQ2 can respectively possess SI1, SI2, and SI3 signal integrity. This is because the physical characteristics of lines DQ0, DQ1, and DQ2 are different from each other. In other words, when the reference voltage VREF is the same, different SIs can be obtained due to the different positions or physical characteristics of the DQ lines. In other words, when the reference voltage VREF is set to VREF1, line DQ0 can have optimal SI, but lines DQ1 and DQ2 may not have optimal SI.

[0065] Reference Figure 5C The reference voltage VREF for line DQ0 can be set to VREF1, the reference voltage VREF for line DQ1 can be set to VREF2, and the reference voltage VREF for line DQ2 can be set to VREF3. In this case, each of the DQ lines can have an optimal SI. In other words, by setting different reference voltages VREF for lines DQ0, DQ1, and DQ2 respectively, each DQ line can have an optimal SI.

[0066] It is possible Figure 3 The read training operation in operation S330 or the write training operation in operation S340 determines the optimal reference voltage VREF for each of the above DQ lines, and the information about the optimal reference voltage VREF can be stored in MRS 210 as a reference voltage parameter code.

[0067] Eye diagram Figures 5A to 5C The diagram shows how shifting the reference level up or down indicates a change in the reference level to sample the voltage passing through the eye at different levels. That is, Figures 5A to 5C The drawing instruction in the text adds a DC offset to the signal line to make it pass through Figure 9The sampler 920 minimizes the error. For example, based on the added offset, Figure 8 The DFE output 810 is adjusted to be in Figure 9 The input of the sampler 920 is at the optimal level.

[0068] Figure 6 This is a diagram showing a portion of the MRS 210 according to an example embodiment.

[0069] Reference Figure 2 and Figure 6 MRS 210 may include a first mode register 610, a second mode register 620, and a third mode register 630. Each of the three registers represents a set of registers associated with a given mode register, identifiable by its address. The first mode register 610 may be identified by the address MR_A1, the second mode register 620 by the address MR_A2, and the third mode register 630 by the address MR_A3.

[0070] The first mode register 610, the second mode register 620, and the third mode register 630 can store operation parameter codes for the reference voltage VREF of the DQ line. The first mode register 610 has three parameter codes stored by multiple registers OP[7:0] for the reference voltage VREF. The OP[2:0] registers can store the parameter VREFL for setting the reference voltage VREF of the DQ line in the lower DQ byte DQ[7:0]. The reference voltage parameter VREFL of the lower DQ byte DQ[7:0] stored in the OP[2:0] registers can be represented by a 3-bit parameter code and can have, for example, 8 set points or step coefficients. The OP[3] register can be reserved for future use (RFU), and the OP[6:4] registers can store the parameter VREFU for setting the reference voltage VREF of the DQ line in the higher DQ byte DQ[15:8]. The reference voltage parameter VREFU of the high DQ byte DQ[15:8] stored in the OP[6:4] register can be represented by a 3-bit parameter code and can have, for example, 8 set points or step coefficients. The reference voltage parameter VREFL of the low DQ byte DQ[7:0] and the reference voltage parameter VREFU of the high DQ byte DQ[15:8] can be referred to as the global reference voltage parameters. The OP[7] register can store the control parameter VREFS, which indicates whether the global reference voltage operation parameters VREFL and VREFU are supported for the DQ lines of the low DQ byte DQ[7:0] and high DQ byte DQ[15:8]. The control parameter VREFS can be a 1-bit parameter code.

[0071] According to the example embodiment, the global reference voltage operating parameters VREFL and VREFU of the low DQ byte DQ[7:0] and high DQ byte DQ[15:8] can be represented by less than 3 bits or more than 3 bits. The control parameter VREFS, indicating whether the global reference voltage operating parameters VREFL and VREFU for the reference voltage VREF with respect to the DQ line are supported, can include more than 1 bit.

[0072] The second mode register 620 has a parameter code for the reference voltage VREF of the DQ0 line stored in the OP[1:0] register. The OP[1:0] register can store the reference voltage sub-parameter VREFDQ0 that sets the reference voltage VREF of the DQ0 line. The reference voltage sub-parameter VREFDQ0 for the DQ0 line stored in the OP[1:0] register can be represented by a 2-bit parameter code and can have, for example, 4 set points or step coefficients.

[0073] pass Figure 3 In the read training operation in operation S330 or the write training operation in operation S340, the DQ0 line can have a reference voltage VREF (e.g., VREF1) with an optimal SI (e.g., SI1). The reference voltage VREF, set by the reference voltage parameter VREFL of the low DQ byte DQ[7:0] stored in the OP[2:0] register of the first mode register 610, will be applied to the DQ0 line. In the DQ0 line, a voltage difference (i.e., offset) can occur between the reference voltage VREF set by the reference voltage parameter VREFL for the low DQ byte DQ[7:0] and the reference voltage VREF with the optimal SI obtained through the training operation. The reference voltage sub-parameter VREFDQ0 of the DQ0 line can represent such an offset. In other words, the DQ0 line can be set by applying (subtracting or adding) the reference voltage sub-parameter VREFDQ0 to the reference voltage VREF set by the reference voltage parameter VREFL for the low DQ byte DQ[7:0]. Therefore, the DQ0 line can have a reference voltage VREF with an optimal SI. The reference voltage sub-parameter VREFDQ0 relative to the reference voltage VREF of the DQ0 line can be referred to as the per-pin reference voltage operating parameter.

[0074] The third mode register 630 has a parameter code for the reference voltage VREF of the DQ line stored in the OP[0] register. The OP[0] register can store the control parameter Per-pin VREFS, which indicates whether the per-pin reference voltage parameter VREFDQ0 for the DQ0 line is supported. The control parameter Per-pin VREFS can be a 1-bit parameter code.

[0075] According to an example embodiment, the reference voltage sub-parameter VREFDQ0, relative to the reference voltage VREF of the DQ0 line, can be represented by fewer than 2 bits or more than 2 bits. The control parameter Per-pin VREFS, indicating whether the reference voltage sub-parameter VREFDQ0 is supported, can include more than 1 bit. Although Figure 6 The description states that the control parameter VREFS can be stored in the first mode register 610 along with the global reference voltage operating parameters VREFL and VREFU regarding the reference voltage VREF of the DQ line; however, the example embodiment is not limited to this. For example, the control parameter VREFS can be stored in a fourth mode register, which is different from the first mode register 610, the second mode register 620, and the third mode register 610.

[0076] Figure 7 This is a diagram showing a portion of the MRS 210 according to an example embodiment. Figure 7 Show settings applied to Figure 6 Example of per-pin reference voltage parameter VREFDQ0 for the DQ0 line and other DQ lines.

[0077] Reference Figure 6 and Figure 7 Multiple mode registers have parameter codes stored for the reference voltages of the DQ[15:0] lines and the lines associated with DQ[15:0] (e.g., data mask / inversion signal DMI, data strobe signal DQS, etc.).

[0078] In the mode register identified by the MR_A21 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ0, which is applied to set the reference voltage VREF of line DQ0. The reference voltage sub-parameter VREFDQ1, which is applied to set the reference voltage VREF of line DQ1, can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ2, which is applied to set the reference voltage VREF of line DQ2, can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ3, which is applied to set the reference voltage VREF of line DQ3, can be stored in the OP[7:6] register.

[0079] In the mode register identified by the address of the MR_A22 mode register, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ4, which is applied to set the reference voltage VREF of line DQ4. The reference voltage sub-parameter VREFDQ5, which is applied to set the reference voltage VREF of line DQ5, can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ6, which is applied to set the reference voltage VREF of line DQ6, can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ7, which is applied to set the reference voltage VREF of line DQ7, can be stored in the OP[7:6] register.

[0080] Based on storage Figure 6 The reference voltage parameter VREFL about the low DQ byte DQ[7:0] in the OP[2:0] register of the first mode register 610, and the reference voltage sub-parameter VREFDQ[7:0] stored in the mode registers corresponding to the MR_A21 mode register address and the MR_A22 mode register address can be selectively used. When the control parameter Per-pinVREFS indicating whether the per-pin reference voltage operation parameter is supported is enabled by the OP[0] register of the third mode register 630, the DQ[7:0] lines can each apply the reference voltage sub-parameter VREFDQ[7:0] to the reference voltage VREF set by the reference voltage parameter VREFL about the low DQ byte DQ[7:0], thereby setting the optimal reference voltage VREF.

[0081] In the mode register identified by the MR_A23 mode register address, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ8, which is applied to set the reference voltage VREF of line DQ8. The reference voltage sub-parameter VREFDQ9, which is applied to set the reference voltage VREF of line DQ9, can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ10, which is applied to set the reference voltage VREF of line DQ10, can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ11, which is applied to set the reference voltage VREF of line DQ11, can be stored in the OP[7:6] register.

[0082] In the mode register identified by the address of the MR_A24 mode register, the OP[1:0] register can store the reference voltage sub-parameter VREFDQ12, which is applied to set the reference voltage VREF of line DQ12. The reference voltage sub-parameter VREFDQ13, which is applied to set the reference voltage VREF of line DQ13, can be stored in the OP[3:2] register, the reference voltage sub-parameter VREFDQ14, which is applied to set the reference voltage VREF of line DQ14, can be stored in the OP[5:4] register, and the reference voltage sub-parameter VREFDQ15, which is applied to set the reference voltage VREF of line DQ15, can be stored in the OP[7:6] register.

[0083] Based on what is stored Figure 6 The reference voltage parameter VREFU of the high DQ byte DQ[15:8] in the OP[6:4] register of the first mode register 610, and the reference voltage sub-parameter VREFDQ[15:8] stored in the mode registers corresponding to the MR_A23 mode register address and the MR_A24 mode register address, can be selectively used. When the control parameter Per-pinVREFS, which indicates whether the per-pin reference voltage operation parameter is supported, is enabled by the OP[0] register of the third mode register 630, the DQ[15:8] lines can each apply the reference voltage sub-parameter VREFDQ[15:8] to the reference voltage VREF set by the reference voltage parameter VREFU of the high DQ byte DQ[15:8], thereby setting the optimal reference voltage VREF.

[0084] In the mode register identified by the address of the MR_A25 mode register, the OP[1:0] register can store the reference voltage sub-parameter VREFDMI0, which is applied to set the reference voltage VREF for the first data mask / inversion signal DMI0 line (the line used for the first data mask / inversion signal DMI0). The OP[3:2] register can store the reference voltage sub-parameter VREFDMI1, which is applied to set the reference voltage VREF for the second data mask / inversion signal DMI1 line. The OP[5:4] register can store the reference voltage sub-parameter VREFDQS0, which is applied to set the reference voltage VREF for the first data strobe signal DQS0 line. The OP[7:6] register can store the reference voltage sub-parameter VREFDQS1, which is applied to set the reference voltage VREF for the second data strobe signal DQS1 line.

[0085] The first data mask / inversion signal DMI0 and the first data strobe signal DQS0 can be used as clock signals and control signals for the low DQ bytes DQ[7:0]. When the low DQ bytes DQ[7:0] are transmitted through memory bus 110 ( Figure 1When the DQ bus is transmitted / received, the first data mask / inversion signal DMI0 line and the first data strobe signal DQS0 line can apply reference voltage sub-parameters VREFDMI0 and VREFDQS0 to the reference voltage VREF set by the reference voltage parameter VREFL with respect to the low DQ byte DQ[7:0], thereby setting the optimal reference voltage VREF for the first data mask / inversion signal DMI0 line and the first data strobe signal DQS0 line respectively.

[0086] The second data mask / inversion signal DMI1 and the second data strobe signal DQS1 can be used as clock and control signals for the high DQ bytes DQ[15:8]. When the high DQ bytes DQ[15:8] are transmitted / received via the DQ bus of memory bus 110, the second data mask / inversion signal DMI1 line and the second data strobe signal DQS1 line can apply reference voltage sub-parameters VREFDMI1 and VREFDQS1 to the reference voltage VREF set by the reference voltage parameter VREFU with respect to the high DQ bytes DQ[15:8], thereby setting the optimal reference voltage VREF for the second data mask / inversion signal DMI1 line and the second data strobe signal DQS1 line respectively.

[0087] Figure 8 This is a diagram illustrating the effect of DFE on the DQ line according to an example embodiment.

[0088] Reference Figure 8 The DQ line 804 can experience loss and signal reflection. In the DQ line 804, inter-symbol interference (ISI) can cause one bit of data to interfere with subsequent bits and become distorted (i.e., smear out and spill over). A bit of the data signal 802 transmitted through the DQ line 804 can be received as a distorted signal 806 with the residue of the previous bit. ISI can become more significant as the data rate increases, and the pulse width representing the data bit narrows accordingly. The value of the distorted signal 806 received at the corresponding sampling point can be referred to as the tap value (e.g., main tap value C0, first tap value C1, second tap value C2, etc.) corresponding to the data signal 802 transmitted through the DQ line 804.

[0089] DFE 808 can calibrate the distorted signal 806 received at the corresponding sampling point by subtracting the residue of the previous bit to determine the current bit and generate a calibrated signal 810. Although Figure 8 An example is shown where only the first tap value C1 is calibrated by the DFE 808, but this is only for ease of explanation and the embodiments are not limited thereto.

[0090] Figure 9 It is used to describe Figure 8A diagram of the DFE 808.

[0091] Reference Figure 9 The DFE 808 may include a filtering unit 910 for calibrating received DQ0 data and a sampler 920 for sampling the filtered data. The filtering unit 910 may include multiple coefficient multipliers (also called DFE taps) 911_1 to 911_n that generate tap values ​​C1 to Cn based on time-delayed samples. Time-delayed samples may be provided by multiple time-delay units 912_1, 912_2, 912_3 to 912_(n-1), which delay the sampled signal SDQ0 received from the sampler 920. For example, the time delay may be τ. The adder 913 may add tap values ​​C1 to Cn to the DQ0 data or subtract tap values ​​C1 to Cn from the DQ0 data before forwarding the signal calibrated by the filtering unit 910 to the sampler 920. Sampler 920 samples the calibrated signal within a specific sampling period set by the write clock signal WCK. DFE taps 911_1 to 911_n each receive a DFE quantity DFEQ optimized for DQ0 data and multiply the delayed sample by the DFEQ to determine tap values ​​C1 to Cn. The DFE quantity DFEQ can be obtained from MRS 210 ( Figure 2 Provided. According to an example embodiment, DFE 808 may be included in... Figure 2 The data is input into buffer 260.

[0092] It is possible Figure 3 The read training operation in operation S330 or the write training operation in operation S340 determines the optimal DFE amount for each DQ[15:0] line including the DQ0 line, and the information about the optimal DFE amount can be stored as a parameter code in MRS 210.

[0093] Figure 10 This is a diagram showing a portion of the MRS 210 according to an example embodiment.

[0094] Reference Figure 2 , Figure 9 and Figure 10 The MRS 210 may include a first mode register 1010, a second mode register 1020, and a third mode register 1030. The first mode register 1010, the second mode register 1020, and the third mode register 1030 represent a register group associated with the DFE quantity DFEQ and may store operation parameter codes for the DFE quantity DFEQ on the DQ[15:0] lines. In this example embodiment, the DFE quantity DFEQ corresponding to the first tap value C1 is shown.

[0095] In the first mode register 1010, identified by the address of the MR_B1 mode register, the OP[2:0] register can store the parameter DFEQL for setting the DFE value DFEQ of the DQ line of the lower DQ byte DQ[7:0]. The DFE value parameter DFEQL of the lower DQ byte DQ[7:0] stored in the OP[2:0] register can be represented by a 3-bit parameter code and can have, for example, 8 set points or step coefficients. The OP[3] register can be reserved for future use (RFU), and the OP[6:4] register can store the parameter DFEQU for setting the DFE value DFEQ of the DQ line of the higher DQ byte DQ[15:8]. The DFE value parameter DFEQU of the higher DQ byte DQ[15:8] stored in the OP[6:4] register can be represented by a 3-bit parameter code and can have, for example, 8 set points or step coefficients. The parameter DFEQL, which sets the DFE quantity DFEQ of the DQ lines in the low DQ bytes DQ[7:0], and the parameter DFEQU, which sets the DFE quantity DFEQ of the DQ lines in the high DQ bytes DQ[15:8], can be referred to as global DFE quantity parameters. The OP[7] register can store a one-bit control parameter DFES, which indicates whether the parameters DFEQL and DFEQU regarding the DFE quantity are supported for the DQ lines in the low DQ bytes DQ[7:0] and high DQ bytes DQ[15:8].

[0096] According to the example embodiment, the global DFE quantity parameters DFEQL and DFEQU of the low DQ byte DQ[7:0] and high DQ byte DQ[15:8] can be represented by less than 3 bits or more than 3 bits. The control parameter DFES, which indicates whether the global DFE quantity parameters DFEQL and DFEQU of the DQ line are supported, can include more than 1 bit.

[0097] The second mode register 1020 has parameter codes for the DFE values ​​DFEQ of the lines that set the DQ[15:0] lines and the signals associated with DQ[15:0] (e.g., data mask / inversion signal DMI, data strobe signal DQS, etc.). In the mode register identified by the MR_B21 mode register address, the OP[1:0] register can store the DFE quantum parameter DFEDQ0 of the DFE value DFEQ applied to set the DQ0 line. The DFE quantum parameter DFEDQ1 of the DFE value DFEQ applied to set the DQ1 line can be stored by the OP[3:2] register, the DFE quantum parameter DFEDQ2 of the DFE value DFEQ applied to set the DQ2 line can be stored by the OP[5:4] register, and the DFE quantum parameter DFEDQ3 of the DFE value DFEQ applied to set the DQ3 line can be stored by the OP[7:6] register. In the mode register identified by the address of the MR_B22 mode register, the OP[1:0] register can store the DFE quantum parameter DFEDQ4, which is applied to set the DFE quantity DFEQ of the DQ4 line. The DFE quantum parameter DFEDQ5, which is applied to set the DFE quantity DFEQ of the DQ5 line, can be stored in the OP[3:2] register, the DFE quantum parameter DFEDQ6, which is applied to set the DFE quantity DFEQ of the DQ6 line, can be stored in the OP[5:4] register, and the DFE quantum parameter DFEDQ7, which is applied to set the DFE quantity DFEQ of the DQ7 line, can be stored in the OP[7:6] register.

[0098] In the mode register identified by the MR_B23 mode register address, the OP[1:0] registers can store the DFE quantum parameter DFEDQ8, which is applied to set the DFE quantity DFEQ of the DQ8 line. The DFE quantum parameter DFEDQ9, which is applied to set the DFE quantity DFEQ of the DQ9 line, can be stored in the OP[3:2] registers; the DFE quantum parameter DFEDQ10, which is applied to set the DFE quantity DFEQ of the DQ10 line, can be stored in the OP[5:4] registers; and the DFE quantum parameter DFEDQ11, which is applied to set the DFE quantity DFEQ of the DQ11 line, can be stored in the OP[7:6] registers. In the mode register identified by the MR_B24 mode register address, the OP[1:0] registers can store the DFE quantum parameter DFEDQ12, which is applied to set the DFE quantity DFEQ of the DQ12 line. The DFE quantum parameter DFEDQ13, which is applied to set the DFE quantity DFEQ of line DQ13, can be stored in the OP[3:2] register; the DFE quantum parameter DFEDQ14, which is applied to set the DFE quantity DFEQ of line DQ14, can be stored in the OP[5:4] register; and the DFE quantum parameter DFEDQ15, which is applied to set the DFE quantity DFEQ of line DQ15, can be stored in the OP[7:6] register.

[0099] In the mode register identified by the address of the MR_B25 mode register, the OP[1:0] register can store the DFE quantum parameter DFEDMI0, which is applied to set the DFE amount DFEQ of the first data mask / inversion signal DMI0 line; the OP[3:2] register can store the DFE quantum parameter DFEDMI1, which is applied to set the DFE amount DFEQ of the second data mask / inversion signal DMI1 line; the OP[5:4] register can store the DFE quantum parameter DFEDQS0, which is applied to set the DFE amount DFEQ of the first data strobe signal DQS0 line; and the OP[7:6] register can store the DFE quantum parameter DFEDQS1, which is applied to set the DFE amount DFEQ of the second data strobe signal DQS1 line.

[0100] The third mode register 1030 can store a 1-bit control parameter Per-pin DFES through the OP[0] register. The control parameter Per-pin DFES indicates whether the DFE quantum parameter DFEDQ[15:0] for the DQ[15:0] line DFE quantity DFEQ is supported. The DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] for the DQ[15:0] line, the data mask / inversion signal DMI0 line and the data mask / inversion signal DMI1 line, and the data strobe signal DQS0 line and the data strobe signal DQS1 line can be referred to as per-pin DFE quantity parameters.

[0101] According to the example embodiment, the DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] regarding the DQ[15:0] lines, the data mask / inversion signal DMI0 lines and the data mask / inversion signal DMI1 lines, and the data strobe signal DQS0 lines and the data strobe signal DQS1 lines can each be represented by a bit representation of less than 2 bits or more than 2 bits. The control parameter Per-pin DFES indicating whether the DFE quantum parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] are supported can include more than 1 bit. Although Figure 10 The description states that the control parameter DFES can be stored in the first mode register 1010 along with the global DFE parameters DFEQL and DFEQU of the DQ line, but the example embodiment is not limited to this. For example, the control parameter DFES can be stored in a fourth mode register, which is different from the first mode register 1010, the second mode register 1020, and the third mode register 1010.

[0102] When the control parameter Per-pin DFES, indicating whether the per-pin DFE quantity operation parameter is supported, is enabled via the OP[0] register of the third mode register 1030, the DQ[7:0] line, the first data mask / inversion signal DMI0 line, and the first data strobe signal DQS0 line can apply the DFE quantum parameters DFEDQ[7:0], DFEDMI0, and DFEDQS0 to the DFE quantity DFEQ set by the DFE quantity parameter DFEQL with respect to the low DQ byte DQ[7:0], the DFE quantity DFEQ of the first data mask / inversion signal DMI0 line, and the DFE quantity DFEQ of the first data strobe signal DQS0 line, respectively, thereby setting the optimal DFE quantity DFEQ for the corresponding data line. Furthermore, the DQ[15:8] line, the second data mask / inversion signal DMI1 line, and the second data strobe signal DQS1 line can apply the DFE quantum parameters DFEDQ[15:8], DFEDMI1, and DFEDQS1 to the DFE quantity DFEQ set by the DFE quantity parameter DFEQU about the high DQ byte DQ[15:8], the DFE quantity DFEQ of the second data mask / inversion signal DMI1 line, and the DFE quantity DFEQ of the second data strobe signal DQS1 line, respectively, thereby setting the optimal DFE quantity DFEQ of the corresponding data lines.

[0103] Figures 11 to 13 This is a diagram illustrating an example of the operation of a memory device 120 according to an example embodiment. Figure 11 This is used to describe the write training operation (operation S340) of memory device 120. Figure 3 The diagram shows... Figure 12 This is a diagram illustrating the operation of storing operation parameter codes in the MRS 210. Figure 11 and Figure 12 In the timing diagram shown, the horizontal and vertical axes represent time and voltage levels, respectively, and are not necessarily drawn to scale.

[0104] Reference Figure 2 , Figure 10 and Figure 11For the write training operation of memory device 120 (operation S340), the CAS command CAS (WS_WR=1) can be received synchronously with the clock signal CLK at time T0. After a predetermined time tWCKENL_WR has elapsed since the CAS command CAS (WS_WR=1), the write clock signal WCK can be synchronized with the clock signal CLK. In one embodiment, the clock signals CLK_t and CLK_c, and the write clock signals WCK_t and WCK_c are differential clock inputs. At time T1, the write command WRITE can be received after the CAS command CAS (WS_WR=1). The deselect command DES can be received after the write command WRITE. At time T2, the write data DQ corresponding to the burst length (e.g., BL16) can be received from the write command WRITE. At this time, the data mask / inversion signal DMI can be received together with the write data DQ.

[0105] When the control parameter DFES, indicating whether the DQ[15:0] line supports the global DFE quantity parameters DFEQL and DFEQU, is disabled, the time point T2 can be set to a predetermined time TWCK2DQI after the write delay WL of the write command WRITE. In this case, operation S310 (for initializing the memory device 120) can be performed. Figure 3 During this period, the global DFE parameters DFEQL and DFEQU are set to the default operating parameters.

[0106] When the control parameter DFES is enabled, the write data DQ line and the data mask / inversion signal DMI line can be pre-driven low for a predetermined pre-drive time tDPRE before time point T2. For example, the pre-drive time tDPRE can be set to approximately 2 unit intervals (UI). UI represents the unit period during which 1 bit of data is held. In other words, because the DFE needs to process previous data and feed it back to the current data, the pre-drive time tDPRE will be required to account for the time elapsed since previous data has been fed back.

[0107] Reference Figure 12 The write training operation of the memory device 120 can be performed in parallel for the DQ[15:0] lines, the data mask / inversion signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines (operation S340). The optimal DFE amount DFEQ of each of the DQ[15:0] lines, the data mask / inversion signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines can be determined by the write training operation (operation S340).

[0108] The optimal DFE values ​​DFEQ for the DQ[15:0] lines, the data mask / inversion signal DMI1[1:0] lines, and the data strobe signal DQS[1:0] lines can be stored in the mode register of the MRS 210 (operation TS1). In this case, the elapsed time tTS1. Since the elapsed mode register write time tM is elapsed for each of the 20 signals DQ[15:0], DMI1[1:0], and DQS[1:0], the time tTS1 is approximately 20 × tM. Furthermore, the DFE value DFEQ for each of the data mask / inversion signal DMI1[1:0] lines and the data strobe signal DQS[1:0] lines can be represented by 8 step coefficients using a 4-bit parameter code. In this case, when 4 bits are allocated to the parameter for the DFE value DFEQ for each of the 20 signals DQ[15:0], DMI1[1:0], and DQS[1:0], a mode register of 20 × 4 = 80 bits is required.

[0109] In contrast, it is represented as Figure 10 The per-pin DFE parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0], which are offset values ​​of the global DFE parameters DFEQL and DFEQU described in the description, can be stored in the mode registers of the MRS 210 (operation TS2). In this case, the elapsed time tTS2 is approximately equal to the write time of the five mode registers MR_B21, MR_B22, MR_B23, MR_B24, and MR_B25 (i.e., approximately 5 × tM). It can be seen that time tTS2 is significantly shorter than time tTS1. Furthermore, when the per-pin DFE parameters DFEDQ[15:0], DFEDMI[1:0], and DFEDQS[1:0] are stored in the five mode registers MR_B21, MR_B22, MR_B23, MR_B24, and MR_B25, as Figure 10 As shown in the diagram, a 40-bit mode register is required, thus saving mode register resources.

[0110] Reference Figure 13Assuming that through the write training operation (operation S340) of memory device 120, the optimal DFE quantity DFEQ of DQ0 line has DFE

[001] among the 8 step coefficients of DFE, and the optimal DFE quantity DFEQ of DQ7 line has DFE

[111] . When the DFE quantity parameter DFEQL of the low DQ byte DQ[7:0] is determined to be DFEQL

[100] among the 8 step coefficients of DFE, the OP[1:0] register of the MR_B21 mode register corresponding to the DFE quantum parameter of DQ0 line can be set to DFEDQ0

[11] , and the OP[7:6] register of the MR_B22 mode register corresponding to the DFE quantum parameter of DQ7 line can be set to DFEDQ7

[11] . When DFE operation is enabled per pin, the DQ0 line obtains the optimal DFE amount DFE

[001] by subtracting DFEDQ0

[11] from DFEQL

[100] , and the DQ7 line obtains the optimal DFE amount DFE

[111] by adding DFEDQ7

[11] to DFEQL

[100] .

[0111] Figure 14 This is a diagram used to describe the swing width calibration of the DQ line according to an example embodiment.

[0112] Reference Figure 2 and Figure 14 The VOH specification SPEC for the data DQ output from the data output buffer 270 of the memory device 120 defines that the swing width of the data DQ has a constant value. The memory device 120 can read the training operation (operation S330, ... Figure 3 The memory device 120 calibrates the swing width of the data DQ by comparing the voltage level of the data DQ output from the data output buffer 270 with the voltage level of the reference voltage VREF, and calibrating the size of the swing widths A_SWING, B_SWING, and C_SWING of the data DQ based on the comparison result. The reference voltage VREF has a voltage value that determines the size of the DQ swing width and is set to the average of the maximum and minimum voltages of the DQ swing width.

[0113] When the level of the reference voltage VREF changes, it is necessary to have DQ swing width parameters, A_SWING, B_SWING, and C_SWING, determined by reading the training operation (operation S330). Similar to... Figure 10 The DQ swing width parameter may include a global DQ swing width parameter and a per-pin DQ swing width parameter represented as an offset value of the global DQ swing width parameter, and may be stored in the MRS 210. According to an example embodiment, the DQ swing width parameter may be... Figure 6 and Figure 7The parameter codes for the reference voltage VREF described herein are used in combination.

[0114] Figure 15 This is a diagram used to describe the pre-emphasis operation of the DQ line according to an example embodiment.

[0115] Reference Figure 2 and Figure 15 This can provide pre-emphasis operation to improve SI of the DQ line and the data mask / inversion signal DMI line. After the signal transmitted via the data bus undergoes attenuation due to transmission lines (such as wires or cables) on the printed circuit board (PCB), fluctuations in the received signal voltage amplitude and received signal timing are expected at the receiving end of the transmission line. It is necessary to extend the data eye aperture area, which is considered an indicator of the normal receiving area at the receiving end.

[0116] Memory device 120 may include a training operation (operation S330) that reads training data. Figure 3 The data output buffer 270 performs a pre-emphasis operation on the DQ line. For example, when the current bit signal on the DQ line and the data mask / inversion signal DMI line changes from logic low to logic high, a first high output voltage Voh1 can be output, thus emphasizing the logic high waveform (emphasis operation). While the current bit signal remains logic high, a second high output voltage Voh2, lower than the first high output voltage Voh1, can be output to prepare for the next signal change (deemphasis operation). Furthermore, when the current bit signal changes from logic high to logic low, a first low output voltage Vol1 can be output, thus emphasizing the logic low waveform (emphasis operation). While the current bit signal remains logic low, a second low output voltage Vol2, higher than the first low output voltage Vol1, can be output to prepare for the next signal change (deemphasis operation). For example, the first high output voltage Voh1, the second high output voltage Voh2, the first low output voltage Vol1, and the second low output voltage Vol2 can be between the power supply voltage VDD and the ground voltage VSS, respectively.

[0117] Pre-emphasis enables signal transmission at higher data rates over longer distances and suppresses signal reflections at the transmitter. Therefore, a DQ pre-emphasis parameter is needed that determines the appropriate DQ pre-emphasis by reading the training operation (operation S330). Similar to... Figure 10 The DQ preemphasis parameters may include global DQ preemphasis parameters and per-pin DQ preemphasis parameters represented as offset values ​​of global DQ preemphasis parameters, and may be stored in the MRS 210.

[0118] As described above, the MRS 210 can set the operating parameters with respect to the reference voltage VREF, DFE amount, swing width calibration and / or pre-emphasis operation as global operating parameters and per-pin operating parameters represented as offset values ​​relative to the global operating parameters by using a set of registers (i.e., the first mode register, the second mode register and the third mode register) associated with the corresponding operating parameters.

[0119] For example, in some embodiments, the global operation parameter code and the first pin (e.g., with) Figure 1 The first offset value of any of the pins associated with DQ in the DQ ( Figure 6 , Figure 7 and Figure 10 The combination of ) is configured to be determined by adjusting the VREF value. Figure 9 The first decision level of the first sampler (e.g., sampler 920), wherein the first sampler is configured to be connected to the first signal line (e.g., ...) of the first pin. Figure 8 Operate on (808). In Figure 8 After the operation of DFE 808 or DFE taps 911_1, ..., 911_n, the signal on the first signal line, which is considered a single pulse, may have the following characteristics: Figure 8 The valid representation shown in item 810 is as follows.

[0120] In another example, in some embodiments, the combination of the global operation parameter code and the first offset value of the first pin is configured to determine the first DFE tap value of the first decision feedback equalizer (DFE) (e.g., DFE 808) used with the first sampler (e.g., sampler 920). Figure 9 The tap 911_1), wherein the first DFE and the first sampler are configured to operate on a first signal line connected to the first pin. Apart from the description of the DFE tap value, the global operation parameter code, the first offset value, the first pin, and the first sampler are as described immediately following the description of the decision level above.

[0121] In yet another example, in some embodiments, a combination of the global operating parameter code and the first offset value of the first pin is configured to determine a first resistance value (OTD) for terminating the first pin, wherein the first pin is connected to the first sampler, and the first sampler is configured to operate on a first signal line connected to the first pin. Apart from the description regarding the resistance value (OTD), the global operating parameter code, the first offset value, the first pin, and the first sampler may be as described immediately following the description of the decision level above.

[0122] Various operating parameters associated with the MRS 210 may include the DQ-ODT value, CA-ODT value, VREF-CA value, VREF-CA range, and VREF-DQ range. These operating parameters can also be set as global operating parameters and per-pin operating parameters represented as offsets relative to the global operating parameters using a set of registers associated with the corresponding operating parameters (i.e., the first mode register, the second mode register, and the third mode register). Global operating parameters associated with the CA-ODT value, VREF-CA value, and VREF-CA range can be provided as operating parameter codes for the entire CA signal.

[0123] The memory device can control signal pins by applying common operating conditions to signal pins associated with operating parameters using global operating parameter codes, and additionally by applying specific offset operating conditions to corresponding signal pins associated with operating parameters using per-pin operating parameter codes. This allows for the utilization of operating conditions optimized for the characteristics of the respective signal pins. Furthermore, by setting the offset, represented as the difference from the global operating parameters, as the per-pin operating parameter code, the number of registers required to store the operating parameter codes in the mode register and the update time of the mode registers can be reduced.

[0124] While exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a memory controller, the method comprising: The first information of the Mode Register Configuration (MRS) of the received memory device includes control parameters that indicate that the memory device supports decision feedback equalizer (DFE) quantity operation of the data (DQ) pin of the memory device. Send CAS commands synchronized with the clock signal to the memory device; Send the write command to the memory device; A write clock signal synchronized with the clock signal is sent to the memory device after a predetermined time has elapsed since the CAS command. The written data is sent to the memory device via the data line; as well as Send the second information to the MRS of the memory device. The data line is pre-driven at logic low for a predetermined pre-drive time based on control parameters, and The second information in the MRS includes global operating parameters and per-pin operating parameters for DFE quantity operations. The global operating parameters are associated with the DQ pins, and the per-pin operating parameters are associated with the corresponding DQ pins.

2. The method according to claim 1, wherein, The operating parameters for each pin are represented as offsets from the global operating parameters.

3. The method according to claim 1, wherein, Global operating parameters include the low-byte DFE parameters of the low-DQ byte pins in the DQ pins and the high-byte DFE parameters of the high-DQ byte pins in the DQ pins.

4. The method according to claim 1, wherein, The second information in the MRS includes at least one of the operating parameters of the memory device, and the operating parameters include a drive strength parameter associated with the DQ pin, a pre-emphasis parameter, an on-chip termination (ODT) parameter, and a reference voltage parameter.

5. The method according to claim 4, wherein, The at least one parameter includes a global parameter associated with the DQ pin and a second per-pin operation parameter associated with the corresponding data DQ pin.

6. The method according to claim 1, further comprising: No command is sent between the CAS command and the write command.

7. The method according to claim 1, further comprising: The data mask / inversion signal associated with the written data is sent to the memory device via signal lines. The signal line is pre-driven at logic low for a predetermined pre-drive time.

8. The method according to claim 1, wherein, The pre-drive time is set before the time when the written data is sent.

9. The method according to claim 8, wherein, The pre-drive time is set to approximately two unit intervals (UI).

10. The method according to claim 9, wherein, UI represents the unit of time during which 1 bit of data is retained.

11. The method according to claim 1, wherein, During the predetermined pre-drive time, the memory device processes the previous data and feeds the previous data back to the current data (DQ).

12. The method according to claim 1, wherein, The first number of bits in the per-pin operation parameter associated with one of the corresponding DQ pins is 2 bits, and the second number of bits in the global operation parameter associated with the DQ pins is 3 bits.

13. A memory controller, comprising: The register control word (RCW) is configured to include information about the mode register configuration (MRS) of the memory device. The MRS information includes control parameters that indicate whether the memory device supports decision feedback equalizer (DFE) quantity operation on the data (DQ) pins of the memory device. as well as The training circuit is configured to perform training on DFE quantity operations and determine the global operating parameters and per-pin operating parameters of the DFE quantity operations. The global operating parameters are associated with the DQ pins, and the per-pin operating parameters are associated with the corresponding DQ pins. Specifically, the memory controller pre-drives the DQ pin to logic low before performing the training. The memory controller is configured as follows: Send CAS commands synchronized with the clock signal to the memory device; Send the write command to the memory device; A write clock signal synchronized with the clock signal is sent to the memory device after a predetermined time has elapsed since the CAS command. The data to be written is sent to the memory device via the data line; and The global operating parameters and per-pin operating parameters of the DFE quantity operations determined by the training circuit are sent to the MRS of the memory device.

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