Apparatus and method for controller signaling refresh operations

Abstract

The invention relates to an apparatus and method for a controller to signal refresh operations. The memory may receive a first or second type of refresh command. In response to the first type of refresh command, a first type of refresh operation (e.g., a sequential refresh operation) may be performed. In response to the second type of refresh operation, a second type of refresh operation (e.g., a target refresh operation) may be performed. This may allow the controller to have greater control over the timing of different types of refresh operations in the memory.

Description

Technical Field

[0001] This application relates to memory devices, and in particular, to an apparatus and method for signaling a refresh operation for a controller. Background Art

[0002] Information can be stored on memory cells of a memory device. The memory cells can be organized at intersections of word lines (rows) and bit lines (columns). Information in the memory cells can decay over time. For example, the information can be stored as charge on a capacitor that can decay over time. The memory device can perform a refresh operation to restore the information and prevent information loss.

[0003] Certain access patterns can cause an increased rate of decay of information in nearby memory cells (e.g., memory cells along nearby word lines). The memory device can use various schemes to identify these access patterns so that additional targeted refresh operations can be performed. The controller can send signals to the memory to perform refresh operations, some of which can be sequential operations to refresh the decaying memory cells at an expected rate, and some of which can be targeted refresh operations. There is a need to give the controller more precise control over the types of refresh operations performed. Summary of the Invention

[0004] In one aspect, this application provides an apparatus including: an aggressor address queue configured to store identified aggressor addresses; a sequential refresh address generator circuit configured to generate a refresh address based on sequence logic in response to a refresh command; and a targeted refresh address generator configured to generate the refresh address based on the identified aggressor addresses stored in the aggressor address queue in response to a refresh management command.

[0005] In another aspect, this application provides a system including: a controller configured to provide a refresh command or a refresh management command; and a memory configured to perform a sequential refresh operation instead of a targeted refresh operation in response to the refresh command, and configured to perform a targeted refresh operation instead of a sequential refresh operation in response to the refresh management command.

[0006] In another aspect, this application provides a method including: receiving, at a memory, a first type of refresh command; performing, in response to the first type of refresh command, a first type of refresh operation; receiving, at the memory, a second type of refresh command; and performing, in response to the second type of refresh command, a second type of refresh operation. Brief Description of the Drawings

[0007] Figure 1 A block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 Block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0009] Figure 3 Block diagram of a controller according to some embodiments of the present disclosure.

[0010] Figure 4 Timing diagram of an example operation of a controller according to some embodiments of the present disclosure.

[0011] Figure 5 Flowchart of a method according to some embodiments of the present disclosure. Detailed Description

[0012] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the systems and methods of the present invention, reference is made to the accompanying drawings, which form a part hereof, and which are shown by way of illustration of specific embodiments in which the described systems and methods may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the systems and methods disclosed herein, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Additionally, for clarity, when the detailed description of certain features would be apparent to those skilled in the art, the detailed description thereof will not be set forth so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0013] Information in a memory array can be accessed through one or more access operations such as read or write operations. During an example access operation, a word line can be activated based on a row address, and then information of selected memory cells along the active word line can be read or written based on which bit lines are accessed, which bit lines can be based on a column address. The memory array can be refreshed on a row-by-row basis (e.g., as part of an auto-refresh and / or self-refresh mode), where memory cells along each row are refreshed periodically. This refresh operation can be referred to as a sequential refresh operation because the memory can use some sequential logic (e.g., a counter) to generate refresh addresses. The speed at which a row is refreshed can be determined based on an expected information decay rate (e.g., the maximum time that any given row will elapse between refreshes).

[0014] Various access patterns to a row (the aggressor row) can cause an increased rate of information decay in nearby memory cells (e.g., along the victim row). For example, 'row hammering' can involve repeated accesses to the aggressor row, which can increase the decay rate of adjacent rows (and / or more distant rows). Thus, it may be important to track the number of accesses to each row to determine if it is an aggressor, such that victim rows can be identified and refreshed as part of a targeted refresh operation. For example, each word line can have an associated count value that is used to determine how many times the word line has been accessed.

[0015] A conventional memory system can be set up such that both the memory and the controller are able to determine when to perform a targeted refresh operation. For example, the memory can be made to 'steal' one out of every N sequential refresh operations to perform a targeted refresh operation. The controller can monitor the access patterns and issue a Refresh Management (RFM) command based on those access patterns. However, this can be inefficient and lead to situations where the memory is over-refreshed, thus spending time that could have been used for sequential refresh operations, which in turn can increase the downtime of the device. Thus, there is a need for the controller to have more control over how to schedule sequential and targeted refresh operations.

[0016] The present disclosure relates to an apparatus, system, and method for a controller to signal a refresh operation. The controller can issue a refresh command or a refresh management command. In response to the refresh command, the memory performs a sequential refresh command. In response to the refresh management command, the memory performs a targeted refresh operation (based on an aggressor address identified by the memory). The controller can include targeted refresh logic that tracks the access patterns to the memory and issues an RFM command based on those accesses. For example, the controller can count the accesses on a per-group basis and, when the access count exceeds a threshold, issue an RFM to the group. This can allow the controller to exert more control over when to perform each type of refresh operation.

[0017] In some embodiments, the memory can perform sequential refresh operations exclusively in response to a refresh command and targeted refresh operations exclusively in response to an RFM command. For example, in response to a refresh command, the memory can perform one or more sequential refresh operations instead of any targeted refresh operations. In response to an RFM command, the memory can perform one or more targeted refresh operations instead of any sequential refresh operations.

[0018] Figure 1Block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The device 100 may be operated by a controller such as the controller 150. The controller may be any device (or collection of devices) that stores information on the memory. For example, the controller 150 may be a processor. In some embodiments, the controller 150 and the memory 100 may be packaged together on a single integrated circuit. In some embodiments, the controller 150 and the memory 100 may be separate. In some embodiments, the controller 150 may operate multiple memory devices 100.

[0019] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. In Figure 1 the embodiment, the memory array 118 is shown as including eight memory banks BANK0 to BANK7. There may be more or fewer banks in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC disposed at the intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0020] The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. In Figure 1 the embodiment, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMP). The read data from the bit lines BL is amplified by the sense amplifiers SAMP and transmitted to the read / write amplifier 120 through complementary local data lines (LIOT / B), transmission gates (TG), and complementary main data lines (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifiers SAMP through the complementary main data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B, and is written in the memory cells MC coupled to the bit lines BL.

[0021] The semiconductor device 100 may employ a plurality of external terminals coupled to the controller 150. The external terminals include command and address (C / A) terminals that are coupled to the controller 150 along a command and address bus to receive commands and addresses. Other external terminals include clock terminals for receiving clock signals CK and / CK along a clock bus, data terminals DQ for transmitting and receiving data along a data bus, and power terminals for receiving power potentials such as VDD, VSS, VDDQ, and VSSQ.

[0022] The controller 150 supplies an external clock CK and / CK to the clock terminals, and the external clock is provided to the input circuit 112. The external clock can be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 110 and is provided to the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for the timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operations of the circuits included in the input / output circuit 122, such as being provided to the data receiver to time the reception of the written data.

[0023] The controller 150 can supply a memory address to the C / A terminals. The memory address supplied to the C / A terminals is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply the decoded bank address BADD, which can indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. A command can be supplied to the C / A terminals. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory (such as a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD that indicate one or more memory cells to be accessed.

[0024] The command can be provided to the command decoder 106 as an internal command signal via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0025] As part of an example read operation, the device 100 can send a read command and a memory address indicating where the read command should be executed. In response to the read command, data is read from the memory cells of the bank specified by BADD at the intersection of the row specified by XADD and the column specified by YADD. The read command is received by the command decoder 106, which provides an internal command such that the read data from the memory array 118 is provided to the read / write amplifier 120. The read data is output from the data terminal DQ to the controller 150 via the input / output circuit 122.

[0026] As part of an example write operation, device 100 may receive a write command and data to be written to the array and a memory address indicating where the write operation should be performed. In response to the write command, data is written to the group specified by BADD at the memory cell at the intersection of the word line specified by XADD and the column specified by YADD. The write command is received by command decoder 106, which provides an internal command such that the write data is received by the data receiver in input / output circuit 122. A write clock may also be provided to an external clock terminal for timing the reception of the write data by the data receiver in input / output circuit 122. The write data is supplied via input / output circuit 122 to read / write amplifier 120 and is supplied by read / write amplifier 120 to memory array 118 for writing to memory cell MC specified by the address.

[0027] Device 100 may also receive a command that causes it to perform a refresh operation. For example, controller 150 of the memory may place device 100 in an auto-refresh mode, where the refresh operation is directed by controller 150. As part of the auto-refresh mode, controller 150 may supply different types of refresh commands (e.g., over the C / A bus to the C / A terminals of the memory). A first type of refresh command (e.g., refresh command REF) may be used to manage sequential refresh operations. A second type of refresh command (e.g., refresh management command RFM) may be used to manage targeted refresh operations.

[0028] Refresh signals REF and RFM are supplied to refresh address control circuit 116. Refresh address control circuit 116 supplies one or more refresh row addresses RXADD to row decoder 108, which refreshes one or more word lines WL identified by the refresh row address RXADD. As described in more detail herein, the use of command REF or RFM may determine the type of refresh operation performed by refresh control circuit 116. A first type of refresh operation (e.g., a sequential refresh operation) may be performed in response to REF, while a second type of refresh operation (e.g., a targeted refresh operation) may be performed in response to RFM. In some embodiments, controller 150 may issue both types of refresh commands REF and RFM together, and memory 100 may perform a mix of sequential and targeted refresh operations. Which type(s) of refresh operation is performed may determine the details of how refresh control circuit 116 performs the refresh, such as how it generates refresh address RXADD, how many word lines are associated with each address RXADD, how many refresh addresses are issued, or a combination thereof.

[0029] In response to a refresh command REF, the refresh control circuit 116 may perform a sequential refresh operation by issuing one or more sequential refresh addresses as RXADD. The sequential refresh addresses may be generated based on an address sequence. For example, after issuing a sequential refresh address, a counter circuit may increment the address to generate the next address in the sequence. The refresh address control circuit 116 may cycle through the sequential address sequence at a rate determined by REF. In some embodiments, the sequence of sequential addresses may include all addresses in the memory bank 118. In some embodiments, the controller 150 may issue the signal REF at a certain frequency such that most or all of the addresses in the memory bank 118 are refreshed within a particular period (e.g., such that there is a maximum specified time between two consecutive sequential refreshes of a given word line), which may be based on the expected rate of information decay in the memory cells MC.

[0030] In response to a targeted refresh command RFM, the refresh control circuit 116 may perform a targeted refresh operation. The refresh control circuit 116 identifies addresses as targets for the targeted refresh operation. These addresses may generally be referred to as violators, although different embodiments may use different criteria to identify these addresses. The refresh control circuit 116 may include a register that stores the identified violators. As part of the targeted refresh operation, one or more refresh addresses are generated based on the selected violators. For example, in some embodiments, the refresh address may represent a word line that is physically adjacent to the word line associated with the identified violator address (e.g., RXADD = XADD + / - 1). Other relationships may be used in other example embodiments. For example, more distant word lines may be refreshed (e.g., RXADD = XADD + / - 2, + / - 3, etc.).

[0031] The memory device 100 may use one or more systems to determine which addresses are violators. For example, a particular system description of the device 100 is stored in the memory array relative to row access counts. However, other types of violator detection may be used instead of or in addition to the violator detection system described herein. For example, other types of violator detection may be based on the row address XADD received from the controller 150 rather than the count value stored in the array 118.

[0032] In Figure 1In an example embodiment, some of the memory cells of the array 118 may be reserved for tracking the aggressor row. Memory cells 126 reserved for such purposes are generally referred to as counter memory cells 126. The counter memory cells may store count values XCount, each of which is associated with one of the word lines. For example, each count value XCount may be stored in a counter memory cell 126 along the word line with which the count value is associated. The count value XCount may be stored as a binary number, with each bit stored in a memory cell along the word line. For clarity, Figure 1 shows a single bit line of the counter memory cell 126. The number of counter memory cells along each word line may be based on the number of bits of the count value XCount. In some embodiments, additional counter memory cells (e.g., longer than the number XCount) may be used, for example, to store error correction information for the count value XCount.

[0033] The counter memory cells 126 may be called counter memory cells due to their use (storing count values), and in some embodiments, may be structurally similar to or equivalent to other memory cells of the array. In some embodiments, the counter memory cells 126 may be grouped together (e.g., at the end of a word line). In other example embodiments, other distributions of the counter memory cells 126 along the word line may be used. In some embodiments, the counter memory cells 126 may not be directly accessible by an external device such as a controller (e.g., to prevent the count value from being overwritten). In other words, the bit lines associated with the counter memory cells 126 may not be accessed by normal column addresses.

[0034] The count value XCount may be used to determine whether the associated word line is an aggressor. For example, whenever a word line is accessed, the count value XCount may be read out to a refresh control circuit, which may update the count, compare the updated count with a threshold, and write the updated count back to the counter memory cell 126. For example, the count may be updated by incrementing. If the updated count exceeds the threshold, the row address XADD (and count XCount) associated with the word line may be stored as an aggressor, and the count value may be updated again by resetting to an initial value (e.g., 0). In some embodiments, the threshold may represent the maximum value of the count, and the count may exceed the threshold by 'rolling' back to the initial value (e.g., from 11111111 to 00000000).

[0035] In some embodiments, the memory device 100 may also have a self-refresh mode, in which the memory device 100 performs its own refresh, for example, to maintain the state of data in the array when in an idle state. In some embodiments, when entering the self-refresh mode, the refresh control circuit 116 may generate a refresh signal with a periodic timing and perform a refresh operation in response to the refresh signal. In some embodiments, when the device is in the self-refresh mode, only sequential refresh may be performed (e.g., because no access is performed and no row will be hammered). In some embodiments, a mix of sequential and targeted refresh operations may be performed. For example, if there are aggressor addresses in the aggressor queue, the refresh control circuit may perform a mix of targeted and sequential refresh operations during the self-refresh mode until the queue is empty.

[0036] A power supply potential VDD and VSS are supplied to the power supply terminals. The power supply potential VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, etc. based on the power supply potential VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potential VARY is mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0037] A power supply potential VDDQ and VSSQ are also supplied to the power supply terminals. The power supply potential VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potential VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potential VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potential VDDQ and VSSQ supplied to the power supply terminals may be a different potential from the power supply potential VDD and VSS supplied to the power supply terminals. The power supply potential VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 such that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0038] Figure 2 It is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. Figure 2 An example layout of a part of the memory device 200 (e.g., Figure 1 the memory device 100) that can implement the memory device may be shown. For example, the memory array 218 may implement Figure 1 the memory array 118, the row decoder 208 may implement Figure 1 the row decoder 108, the refresh control circuit 216 may implement Figure 1 the refresh control circuit 116, etc.

[0039] Certain internal components and signals of the refresh address control circuit 216 are shown to illustrate the operation of the refresh address control circuit 216. For example, the refresh control circuit 216 includes a violator address register or violator address queue 244 that stores the identified violator address, a refresh address generator 250 that generates a refresh address RXADD, and a violator detector circuit 217 that determines whether an address XADD is a violator address HitXADD. The refresh control circuit 216 also includes a self-refresh (SREF) logic circuit 260 that can control the refresh operation in the self-refresh mode.

[0040] The dashed lines around the refresh address control circuit 216, row decoder 208, and memory array 218 are shown to indicate that in some embodiments, each of the components within the dashed lines can correspond to a particular memory bank, and these components can be repeated for each of the memory banks. In some embodiments, the components shown within the dashed lines can be associated with each of the memory banks. Thus, there can be multiple refresh address control circuits 216, each of which has its own violator address in its own violator queue 244. For simplicity, only a single group of components will be described.

[0041] The DRAM interface 240 can provide one or more signals to the address refresh control circuit 216 and the row decoder 208, which in turn (along with a column decoder, not shown) can perform access operations on the memory array 218. The DRAM interface 240 represents various components of the memory that, as part of the access operation, send signals to, receive signals from, and / or decode signals for the controller. For example, the DRAM interface 240 can represent a command / address input circuit (e.g., Figure 1 of 102), an address decoder (e.g., Figure 1 of 104), and a command decoder (e.g., Figure 1 of 106). During an example access operation, the DRAM interface 240 provides a row address XADD, as well as Figure 2 other signals not shown, such as an activate signal ACT and a precharge signal Pre. The DRAM interface 240 also provides commands received from the controller (e.g., Figure 1 of 150), such as a refresh command REF and a refresh management command RFM.

[0042] In response to a refresh command REF, the memory performs one or more sequential refresh operations. As part of the sequential refresh operations, a refresh address generator circuit 250 provides one or more refresh addresses RXADD generated by a sequential refresh address circuit 252. The sequential refresh address generator circuit may use logic to generate each new refresh address as part of a sequence. Each new sequential refresh address may be based on a previous sequential refresh address. In other words, sequential logic may be used to update a previous refresh address provided by the sequential address generator circuit 252 to generate a next refresh address to be provided by the sequential address generator circuit 252. For example, the sequential refresh address generator circuit 252 may include a counter circuit that updates the value of a previous sequential refresh address to generate a new sequential refresh address (e.g., RXADD(i) = RXADD(i - 1)+1). In other example embodiments, other logic may be used to generate a sequence of sequential refresh addresses.

[0043] In response to a refresh management command RFM, a refresh control circuit 216 may perform one or more targeted refresh operations. As part of the targeted refresh operations, a targeted refresh address generator circuit 254 of a refresh address generator 250 provides one or more targeted refresh addresses as the refresh address RXADD. The targeted refresh address generator circuit 254 of the refresh address generator 250 generates the targeted refresh addresses based on identified aggressor addresses HitXADD stored in an aggressor queue 244. For example, the targeted refresh address generator 254 may generate two targeted refresh addresses based on an aggressor address HitXADD representing a word line adjacent to HitXADD (e.g., RXADD = HitXADD+ / -1) in an array 218. In other example embodiments, other numbers of addresses per aggressor and other methods of generating refresh addresses based on aggressors may be used.

[0044] In response to the refresh address RXADD (whether sequential or targeted) and the signal REF or RFM, a row decoder 208 refreshes memory cells along one or more word lines indicated by the refresh address. In some embodiments, the sequential refresh address may indicate a different number of word lines than the targeted refresh address. For example, the sequential refresh address may be associated with more word lines than the targeted refresh address. In some embodiments, the sequential refresh address may be associated with multiple word lines, while the targeted refresh address is associated with a single word line.

[0045] The refresh control circuit 216 may include an optional self-refresh logic circuit 260. The controller may put the memory into a self-refresh mode (e.g., by sending a self-refresh entry command, by putting the memory in an idle state, etc.). During the self-refresh mode, the self-refresh logic circuit 260 may control the refresh operation without external commands such as REF and RFM. For example, during the self-refresh mode, the self-refresh logic circuit 260 may periodically output a refresh signal. In response to the refresh signal, a sequential refresh address generator may generate a refresh address RXADD and the row decoder 208 performs a refresh operation. In some embodiments, the self-refresh logic 260 may perform sequential refresh operations only in the self-refresh mode. In some embodiments, the self-refresh logic 260 may check the status of the queue 244 and may perform a mix of targeted and sequential refresh operations (e.g., by providing a refresh signal and a targeted refresh signal) until the queue 244 is empty.

[0046] The refresh control circuit 216 includes an aggressor detector circuit 217 that determines an aggressor address to be stored in the aggressor queue 244. Various schemes may be used to determine whether an address is an aggressor. As described in more detail herein, Figure 2 is shown with respect to an embodiment using a counter memory cell 226. However, in other example embodiments, other schemes for detecting aggressors may be used. In some embodiments, an address may be identified as an aggressor by random sampling. For an accessed address XADD, it may be randomly selected and added to the queue 244. In some embodiments, accesses to different addresses may be tracked. For example, whenever an address is accessed, the address may be added to a register and a count associated with the entry in the register may be changed (e.g., incremented). If the count exceeds a threshold, the address is added to the queue 244.

[0047] In Figure 2 the example embodiment shown, a counter memory cell 226 in the memory array 218 is used to track the access count associated with the word line. The aggressor detector circuit 217 includes a counter circuit 248 that updates the count value XCount of the accessed word line and a comparator circuit 246 that determines whether the address XADD is an aggressor based on the updated count value.

[0048] When accessing a row of the memory array 218, the value of the counter memory cell 226 along the row is read into the counter circuit 246. For example, the counter memory cell 226 may store bits representing a count value. For example, if the number is a 16-bit number, then 16 or more counter memory cells may store the bits of the number. The counter 246 may determine the value of the access count of the row based on the value read from the counter memory cell 226. The counter 246 may be a count control circuit that may manage the count value stored in the counter memory cell 226 (e.g., by reading the raw data in the counter memory cell 226 as a numerical value, writing a new numerical value to the counter memory cell 226, etc.). The counter circuit 246 may change the count value (e.g., by incrementing the count value) and provide the changed count value to the threshold comparator 246, which may determine whether the changed count value exceeds a threshold (e.g., whether the value is greater than or greater than or equal to the threshold). If the value does not exceed the threshold (e.g., if the value is less than or equal to or less than the threshold), then the counter circuit 248 may write the changed count back to the counter memory cell 226. If the value does exceed the threshold, then the current address XADD may be determined as the violator address HitXADD and the threshold comparator circuit 246 provides a violator detected signal Agg to the violator queue 244. In response to the signal Agg, the violator address register 244 stores the row address XADD. Also in response to the signal Agg, the counter circuit 248 may change the count value XCount. In some embodiments, the count value may be reset (e.g., to an initial value) or changed in a direction opposite to the direction in which it changes in response to an access (e.g., if the count for an access increases, then the count value may decrease in response to the signal Agg). In some embodiments, the change in the count value may be inherent. For example, a mitigation threshold MT may be set to the maximum value of the count value XCount, and when XCount reaches the threshold and is incremented again, the count may roll back to the initial value (e.g., 0).

[0049] In some embodiments, the violator detector circuit 217 may be located in a region of the memory device that is closer to the array 218 than the rest of the refresh control circuit 216. For example, the violator detector 217 may be located in the bank logic region associated with the array 218, while the rest of the components may be located in a more central region.

[0050] Figure 3 A block diagram of a controller according to some embodiments of the present disclosure. In some embodiments, the memory 300 may implement Figure 1 the controller 150. The controller operates the memory 340 (e.g., Figure 1100). The controller 300 operates the memory 340 by sending and receiving various signals such as commands, addresses, and / or data along various buses. For clarity, Figure 3 only certain signals are shown, and other signals and their buses have been omitted.

[0051] The controller 300 includes access logic circuitry 302 that controls when to send access commands to the memory 340. The access logic 302 can perform an access operation by providing commands and addresses to the C / A terminals of the memory 340 along the C / A bus. For example, the access logic 302 can provide row, column, and bank addresses (XADD, YADD, and BADD, respectively) and a command (e.g., a read or write command R / W) along the C / A bus.

[0052] The controller 300 also includes an auto - refresh logic circuitry 304 that sends a refresh command REF and a refresh management command RFM to the memory 340. The auto - refresh logic circuitry 304 includes a sequential refresh timing circuit 306 that provides the refresh command REF. The sequential refresh timing circuit 306 can use timing logic to determine the frequency at which the refresh command REF should be sent. For example, there can be a refresh interval, and the sequential refresh timing circuit 306 can typically send the refresh command REF at least once in each refresh interval. The refresh interval can be based on the rate at which information is expected to decay in the memory under 'normal' conditions. In some embodiments, the refresh interval can be adjusted by factors such as the temperature of the memory 340.

[0053] The auto - refresh logic circuitry 304 also includes a targeted refresh logic circuit 310 that tracks accesses to the memory 340 to determine when the RFM command should be sent. The tracking and the RFM command can be provided on a per - bank basis. For example, the targeted refresh logic circuit 310 includes: a counter circuit 312 that stores count values, each of which is associated with a bank of the memory 340; and a comparator circuit 314 that determines whether any of the count values has exceeded a threshold. When a bank is accessed, the counter circuit 312 can change the count value associated with that bank. For example, the count can be incremented. If the comparator determines that the count for one or more banks has exceeded the threshold, then those banks can be marked as due for targeted refresh. When the controller 300 sends an RFM command to one of the marked banks, the counter circuit 312 can change the count value associated with that bank. For example, the count value can be decremented. In some embodiments, the count value can be decremented by the amount of the threshold.

[0054] Figure 4 A timing diagram for the operation of an example of a controller according to some embodiments of the present disclosure. In some embodiments, the timing diagram 400 can represent, for example Figure 1controller 150 and / or Figure 3 operation of the controller of controller 300. The timing diagram represents a simplified set of operations of the controller to show how accesses to different groups can be tracked and, for example, an RFM command is issued by the auto-refresh logic circuit 304 of, for example, Figure 3 Various operations and timings have been simplified in the view of Figure 3 .

[0055] Timing diagram 400 shows accesses to two groups A and B, as well as refresh commands REF issued to the two groups and an RFM command issued to either of the groups. The timing diagram also shows count values (e.g., stored in Figure 3 counter circuit 312 of Figure 3 ), each of the count values being associated with one of the groups. In an example embodiment of

[0056] At an initial time t0, the counter for group A is set to 508 and the counter for group B is set to 23. At a first time t1, just after an access command is issued to group A, the count for group A is 509 and the count for group B remains 23. At time t2, just after the access to group B, the count for group A remains 509 and the count for group B is now 24. At time t2, a refresh command REF is issued to both groups. At time t3, just after the refresh command REF, the counts for the two groups remain unchanged at 509 and 24, respectively. Since the target refresh operation is not performed in response to the refresh command REF, the two count values do not change in response to the REF command.

[0057] After time t3, several additional accesses are performed to group A until its count value reaches the threshold 512. In response thereto, at time t4, an RFM command is issued to group A. In response thereto, the count value of group A decreases. For example, the threshold 512 can be subtracted from the count of group A. In this example, the count is reset to the initial value 0.

[0058] Figure 5 is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 can be implemented by one or more of the systems and devices described herein, such as by a memory (e.g., Figure 1 100 of Figure 2 200 and / or Figure 3 340 of Figure 1 150 and / or Figure 3 300 of

[0059] Method 500 includes block 510, which describes receiving a first type of refresh command. Method 500 may include the controller providing the first type of refresh command to the memory along the C / A bus. The first type of refresh command may be the refresh command REF. Method 500 may include using a sequential refresh timing circuit (e.g., Figure 3 's 306) to generate a refresh signal based on the timing of the refresh interval.

[0060] Following block 510 may be block 520, which describes performing a first type of refresh operation in response to the first type of refresh command. For example, method 500 may include performing a sequential refresh operation using the memory in response to receiving the first type of refresh command. Performing the sequential refresh operation may include using a sequential refresh address generator circuit (e.g., Figure 2 's 252) to generate a refresh address. Generating the refresh address may involve generating a sequential refresh address based on a previous refresh address generated in response to the first type of refresh command.

[0061] Method 500 also includes block 530, which describes receiving a second type of refresh command. Method 500 may include the controller providing the second type of refresh command to the memory along the C / A bus. The second type of refresh command may be the RFM command. Method 500 may include tracking accesses to groups of the memory and providing an RFM command in response to an access exceeding a threshold. For example, the controller may store a plurality of count values, each associated with a group, and method 500 may include changing one of the plurality of count values in response to accessing a group. The method may include providing an RFM command to the group in response to the count exceeding the threshold. Method 500 may include changing the count value in response to providing the RFM command. Method 500 may include not changing the count value in response to providing the REF command.

[0062] Following block 530 may be block 540, which describes performing a second type of refresh operation in response to the second type of refresh command. For example, method 500 may include performing a targeted refresh operation using the memory in response to the second type of refresh command. Performing the targeted refresh operation may include using a targeted refresh address generator circuit (e.g., Figure 2 's 254) to generate a refresh address. Method 500 may include identifying a violator address (e.g., using Figure 2 's violator detector 217) and storing the identified violator in a violator queue (e.g., Figure 2 's 244). Method 500 may include generating a refresh address based on the identified violator address in the queue in response to the second type of refresh command.

[0063] Method 500 may include refreshing one or more word lines of a memory array in response to a refresh address, which is generated in response to a first or second type of refresh command. Method 500 may include putting the memory into self-refresh mode and, while in self-refresh mode, periodically generating a refresh signal within the memory and performing a first type of refresh operation in response to the refresh signal.

[0064] It should be understood that any one of the examples, embodiments, or processes described herein may be combined with, separated from, and / or performed between separate devices or portions of devices of one or more other examples, embodiments, and / or processes in a system, apparatus, and method according to the present invention.

[0065] Finally, the foregoing discussion is intended only to illustrate the systems of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Accordingly, while the systems of the present invention have been described in detail with reference to exemplary embodiments, it should also be understood that many modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the systems of the present invention as set forth in the appended claims. Therefore, the specification and drawings are to be regarded in an illustrative manner and not an intent to limit the scope of the appended claims.

Claims

1. A device comprising: an aggressor address queue configured to store the identified aggressor addresses; a sequential refresh address generator circuit configured to generate a refresh address based on sequence logic in response to a refresh command; A target refresh address generator is configured to generate the refresh address based on the identified aggressor address stored in the aggressor address queue in response to a refresh management command.

2. The apparatus of claim 1, wherein the target refresh address generator does not generate the refresh address in response to the refresh command, and the sequential refresh address generator circuit does not generate the refresh address in response to the refresh management command.

3. The apparatus according to claim 1, further comprising: Memory array; and Line decoder, Wherein the row decoder is configured to refresh one or more word lines of the memory array associated with the refresh address.

4. The apparatus of claim 1, further comprising an aggressor detector circuit configured to identify the aggressor address.

5. The apparatus according to claim 4, further comprising: A memory array includes a plurality of word lines, each of the plurality of word lines configured to store a count value associated with the word line, wherein the aggressor detector circuit is configured to identify the aggressor address based on the count value.

6. The apparatus of claim 1, further comprising a self-refresh logic circuit configured to generate a refresh signal during a self-refresh mode, wherein the sequential refresh address generator circuit is configured to generate the refresh address based on the sequence logic in response to the refresh signal.

7. A system comprising: a controller configured to provide a refresh command or a refresh management command; and A memory is configured to perform a sequential refresh operation instead of a targeted refresh operation in response to the refresh command, and is configured to perform a targeted refresh operation instead of a sequential refresh operation in response to the refresh management command.

8. The system of claim 7, wherein the memory includes a plurality of groups, and wherein in response to the refresh management command, the memory performs the target refresh operation on a selected one of the plurality of groups.

9. The system of claim 7, wherein the controller includes a counter circuit storing a plurality of count values, each of the count values ​​being associated with one of the plurality of groups of the memory, and Wherein one of the plurality of count values ​​is changed in response to providing the refresh management command and not in response to providing the refresh command.

10. The system of claim 9, wherein the counter circuit changes one of the plurality of count values ​​in response to the controller providing an access command.

11. The system of claim 7, wherein the memory includes a refresh address generator having a sequential refresh address generator circuit and a target refresh address generator circuit, wherein in response to the refresh command, the sequential refresh generator circuit provides a refresh address instead of the target refresh address generator circuit, and Wherein in response to the refresh management command, the target refresh address generator circuit provides the refresh address instead of the sequential refresh address generator circuit.

12. The system of claim 7, wherein the memory comprises an aggressor detector circuit configured to identify an aggressor address, wherein the target refresh address generator circuit is configured to generate the refresh address based on the identified aggressor address.

13. The system of claim 7, wherein the controller is configured to cause the memory to enter a self-refresh mode, and wherein the memory is configured to perform a sequential refresh operation during the self-refresh mode.

14. A method comprising: receiving a refresh command of a first type at the memory; performing a first type of refresh operation in response to the first type of refresh command; receiving a refresh command of a second type at the memory; and A second type of refresh operation is performed in response to the second type of refresh command.

15. The method according to claim 14, further comprising: performing the first type of refresh operation instead of the second type of refresh operation in response to the first type of refresh command; and The second type of refresh operation is performed instead of the first type of refresh operation in response to the second type of refresh command.

16. The method of claim 14, wherein the first type of refresh command is a refresh command, and the first type of refresh operation is a sequential refresh operation, and The second type of refresh command is a refresh management command, and the second type of refresh operation is a target refresh operation.

17. The method of claim 14, further comprising: Identifying an aggressor address and storing the aggressor address in an aggressor queue; and A refresh address is generated based on the aggressor address in the aggressor queue in response to the refresh command of the second type.

18. The method of claim 14, further comprising generating the refresh address in response to the first type of refresh command based on a previous refresh address generated in response to the first type of refresh command.

19. The method of claim 14, further comprising: providing access commands to the group of memories; changing a count value in a first direction in response to providing the access command; providing a refresh command of the second type in response to the count value exceeding a threshold; and The count value is changed in a second direction in response to providing the second type of refresh.

20. The method of claim 19, further comprising periodically providing the first type of refresh commands and not changing the count value in response to the first type of refresh commands.

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