Decoding circuit, memory device and control method thereof, and memory system

Abstract

The embodiment of the invention discloses a decoding circuit, a memory device, a control method of the memory device and a memory system, and the decoding circuit comprises a power supply control circuit which comprises a first transistor, a second transistor and a reverse circuit; the input end of the first transistor is connected with a low-level voltage node, and the output end of the first transistor outputs a first ground voltage; the input end of the second transistor is connected with the high-level voltage node, and the output end of the second transistor outputs a first voltage; the input end of the reverse circuit receives a semiconductor element enable signal; the output end of the reverse circuit is connected with the control end of one of the first transistor and the second transistor; the control end of the transistor which is not connected with the reverse circuit receives a semiconductor element enable signal; and the decoding circuit comprises a plurality of sub-circuits, the power supply interfaces of the sub-circuits are connected with the output end of the second transistor, or the grounding interfaces of the sub-circuits are connected with the output end of the first transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a decoding circuit, a memory device, a control method thereof, and a memory system. Background Art

[0002] A memory device is a storage device used to store information in modern information technology. For example, a dynamic random access memory (DRAM) may include a memory cell array and a peripheral circuit. The peripheral circuit can control the memory cell array and operate the memory cell array to perform read, write, or refresh operations.

[0003] However, with the continuous improvement of people's requirements for storage devices, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0004] According to some aspects of embodiments of the present disclosure, a decoding circuit is provided, including: a power supply control circuit, including: a first transistor, a second transistor, and an inverter circuit; wherein, an input end of the first transistor is connected to a low-level voltage node, and an output end of the first transistor outputs a first ground voltage; an input end of the second transistor is connected to a high-level voltage node, and an output end of the second transistor outputs a first voltage; an input end of the inverter circuit receives a semiconductor element enable signal; an output end of the inverter circuit is connected to a control end of one of the first transistor or the second transistor; a control end of the transistor not connected to the inverter circuit receives the semiconductor element enable signal; a decoding circuit, including a plurality of sub-circuits, a power supply interface of the sub-circuit is connected to an output end of the second transistor, or a ground interface of the sub-circuit is connected to an output end of the first transistor.

[0005] In some embodiments, the plurality of sub-circuits include a first sub-circuit and / or a second sub-circuit; wherein, an output interface of the first sub-circuit outputs a low-level voltage, a power supply interface of the sub-circuit is connected to an output end of the second transistor, and a ground interface is connected to the low-level voltage node; an output interface of the second sub-circuit outputs a high-level voltage, a ground interface of the sub-circuit is connected to an output end of the first transistor, and a power supply interface is connected to the high-level voltage node.

[0006] In some embodiments, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0007] In some embodiments, a control terminal of the second transistor is connected to an output terminal of the reverse circuit, and a control terminal of the first transistor receives the semiconductor element enable signal; the semiconductor element enable signal indicates a high-level voltage when the semiconductor element is in an enabled state.

[0008] In some embodiments, a control terminal of the first transistor is connected to an output terminal of the reverse circuit, and a control terminal of the second transistor receives the semiconductor element enable signal; the semiconductor element enable signal indicates a low-level voltage when the semiconductor element is in an enabled state.

[0009] According to some aspects of embodiments of the present disclosure, a memory device is provided, including: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes memory blocks, the memory blocks have multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit includes a column decoding circuit corresponding to the memory blocks, the column decoding circuit is coupled to the multiple columns of bit lines in the corresponding memory blocks, and is configured to receive a column address signal, perform decoding processing on the column address signal, and output a column selection signal, the column selection signal indicating to activate the corresponding bit lines in the memory blocks in an enabled state; wherein during the decoding process, for the memory blocks in an enabled state, power supply interfaces and ground interfaces of each sub-circuit in the column decoding circuit are both normally powered; for the memory blocks in a non-enabled state, one of the power supply interfaces or the ground interfaces of each sub-circuit in the column decoding circuit floats according to a preset rule.

[0010] In some embodiments, the column decoding circuit includes: a power supply control circuit, including: an input interface, a first output interface, and a second output interface, the input interface receives a memory block enable signal, the first output interface outputs a first voltage, and the second output interface outputs a first ground voltage; when the memory block enable signal indicates that the memory block is in an enabled state, the first output interface is connected to a high-level voltage node, and the second output interface is connected to a low-level voltage node; when the memory block enable signal indicates that the memory block is in a non-enabled state, both the first voltage and the first ground voltage float; and a decoding circuit, including multiple sub-circuits, each sub-circuit includes: a power supply interface, a ground interface, and an output interface, the power supply interface of the sub-circuit receives the first voltage or the ground interface receives the first ground voltage, and the output interface of the sub-circuit outputs a corresponding fixed-level voltage when the memory block enable signal indicates that the memory block is in a non-enabled state.

[0011] In some embodiments, the power supply control circuit includes: a first transistor, a second transistor, and an inverter circuit; wherein, an input end of the first transistor is connected to a low-level voltage node, and an output end of the first transistor outputs a first ground voltage; an input end of the second transistor is connected to the high-level voltage node, and an output end of the second transistor outputs the first voltage; an input end of the inverter circuit receives the storage block enable signal, and an output end of the inverter circuit is connected to a control end of one of the first transistor or the second transistor; a control end of the transistor not connected to the inverter circuit receives the storage block enable signal.

[0012] In some embodiments, the plurality of sub-circuits includes a first sub-circuit and / or a second sub-circuit; wherein, an output interface of the first sub-circuit outputs a low-level voltage, a power supply interface of the sub-circuit is connected to an output end of the second transistor, and a ground interface is connected to the low-level voltage node; an output interface of the second sub-circuit outputs a high-level voltage, a ground interface of the sub-circuit is connected to an output end of the first transistor, and a power supply interface is connected to the high-level voltage node.

[0013] In some embodiments, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0014] In some embodiments, a control end of the second transistor is connected to an output end of the inverter circuit, and a control end of the first transistor receives the storage block enable signal; the storage block enable signal indicates a high-level voltage when the storage block is in an enabled state.

[0015] In some embodiments, a control end of the first transistor is connected to an output end of the inverter circuit, and a control end of the second transistor receives the storage block enable signal; the storage block enable signal indicates a low-level voltage when the storage block is in an enabled state.

[0016] In some embodiments, the decoding circuit includes a control signal generation circuit and an address enable generation circuit; wherein, the control signal generation circuit is coupled to the power supply control circuit and is configured to at least generate a local data line read control signal and a local data line write control signal; the address enable generation circuit is coupled to the power supply control circuit and is configured to receive a column address signal and a storage block enable signal, and generate a column selection signal corresponding to each bit line by using the column address signal and the storage block enable signal.

[0017] In some embodiments, the peripheral circuit further includes: a sense amplifier circuit and a local data line control circuit; wherein, the local data line control circuit is coupled to the column decoding circuit and is coupled to the sense amplifier circuit through a local data line, and is configured to receive the local data line read control signal and the local data line write control signal, and control the data interaction direction between the local data line and the global data line by using the local data line read control signal and the local data line write control signal; the sense amplifier circuit is coupled to the column decoding circuit and the bit lines in the memory cell array; the column decoding circuit is further configured to control the data interaction between the local data line and the bit line by using the column selection signal; the sense amplifier circuit is configured to detect and amplify the voltage difference on the bit line.

[0018] In some embodiments, the memory cell array is disposed on a first semiconductor structure, and the peripheral circuit is disposed on a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by bonding; each of the decoding circuits, the sense amplifier circuit, the local data line control circuit, and the word line driving circuit corresponding to each memory block are located at a position corresponding to the orthographic projection of a corresponding memory block on the plane where the second semiconductor structure is located.

[0019] In some embodiments, the memory cell array includes a plurality of memory banks, and each memory bank includes a plurality of row memory blocks and a plurality of column memory blocks; the column decoding circuit further includes a primary decoding circuit, which is configured to receive a primary column address signal, perform decoding processing, and output the column address signal; the number of transmission lines corresponding to the primary column address signal is less than the number of transmission lines corresponding to the column address signal; each memory bank corresponds to a plurality of the primary decoding circuits, a plurality of the power supply control circuits, and a plurality of decoding circuits, each primary decoding circuit corresponds to a column of memory blocks, and each power supply control circuit and decoding circuit corresponds to one memory block in a column of memory blocks.

[0020] In some embodiments, the memory device includes a dynamic random access memory.

[0021] According to some aspects of the embodiments of the present disclosure, a memory system is provided, including: one or more of the above-mentioned memory devices; and a memory controller, which is coupled to the memory device and controls the memory device.

[0022] According to some aspects of the embodiments of the present disclosure, a control method for a memory device is provided, including: in response to a storage block being in an enabled state, inputting a first voltage and a first ground voltage to a column decoding circuit corresponding to the storage block to perform decoding processing on a column address signal and output a column selection signal; the column selection signal indicating activation of corresponding bit lines in the storage block in the enabled state; in response to the storage block being in a disabled state, floating one of the interfaces in the column decoding circuit corresponding to the storage block that receives the first voltage or the ground voltage according to a preset rule.

[0023] In some embodiments, the control method includes: inputting an enabling signal of the storage block to a power supply control circuit, and in response to the storage block being in an enabled state, causing the power supply control circuit to output a first voltage and a first ground voltage to a decoding circuit, causing the decoding circuit to output corresponding fixed-level voltages; in response to the storage block being in a disabled state, floating the first voltage and the first ground voltage, causing the decoding circuit to output the corresponding fixed-level voltages.

[0024] In the embodiments of the present disclosure, when a semiconductor element is in an enabled state, the enabling signal of the semiconductor element turns on both a first transistor and a second transistor. The output end of the first transistor outputs a first ground voltage to a ground interface of the decoding circuit, and the output end of the second transistor outputs a first voltage to a power supply interface of the decoding circuit to realize normal power supply for the decoding circuit. When the semiconductor element is in a disabled state, both the first transistor and the second transistor are turned off, and the output ends of the first transistor and the second transistor are both floating, without voltage output. One of the power supply interface and the ground interface of each sub-circuit in the decoding circuit is connected to the corresponding output end of the first transistor and the second transistor, and this interface is floating. The remaining interfaces of each sub-circuit in the plurality of sub-circuits are normally powered. Thus, for a semiconductor element in a disabled state, its output is the fixed-level voltage corresponding to normal power supply of the remaining interfaces, and no current is formed between its power supply interface and the ground interface. Thus, on the premise of ensuring that semiconductor elements in various states can work normally, the leakage and power consumption of the power supply interface and the ground interface of the semiconductor element in the disabled state are reduced. Description of the Drawings

[0025] Figure 1 is a schematic diagram of a memory cell array shown according to an embodiment of the present disclosure;

[0026] Figure 2 is a layout schematic diagram of a memory cell array shown according to an embodiment of the present disclosure;

[0027] Figure 3a and Figure 3b is a schematic diagram of a power supply control circuit shown according to an embodiment of the present disclosure;

[0028] Figures 4a to 4f is a schematic diagram of a partial sub-circuit of a decoding circuit shown according to an embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram of the connection relationship of a partial component circuit of a peripheral circuit shown according to an embodiment of the present disclosure;

[0030] Figure 6 is a schematic diagram of the connection relationship of a partial component circuit of a partial peripheral circuit corresponding to a storage block shown according to an embodiment of the present disclosure;

[0031] Figures 7a to 7c is a schematic diagram of a sense amplifier control circuit shown according to an embodiment of the present disclosure;

[0032] Figure 8 is a schematic diagram of the coupling of a sense amplifier circuit and a bit line shown according to an embodiment of the present disclosure;

[0033] Figure 9 is a schematic diagram of the bonding of a memory cell array and a peripheral circuit shown according to an embodiment of the present disclosure Figure 1 ;

[0034] Figure 10 is a schematic diagram of the bonding of a memory cell array and a peripheral circuit shown according to an embodiment of the present disclosure Figure 1 ;

[0035] Figure 11 is a schematic layout diagram of a partial peripheral circuit and a storage block shown according to an embodiment of the present disclosure;

[0036] Figure 12 is a top-down schematic diagram of the distribution of storage blocks, a preliminary column decoding circuit, and a column decoding circuit in a memory bank shown according to an embodiment of the present disclosure;

[0037] Figure 13 is a schematic diagram of a system including a memory device shown according to an embodiment of the present disclosure Figure 1 ;

[0038] Figure 14 is a schematic diagram of a system including a memory device shown according to an embodiment of the present disclosure Figure 2 ;

[0039] Figure 15 is a schematic diagram of a control method of a memory device shown according to an embodiment of the present disclosure;

[0040] Figure 16 is a schematic diagram of a control method of a decoding circuit in a memory device shown according to an embodiment of the present disclosure.

[0041] In the above figures (which are not necessarily drawn to scale), like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The figures generally illustrate various embodiments discussed herein by way of example and not limitation. Detailed Description

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying figures. Although the exemplary embodiments of the present disclosure are shown in the figures, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described, and well-known functions and structures are not described in detail.

[0044] In the figures, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the figures denote like elements.

[0045] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be denoted as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0046] Spatial relation terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and not to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0048] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not used to limit the embodiments of the present disclosure.

[0049] It should be understood that the "some embodiments" or "an embodiment" mentioned throughout the specification means that a particular feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in some embodiments" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the order numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0050] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0051] The memory device in the embodiments of the present disclosure may be a DRAM, or at least a part of the devices in the DRAM, and is applicable to double data rate synchronous dynamic random access memories adopting DDR4 memory specifications and DDR5 memory specifications, and low-power double data rate synchronous dynamic random access memories adopting LPDDR5 memory specifications. It should be noted that the embodiments of the present disclosure are not limited to DRAMs, but in the following descriptions, for the sake of clarity, only DRAMs are taken as examples for illustration. The decoding circuit may be a part of the peripheral circuit of the memory device.

[0052] Figure 1 is a circuit schematic diagram of a memory cell array shown according to an exemplary embodiment of the present disclosure. As Figure 1 shown, in a DRAM, the memory cell array may be arranged in rows and columns, so that the memory cells can be addressed by specifying the rows and columns of its array. The memory cell array includes multiple word lines, such as Figure 1 the WLn, WLn+1, WLn-1, and WLn-2 shown in; the memory cell array also includes multiple bit lines, such as Figure 1 the BLn, BLn+1, BLn-1, and BLn-2 shown in. The word lines and bit lines cross, and the memory cell at the intersection of the selected word line and the selected bit line is selected, and read, write, or refresh operations are performed. Figure 1 As shown in, a memory cell may include a capacitor and a transistor. A memory cell may include a transistor and a capacitor. The gate of the transistor is coupled to the word line, one controlled end (source) of the transistor is coupled to one electrode (the first electrode) of the capacitor, the other controlled end (drain) of the transistor is coupled to the bit line, and the other electrode (the second electrode) of the capacitor may be grounded or applied with other voltages (such as vdd / 2). Figure 1 As shown, the memory cell array is arranged in an x-row and y-column manner. The rows and columns may be perpendicular or not perpendicular. The x direction may be the second direction mentioned in the embodiments of the present disclosure, and the y direction may be the first direction mentioned in the embodiments of the present disclosure. The extending direction of the word line may be parallel to the x direction or have an angle with the x direction. The extending direction of the bit line may be parallel to the y direction or have an angle with the y direction. The positive projection of the word line on the xoy plane is perpendicular to the positive projection of the bit line on the xoy plane, or not perpendicular and has a certain angle. The embodiments of the present disclosure do not limit this. When performing read or write operations, the corresponding word line may be selected by using the word line selection signal, and the corresponding bit line may be selected according to the column selection signal. The simultaneous selection of the word line and the bit line can locate the selected memory cell for reading and writing operations. In some embodiments, Figure 1 the capacitor in may be replaced with other memory structures, including but not limited to: phase change memory structures, resistive change memory structures, or magnetic change memory structures, etc.

[0053] In some embodiments, a capacitor represents logically 1 and 0 by the amount of charge stored therein, or equivalently, by the high and low voltage differences across the capacitor. A voltage signal on the word line is applied to the gate to control the conduction or cutoff of the transistor, thereby selecting or deselecting the capacitor. Subsequently, data information stored in the capacitor is read through the bit line, or data is written into the capacitor through the bit line for storage. When reading a memory cell, the voltage fluctuations generated on the bit line due to the charging and discharging of the capacitor are relatively weak, and the time of the voltage fluctuations generated by the charging and discharging of the capacitor is also very short. Therefore, a sense amplifier circuit (SA) is provided in the peripheral circuit and coupled to the bit line. The sense amplifier circuit is used to capture the weak voltage fluctuations on the bit line and restore the capacitor voltage of the memory cell locally according to the situation of the voltage fluctuations. The sense amplifier circuit may include a latch, which can latch the restored capacitor voltage value, so that the information stored in the memory cell is transferred from the capacitor to the amplifier circuit. The peripheral circuit may further include other devices such as control logic, word line drivers, and voltage generators. The sense amplifier circuit may include a differential sense amplifier circuit, which is coupled to two bit lines and operates using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines.

[0054] In some embodiments, as Figure 2 shown, according to the layout design of the memory device, the memory cell array can be divided into banks 201 and blocks 204. Among them, the block 204 includes a plurality of Figure 1 memory cells arranged along the x and y directions as shown. The bank 201 includes a plurality of Figure 2 arrays of blocks 204 arranged along the x and y directions as shown. A semiconductor device (or called a die) may include a plurality of Figure 2 banks 201 arranged along the x and y directions as shown. A memory device may include at least one die. A memory system may include a memory controller and at least one memory device coupled to the memory controller. The memory controller is configured to control the memory device to perform read, write, and other operations.

[0055] Continuing as Figure 2 shown, the peripheral circuit may include a control circuit for controlling multiple levels of memory cell arrays, which may include a control circuit corresponding to the bank level and a control circuit corresponding to the block level. Each control circuit at the block level is connected to the control circuit at the bank level through an interconnection line (local interconnection line). Each control circuit at the bank level is connected to other common areas of the peripheral circuit, such as logic control, through an interconnection line (primary bus). The logic control is used to receive instructions from the host or the memory controller and perform read, write, or refresh operations on the memory cell array.

[0056] In some embodiments, the peripheral circuit may include a repository control circuit. The repository control circuit includes a repository row control circuit (Bank ROW CTL) 203 between two adjacent repositories in the x direction (row direction), and may include a repository row decoder, which may be configured to address the row where the repository 201 is located and apply an operating voltage to the word line. The repository control circuit further includes a repository column control circuit (Bank COLCTL) 202 between two adjacent repositories 201 in the y direction (column direction), such as a repository column decoder, which may be configured to address the column where the repository 201 is located, and may be configured to be coupled to the bit line, apply a bit line voltage, or receive a bit line voltage. In some other embodiments, as Figure 2 shown, the peripheral circuit further includes control logic, located in the gap area (Peri) between the repositories 201, for data interaction between the repositories 201 and also for data interaction with the host.

[0057] In some embodiments, in the x direction, a word line driver is provided between two adjacent memory blocks 204 to apply a voltage to a selected word line; in the y direction (column direction), a sense amplifier circuit, such as the sense amplifier circuit 206 shown hereinafter Figure 5 is provided between two adjacent memory blocks 204. The peripheral circuit includes a plurality of sense amplifier circuits 206. Each sense amplifier circuit 206 is coupled to two adjacent bit lines in the y direction. The sense amplifier circuits 206 may be coupled and interconnected through a connection circuit, and the plurality of sense amplifier circuits 206 may be interconnected through a connection circuit. The sense amplifier circuit 206 is coupled to two bit lines and operates using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines.

[0058] In some embodiments, in Figure 5 a part of the peripheral circuit, a column decoding circuit 210 is coupled to the multiple columns of bit lines in the corresponding memory block 204, and is configured to receive a column address signal, decode the column address signal, and output a column selection signal. The column selection signal indicates to activate the corresponding bit line in the memory block 204 in the enabled state. The column decoding circuit 210 may include a decoding circuit 212, which is configured to generate at least a read control signal for controlling the bit line and a write control signal for controlling the bit line.

[0059] In some embodiments, the column decoding circuit 210 can access the operating voltage vdd from a power supply device such as a voltage generator, as well as the common ground voltage vss of the circuit. Vdd is a high logic level voltage, and vss is a low logic level voltage. When one or more memory blocks 204 are selected, the state of the selected memory block 204 can be defined as the enabled state, and its corresponding column decoding circuit 210 can be defined as the enabled state. A high-level voltage and a low-level voltage are supplied to the column decoding circuit 210 corresponding to the selected memory block 204, enabling the column decoding circuit 210 to complete its decoding and other operations to perform read, write, or refresh operations on the selected memory block 204. When the memory block 204 is not selected, the state of the unselected memory block 204 can be defined as the disabled state, and its corresponding column decoding circuit 210 can be defined as the disabled state. The column decoding circuit 210 corresponding to the memory block 204 in the disabled state is also continuously powered, so that when each sub-circuit of the column decoding circuit 210 is not performing relevant operations such as read, write, or refresh, the signal output of each circuit is the same as when selected, to reduce the loss of data due to the power-down of the capacitance storing data in the memory block 204, and to enable the column decoding circuit 210 to respond quickly when the memory block 204 transitions from the disabled state to the enabled state.

[0060] In the actual use process of some column decoding circuits 210, when continuously powering the column selection circuit in the disabled state, some input and output signals of the column selection circuit in the disabled state will leak, causing interference to the column decoding circuit 210 in the enabled state, affecting the circuit stability, and increasing the power consumption. The output signals of the column decoding circuit 210 include but are not limited to control signals (or feedback signals) for bit lines and the sense amplifier circuit 206, and control signals (or feedback signals) for the local data line control circuit 207 coupled to the sense amplifier circuit 206. The input signals of the column decoding circuit 210 include but are not limited to: the enable signal of the memory block 204, and high and low level signals (voltages) provided by the voltage generator to the input terminals of devices such as transistors of the column decoding circuit 210.

[0061] In view of this, embodiments of the present disclosure provide a decoding circuit. The decoding circuit can be configured as at least a part of the above column decoding circuit 210. A power supply control circuit 211 is provided in the decoding circuit. When the semiconductor element is in the disabled state, some input terminals of the part of the power supply control circuit 211 that provides voltage input are floated, and no power supply is provided. At the same time, the output signals of the column selection circuit in the disabled state are made the same as the output signals of the column selection circuit in the enabled state, reducing interference and power consumption while reducing data loss and maintaining the high-speed response of the column decoding circuit 210.

[0062] According to some aspects of embodiments of the present disclosure, a decoding circuit is provided. The decoding circuit includes: a power supply control circuit 211, including: Figure 3aThe first transistor 2111, the second transistor 2112, and the inverter circuit shown; wherein, the input end of the first transistor 2111 is connected to the low-level voltage node, and the output end of the first transistor 2111 outputs the first ground voltage; the input end of the second transistor 2112 is connected to the high-level voltage node, and the output end of the second transistor 2112 outputs the first voltage; the input end of the inverter circuit receives the semiconductor device enable signal; the output end of the inverter circuit is connected to the control end of one of the first transistor 2111 or the second transistor 2112; the control end of the transistor not connected to the inverter circuit receives the semiconductor device enable signal; the decoding circuit 212 includes a plurality of sub-circuits, the power supply interface of the sub-circuit is connected to the output end of the second transistor 2112, or the ground interface of the sub-circuit is connected to the output end of the first transistor 2111.

[0063] In some embodiments, the first transistor 2111 is an N-type transistor, and the second transistor 2112 is a P-type transistor. Each transistor includes an output end, an input end, and a control end. The output end and the input end can be the source or drain of the transistor, or two active regions of the transistor. The source and drain can be interchanged, and the embodiments of the present disclosure do not limit the positions of the source and the drain. The control end is the gate of the transistor. By applying different operating voltages to the gate, the conduction of the transistor channel is achieved, so that the voltage at the input end of the transistor is transmitted to the output end, and the voltage at the output end may have a certain voltage drop compared with the input end, and this voltage drop is within the designed voltage drop of the device or integrated circuit.

[0064] The first transistor 2111 can be an N-type transistor. Applying a high-level voltage to its control end turns on the first transistor 2111, and the voltage at the input end is transmitted to the output end; applying a low-level voltage to its control end turns off the first transistor 2111, and the output end is in a floating state. The input end of the first transistor 2111 can input a low-level voltage, which can be the ground voltage vss, and the output end outputs a low-level voltage to the ground interface of the decoding circuit 212. For example, when the first transistor 2111 is turned on, the output end can output the first ground voltage vn. The first ground voltage vn is connected to the low-level voltage node and outputs a low-level voltage, which can provide a low-level voltage for the ground interface in the decoding circuit 212; when the first transistor 2111 is not turned on, the output end is floating, the output voltage is in an uncertain state or there is no voltage output, and the ground interface in the decoding circuit 212 is also floating.

[0065] The second transistor 2112 can be a P-type transistor. Applying a low-level voltage to its control terminal turns on the second transistor 2112, and the voltage at the input terminal is transmitted to the output terminal. Applying a high-level voltage to its control terminal turns off the second transistor 2112, and the output terminal is in a floating state. A high-level voltage can be input to the input terminal of the second transistor 2112, which can be vdd2h, and the first voltage is output at the output terminal. For example, when the second transistor 2112 is turned on, the first voltage output at the output terminal is connected to the high-level voltage node, and the high-level voltage vp is output, which can provide a high-level voltage for the power supply interface in the decoding circuit 212. When the second transistor 2112 is not turned on, the output terminal is floating, and the output voltage is in an uncertain state or no voltage is output, and the grounding interface in the decoding circuit 212 is also floating. The voltage magnitude of the first voltage vp compared to vdd2h may have a certain voltage drop. The magnitude of the first voltage vp compared to the first ground voltage vn has a logic level belonging to the high-level voltage.

[0066] The node or interconnection line providing a low-level voltage in the power supply network of the circuit is coupled to the input terminal of the first transistor 2111, and a low-level voltage is input to the input terminal of the first transistor 2111. The node or interconnection line providing a high-level voltage in the power supply network of the circuit is coupled to the input terminal of the second transistor 2112, and a high-level voltage is input to the input terminal of the second transistor 2112. The low-level voltage and the high-level voltage can be provided by devices such as a voltage generator.

[0067] The semiconductor element may include Figure 1 the storage cell array shown, or include a repository 201 or a storage block 204 in the storage cell array. The enable signal of the semiconductor element can be generated by a device that directly or indirectly controls the semiconductor element, and this enable signal indicates that the semiconductor element is in an enabled state. For example, the semiconductor element may include a storage block 204, and the enable signal of the storage block 204 can be generated by a peripheral circuit, a memory controller, or a host that controls the operation of the storage block 204. This enable signal indicates that the storage block 204 is in an enabled state, and the enable signal can be a high-level voltage or a low-level voltage. The reverse circuit may include an inverter. When a high-level voltage is input to the input terminal of the reverse circuit, a low-level voltage is output at its output terminal. When a low-level voltage is output at the input terminal of the reverse circuit, a high-level voltage is output at its output terminal. One of the control terminals of the first transistor 2111 and the control terminal of the second transistor 2112 is connected to the reverse circuit, and the other control terminal is not connected to the reverse circuit and directly receives the enable signal.

[0068] In some embodiments, such as Figure 3aAs shown, the control terminal of the second transistor 2112 is connected to the output terminal of the reverse circuit, and the control terminal of the first transistor 2111 receives the semiconductor device enable signal; the semiconductor device enable signal indicates a high-level voltage when the semiconductor device is in the enabled state.

[0069] The input terminal of the reverse circuit receives the high-level enable signal Blk_en, outputs a low-level voltage to the control terminal of the second transistor 2112 to turn on the second transistor 2112, and the output terminal of the second transistor 2112 outputs a high-level first voltage vp to the power supply interface of the decoding circuit 212. The control terminal of the first transistor 2111 is not coupled to the reverse circuit. The control terminal of the first transistor 2111 receives the high-level enable signal Blk_en, and the first transistor 2111 is turned on. Its output terminal outputs a first ground voltage vn to the ground interface of the decoding circuit 212. In Figure 3a if the high-level enable signal Blk_en is not applied, or a low-level signal is applied, that is, the semiconductor device is in the disabled state, the first transistor and the second transistor 2112 are not turned on, the output terminals of both transistors are floating, no voltage is output, and the ground interface and the power supply interface of the decoding circuit 212 are both floating, with no voltage input.

[0070] In some embodiments, as Figure 3b shown, the control terminal of the first transistor 2111 is connected to the output terminal of the reverse circuit, and the control terminal of the second transistor 2112 receives the semiconductor device enable signal; the semiconductor device enable signal indicates a low-level voltage when the semiconductor device is in the enabled state.

[0071] The output terminal of the reverse circuit receives the low-level enable signal Blk_en, outputs a high-level voltage to the control terminal of the first transistor 2111 to turn on the first transistor 2111, and the output terminal of the first transistor 2111 outputs a low-level first ground voltage vn to the ground interface of the decoding circuit 212. The control terminal of the second transistor 2112 is not coupled to the reverse circuit. The control terminal of the second transistor 2112 receives the low-level enable signal Blk_en, and the second transistor 2112 is turned on. Its output terminal outputs a high-level first voltage vp to the power supply interface of the decoding circuit 212. Figure 3b if the low-level enable signal Blk_en is not applied, or a high-level signal is applied, that is, the semiconductor device is in the disabled state, the first transistor 2111 and the second transistor 2112 are not turned on, the output terminals of both transistors are floating, no voltage is output, and the ground interface and the power supply interface of the decoding circuit 212 are both floating, with no voltage input.

[0072] In an embodiment of the present disclosure, when the semiconductor element is in an enabled state, the enable signal of the semiconductor element turns on both the first transistor 2111 and the second transistor 2112. The output terminal of the first transistor 2111 outputs a first ground voltage to the ground interface of the decoding circuit 212, and the output terminal of the second transistor 2112 outputs a first voltage to the power supply interface of the decoding circuit 212 to enable the decoding circuit 212 to supply power to the device normally. When the semiconductor element is in a disabled state, both the first transistor 2111 and the second transistor 2112 are turned off, and the output terminals of the first transistor 2111 and the second transistor 2112 are both floating, without voltage output. One of the power supply interface and the ground interface of each sub-circuit in the plurality of sub-circuits of the decoding circuit is connected to the corresponding output terminal of the first transistor 2111 and the second transistor 2112, and this interface is floating. The remaining interfaces of each sub-circuit in the plurality of sub-circuits are supplied with power normally. Thus, for the semiconductor element in the disabled state, its output is a fixed-level voltage corresponding to the normal power supply of the remaining interfaces, and no current is formed between its power supply interface and the ground interface. Thus, on the premise of ensuring that semiconductor elements in various states can work normally, the leakage and power consumption of the power supply interface and the ground interface of the semiconductor element in the disabled state are reduced.

[0073] In some embodiments, the plurality of sub-circuits include a first sub-circuit and / or a second sub-circuit; wherein, the output interface of the first sub-circuit outputs a low-level voltage, the power supply interface of the sub-circuit is connected to the output terminal of the second transistor 2112, and the ground interface is connected to the low-level voltage node; the output interface of the second sub-circuit outputs a high-level voltage, the ground interface of the sub-circuit is connected to the output terminal of the first transistor 2111, and the power supply interface is connected to the high-level voltage node.

[0074] Figures 4a to 4e The schematic diagram of some sub-circuits of the decoding circuit 212 is shown. It should be noted that the sub-circuits shown in the figure can be an example of a part of the decoding circuit 212. Any circuit in the figure can be arbitrarily selected and coupled to form a decoding circuit 212 with different device functions. The interfaces or terminals that can input or output the same voltage shown in the figure can be coupled to each other to form different decoding circuits 212.

[0075] Such as Figure 4aAs shown, a sub-circuit of the decoding circuit 212 includes a coupled first sub-circuit 2121 and second sub-circuit 2122. The second sub-circuit 2122 may include an inverter circuit composed of two transistors. The input interface (or input terminal) of the second sub-circuit 2122 receives a pulse voltage signal ypulse. Its power supply interface is connected to the high-level voltage node, and its ground interface may be connected to the output terminal of the first transistor 2111. The second sub-circuit 2122 outputs a high-level voltage to the input terminal of the first sub-circuit 2121. The first sub-circuit 2121 may include an inverter circuit. The power supply interface of the first sub-circuit 2121 is connected to the output terminal of the second transistor 2112, and the ground interface is connected to a low-level voltage node, such as the ground node. The first sub-circuit 2121 outputs a first timing control signal lypulse of low-level voltage. When the semiconductor element is in the enabled state, both the first transistor 2111 and the second transistor 2112 are turned on, and all ports of the second sub-circuit 2122 and the first sub-circuit 2121 are normally powered. When the semiconductor element is in the disabled state, both the first transistor 2111 and the second transistor 2112 are turned off, the ground interface of the second sub-circuit 2122 and the power supply interface of the first sub-circuit 2121 are floating and have no voltage supply, and the power supply port of the second sub-circuit 2122 and the ground port of the first sub-circuit 2121 are normally powered.

[0076] It can be understood that in the second sub-circuit 2122, when the pulse voltage signal ypulse is at a low level voltage, the P-type transistor will conduct, while the N-type transistor will not conduct. The power supply input terminal of the P-type transistor is connected to the high-level voltage node vdd2h, and the output terminal of the N-type transistor is floating or normally powered. The output interface of the second sub-circuit 2122 will output a high-level voltage. That is to say, at this time, whether the first transistor 2111 conducts or not, the output voltage of the output interface of the second sub-circuit 2122 can remain unchanged, or the logic level remains unchanged. The input interface of the first sub-circuit 2121 is coupled to the output interface of the second sub-circuit 2122. As long as the ground interface is normally powered, whether the power supply interface of the first sub-circuit 2121 is floating or normally powered, the output interface of the first sub-circuit 2121 will output a first timing control signal lypulse of low-level voltage. Whether the second transistor 2112 conducts or not, the output voltage of the output interface of the first sub-circuit 2121 can remain unchanged, or the logic level remains unchanged.

[0077] It should be noted that the second sub-circuit 2122 and the first sub-circuit 2121 may include circuits having multiple input terminals (at least including a power supply interface and a ground interface) and an output interface. The input terminals of the circuit input at least one high-level voltage and one low-level voltage, including but not limited to: various gate circuits; including but not limited to: one or more of an AND gate, an OR gate, a NOT gate (inverter), a NAND gate, and a NOR gate.

[0078] In some embodiments, such as Figure 4b , a circuit example is shown in which a sub - circuit of a decoding circuit 212 is composed of a plurality of second sub - circuits 2122 and a plurality of first sub - circuits 2121. The second sub - circuit 2122 may include a NOT gate (inverter), and the first sub - circuit 2121 may include a NOT gate or may include a NOR gate. Figure 4b In, the signal flow is from left to right. The input port of the first second sub - circuit 2122a receives a first timing control signal lypulse with a low - level voltage. The power supply interface is connected to a high - level voltage node, and the ground interface is connected to the output terminal of the first transistor 2111. The output terminal of the first transistor 2111 normally outputs a low - level voltage or floats. The output interfaces of the first second sub - circuit 2122a all output a high - level voltage to the first first sub - circuit 2121a. The power supply interface of the first sub - circuit 2121a is connected to the output terminal of the second transistor 2112. The output terminal of the second transistor 2112 normally outputs a high - level voltage or floats. The output interfaces of the first first sub - circuit 2121a all output a second timing control signal lypulse_eq with a low - level voltage. The second timing control signal lypulse_eq with a low - level voltage passes through two NOT gates (the second second sub - circuit 2122b and the second first sub - circuit 2121b) in sequence and then outputs a third timing control signal lypulse_d with a low - level voltage. The third timing control signal lypulse_d with a low - level voltage and the second timing control signal lypulse_eq with a low - level voltage are input into a NOR gate (the third first sub - circuit 2121c). The ground interface of the NOR gate is connected to the ground node, and the power supply interface of the NOR gate is connected to the output terminal of the second transistor 2112. The output terminal of the second transistor 2112 normally outputs a high - level voltage or floats. The output ports of the NOR gate all output a first local control signal ldl_eq with a low - level voltage. The first timing control signal lypulse with a low - level voltage can be Figure 4a generated and input by the circuit in Figure 4a and Figure 4b the circuit shown.

[0079] In some embodiments, such as Figure 4cAs shown, the second sub-circuit 2122 may include a NOT gate (inverter), the first sub-circuit 2121 may include a NOR gate, and the output interface of the second sub-circuit 2122 is connected to an input interface of the first sub-circuit 2121. The second sub-circuit 2122 inputs a second local control signal ldl_rden with a low-level voltage, the power supply interface is connected to a high-level voltage node, the ground interface is connected to the output terminal of the first transistor 2111, and when the output terminal of the first transistor 2111 outputs a low-level voltage or floats, the output interface of the second sub-circuit 2122 outputs a high-level voltage to the first input interface of the first sub-circuit 2121. The second input port of the first sub-circuit 2121 receives a first local control signal ldl_eq with a low-level voltage input, the ground interface of the first sub-circuit 2121 is connected to a ground node, the power supply interface of the first sub-circuit 2121 is connected to the output terminal of the second transistor 2112, and the output terminal of the second transistor 2112 normally outputs a high-level voltage or floats, and the output interface outputs a third local control signal ldl_rd with a low-level voltage. The first local control signal ldl_eq with a low-level voltage may be generated and input by Figure 4b the circuit in Figure 4b and Figure 4c the circuit shown.

[0080] In some embodiments, as Figure 4d shown, the sub-circuit of the decoding circuit 212 may include a first sub-circuit 2121, and the first sub-circuit 2121 may include a NOR gate. The input terminal of the first sub-circuit 2121 receives a first local control signal ldl_eq with a low-level voltage and a second local control signal ldl_rden with a low-level voltage. The ground interface of the first sub-circuit 2121 is connected to a ground node, the power supply interface is connected to the output terminal of the second transistor 2112, and the output terminal of the second transistor 2112 normally outputs a high-level voltage or floats, and the output terminal outputs a fourth local control signal ldl_wr with a low-level voltage. The low-level voltage ldl_eq may be generated and input by Figure 4b the circuit in Figure 4b and Figure 4d the circuit shown.

[0081] In some embodiments, as Figure 4eAs shown, the sub - circuit of the decoding circuit 212 may include a second sub - circuit 2122. The second sub - circuit 2122 may include NAND gates. The input terminals of the second sub - circuit 2122 receive the third timing control signal lypulse_d with a low - level voltage and the second local control signal ldl_rden with a low - level voltage. The power supply interface is connected to the high - level voltage node, and the ground interface is connected to the output terminal of the first transistor 2111. The output terminal of the first transistor 2111 normally outputs a low - level voltage or floats. The output interfaces of the second sub - circuit 2122 all output high - level voltages.

[0082] In some embodiments, as Figure 4f shown, the decoding circuit 212 may include a more complex circuit composition. The first sub - circuit 2121 and the second sub - circuit 2122 may have more input terminals, and the coupling method is also more complex. The power supply interface is connected to the high - level voltage node, and the ground interface is connected to the output terminal of the first transistor 2111. The high - level voltage signals vout_1 and vout_2 are output from the output terminal of the second sub - circuit 2122. The ground interface of the first sub - circuit 2121 is connected to the ground node, and the power supply interface is connected to the output terminal of the second transistor 2112. The low - level voltage signal vout_3 is output from the output terminal of the first sub - circuit 2121.

[0083] For the power supply control circuit 211 of the embodiments of the present disclosure, when the semiconductor element is in the enabled state, both the first transistor 2111 and the second transistor 2112 are turned on to supply power to the decoding circuit normally; when the semiconductor element is in the disabled state, both the first transistor 2111 and the second transistor 2112 are turned off, and the interfaces connected to the output terminals of the first transistor 2111 and the second transistor 2112 in the decoding circuit 212 float without voltage input, reducing circuit interference and power consumption. The output interfaces of the sub - circuits of the decoding circuit 212 output corresponding fixed - level voltages when the semiconductor element is in the enabled or disabled state to reduce data loss caused by power - down and maintain the high - speed response of the decoding circuit. The decoding circuit of the embodiments of the present disclosure can be applied to the column decoding circuit 210 of a memory device, and the memory device may include a dynamic random access memory.

[0084] According to some aspects of embodiments of the present disclosure, a memory device is provided, including: a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes at least one memory block 204, the memory block is provided with multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit includes a column decoding circuit 210 corresponding to the memory block 204, the column decoding circuit 210 is coupled to multiple columns of bit lines in the corresponding memory block 204, and is configured to receive a column address signal and perform decoding processing on the column address signal to output a column selection signal, the column selection signal indicates to activate the corresponding bit lines in the memory block 204 in the enabled state; wherein during the decoding process, for the memory block 204 in the enabled state, the power supply interfaces and ground interfaces of each sub-circuit in the column decoding circuit 210 are both normally powered; for the memory block 204 in the non-enabled state, one of the power supply interfaces or ground interfaces of each sub-circuit in the column decoding circuit 210 floats according to a preset rule.

[0085] The memory cell array may include Figure 1 The memory cell array shown, the memory device in the embodiments of the present disclosure may be a DRAM, or at least a part of the devices in the DRAM, and may be applicable to double data rate synchronous dynamic random access memories using DDR4 memory specifications, DDR5 memory specifications, and low-power double data rate synchronous dynamic random access memories using LPDDR5 memory specifications. One memory block 204 in the memory cell array may be a semiconductor element as in the above embodiments.

[0086] In combination with Figure 2 As shown, one memory block 204 may correspond to one column decoding circuit 210, the column decoding circuit 210 is coupled to all the bit lines in the memory block 204, and the column decoding circuit 210 may be located between two adjacent memory blocks 204 in the y direction; one memory block 204 may correspond to one word line driver (or row decoding circuit), and the word line decoder may be located between two adjacent memory blocks 204 in the x direction and is coupled to the word lines of the corresponding memory block 204. Figure 5 A partial schematic diagram of the peripheral circuit is provided. As Figure 5 shown, the peripheral circuit of the memory device may include a column decoding circuit 210, and the column decoding circuit 210 may include a decoding circuit 212 and a power supply control circuit 211 coupled to the decoding circuit 212.

[0087] Exemplarily, when the memory device receives an access request from the host or the memory controller, receives an address signal, and performs read, write, or refresh operations on the memory cells corresponding to the address signal, the address signal may include a row address signal and a column address signal. The peripheral circuit performs address decoding or addressing operations. The row address signal can be input into the row address buffer, decoded by the word line driver, and a row selection signal is output. The row selection signal indicates the activation of the word line where the memory cell to be operated is located. The column address signal is input into the column address buffer, decoded by the column decoding circuit 210, and a column selection signal is output. The column selection signal indicates the activation of the bit line where the memory cell to be operated is located. The memory cell at the intersection of the activated bit line and the activated word line, or the memory cell that is coupled to both the activated bit line and the activated word line simultaneously, is the memory cell to be operated. When the peripheral circuit performs address decoding or addressing operations, taking column decoding as an example, the memory block 204 where the memory cell to be operated is located can be determined according to the address signal, an enable signal is generated to indicate that the memory block 204 is in an enabled state, and the enable signal is sent to the column decoding circuit 210 corresponding to the enabled memory block 204. The decoding circuit that receives the enable signal performs the decoding operation.

[0088] During the decoding process of the column decoding circuit 210, for the memory block 204 in the enabled state, the power supply interfaces and ground interfaces of each sub - circuit in the column decoding circuit 210 corresponding to the enabled memory block are normally powered; for the memory block 204 in the non - enabled state, one of the power supply interfaces or ground interfaces of each sub - circuit in the column decoding circuit 210 corresponding to the non - enabled memory block floats according to a preset rule, thereby reducing the leakage current in the column decoding circuit 210 and reducing power consumption. When one of the power supply interfaces or ground interfaces of each sub - circuit in the column decoding circuit 210 floats according to a preset rule, it outputs a corresponding fixed - level voltage when each interface in the column decoding circuit 210 is normally powered, so as to reduce the data loss phenomenon caused by power - down and maintain the high - speed response of the decoding circuit.

[0089] In some embodiments, the column decoding circuit 210 includes: a power supply control circuit 211, including: an input interface, a first output interface, and a second output interface. The input interface receives the storage block 204 enable signal. The first output interface outputs a first voltage, and the second output interface outputs a first ground voltage. When the storage block 204 enable signal indicates that the storage block 204 is in an enabled state, the first output interface is connected to the high-level voltage node, and the second output interface is connected to the low-level voltage node. When the storage block 204 enable signal indicates that the storage block 204 is in a disabled state, both the first voltage and the first ground voltage are floating; and a decoding circuit 212, including a plurality of sub-circuits. Each sub-circuit includes: a power supply interface, a ground interface, and an output interface. The power supply interface of the sub-circuit receives the first voltage or the ground interface receives the first ground voltage. When the storage block 204 enable signal indicates that the storage block 204 is in a disabled state, the output interface of the sub-circuit outputs a corresponding fixed-level voltage.

[0090] In some embodiments, the power supply control circuit 211 includes: a first transistor 2111, a second transistor 2112, and an inverter circuit. Wherein, the input end of the first transistor 2111 is connected to the low-level voltage node, and the output end of the first transistor 2111 outputs the first ground voltage. The input end of the second transistor 2112 is connected to the high-level voltage node, and the output end of the second transistor 2112 outputs the first voltage. The input end of the inverter circuit receives the storage block 204 enable signal, and the output end of the inverter circuit is connected to the control end of one of the first transistor 2111 or the second transistor 2112. The control end of the transistor not connected to the inverter circuit receives the storage block 204 enable signal.

[0091] In some embodiments, the first transistor 2111 is an N-type transistor and the second transistor 2112 is a P-type transistor.

[0092] In some embodiments, as Figure 3a shown, the control end of the second transistor 2112 is connected to the output end of the inverter circuit, and the control end of the first transistor 2111 receives the storage block 204 enable signal. When the storage block 204 enable signal indicates that the storage block 204 is in an enabled state, it is a high-level voltage.

[0093] The input terminal of the reverse circuit receives the high-level enable signal Blk_en, outputs a low-level voltage to the control terminal of the second transistor 2112 to turn on the second transistor 2112, and the output terminal of the second transistor 2112 outputs a high-level first voltage vp to the power supply interface of the decoding circuit 212. The control terminal of the first transistor 2111 is not coupled to the reverse circuit. The control terminal of the first transistor 2111 receives the high-level enable signal Blk_en, and the first transistor 2111 is turned on. Its output terminal outputs a first ground voltage vn to the ground interface of the decoding circuit 212. When the high-level enable signal Blk_en is not applied or a low-level signal is applied, that is, the storage block 204 is in a non-enabled state, both the first transistor 2111 and the second transistor 2112 are not turned on, and the output terminals of the two transistors are both floating, without voltage output. One of the power supply interface and the ground interface of each sub-circuit in the multiple sub-circuits of the decoding circuit 212 is connected to the corresponding output terminal of the first transistor and the second transistor, and this interface is floating, and the remaining interfaces of each sub-circuit in the multiple sub-circuits are normally powered.

[0094] In some embodiments, such as Figure 3b shown, the control terminal of the first transistor 2111 is connected to the output terminal of the reverse circuit, and the control terminal of the second transistor 2112 receives the enable signal of the storage block 204; the enable signal of the storage block 204 is a low-level voltage when indicating that the storage block 204 is in an enabled state.

[0095] The output terminal of the reverse circuit receives the low-level enable signal Blk_en, outputs a high-level voltage to the control terminal of the first transistor 2111 to turn on the first transistor 2111, and the output terminal of the first transistor 2111 outputs a low-level first ground voltage vn to the ground interface of the decoding circuit 212. The control terminal of the second transistor 2112 is not coupled to the reverse circuit. The control terminal of the second transistor 2112 receives the low-level enable signal Blk_en, and the second transistor 2112 is turned on. Its output terminal outputs a high-level first voltage vp to the power supply interface of the decoding circuit 212. When the low-level enable signal Blk_en is not applied or a high-level signal is applied, that is, the storage block 204 is in a non-enabled state, the first transistor 2111 and the second transistor 2112 are not turned on, and the output terminals of the two transistors are both floating, without voltage output. One of the power supply interface and the ground interface of each sub-circuit in the multiple sub-circuits of the decoding circuit 212 is connected to the corresponding output terminal of the first transistor and the second transistor, and this interface is floating, and the remaining interfaces of each sub-circuit in the multiple sub-circuits are normally powered.

[0096] In some embodiments, such as Figures 4a to 4fAs shown, the multiple sub-circuits of the decoding circuit 212 include a first sub-circuit 2121 and / or a second sub-circuit 2122; wherein, the output interface of the first sub-circuit 2121 outputs a low-level voltage, the power supply interface of the sub-circuit is connected to the output end of the second transistor 2112, and the ground interface is connected to the low-level voltage node; the output interface of the second sub-circuit 2122 outputs a high-level voltage, the ground interface of the sub-circuit is connected to the output end of the first transistor 2111, and the power supply interface is connected to the high-level voltage node.

[0097] It should be noted that Figures 4a to 4f The sub-circuits shown can be examples of a part of the decoding circuit 212. Any circuit in the figure can be arbitrarily selected and coupled to form a decoding circuit 212 with different device functions. The first sub-circuit 2121 and the second sub-circuit 2122 can include circuits with multiple input terminals (at least including a power supply interface and a ground interface) and an output interface. One of the power supply interfaces or the ground interfaces of the first sub-circuit 2121 and the second sub-circuit 2122 is connected to the corresponding output end of the first transistor and the second transistor, and this interface is floating. The remaining interfaces of each sub-circuit in the multiple sub-circuits are normally powered. The first sub-circuit 2121 and the second sub-circuit 2122 include but are not limited to: various logic gates; including but not limited to: one or more of an AND gate, an OR gate, a NOT gate (inverter), a NAND gate, and a NOR gate.

[0098] Taking Figure 4b as an example, Figure 4b A circuit example is shown in which the sub-circuit of a decoding circuit 212 is composed of multiple second sub-circuits 2122 and multiple first sub-circuits 2121. The second sub-circuit 2122 can include a NOT gate (inverter), and the first sub-circuit 2121 can include a NOT gate or a NOR gate. Figure 4bThe signal flow in the middle is from left to right. The first second sub-circuit 2122a inputs a low-level voltage lypulse, the vdd2h power supply interface inputs a high-level voltage, the vs_ydec ground interface is connected to the vn output terminal of the first transistor 2111 for normal power supply or floating, and the output interfaces all output high-level voltages to the first first sub-circuit 2121a. The vp_ydec power supply interface of the first sub-circuit 2121a is connected to the vp output terminal of the second transistor 2112 for normal power supply or floating, and the output interfaces all output a low-level voltage lypulse_eq. The low-level voltage lypulse_eq passes through two NOT gates (the second second sub-circuit 2122b and the second first sub-circuit 2121b) in sequence and then outputs a low-level voltage lypulse_d. The low-level voltage lypulse_d and the low-level voltage lypulse_eq are input into a NOR gate (the third first sub-circuit 2121c). The ground interface of the NOR gate is grounded, and the vp_ydec power supply interface of the NOR gate is connected to the vp output terminal of the second transistor 2112 for normal power supply or floating, and the output ports all output a low-level voltage ldl_eq. The low-level voltage lypulse can be generated and input by Figure 4a the circuit in Figure 4a and Figure 4b the circuit shown. When the storage block 204 is in the enabled state, the first transistor 2111 and the second transistor 2112 of the power supply control circuit 211 are both turned on to supply power to the vp_ydec power supply interface and the vs_ydec ground interface in the sub-circuit; when the storage block 204 is in the non-enabled transition state, the first transistor 2111 and the second transistor 2112 are both turned off, and the vp_ydec power supply interface and the vs_ydec ground interface in the circuit are both floating; the output interfaces of each sub-circuit output corresponding level voltages with the same logic level when the storage block 204 is in the enabled or non-enabled state. The low-level voltage ldl_eq can be generated and input by Figure 4b the circuit in Figure 4b and Figure 4c the circuit shown.

[0099] The power supply control circuit 211 according to the embodiments of the present disclosure, when the storage block 204 is in the enabled state, both the first transistor 2111 and the second transistor 2112 are turned on to supply power to the decoding circuit 212 normally; when the storage block 204 is in the disabled state, both the first transistor 2111 and the second transistor 2112 are turned off, and the output terminals of the first transistor 2111 and the second transistor 2112 are both floating, without voltage output. One of the power supply interface and the ground interface of each sub-circuit in the multiple sub-circuits of the decoding circuit is connected to the corresponding output terminal of the first transistor 2111 and the second transistor 2112, and this interface is floating, and the remaining interfaces of each sub-circuit in the multiple sub-circuits are supplied with power normally. In this way, for a semiconductor element in the disabled state, its output is the fixed-level voltage corresponding to the normal power supply of the remaining interfaces, and no current is formed between its power supply interface and the ground interface. In this way, on the premise of ensuring that semiconductor elements in various states can work normally, the leakage and power consumption of the power supply interface and the ground interface of the semiconductor elements in the disabled state are reduced.

[0100] In some embodiments, the decoding circuit 212 includes a control signal generation circuit and an address enable generation circuit; wherein, the control signal generation circuit is coupled to the power supply control circuit 211 and is configured to generate at least a local data line read control signal and a local data line write control signal; the address enable generation circuit is coupled to the power supply control circuit 211 and is configured to receive a column address signal and a storage block enable signal, and generate a column selection signal corresponding to each bit line by using the column address signal and the storage block enable signal.

[0101] In some specific embodiments, the control signal generation circuit may include Figures 4a to 4e a circuit formed by coupling circuits, and the control signal generation circuit may further include other sub-circuits. It should be noted that Figures 4a to 4e the same signal flags in Figure 4a the circuit need to be connected together. For example, Figure 4b the first timing control signal lypulse of the circuit can be connected to the first timing control signal lypulse of

[0102] the circuit. The generated third local control signal ldl_rd signal can be a local data line read control signal, the second local control signal ldl_rden can be a local data write / read control enable signal, and the fourth local control signal ldl_wr signal can be a local data line write control signal. Figure 4f the circuits shown in Figure 4f the number of the circuits shown in Figure 4f is the same as the number of bit lines included in the storage block, and the preliminary column decoding signals received by each Figure 4fThe received preliminary column decoding signal of the shown circuit is the first decoding signal AY_1 <m-1:0>Any one of the multiple data bits and the second decoding signal AY_1 <k-1:0>any one of the multiple data bits in, for example Figure 4f AY_2<0> and AY_1<0> shown in Figure 4f , each Figure 4f The circuit shown in Figure 4f also needs to receive a storage block enable signal Blk_en and a first timing control signal lypulse, and output a column selection signal cls through Figure 4f the address enable generation circuit shown in Figure 4f <n-1:0>, for example Figure 4f the cls shown <n-1>。

[0103] It should be noted that here, K, M, and n are all positive integers, and n = M * K. n can be the same as the number of bits included in a storage block, cls <n-1:0>The corresponding n data bits are respectively connected to a bit line in the memory block.

[0104] In some embodiments, the peripheral circuit further includes: a sense amplifier circuit 206 and a local data line control circuit 207; wherein, the local data line control circuit 207 is coupled to the column decoding circuit 210 and is coupled to the sense amplifier circuit 206 through the local data line, and is configured to receive a local data line read control signal and a local data line write control signal, and use the local data line read control signal and the local data line write control signal to control the data interaction direction between the local data line and the global data line; the sense amplifier circuit 206 is coupled to the column decoding circuit 210 and the bit lines in the memory cell array; the column decoding circuit 210 is further configured to use the column selection signal to control the data interaction between the local data line and the bit line; the sense amplifier circuit 206 is configured to detect and amplify the voltage difference on the bit line.

[0105] Figure 5 It is a schematic diagram of the connection relationship of a partial component circuit of a peripheral circuit shown according to an embodiment of the present disclosure; Figure 6 It is a schematic diagram of the connection relationship of a partial component circuit of a partial peripheral circuit corresponding to a memory block shown according to an embodiment of the present disclosure. As Figure 5 、 6 shown, a memory block 204 can correspond to multiple sense amplifier circuits (SAs) 206, and the column decoding circuits corresponding to a memory block 204 are respectively coupled to the multiple sense amplifier circuits 206 through multiple bit lines Bl_n and complementary bit lines bl. Here, the bit line Bl_n is the bit line where the memory cell to be operated is located, and there is no memory cell to be operated on the complementary bit line bl.

[0106] As Figure 5 、 6 shown, the global data lines in the peripheral circuit may include dlb and dl, and the local data lines may include ldlb and ldl. As shown in the figure, each memory block 204 corresponds to an ldlb and an ldl, and the ldlb is coupled to all the bit lines in the memory block 204 ( Figure 6 Among them, Bl_0 to Bl_n-1), the ldl is coupled to the complementary bit lines bl corresponding to each bit line in the storage block 204. The local data line is coupled to the local data line control circuit 207. The global data line dlb and dl are respectively coupled to the ldlb and ldl through the local data line control circuit 207. One global data line dlb can be coupled to the local data lines ldlb corresponding to multiple storage blocks 204 for communicating with the bit line Bl_n; one global data line dl can be coupled to the local data lines ldl corresponding to multiple storage blocks 204 for communicating with the complementary bit line bl. The sense amplifier is coupled to the bit line Bl_n and the complementary bit line bl. The bit line Bl_n and the complementary bit line bl are coupled to the local data line control circuit 207 through the local data line. The local data line control circuit 207 responds to the local data line read control signal and controls the data to be transmitted from the bit line to the local data line and then to the global data line to feedback the host to read the data. The local data line control circuit 207 responds to the local data line write control signal and controls the data to be transmitted from the global data line to the local data line to perform a write operation on the storage unit. During the read or write operation, the column decoder responds to the relevant operation signal and generates the column selection signal cls <n-1:0>, select or enable the bit line or complementary bit line that needs to perform an operation. The bit line and the complementary bit line then output data to the local data line or obtain data from the local data line.

[0107] The peripheral circuit further includes a sense amplifier control circuit (SA control logic) 205 coupled to a plurality of sense amplifier circuits 206 for controlling the sense amplifier circuits 206. In some embodiments, the sense amplifier control circuit 205 may include Figures 7a to 7c the circuit shown. Figure 7a The circuit in may include an inverter circuit. The output terminal of the inverter circuit is coupled to the control terminal of a transistor. When the input signal to the inverter circuit is San_i, the inverter circuit outputs a voltage of the opposite level of San_i to the transistor control terminal and turns on the transistor, and outputs the SAP signal to the sense amplifier circuit 206. Figure 7b The circuit in may include an inverter circuit. The output terminal of the inverter circuit is coupled to the control terminal of a transistor. When the input signal to the inverter circuit is Sap_i, the inverter circuit outputs a voltage of the opposite level of Sap_i to the transistor control terminal and turns on the transistor, and outputs the SAN signal to the sense amplifier circuit 206. Figure 7c The circuit in may include an inverter circuit. When the input signal is Bleq_i, Bleq that outputs a voltage of the opposite level of Bleq_i is transmitted to the sense amplifier circuit 206.

[0108] In some embodiments, Figure 8 shows a schematic diagram of the sense amplifier circuit 206 coupled to the bit line Bl_n and the complementary bit line bl. The sense amplifier circuit 206 may include four transistors, namely transistor 2061, transistor 2062, transistor 2063, and transistor 2064. Among them, transistor 2061 and transistor 2063 are P-type transistors, and transistor 2062 and transistor 2064 are N-type transistors.

[0109] In some embodiments, a read process includes a precharge operation, a charge sharing operation, a sensing operation, and a restore operation. When performing the precharge, the word line is turned off, and after a period of time, the sense amplifier circuit 206 is turned off, so that the voltages on bit line Bl_n and bit line Bl_n are stabilized at Vref, where Vref = (1 / 2)vdd. After the precharge operation, the charge sharing operation is entered. The word line is turned on, and the positive charge stored in the capacitor in the memory cell will flow to bit line Bl_n. At this time, the voltage of bit line Bl_n is pulled up to Vref+, and charge sharing occurs between the charge on bit line Bl_n and the charge stored in the capacitor. Vref+ is for the case where the memory cell stores "1". When the memory cell stores "0", the voltage of bit line Bl_n will be pulled down to Vref-, and Vref- is for the case where the memory cell stores "0".

[0110] After the voltage of bit line Bl_n is pulled up to Vref+ Figure 8 the first N-type transistor 2064 shown in will be more conductive than the second N-type transistor 2062, and the first P-type transistor 2061 will be more conductive than the second P-type transistor 2063. In the sensing operation, SAN can be a ground voltage and SAP can be a high-level voltage. Since the first N-type transistor 2064 is more conductive than the second N-type transistor 2062, the voltage on the complementary bit line bl will be pulled to the ground voltage by SAN faster. Similarly, the voltage on bit line Bl_n will be pulled to the high-level voltage by SAP faster. The first P-type transistor 2061 and the first N-type transistor 2064 are turned on, while the second P-type transistor 2063 and the second N-type transistor 2062 are turned off, and the voltages on bit line Bl_n and the complementary bit line bl both enter a stable state, correctly presenting the information stored in the capacitor.

[0111] After the sensing operation is completed, in the restore operation, bit line Bl_n is at a stable high-level voltage. At this time, bit line Bl_n will charge the capacitor, and after a period of time, the charge of the capacitor is restored to the state before the read operation. In the sensing operation, the control column selection signal turns on the column selection transistor on bit line Bl_n, and the information stored in the capacitor is output to the output line by the sense amplifier circuit 206, so that the outside world can read the specific information on the capacitor from bit line Bl_n.

[0112] In some embodiments, part of the write operation process of the memory cell is similar to the read operation. In addition to including the precharge operation, the charge sharing operation, the sensing operation, and the restore operation in the read operation, it also includes a write restore operation. During the write restore operation, by controlling the write enable signal, the write enable transistor ( Figure 8 When the transistor (not shown in the figure) is turned on, the bit line Bl_n will be pulled to the ground voltage, and the complementary bit line bl will be pulled to the high-level voltage. After a certain period of time, the charge of the capacitor is discharged to the 0 state. Then, the word line is controlled to cut off the transistor connected to the capacitor, completing the write 0 operation. It should be noted that the write enable transistor is similar to the column selection transistor. Each bit line is coupled to a column selection transistor and a write enable transistor, and the column selection transistor and the write enable transistor are serially coupled. During the write recovery operation, the column selection transistor and the write enable transistor of the bit line Bl_n are turned on simultaneously.

[0113] In some embodiments, the memory cell array is disposed on the first semiconductor structure 21, and the peripheral circuit is disposed on the second semiconductor structure 22; the first semiconductor structure 21 and the second semiconductor structure 22 are stacked and electrically connected by bonding; each decoding circuit 212, the sense amplifier circuit 206, the local data line control circuit 207, and the word line driving circuit corresponding to each memory block 204 are all located at the position of the positive projection of a corresponding memory block 204 on the plane where the second semiconductor structure is located.

[0114] Figure 9 The figure shows a schematic diagram of the bonding connection between the first semiconductor structure 21 and the second semiconductor structure 22 through the first bonding contact 211 and the second bonding contact 221. The word lines and bit lines are shown in the figure by way of example. The arrangement of the memory cell array, word lines, and bit lines can be as Figure 1 shown.

[0115] As Figure 10 shown, the first bonding layer is located on one surface of the first semiconductor structure 21 in the negative z direction. The first bonding layer includes a first dielectric layer, and a plurality of first bonding contacts 211 penetrate the first dielectric layer and are coupled to the circuit layer in the first semiconductor structure 21 to lead out the electrical signals of device structures such as word lines and bit lines. The second bonding layer is located on one surface of the second semiconductor structure 22 in the positive z direction. The second bonding layer includes a second dielectric layer, and the second bonding contacts 221 penetrate the second dielectric layer and are coupled to the circuit layer in the second semiconductor structure 22 to lead out the electrical signals of the peripheral circuit. The first bonding contact 211 and the first bonding contact 211 are in bonding contact to realize the electrical signal interconnection of the peripheral circuit of the memory cell array and realize the control of the peripheral circuit over the memory cell array.

[0116] Exemplarily, the constituent materials of the word lines, bit lines, first bonding contacts 211, second bonding contacts 221, and the interconnect layer include conductive materials such as copper, tungsten, gold, silver, titanium, nickel, etc. The constituent materials of the first dielectric layer and the second dielectric layer may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. The first dielectric layer and the second dielectric layer can electrically isolate the bonding contacts, and can provide a better plane for the bonding surface, provide a larger bonding area, and improve the bonding adhesion force.

[0117] It can be understood that in the first semiconductor structure 21 and the second semiconductor structure 22, there are multiple stacked and mutually coupled interconnect layers and conductive plugs for leading out the electrical signals of the device structures existing at different hierarchical heights.

[0118] In some embodiments, during bonding, the first wafer including a plurality of first semiconductor structures 21 and the second wafer including a plurality of second semiconductor structures 22 can be bonded. The bonding may include hybrid bonding, and the electrical signals between the two wafers are interconnected through conductive bonding contacts. The insulating dielectric layer provides electrical isolation and a larger bonding surface, improving the bonding adhesion force.

[0119] As Figure 11 shown, a schematic diagram of the distribution of some memory blocks 204 on the first semiconductor structure 21 in the xoy plane and a schematic diagram of the distribution of the corresponding part of the peripheral circuit on the second semiconductor structure 22 corresponding to the memory block 204 in the xoy plane are shown. One memory block 204 can correspond to Figure 5 shown column decoding circuit ydec (including power supply control circuit 211 and decoding circuit 212), multiple sense amplifier circuits (SAs), and sense amplifier circuit control circuit (SA control logic), local data line control circuit (LDL_SW). The multiple sense amplifier circuits can be arranged along the x direction. The sense amplifier circuit control circuit, column decoding circuit, and local data line control circuit are located between two rows of sense amplifier circuits 206. The area occupied by the two rows of sense amplifier circuits and the sense amplifier circuit control circuit, column decoding circuit, and local data line control circuit between them on the second semiconductor structure 22 can be denoted as circuit block 220. The area of the circuit block 220 can be equal to or unequal to the area of the memory block 204. The peripheral circuit further includes a word line driver, which is located between two adjacent circuit blocks 220 in the x direction and is coupled to the word lines of the corresponding memory blocks 204. After the first semiconductor structure 21 and the second semiconductor structure 22 are bonded, the projection of the circuit block 220 in the xoy plane can at least partially overlap with the projection of the memory block 204 in the xoy plane.

[0120] In some embodiments, the memory cell array includes a plurality of memory banks 201, each memory bank 201 including a plurality of row memory blocks 204 and a plurality of column memory blocks 204; the column decoding circuit 210 further includes a primary decoding circuit configured to receive a primary column address signal, perform decoding processing, and output the column address signal; the number of transmission lines corresponding to the primary column address signal is less than the number of transmission lines corresponding to the column address signal; each memory bank 201 corresponds to a plurality of the primary decoding circuits, a plurality of the power supply control circuits 211, and a plurality of decoding circuits 212. Each primary decoding circuit corresponds to one column of memory blocks 204, and each power supply control circuit 211 and decoding circuit 212 corresponds to one memory block 204 in one column of memory blocks 204.

[0121] Figure 12 is a top-down distribution schematic diagram of memory blocks, a preliminary column decoding circuit, and a column decoding circuit in a memory bank shown according to an embodiment of the present disclosure. As Figure 12 shown, one column decoding circuit 210 corresponds to one column of memory blocks. One column decoding circuit 210 includes a primary decoding circuit (primary ydec) and a plurality of the foregoing power supply control circuits and decoding circuits (the power supply control circuit + decoding circuit is represented as Figure 12 ydec in). The number of the power supply control circuit + decoding circuit is the same as the number of memory blocks in one column of memory blocks. The primary column address signal output by the primary decoding circuit includes the foregoing first decoding signal AY_1 <m-1:0>and a second decoding signal AY_1 <k-1:0>。

[0122] In some embodiments, the memory device includes a dynamic random access memory.

[0123] According to some aspects of embodiments of the present disclosure, a memory system 102 is provided, including: one or more memory devices 104 of the above embodiments; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0124] As Figure 13 shown, embodiments of the present disclosure provide a system 100 including a host. The host 108 is coupled to the memory controller 106, and the memory controller 106 is coupled to one or more memory devices 104. The memory device 104 may include a DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure.

[0125] The memory system 102 can be used as the computer memory in the system 100 or as a cache in the system 100.

[0126] In some specific examples, the memory system 102 can be used as an auxiliary in a solid-state drive, which can bring improvements in aspects such as reading and writing to the solid-state drive. Currently, most high-end solid-state drive products choose to embed DRAM to improve product performance and random read / write speed. Exemplarily, when writing files, especially small files, the small files are processed by the DRAM and then stored in the Flash, making the solid-state drive have higher storage efficiency and faster speed. The Flash includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0127] In some other embodiments, as Figure 14 shown, the system 100 may only include the host 108 and the memory device 104 coupled thereto. The controller for controlling the memory device 104 may be located inside the host 108, such as a memory controller integrated in a central processing unit (CPU), or a northbridge or southbridge chip integrated on the motherboard of the system 100. The memory device may include but not be limited to: double data rate synchronous dynamic random access memory with DDR4 memory specification, double data rate synchronous dynamic random access memory with DDR5 memory specification, and low-power double data rate synchronous dynamic random access memory with LPDDR5 memory specification.

[0128] In some embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the direct or indirect coupling between the components shown or discussed with each other.

[0129] According to some aspects of the embodiments of the present disclosure, Figure 15 A control method for a memory device is provided, including:

[0130] Step S101: In response to the storage block being in an enabled state, input a first voltage and a first ground voltage to the column decoding circuit corresponding to the storage block to perform decoding processing on the column address signal and output a column selection signal; the column selection signal indicates activating the corresponding bit lines in the storage block in the enabled state;

[0131] Step S102: In response to the storage block being in a disabled state, float one of the interfaces in the column decoding circuit corresponding to the storage block that receives the first voltage or the ground voltage according to a preset rule.

[0132] In some embodiments, as Figure 16 shown, the control method of the decoding circuit includes:

[0133] Step S201: Input the storage block enable signal to the power supply control circuit. In response to the storage block being in an enabled state, cause the power supply control circuit to output a first voltage and a first ground voltage to the decoding circuit, and cause the decoding circuit to output a corresponding fixed-level voltage;

[0134] Step S202: In response to the storage block being in a disabled state, float the first voltage and the first ground voltage, and cause the decoding circuit to output the corresponding fixed-level voltage.

[0135] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A decoding circuit, characterized in that, it includes: A power supply control circuit, including: a first transistor, a second transistor and a reverse circuit; wherein, The input end of the first transistor is connected to a low-level voltage node, and the output end of the first transistor outputs a first ground voltage; The input end of the second transistor is connected to a high-level voltage node, and the output end of the second transistor outputs a first voltage; The input end of the reverse circuit receives a semiconductor element enable signal; the output end of the reverse circuit is connected to the control end of one of the first transistor or the second transistor; The control end of the transistor not connected to the reverse circuit receives the semiconductor element enable signal; A decoding circuit, including a plurality of sub-circuits, the power supply interface of the sub-circuit is connected to the output end of the second transistor, or the ground interface of the sub-circuit is connected to the output end of the first transistor.

2. The decoding circuit according to claim 1, characterized in that, The plurality of sub-circuits include a first sub-circuit and / or a second sub-circuit; wherein, The output interface of the first sub-circuit outputs a low-level voltage, the power supply interface of the sub-circuit is connected to the output end of the second transistor, and the ground interface is connected to the low-level voltage node; The output interface of the second sub-circuit outputs a high-level voltage, the ground interface of the sub-circuit is connected to the output end of the first transistor, and the power supply interface is connected to the high-level voltage node.

3. The decoding circuit according to claim 1, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

4. The decoding circuit according to claim 1, characterized in that, The control end of the second transistor is connected to the output end of the reverse circuit, and the control end of the first transistor receives the semiconductor element enable signal; the semiconductor element enable signal is a high-level voltage when indicating that the semiconductor element is in an enabled state.

5. The decoding circuit according to claim 1, characterized in that, The control end of the first transistor is connected to the output end of the reverse circuit, and the control end of the second transistor receives the semiconductor element enable signal; the semiconductor element enable signal is a low-level voltage when indicating that the semiconductor element is in an enabled state.

6. A memory device, including: A memory cell array and a peripheral circuit coupled to the memory cell array; characterized in that, The memory cell array includes memory blocks, the memory blocks have multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; The peripheral circuit includes a column decoding circuit corresponding to the memory block. The column decoding circuit is coupled to multiple columns of bit lines in the corresponding memory block and is configured to receive a column address signal, decode the column address signal, and output a column selection signal, where the column selection signal indicates to activate the corresponding bit lines in the enabled memory block. During the decoding process, for the enabled memory block, the power supply interfaces and ground interfaces of each sub - circuit in the column decoding circuit are normally powered; for the disabled memory block, one of the power supply interfaces or ground interfaces of each sub - circuit in the column decoding circuit floats according to a preset rule.

7. The memory device according to claim 6, wherein, the column decoding circuit includes: a power supply control circuit, including: an input interface, a first output interface, and a second output interface. The input interface receives a memory block enable signal, the first output interface outputs a first voltage, and the second output interface outputs a first ground voltage. When the memory block enable signal indicates that the memory block is in the enabled state, the first output interface is connected to a high - level voltage node, and the second output interface is connected to a low - level voltage node. When the memory block enable signal indicates that the memory block is in the disabled state, both the first voltage and the first ground voltage float; and a decoding circuit, including multiple sub - circuits. Each sub - circuit includes: a power supply interface, a ground interface, and an output interface. The power supply interface of the sub - circuit receives the first voltage or the ground interface receives the first ground voltage. The output interface of the sub - circuit outputs a corresponding fixed - level voltage when the memory block enable signal indicates that the memory block is in the disabled state.

8. The memory device according to claim 7, wherein, the power supply control circuit includes: a first transistor, a second transistor, and an inverter circuit; wherein, the input end of the first transistor is connected to the low - level voltage node, and the output end of the first transistor outputs the first ground voltage. The input end of the second transistor is connected to the high - level voltage node, and the output end of the second transistor outputs the first voltage. The input end of the inverter circuit receives the memory block enable signal, and the output end of the inverter circuit is connected to the control end of one of the first transistor or the second transistor. The control end of the transistor not connected to the inverter circuit receives the memory block enable signal.

9. The memory device according to claim 8, wherein, the multiple sub - circuits include a first sub - circuit and / or a second sub - circuit; wherein, the output interface of the first sub - circuit outputs a low - level voltage. The power supply interface of the sub - circuit is connected to the output end of the second transistor, and the ground interface is connected to the low - level voltage node; the output interface of the second sub - circuit outputs a high - level voltage. The ground interface of the sub - circuit is connected to the output end of the first transistor, and the power supply interface is connected to the high - level voltage node.

10. The memory device according to claim 8, wherein, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

11. The memory device according to claim 8, wherein, a control terminal of the second transistor is connected to an output terminal of the reverse circuit, and a control terminal of the first transistor receives the storage block enable signal; the storage block enable signal is at a high-level voltage when indicating that the storage block is in an enabled state.

12. The memory device according to claim 8, wherein, a control terminal of the first transistor is connected to an output terminal of the reverse circuit, and a control terminal of the second transistor receives the storage block enable signal; the storage block enable signal is at a low-level voltage when indicating that the storage block is in an enabled state.

13. The memory device according to claim 7, wherein, the decoding circuit includes a control signal generation circuit and an address enable generation circuit; wherein, the control signal generation circuit is coupled to the power supply control circuit and is configured to generate at least a local data line read control signal and a local data line write control signal; the address enable generation circuit is coupled to the power supply control circuit and is configured to receive a column address signal and a storage block enable signal, and generate a column selection signal corresponding to each bit line by using the column address signal and the storage block enable signal.

14. The memory device according to claim 13, wherein, the peripheral circuit further includes: a sense amplifier circuit and a local data line control circuit; wherein, the local data line control circuit is coupled to the column decoding circuit and is coupled to the sense amplifier circuit through a local data line, and is configured to receive the local data line read control signal and the local data line write control signal, and control a data interaction direction between the local data line and the global data line by using the local data line read control signal and the local data line write control signal; the sense amplifier circuit is coupled to the column decoding circuit and a bit line in the memory cell array; the column decoding circuit is further configured to control a data interaction between the local data line and the bit line by using the column selection signal; the sense amplifier circuit is configured to detect and amplify a voltage difference on the bit line.

15. The memory device according to claim 14, wherein, the memory cell array is disposed on a first semiconductor structure, and the peripheral circuit is disposed on a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by a bonding method; each of the decoding circuits, the sense amplifier circuit, the local data line control circuit, and the word line driving circuit corresponding to each storage block are all located at a position of a positive projection of a corresponding storage block on a plane where the second semiconductor structure is located.

16. The memory device according to claim 7, wherein, the memory cell array includes a plurality of memory banks, and each memory bank includes a plurality of row storage blocks and a plurality of column storage blocks; The column decoding circuit further includes a primary decoding circuit configured to receive a primary column address signal, perform decoding processing, and output the column address signal; the number of transmission lines corresponding to the primary column address signal is less than the number of transmission lines corresponding to the column address signal; Each of the memory banks corresponds to a plurality of the primary decoding circuits, a plurality of the power supply control circuits, and a plurality of decoding circuits. Each of the primary decoding circuits corresponds to one column of memory blocks, and each of the power supply control circuits and the decoding circuits corresponds to one memory block in one column of memory blocks.

17. The memory device according to any one of claims 6 to 16, wherein, the memory device includes a dynamic random access memory.

18. A memory system, wherein, comprises: one or more memory devices as claimed in claims 6-17; and a memory controller coupled to and controlling the memory device.

19. A control method for a memory device, wherein, comprises: In response to the memory block being in an enabled state, input a first voltage and a first ground voltage to the column decoding circuit corresponding to the memory block to perform decoding processing on the column address signal and output a column selection signal; the column selection signal indicates activation of corresponding bit lines in the memory block in the enabled state; In response to the memory block being in a disabled state, float one of the interfaces in the column decoding circuit corresponding to the memory block that receives the first voltage or the ground voltage according to a preset rule.

20. The control method according to claim 19, wherein, the control method comprises: Input the memory block enable signal to the power supply control circuit. In response to the memory block being in an enabled state, cause the power supply control circuit to output a first voltage and a first ground voltage to the decoding circuit, and cause the decoding circuit to output a corresponding fixed-level voltage; In response to the memory block being in a disabled state, float the first voltage and the first ground voltage, and cause the decoding circuit to output the corresponding fixed-level voltage.

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