Parallel folding and host write handling

Abstract

The invention relates to parallel folding and host write handling. The memory system can perform a first program operation on a first die as part of a first folding operation, the first program operation having a duration. During the duration, the memory system can perform at least a portion of a second program operation on a second die as part of a second folding operation and perform host writes. For example, a host system can transmit a command to write data to the memory system during the duration of the first programming operation. Based on the command, the memory system can suspend (e.g., delay) the second folding operation to write the data and resume (e.g., start) the second programming operation after completion of the write operation.

Description

[0001] Cross-reference

[0002] This patent application claims the benefit of priority of U.S. patent application Ser. No. 18 / 954,258, filed Nov. 20, 2024, and titled “PARALLEL FOLDING AND HOST WRITE HANDLING,” and U.S. Provisional Patent Application Ser. No. 63 / 604,779, filed Nov. 30, 2023, and titled “PARALLEL FOLDING AND HOST WRITE HANDLING,” each of which is assigned to its assignee and each of which is hereby incorporated by reference in its entirety.

[0003] The technical field relates to parallel folding and host write handling. BACKGROUND OF THE INVENTION

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of an external power supply. Memory cells configured in a volatile configuration lose their stored state when disconnected from an external power supply. SUMMARY OF THE INVENTION

[0006] Describe a device. The device may include: a memory device; and a controller coupled to the memory device, wherein the controller is configured to cause the device to: perform a first programming operation at a first die of the device during a duration as part of first data being transferred from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation; receive, during the duration, a command from a host system to write second data to the device; and perform, during the duration and at least partially based on the command, a write operation of writing the second data to a second die of the device and at least a portion of a second programming operation as part of third data being transferred from a source data block of the second die to a destination data block of the second die.

[0007] Describe a non - transitory computer - readable medium that stores code. The non - transitory computer - readable medium storing the code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: perform a first programming operation at a first die of a memory system during a duration as part of first data being transferred from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation; receive, during the duration, a command from a host system to write second data to the memory system; and perform, during the duration and at least partially based on the command, a write operation of writing the second data to a second die of the memory system and at least a portion of a second programming operation as part of third data being transferred from a source data block of the second die to a destination data block of the second die.

[0008] Describe a method. The method may include: performing a first programming operation at a first die of a memory system during a duration as part of first data being transferred from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation; receiving, during the duration, a command from a host system to write second data to the memory system; and performing, during the duration and at least partially based on the command, a write operation of writing the second data to a second die of the memory system and at least a portion of a second programming operation as part of third data being transferred from a source data block of the second die to a destination data block of the second die. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Show an example of a system that supports parallel folding and host - write handling according to the examples disclosed herein.

[0010] Figure 2An example of a data transfer diagram supporting parallel folding and host write handling according to an example disclosed herein is shown.

[0011] Figure 3 and 4 An example of a timing diagram supporting parallel folding and host write handling according to an example disclosed herein is shown.

[0012] Figure 5 A block diagram of a memory system supporting parallel folding and host write handling according to an example disclosed herein is shown.

[0013] Figure 6 A flowchart illustrating one or more methods supporting parallel folding and host write handling according to an example disclosed herein is shown. DETAILED DESCRIPTION

[0014] A memory system may support storing information in memory devices, including memory cells capable of storing various amounts of information bits (e.g., 1, 2, 3, or 4 information bits). The memory system may include memory cells with higher storage density (e.g., which may be referred to as multi-programming pass cells) (e.g., quad-level cells (QLC)) and may include memory cells with lower storage density (e.g., which may be referred to as single-programming pass cells) (e.g., single-level cells (SLC), multi-level cells (MLC), and triple-level cells (TLC)). For example, writing data to a multi-programming pass cell may be associated with a relatively high programming time due to the multiple programming operations (e.g., phases, passes) involved in writing data. Thus, writing data to a single-programming pass cell (e.g., SLC, MLC, TLC) may be faster than writing data to a multi-programming pass cell (e.g., QLC). Accordingly, the memory system may first write data (e.g., host data) to a single-programming pass cell to, for example, support faster host write performance (e.g., relative to first storing host data to QLC) and then fold (e.g., transfer) the data to a multi-programming pass cell to, for example, increase storage density and efficiency.

[0015] Some host systems may have host write performance constraints associated with the memory system (e.g., at least 60 megabytes per second (MB / s)). To support meeting the host write performance constraints, the memory system may be configured such that at least one die is available for host writes (e.g., not occupied by performing one or more operations (such as folding)), because a die occupied by some operations (such as folding) cannot be used for host writes. In some cases, the memory system may adjust (e.g., reduce) the host write performance to be less than or equal to the folding performance. Otherwise, over time, the rate of folding data from lower storage density blocks (e.g., blocks of lower storage density cells, single-programming pass cells) will be less than the rate of writing host data to the lower storage density blocks, such that the lower storage density blocks will be filled with data associated with host writes before the memory system can fold the data to higher storage density blocks and erase the lower storage density blocks. If the lower storage density blocks are filled, then the host write performance will be limited by the folding performance. That is, the host write rate will be limited by the folding (e.g., QLC folding) rate. But in some cases, the folding performance may be less than the host write performance constraint, and thus the memory system cannot operate according to the host write performance constraint. Therefore, there is a need to improve the folding performance to meet the host write performance constraint.

[0016] According to examples disclosed herein, the memory system may be configured to support a higher folding rate and thus support a higher host write rate, such that the host write performance constraint can be met (e.g., complied with, exceeded). For example, the memory system may perform a corresponding first programming operation (e.g., the programming pass portion of the folding operation) as part of a first folding operation on a first die and perform at least a portion of a corresponding second programming operation as part of a second folding operation on a second die during a duration in which the memory system can accept (e.g., perform) one or more host writes to the second die. For example, the one or more host writes may have a completion time less than the duration of the first programming operation, and the time that the second die remains idle (e.g., due to being reserved for accepting host writes) may instead be spent performing at least a portion of the second programming operation. In other words, rather than reserving one or more dies for accepting host writes, the memory system may perform corresponding programming operations on multiple (e.g., 2, all) dies as part of corresponding folding operations and temporarily interrupt (e.g., pause, delay) the programming operation on a given die to perform a host write to the die.

[0017] For example, a host system may transmit a write command to a memory system, and the memory system may pause (e.g., delay) a programming operation on one of the dies (e.g., the second die) to write data to the die, and then resume (e.g., start) the programming operation on this die after the write execution. The memory system may alternate between pausing the die on which it folds to perform a host write, such that after a duration, a different die (e.g., the first die) may be used to perform one or more host writes received during a second duration. The increased time spent performing the programming operation that is part of the folding operation improves the folding operation performance and efficiency. Thus, the host write performance may be improved such that the memory system can meet host write performance constraints and other benefits.

[0018] The features of the present disclosure are first described in the context of a system of reference Figure 1 The features of the present disclosure are described in the context of the data transfer diagrams and timing diagrams of reference Figures 2 to 4 The features of the present disclosure are further illustrated and described in the context of the device diagrams and flowcharts related to parallel folding and host write handling of reference Figures 5 to 6 These and other features of the present disclosure.

[0019] Figure 1 An example of a system 100 that supports parallel folding and host write handling according to an example disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be included in a computing device such as, for example, a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0020] The memory system 110 may be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other devices.

[0021] System 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to and read data from the memory system 110. Although Figure 1 a memory system 110 is shown, the host system 105 may be coupled to any number of memory systems 110.

[0022] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface may include (but are not limited to) a SATA interface, a Universal Flash Storage (UFS) interface, an embedded MultiMediaCard (eMMC) interface, a PCIe interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some instances, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example of

[0024] the memory system 110 may include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, then the different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at the memory arrays within the one or more memory devices 130). For example, the memory system controller 115 may receive a command or operation from the host system 105 and may convert the command or operation into an instruction or appropriate command to effect the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or combinations thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic for performing the operations ascribed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) executable by the memory system controller 115 to perform the functions ascribed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, e.g., internal storage or computations related to the functions ascribed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130, and the data may be used within the local memory 120 for subsequent retrieval by or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0028] Although Figure 1 the example of the memory system 110 in

[0029] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, the memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the corresponding memory device 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, as Figure 1 illustrated, the memory device 130-a may include a local controller 135-a and the memory device 130-b may include a local controller 135-b.

[0031] In some cases, the memory device 130 may be or include a NAND device (e.g., a NAND flash device). The memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, the memory device 130 may be a package that includes one or more dies 160. In some instances, the die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as SLC. Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as MLC when configured to each store two bits of information, TLC when configured to each store three bits of information, QLC when configured to each store four bits of information, or more generally as multi-level memory cells. The multi-level memory cells may provide a greater storage density relative to the SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for the support circuitry.

[0033] In some cases, a plane 165 may refer to a number of groups of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, the concurrent operations may be performed on memory cells within different blocks 170, so long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d that are in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes that include memory devices 130-a and 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations on different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., coupled to a common word line), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., coupled to a common digit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit (e.g., group of memory cells) of the memory that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., group of memory cells) of the memory that can be independently erased (e.g., concurrently erased as part of a single erase operation). Additionally, in some cases, the NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, the used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0036] In some cases, to update some of the data within block 170 while leaving other data within block 170 unchanged, memory device 130 can copy the data to be left unchanged to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 can mark or otherwise label the data remaining in the old block 170 as invalid or obsolete and can update the logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, for example, due to latency or wear considerations, this copy and remapping can be performed instead of erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table can be stored within the memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by local controller 135 or memory system controller 115.

[0037] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting until all pages 175 in the block 170 have invalid data before erasing and reusing the block 170, an algorithm called "garbage collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that, for example, include: selecting a block 170 containing both valid and invalid data; selecting the pages 175 within the block that contain valid data; copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected pages 175 as invalid; and erasing the selected block 170. Thus, the number of blocks 170 that have been erased can be increased so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0038] In some cases, the memory system 110 may utilize the memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or within-package) controller (e.g., the local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] System 100 may include any number of non-transitory computer-readable media that support parallel folding and host write handling. For example, the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135) may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, when executed by the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135), such instructions may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0040] The memory system 110 may include multi-programming pass units (e.g., QLC) and single-programming pass units (e.g., SLC, MLC, TLC). That is, the memory system 110 (e.g., the memory system controller 115) may perform multiple programming operations (e.g., passes, phases of write operations) to write data to the multi-programming pass units, and to write data to the single-programming pass units, the memory system 110 may perform a single programming operation. Thus, writing to the single-programming pass units may be faster than writing to the multi-programming pass units. Therefore, in some instances, the memory system 110 may first write data (e.g., host data) to the single-programming pass units to, for example, support faster host write performance (e.g., relative to first writing host data to QLC) and then fold (e.g., transfer) the data to the multi-programming pass units to, for example, increase storage density and efficiency.

[0041] Some host systems 105 may have host write performance constraints (e.g., minimum write speed, e.g., 60 MB / s) on the memory system 110. To support meeting the host write performance constraints, the memory system 110 needs to leave at least one die 160 available for host writes (e.g., not occupied by performing folding), because the other dies 160 may be occupied by folding and not available for host writes. In some cases, the memory system 110 may adjust (e.g., reduce) the host write performance to be less than or equal to the folding performance, because if the data blocks (e.g., virtual blocks 180, blocks 170) containing the single-programming pass units are filled, then the host write performance will be limited by the folding performance anyway. In some cases, the folding performance may be less than the host write performance constraint, and thus the memory system 110 cannot operate according to the host write performance constraint. Therefore, it is necessary to improve the folding performance to meet the host write performance constraint.

[0042] According to the examples disclosed herein, the memory system 110 may be configured to support a higher folding rate and thus support a higher host write rate, such that the host write performance constraint can be met (e.g., complied with, exceeded). For example, the memory system 110 may perform a corresponding first programming operation on the first die 160 as part of a first folding operation and perform at least a part of a corresponding second programming operation on the second die 160 as part of a second folding operation during a duration in which the memory system 110 may receive (e.g., perform) one or more host writes to the second die 160 (e.g., the one or more host writes require less completion time than the first programming operation, and the time during which the second die remains idle may instead be spent on performing at least part of the second programming operation).

[0043] For example, the memory system 110 may perform corresponding programming operations (e.g., passes of the folding operation) in multiple (e.g., 2, all) dies 160. One or more dies 160 (e.g., the second die 160) may be used to perform host writes in addition to performing the corresponding programming operations (e.g., performing host writes when the host system 105 transmits a write command). Other dies 160 may be dedicated to performing programming operations as part of the corresponding folding operation (e.g., QLC folding). For example, the host system 105 may transmit a write command to the memory system 110 and the memory system may pause (e.g., delay) a programming operation (e.g., QLC programming pass) on one of the dies 160 (e.g., the second die 160) to write data to the die 160 and then resume (e.g., start) the programming operation on this die 160 after the write is performed. The memory system 110 may alternate between the dies 160 that pause their folding to perform host writes such that after a duration (e.g., the first programming operation), a different die 160 (e.g., the first die 160) may be used to perform one or more host writes received during a second duration. The memory system 110 may alternate or rotate between the dies in any order, and the memory system 110 may perform host writes on the same die 160 during multiple (e.g., non-consecutive) durations.

[0044] In addition to being applied to the memory systems described herein, techniques for a method of handling host writes in parallel with QLC folding can generally also be implemented to improve the performance of various electronic devices and systems, including gaming applications. Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements while benefiting from a relatively fast response time to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve the performance of the electronic device. Implementing the techniques described herein can improve the performance of the electronic device by reducing host write conditioning and improving host write and folding performance (e.g., rate), which can reduce processing and / or latency time, improve response time, and / or otherwise improve the user experience and other benefits.

[0045] Figure 2 An example of a data transfer diagram 200 that supports parallel folding and host write handling in accordance with examples disclosed herein is shown. The data transfer diagram 200 may illustrate the operation of one or more components of the system 100 described with reference to Figure 1 For example, the data transfer diagram 200 illustrates a host system 205 and a memory system 210 that includes a memory system controller 215, where the host system 205, the memory system 210, and the memory system controller 215 may be, respectively, as referenced in Figure 1Examples of the described host system 105, memory system 110, and memory system controller 115. The data transfer diagram 200 may illustrate writing data 220 to blocks of one or more dies 225 and transferring (e.g., folding) data 220 between the blocks. The one or more dies 225 may be examples of the one or more dies 160 described with reference to Figure 1 Examples of the one or more dies 160 described. The memory system 210 may support writing data 220 to the die 225.

[0046] The die 225 may support performing a folding operation 245, where data is folded (e.g., transferred) from a block 230 to a block 235 within the die 225 (e.g., or another die 225). Refer to Figure 3 The timing of the folding operation 245 and the write operation 250 is discussed in more detail. In some examples, the memory system controller 215 may represent a controller that includes volatile memory (e.g., SRAM and other types of volatile memory). For example, the memory system controller 215 may include a buffer that includes SRAM memory (e.g., including local memory 120).

[0047] The memory system 210 may include any number of dies 225, and each die 225 may each include any number of blocks 230, 235, and 240, which may be referred to as data blocks. In some examples, the data blocks may be examples of the virtual blocks 180 or blocks 170 described with reference to Figure 1 In an example of Figure 2 die 225-a may include blocks 230-a, 235-a, and 240. Die 225-b may include blocks 230-b and 235-b. Each of the blocks 230, 235, and 240 may be operable to store corresponding data 220 in one or more pages (e.g., page 175) of the corresponding blocks 230, 235, and 240. In some examples, the blocks 230, 235, and 240 may represent source data blocks or destination data blocks depending on how the blocks are used during one or more access, write, or transfer operations. For example, the source data block 230 may be the data block from which data is transferred as part of the folding operation 245, the destination data block 235 may be the data block to which data is transferred as part of the folding operation 245, and the block 240 may be the data block to which data is written to the memory system 210 as part of the write operation 250 associated with a write command 255 from the host system 205.

[0048] In some cases, blocks 230, 235, and 240 may include SLC, MLC, TLC, or QLC (e.g., at a given time). That is, in some cases, the memory cells of a data block may be programmed as one type of memory cell at a first time and as a second type of memory cell at a second time (e.g., after erasing the data block). In some other cases, some data blocks may include a fixed (e.g., unchanging) type of memory cell. Compared to memory cells with a higher storage density (e.g., QLC), memory cells with a lower storage density (e.g., memory cells that store fewer bits per memory cell, such as SLC, MLC, and TLC) may have a faster programming time (e.g., TRROG). For example, SLC and TLC may have a TPROG of approximately 85 μs and 300 μs, respectively, while QLC may have a TPROG of approximately 3 ms or longer. In some cases, programming data into (e.g., writing to) QLC may include two-pass programming, including performing two programming operations (e.g., phases, passes) to accurately program one or more QLCs. For example, the first pass of programming QLC may span a duration of 2 ms (and other possible durations), while the second pass of programming QLC may span a duration of 3 ms (and other possible durations).

[0049] In some cases, a data block (e.g., block 240) into which data is written as part of a host write may be a data block that includes a single-programming-pass unit (e.g., a memory cell with a lower storage density). For example, if used to store data as part of a host write, block 240 may include memory cells with a lower storage density (e.g., SLC, MLC, or TLC), which may support faster writing to block 240. In some instances, block 230 may include memory cells with a lower storage density or memory cells with a higher storage density and be a source data block for a folding operation. Block 235 may include memory cells with a high storage density (e.g., QLC) to enable compressed information storage. In some instances, block 230, for example, if previously used as a destination data block for a folding operation, may include memory cells with a higher storage density.

[0050] Memory system 210 may perform one or more write operations 250 in response to one or more write commands 255 received from host system 205. For example, memory system controller 215 may receive write command 255 from host system 205 to write data 220-a1 and 220-a2 to memory system 210. Memory system controller 215 may temporarily store data 220-a1 and 220-a2 in a buffer (e.g., local memory 120) of memory system controller 215. Memory system controller 215 may determine the locations within memory system 210 where data 220-a1 and 220-a2 are to be written, such as to one or more pages of block 240. After storing the data in the buffer, memory system controller 215 may write data 220-a1 and 220-a2 to one or more pages of block 240.

[0051] Memory system 210 may determine to transfer (e.g., fold) data 220 from one or more of blocks 230 to one or more of blocks 235. Memory system controller 215 may begin to fold data 220 from pages of one or more blocks 230 to one or more blocks 235 (e.g., to free blocks 230 such that blocks 230 can be erased) (e.g., initiate transfer of data 220, e.g., part of garbage collection) as part of fold operation 245. In Figure 2 an example, memory system controller 215 may fold data 220-b1 and 220-b2 from block 230-a to block 235-a (e.g., within the same die 225-a). Similarly, memory system controller 215 may fold data 220-b3 to 220-b5 from block 230-b to block 235-b. In some instances, data may be folded from a source data block 230 in one die 225 to a destination data block 235 in a different die 225.

[0052] In some instances, the memory system 210 may not support concurrent (e.g., parallel) folding and access operations (e.g., host writes) to the same die 225 simultaneously. In some cases, the memory system 210 may reserve one or more dies 225 for host writes while other dies 225 participate in the folding operation 245. In some cases, the memory system 210 may throttle (e.g., reduce) the host write performance to be less than or equal to the folding performance. Otherwise, over time, the blocks 240 would be filled with data 220 faster than the data from the blocks 230 could be folded and erased to accommodate additional host writes. Additionally, in some cases, since the duration for folding (e.g., to QLC) is longer than the duration for writing to the blocks 240 (e.g., to SLC, MLC, or TLC) (e.g., if the blocks 240 are unavailable for storing data 220 (e.g., full)), the buffer (e.g., cache) of the memory system controller 215 (e.g., a portion of the buffer allocated to support host writes) may start to be filled with data 220. Thus, when the memory system controller 215 receives a command 255 indicating to write data 220 to one or more dies 225, the buffer may hold the data 220 instead of performing the host write operation 250. If the buffer fills up, then one or more write commands 255 may be rejected or delayed (e.g., the host write operation 250 may be suspended). Consequently, the host write performance may degrade due to the slow folding operation and, in some cases, may not meet the host write performance constraints.

[0053] As described herein, the memory system 210 may perform a programming operation (e.g., as part of a folding operation 245) on multiple (e.g., all) dies 225 and pause (e.g., or delay) the programming operation on one or more of the dies 225 to perform one or more write operations 250. The memory system 210 does not reserve one or more dies 225 for host writes, but rather multiple (e.g., all) dies 225 may be used to perform the folding operation 245 (e.g., the programming operation portion of the folding operation 245) and the folding operation 245 on one die 225 (e.g., die 225-a) may be paused or delayed to perform the write operation 250. For example, the memory system controller 215 may receive (e.g., from the host system 105) a command indicating to write data 220-a1 to die 225 and may store the data 220-a1 in a buffer of the memory system controller 215. In response to receiving the write command 255, the memory system controller 215 may pause or delay the folding operation 245-a on die 225-a and write the data 220-a1 to die 225-a while the folding operation 245-a is paused. After the write operation 250 is complete, the memory system controller 215 may resume the folding operation 245-a on die 225-a. The folding operation 245-a and the write operation 250 may occur concurrently with the folding operations (e.g., the folding operation 245-b on die 225-b) of one or more other dies 225.

[0054] The memory system 210 may alternate which dies are available to perform the host write operation 250. As depicted in the data transfer diagram 200, die 225-a may perform the write operation 250. After a particular duration (e.g., the duration is the length of time to complete the programming operation (e.g., the programming pass during QLC folding) on die 225-b as part of the folding operation 245-b), the memory system 210 may perform the write operation 250 on die 225-b. Similarly, the memory system may pause or delay the folding operation on die 225-b to perform the write operation 250. After a second duration (e.g., the duration is the length of time to complete the second programming operation (e.g., the second programming pass during QLC folding) on die 225-a as part of the folding operation 245-a), the memory system 210 may perform the write operation 250 on a different die (e.g., again die 225-a or another die 225 not depicted). The memory system 210 may switch between performing the write operation 250 on different dies 225 while the corresponding folding operations 245 (e.g., QLC programming passes) are ongoing on the dies 225. Refer to Figure 3 Further details associated with pausing or delaying a programming operation to accommodate a host write are described.

[0055] The techniques described herein can provide increased efficiency and performance and reduced latency in the operation of memory system 210. For example, the time that die 225-a remains idle (e.g., if die 225-a is reserved for host writes during the duration in which a programming operation is performed on die 225-b) can instead be used for programming operations (e.g., QLC programming, part of the folding operation 245), which can increase the folding performance (e.g., garbage collection performance) to, for example, 85 MB / s. Thus, the operations described herein can improve the latency of access operations (e.g., by reducing the throttling of host writes), which can enable memory system 210 to meet one or more latency, host write, or customer constraints (e.g., the host write performance can be increased to meet a 60 MB / s constraint). Additionally, pausing or delaying a programming operation that is part of the folding operation 245 to perform a write operation 250 can enable a smaller buffer size to be used for memory system controller 215 while meeting the host write performance constraint, which can reduce the cost of memory system 210.

[0056] Figure 3 An example of a timing diagram 300 that supports parallel folding and host write handling according to an example disclosed herein is shown. Timing diagram 300 can illustrate operations performed on a first die 305-a and a second die 305-b during three programming durations 310 (e.g., in time sequence). Dies 305 can be included in a memory system and can be examples of die 160 or 225 respectively referenced Figure 1 and 2 described. Each programming duration 310 can correspond to the duration (e.g., 2 ms, 3 ms, 4 ms, and other durations) for completion of a programming operation 320 that is part of a folding operation.

[0057] During programming duration 310, the memory system (e.g., memory system 210, memory system 110) can start, pause, delay, resume, or complete a programming operation 320 (e.g., part of the folding operation 245) and a write operation on die 305 at respective times 315 within the respective programming duration 310. Die 305 can be used to perform multiple write operations 325 during programming duration 310. The memory system can start to perform write operation 325 at the start of programming duration 310 or during programming duration 310. In some examples, write operation 325 can be performed in response to the write buffer of the memory system (e.g., a volatile memory device of the memory system controller, e.g., part of the local memory 120 allocated to support host writes) being full. In some examples, write operation 325 can be performed when there is available space in the write buffer.

[0058] The timing diagram 300 includes three programming durations 310 and two dies 305. However, any number of programming durations 310 and dies 305 are possible. The programming durations 310-a, 310-b, and 310-c can be the same or different lengths. In some instances, the respective lengths of the programming durations 310 can be based on whether the programming duration 310 corresponds to the first or second pass of a QLC write operation, and the first and second passes may have different durations (e.g., the programming duration 310-a corresponds to the first pass for die 305-b, and the programming duration 310-c corresponds to the second pass for die 305-b). For example, the programming duration 310 corresponding to the first programming pass of a multi-pass write operation (e.g., a QLC write operation) can be shorter than the programming duration 310 corresponding to the second programming pass of the multi-pass write operation.

[0059] During the programming duration 310-a, the memory system can perform a programming operation 320-a1 on the first die 305-a (e.g., the first part 320-a1-1 of the programming operation 320-a1 can be executed). For example, the execution of the programming operation 320-a1 can be part of the transfer of first data from a source data block (e.g., block 230) of die 305-a to a destination data block (e.g., block 235) of die 305-a. The memory system can start and execute at least a part (e.g., part 320-a1-1) of the programming operation 320-a1 from time 315-a0 until time 315-a1.

[0060] The programming duration 310 can include various time intervals 330 (e.g., step points, checkpoints) during which the memory system can determine whether a write command for writing host data has been received. For example, within the time intervals 330 (e.g., time intervals 330-a to 330-f), the memory system can check for write commands from the host system. In Figure 3 an example, the memory system can receive a write command, and within the time interval 330-c (e.g., at time 315-a1), the memory system can pause (e.g., abort, interrupt) the programming operation 320-a1 on die 305-a and perform a write operation 325-a of writing second data to die 305-a in response to the write command while the programming operation 320-a1 is paused.

[0061] In some instances, write operation 325-a may include overwriting one or more latches containing first data associated with programming operation 320-a1. For example, as part of transferring the first data from the source data block of die 305-a to the destination data block, the memory system may write (e.g., transfer) the first data from the source data block to one or more latches of the memory system (e.g., for subsequently writing the latched first data to the destination data block). In some cases, to support the execution of write operation 325-a, the memory system may overwrite the first data in one or more latches with second data (e.g., to support writing the second data from the one or more latches to die 305-a). In some instances, the memory system may overwrite one or more latches with second data due to a write command being received after the first data has been written to the one or more latches. The memory system may rewrite the first data associated with programming operation 320-a1 to one or more latches based on the overwrite and after write operation 325-a is executed. Write operation 325-a may be completed (e.g., executed) in less time than the duration of programming duration 310-a. That is, the duration for executing write operation 325-a may be less than programming duration 310-a.

[0062] After write operation 325-a is completed at time 315-a2 (e.g., once write operation 325-a is completed at time 315-a2), die 305-a may resume programming operation 320-a1 (e.g., may resume executing the second part 320-a1-2 of programming operation 320-a1). The memory system may track the state of programming operation 320-a1 such that programming operation 320-a1 may resume at the point in programming operation 320-a1 where programming operation 320-a1 was paused to execute write operation 325-a. In other words, part 310-a1-2 of programming operation 310-a1 may pick up where part 310-a1-1 stopped. The memory system may also track the state of write operation 325-a to, for example, determine at what time (e.g., time 315-a2) to resume programming operation 320-a1.

[0063] In some instances, the memory system may write first data associated with programming operation 320-a1 from one or more latches to a destination data block. The memory system may continue to perform programming operation 320-a1 until programming duration 310-a ends at time 315-a3. The memory system may continue to check write commands during time intervals 330-d to 330-f between times 315-a2 and 315-a3. During programming duration 310-a, second die 305-b may be used to perform programming operation 320-a2 (e.g., the first or second pass of a QLC programming operation). That is, during programming duration 310-a, the memory system may perform programming operation 320-a2 as part of transferring third data from a source data block of die 305-b to a destination data block of die 305-b.

[0064] The memory system may alternate between dies designated (e.g., for) performing write operation 325. In some instances, the memory system may alternate between dies 305 for each write command. In some instances, the memory system may alternate between dies 305 for different programming durations 310. For example, during programming duration 310-b, second die 305-b may be used by the memory system to perform write operation 325 corresponding to a write command received during the duration of programming duration 310-b. During programming duration 310-b, first die 305-a may be dedicated to performing programming operation 320-b1 (e.g., a continuation of programming operation 320-a1, the first or second pass of a QLC programming operation). In some instances, a write command may be received before programming duration 310 begins (e.g., before time 315-b0). The memory system may check write commands during a time interval of programming duration 310-b similar to time interval 330 of programming duration 310-a. In Figure 3 an instance, a write command may be received before programming duration 310-b, and the memory system may perform write operation 325-b at time 315-b0 (e.g., the start time of programming duration 310-b) in response to the write command. In this case, if the memory system has not yet started performing write operation 325-b, it may delay (e.g., rather than pause) a programming operation of die 305-b that was originally to start at time 315-b0. Thus, after write operation 325-b is completed (e.g., once write operation 325-b is completed), at time 315-b1, die 305-b may start and perform at least a part of programming operation 320-b2 (e.g., until time 315-b2 corresponding to the end time of programming duration 310-b).

[0065] Multiple write operations 325 may be performed during a single programming duration 310. Here, the programming operation 320 (e.g., programming operation 320-c1) may be paused multiple times during the programming duration 310. For example, during the programming duration 310-c, the memory system may use the first die 305-a to perform the write operation 325 corresponding to the write command received during the duration of the programming duration 310-c. During the programming duration 310-c, the second die 305-b may be used to perform the programming operation 320-c2. The memory system may check for write commands during a time interval 330 (not shown) of the programming duration 310-c similar to the time interval 330 of the programming duration 310-a.

[0066] In Figure 3 an example, the memory system may initiate the programming operation 320-c1 (e.g., the first part 320-c1-1 of the programming operation 320-c1) at time 315-c0 (e.g., the start time of the programming duration 310-c). The memory system may receive a write command after the start time 315-c0 of the programming duration 310-c (e.g., between time 315-c0 and time 315-c1). The memory system may pause the programming operation 320-c1 and perform the write operation 325-c1 while the programming operation 320-c1 is paused. At time 315-c2, the write operation 325-c1 may be completed and the memory system may resume the programming operation 320-c1 (e.g., may start to perform the second part 320-c1-2 of the programming operation 320-c1). The memory system may receive an additional write command after time 315-c2 (e.g., between time 315-c2 and 315-c3) and may pause the programming operation 320-c1 again at time 315-c3 to perform another write operation 325-c2. At time 315-c4, the write operation 325-c1 may be completed and the memory system may resume the programming operation 320-c1 (e.g., may start to perform the third part 320-c1-3 of the programming operation 320-c1) and perform the programming operation 320-c1 until time 315-c5 (e.g., the end of the programming duration 310-c).

[0067] In some instances, each programming duration 310 may be referred to as an iteration. An iteration may have a duration corresponding to the duration of a programming pass, such as 2,100 microseconds (μs) or another duration. In a first iteration (e.g., programming duration 310-a), a buffer associated with the memory system (e.g., a 576 KB SRAM buffer) may have available space (e.g., the buffer may be idle). The memory system may receive a host write command and perform a corresponding write operation 325 in die 305-a. In some instances, die 305-a may have multiple planes (e.g., plane 165) and the memory system may write to one or more of the planes of die 305-a. In some instances, the memory system may write to TLC and write operation 325 may cause the memory system to be busy for 900 μs or another duration. During the remainder of programming duration 310 (e.g., 1,200 μs), die 305-a may be used to perform at least a portion of a first QLC programming operation or other operations (e.g., it is part of a folding operation for transferring data from a source data block to a destination data block). In the first iteration, other dies of the memory system (e.g., die 305-b) may be used to perform at least a portion of a second QLC programming operation throughout the duration.

[0068] In a second iteration (e.g., programming duration 310-b) of a second duration, a buffer associated with the memory system may have available space (e.g., the buffer may be idle). The memory system may receive a second host write command and perform a corresponding second write operation 325 in die 305-b. In some instances, the memory system may write to TLC and second write operation 325 may cause the memory system to be busy for 900 μs or another duration. During the remainder of the second duration (e.g., 1,200 μs), die 305-b may be used to perform at least a portion of a third QLC programming operation or other operations. In the second iteration, other dies of the memory system (e.g., die 305-a) may be used to perform at least a portion of a fourth QLC programming operation throughout the duration.

[0069] The memory system may continue to perform QLC programming and write operations to alternate write operations 325 between dies. For example, a third iteration may be similar to the first operation and a fourth iteration may be similar to the second operation.

[0070] Figure 4An example of a timing diagram 400 that supports parallel folding and host write handling according to the examples disclosed herein is shown. The timing diagram 400 may be a timing instance of the timing diagram 300 and may illustrate various operations 410 performed on a die 405 in a memory system (e.g., memory system 110 or 210) and corresponding start times 415, end times 420, and durations 425. The die 405 may be an instance of die 305, die 225, or die 160 or a combination thereof. Two dies D0 (die 405-a) and D1 (die 405-b) are depicted; however, any number of dies is possible. The operations 410, start times 415 (e.g., respective start times 415-a and 415-b of die 405-a and 405-b), end times 420 (e.g., respective end times 420-a and 420-b of die 405-a and 405-b), and durations 425 (e.g., respective durations 425-a and 425-b of die 405-a and 405-b) are included as non-limiting examples; the memory system may perform various operations corresponding to various start times, end times, and durations different from those described in Figure 4 . In some examples, the operations 410 of die 405 may be sub-operations of a folding operation (e.g., folding operation 245) and a write operation (e.g., write operation 250, write operation 325). In some examples, the operations 410 may have start times 415 and end times 420 that do not correspond to the programming duration 310.

[0071] The memory system may perform various operations 410-a on die 405-a. For example, at a start time of 0 μs, the memory system may perform TLC transfer for 210 μs. At time 210 μs, the memory system may perform a TLC programming operation that lasts for 933 μs. The TLC programming operation may correspond to at least a portion of the write operation 325. In some examples, a QLC programming operation that is part of a folding operation may be paused or delayed to perform the TLC programming operation. At time 1143 μs, the memory system may perform TLC read for a duration of 140 μs to, for example, verify that the TLC programming operation was successful. At time 1283 μs, the memory system may transfer data out of a buffer (e.g., cache, volatile memory of the memory system controller) of the memory system for a duration of 280 μs. At time 1563 μs, the memory system may transfer data into the buffer for a duration of 280 μs.

[0072] At time 1843 μs, the memory system may perform at least a portion (e.g., the first or second programming pass, a portion of the first or second programming pass) of the QLC programming operation for a duration of 2404 μs. At time 4247 μs, the memory system may perform a QLC read for a duration of 77 μs to, for example, verify that the QLC programming operation was successful. The QLC programming operation may correspond to at least a portion of programming operation 320. At time 4324 μs, the memory system may transfer data out of the buffer for a duration of 280 μs. At time 4604 μs, the memory system may perform a TLC read for a duration of 140 μs. At time 4744 μs, the memory system may transfer data out of the buffer for a duration of 280 μs. At time 5024 μs, the memory system may transfer data into the buffer for a duration of 280 μs. At time 5304 μs, the memory system may perform at least a portion (e.g., the second programming pass, the second portion of the first programming pass) of a second QLC programming operation for a duration of 2404 μs. In some instances, the second QLC programming operation may perform the programming operation during a duration in which die 405-a is dedicated to performing it. At time 7708 μs, the memory system may perform a QLC read for a duration of 77 μs.

[0073] The memory system can perform various operations 410-b on die 405-b. For example, at start time 0 μs, the memory system can perform TLC read for 140 μs. At time 140 μs, the memory system can transfer data out of the buffer, where the transfer duration is 280 μs. At time 420 μs, the memory system can transfer data into the buffer within a duration of 280 μs. At time 700 μs, the memory system can perform a QLC programming operation for a duration of 2404 μs. At time 3104 μs, the memory system can perform QLC read for a duration of 77 μs to verify, for example, that the QLC programming operation was successful. The QLC programming operation can correspond to at least a portion of programming operation 320. At time 3181 μs, the memory system can transfer data out of the buffer within a duration of 280 μs. At time 3461 μs, the memory system can perform TLC read for a duration of 140 μs. At time 3601 μs, the memory system can transfer data out of the buffer within a duration of 280 μs. At time 3881 μs, the memory system can transfer data into the buffer within a duration of 280 μs. At time 4161 μs, the memory system can perform a second QLC programming operation for a duration of 2404 μs. At time 6565 μs, the memory system can perform a second QLC read for a duration of 77 μs to verify that the second QLC programming operation was successful. At 6642 μs, the memory system can transfer data out of the buffer within a duration of 280 μs. At time 6922 μs, the memory system can perform TLC transfer for a duration of 210 μs. At time 7132 μs, the memory system can perform a TLC programming operation on die 405-b for a duration of 933 μs.

[0074] Two dies 405 can perform QLC programming operations simultaneously (e.g., the first QLC TPROG corresponding to die 405-a overlaps in time with the first QLC TPROG corresponding to die 405-b). One die 405 can perform a write operation (e.g., a TLC programming operation), while the other die 405 can perform a QLC programming operation (e.g., the TLC TPROG corresponding to die 405-a overlaps in time with the first QLC TPROG corresponding to die 405-b, and the TLC TPROG corresponding to die 405-b overlaps in time with the second QLC TPROG corresponding to die 405-a). In some instances, the memory system can alternate which dies 405 perform TLC programming operations. In some instances, the memory system can track the respective states of the various operations 410 on the dies 405. This tracking can enable the memory system to switch between performing different operations 410 (e.g., pausing and resuming the various operations 410). In some instances, the two dies 405 can remain occupied (e.g., no die 405 consumes idle time).

[0075] Figure 5 FIG. 500 is a block diagram showing a memory system 520 that supports parallel folding and host write handling in accordance with an example disclosed herein. The memory system 520 can be an example of aspects of the memory system described in reference Figures 1 to 4 described. The memory system 520 or its various components can be examples of components for performing various aspects of parallel folding and host write handling, as described herein. For example, the memory system 520 can include a folding component 525, a command component 530, a write component 535, a status component 540, or any combination thereof. Each of these components can communicate directly or indirectly with each other (e.g., via one or more buses).

[0076] The folding component 525 can be configured to or otherwise support components for performing a first programming operation at a first die of a memory system (e.g., memory system 520) during a duration as part of transferring first data from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation. The command component 530 can be configured to or otherwise support components for receiving, during the duration, a command from a host system to write second data to the memory system. The write component 535 and the folding component 525 can be configured to or otherwise support components for performing, during the duration and at least in part based on the command, a write operation of writing the second data to a second die of the memory system (e.g., by the write component 535) and at least a portion of a second programming operation as part of transferring third data from a source data block of the second die to a destination data block of the second die (e.g., by the folding component 525).

[0077] In some instances, to support at least part of the execution of the second programming operation, the folding component 525 may be configured to or otherwise support a component for initiating a second programming operation for programming second data into a destination data block of the second die before receiving a command. In some instances, to support at least part of the execution of the second programming operation, the folding component 525 may be configured to or otherwise support a component for pausing the second programming operation at least in part based on initiating a write operation in response to receiving a command. In some instances, to support at least part of the execution of the second programming operation, the folding component 525 may be configured to or otherwise support a component for resuming the second programming operation after the write operation is executed.

[0078] In some instances, to support the execution of the write operation, the write component 535 may be configured to or otherwise support a component for performing the write operation while the second programming operation is paused.

[0079] In some instances, the status component 540 may be configured to or otherwise support a component for tracking the status of the second programming operation, wherein the second programming operation is resumed at least in part based on the tracked status.

[0080] In some instances, the second programming operation is paused and the write operation is performed at least in part based on the volatile memory device of the memory system from which the second data is written being full.

[0081] In some instances, the folding component 525 may be configured to or otherwise support a component for performing a third programming operation at the second die during a second duration after a duration as part of a transfer of fourth data from a source data block of the second die to a destination data block of the second die, the second duration including a second time period for performing the third programming operation. In some instances, the command component 530 may be configured to or otherwise support a component for receiving a second command to write fifth data to the memory system from the host system during the second duration. In some instances, the folding component 525 and the write component 535 may be configured to or otherwise support a component for performing a second write operation of writing the fifth data to the first die (e.g., via the write component 535) and at least a part of a fourth programming operation during the second duration and at least in part based on the second command as part of a transfer of sixth data from a source data block of the first die to a destination data block of the first die (e.g., via the folding component 525).

[0082] In some instances, the third programming operation as part of the transfer of the fourth data corresponds to a second programming pass of the transfer of the third data. In some instances, the fourth programming operation as part of the transfer of the sixth data corresponds to a second programming pass of the transfer of the first data.

[0083] In some instances, to support at least part of the execution of a second programming operation, the folding component 525 may be configured to or otherwise support a component for initiating the second programming operation during a duration. In some instances, to support at least part of the execution of a second programming operation, the command component 530 may be configured to or otherwise support a component for determining whether a command has been received within one or more time intervals during a duration. In some instances, to support at least part of the execution of a second programming operation, the folding component 525 may be configured to or otherwise support a component for pausing the second programming operation based at least in part on determining that a command has been received within a time interval of one or more time intervals.

[0084] In some instances, the command component 530 may be configured to or otherwise support a component for receiving, from a host system, a second command to write fourth data to the memory system during a duration. In some instances, the write component 535 may be configured to or otherwise support a component for performing a second write operation to write the fourth data to a second die during a duration based at least in part on temporarily pausing the second programming operation in response to the second command.

[0085] In some instances, to support at least part of the execution of a second programming operation, the folding component 525 may be configured to or otherwise support a component for writing third data from a source data block of the second die to one or more latches of the memory system. In some instances, to support the execution of a write operation, the write component 535 may be configured to or otherwise support a component for overwriting one or more latches with second data based at least in part on receiving a command after the third data is written to the one or more latches.

[0086] In some instances, to support at least part of the execution of a second programming operation, the folding component 525 may be configured to or otherwise support a component for rewriting the third data from the source data block of the second die to one or more latches based at least in part on the overwriting after the write operation is performed. In some instances, to support at least part of the execution of a second programming operation, the folding component 525 may be configured to or otherwise support a component for initiating programming the third data from the one or more latches to a destination data block of the second die.

[0087] In some instances, the command is received before the start time of the duration.

[0088] In some instances, the command is received after the start time of the duration and during the duration.

[0089] In some instances, the destination data block of the first die and the destination data block of the second die include QLC. In some instances, the second data is written to SLC, MLC, or TLC of the second die.

[0090] In some instances, a second duration for performing a write operation is less than the duration.

[0091] Figure 6 FIG. shows a flow chart illustrating a method 600 that supports parallel folding and host write handling according to the examples disclosed herein. The operations of method 600 may be implemented by the memory system or components thereof described herein. For example, the operations of method 600 may be performed by the memory system referenced Figures 1 to 5 described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0092] At 605, the method may include performing a first programming operation at a first die of the memory system during a duration as part of transferring first data from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation. Operation 605 may be performed according to the examples disclosed herein. In some instances, aspects of operation 605 may be performed by the folding component 525 referenced Figure 5 described.

[0093] At 610, the method may include receiving, during the duration, from a host system a command to write second data to the memory system. Operation 610 may be performed according to the examples disclosed herein. In some instances, aspects of operation 610 may be performed by the command component 530 referenced Figure 5 described.

[0094] At 615, the method may include performing, during the duration and at least in part based on the command, a write operation and at least a portion of a second programming operation to write the second data to a second die of the memory system as part of transferring third data from a source data block of the second die to a destination data block of the second die. Operation 615 may be performed according to the examples disclosed herein. In some instances, aspects of operation 615 may be performed by the write component 535 and the folding component 525 referenced Figure 5 described.

[0095] In some instances, the devices described herein may execute one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure or any combination thereof:

[0096] Aspect 1: A method, apparatus, or non-transitory computer-readable medium that includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: performing a first programming operation at a first die of a memory system during a duration as part of first data being transferred from a source data block of the first die to a destination data block of the first die, the duration including a length of time for performing the first programming operation; receiving, during the duration, a command from a host system to write second data to the memory system; and performing, during the duration and at least in part based on the command, a write operation and at least a portion of a second programming operation to write the second data to a second die of the memory system as part of third data being transferred from a source data block of the second die to a destination data block of the second die.

[0097] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein performing at least the portion of the second programming operation includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: initiating the second programming operation to program the second data to the destination data block of the second die before receiving the command; pausing the second programming operation at least in part based on initiating the write operation in response to receiving the command; and resuming the second programming operation after the write operation is performed.

[0098] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, wherein performing the write operation includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: performing the write operation while the second programming operation is paused.

[0099] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 3, further including operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: tracking a state of the second programming operation, wherein the second programming operation is resumed at least in part based on tracking the state.

[0100] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 4, wherein the second programming operation is paused and the write operation is performed at least in part based on a volatile memory device of the memory system from which the second data is written being full.

[0101] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: performing a third programming operation at the second die during a second duration after the duration as part of transfer of fourth data from a source data block of the second die to a destination data block of the second die, the second duration including a second time period for performing the third programming operation; receiving, during the second duration, from the host system a second command to write fifth data to the memory system; and performing, during the second duration and at least in part based on the second command, at least a portion of a second write operation and a fourth programming operation to write the fifth data to the first die as part of transfer of sixth data from a source data block of the first die to a destination data block of the first die.

[0102] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to Aspect 6, wherein the third programming operation as part of the transfer of the fourth data corresponds to a second programming pass of the transfer of the third data, and the fourth programming operation as part of the transfer of the sixth data corresponds to a second programming pass of the transfer of the first data.

[0103] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein performing at least the portion of the second programming operation comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: initiating the second programming operation during the duration; determining, at one or more time intervals during the duration, whether the command has been received; and pausing the second programming operation at least in part based on determining that the command has been received at a time interval among the one or more time intervals.

[0104] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving, during the duration, from the host system a second command to write fourth data to the memory system; and performing, during the duration, a second write operation to write the fourth data to the second die at least in part based on temporarily pausing the second programming operation in response to the second command.

[0105] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein performing at least the portion of the second programming operation includes operations, features, circuitry, logic, components, or instructions for the following or any combination thereof: writing the third data from the source data block of the second die to one or more latches of the memory system, wherein performing the write operation includes overwriting the one or more latches with the second data at least in part based on receiving the command after the third data is written to the one or more latches.

[0106] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to aspect 10, wherein performing at least the portion of the second programming operation includes operations, features, circuitry, logic, components, or instructions for the following or any combination thereof: rewriting the third data from the source data block of the second die to the one or more latches at least in part based on the overwriting after the write operation is performed; and initiating programming of the third data from the one or more latches to the destination data block of the second die.

[0107] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the command is received before the start time of the duration.

[0108] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the command is received after the start time of the duration and during the duration.

[0109] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 13, wherein the destination data block of the first die and the destination data block of the second die include QLC, and the second data is written to SLC, MLC, or TLC of the second die.

[0110] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 14, wherein a second duration for performing the write operation is less than the duration.

[0111] It should be noted that the described techniques include possible embodiments, and the operations and steps may be rearranged or otherwise modified and other embodiments are possible. Additionally, portions from two or more of the methods may be combined.

[0112] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0113] The terms "electronically communicate", "electrically contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or electrically contacting or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or electrically contacting or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0114] The term "coupled" (e.g., "electrically coupled") may refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently pass between the components through a conductive path) to a closed-circuit relationship between the components (where signals can pass between the components through a conductive path). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0115] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, if a switch located between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components through a conductive path that previously allowed signal flow.

[0116] The terms "if", "when", "based on", or "at least partially based on" may be used interchangeably. In some instances, the terms may be interchangeable if the terms "if", "when", "based on", or "at least partially based on" are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0117] The term "responsive to" can refer to a condition or action occurring at least in part (if not entirely) as a result of a previous condition or action. For example, a first condition or action can be performed and a second condition or action can occur at least in part as a result of the previous condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0118] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0119] The switching components or transistors discussed herein can represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive materials such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0120] The descriptions presented herein describe example configurations in conjunction with the accompanying drawings and do not represent all examples that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "better than other examples". "Detailed description" includes specific details for providing an understanding of the described technology. However, the technology can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0121] In the drawings, like components or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by following the reference numeral with a hyphen and a second numeral that differentiates the like components. If only the first reference numeral is used in the specification, the description applies to any of the like components having the same first reference numeral, regardless of the second reference numeral.

[0122] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0123] For example, the various illustrative blocks and components described herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0124] As used herein (including in the claims), the "or" in a list of items (e.g., a list that begins with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C, for example, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0125] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one location to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code in the form of instruction or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. By way of example, if software is transmitted using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disk, optical disk, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0126] The description provided herein enables a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory device; and a controller coupled to the memory device, wherein the controller is configured to cause the apparatus to: performing a first programming operation at a first die of the device as part of transferring first data from a source data block of the first die to a destination data block of the first die during a duration, the duration including a length of time for performing the first programming operation; receiving a command from a host system to write second data to the device during the duration; and A write operation to write the second data to a second die of the device and at least a portion of a second programming operation as part of transferring third data from a source data block of the second die to a destination data block of the second die is performed during the duration and based at least in part on the command.

2. The apparatus of claim 1 , wherein performing at least the portion of the second programming operation is configured to cause the apparatus to: initiating the second programming operation of programming the second data to the destination data block of the second die before receiving the command; suspending the second programming operation based at least in part on initiating the write operation in response to receiving the command; and The second programming operation is resumed after the writing operation is performed.

3. The apparatus of claim 2, wherein performing the write operation is configured to cause the apparatus to: The write operation is performed while the second program operation is suspended.

4. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: A status of the second programming operation is tracked, wherein the second programming operation is resumed based at least in part on tracking the status.

5. The apparatus of claim 2, wherein the second programming operation is suspended and the write operation is performed based at least in part on a volatile memory device of the apparatus from which the second data is written being full.

6. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: performing a third programming operation at the second die as part of transferring fourth data from the source block of data of the second die to the destination block of data of the second die during a second duration after the duration, the second duration including a second length of time for performing the third programming operation; receiving, from the host system during the second duration, a second command to write fifth data to the device; and A second write operation and at least a portion of a fourth programming operation that writes the fifth data to the first die as part of transferring sixth data from the source data block of the first die to the destination data block of the first die is performed during the second duration and based at least in part on the second command.

7. The apparatus of claim 6 , wherein the third programming operation as part of the transfer of the fourth data corresponds to a second programming pass of the transfer of the third data, and the fourth programming operation as part of the transfer of the sixth data corresponds to a second programming pass of the transfer of the first data.

8. The apparatus of claim 1 , wherein executing at least the portion of the second programming operation is configured to cause the apparatus to: initiating the second programming operation during the duration; determining whether the command has been received within one or more time intervals during the duration; and The second programming operation is suspended based at least in part on determining that the command has been received within a time interval in the one or more time intervals.

9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receiving a second command from the host system during the duration to write fourth data to the second die; and A second write operation of writing the fourth data to the device is performed during the duration based at least in part on temporarily suspending the second program operation in response to the second command.

10. The apparatus of claim 1, wherein performing at least the portion of the second programming operation is configured to cause the apparatus to: Writing the third data from the source data block of the second die to one or more latches of the device, wherein performing the write operation comprises: The one or more latches are overwritten with the second data based at least in part on receiving the command after the third data is written to the one or more latches.

11. The apparatus of claim 10, wherein performing at least the portion of the second programming operation is configured to cause the apparatus to: rewriting the third data from the source data block of the second die to the one or more latches based at least in part on the overwriting after the write operation is performed; and Programming of the third data from the one or more latches to the destination data block of the second die is initiated.

12. The apparatus of claim 1, wherein the command is received prior to a start time of the duration.

13. The apparatus of claim 1, wherein the command is received after a start time of the duration and during the duration.

14. The apparatus of claim 1, wherein: The destination data block of the first die and the destination data block of the second die include quad-level cells, and The second data is written to a single-level cell, a multi-level cell, or a triple-level cell of the second die.

15. The apparatus of claim 1, wherein a second duration for performing the write operation is less than the duration.

16. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: performing a first programming operation at a first die of a memory system as part of transferring first data from a source data block of the first die to a destination data block of the first die during a duration, the duration including a length of time for performing the first programming operation; receiving a command from a host system to write second data to the memory system during the duration; and During the duration and based at least in part on the command, a write operation to write the second data to a second die of the memory system and at least a portion of a second programming operation are performed as part of transferring third data from a source data block of the second die to a destination data block of the second die.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions for performing at least the portion of the second programming operation, when executed by the processor of the electronic device, further cause the electronic device to: initiating the second programming operation of programming the second data to the destination data block of the second die before receiving the command; suspending the second programming operation based at least in part on initiating the write operation in response to receiving the command; and The second programming operation is resumed after the writing operation is performed.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions for performing the write operation, when executed by the processor of the electronic device, further cause the electronic device to: The write operation is performed while the second program operation is suspended.

19. A method comprising: performing a first programming operation at a first die of a memory system as part of transferring first data from a source data block of the first die to a destination data block of the first die during a duration, the duration including a length of time for performing the first programming operation; receiving a command from a host system to write second data to the memory system during the duration; and During the duration and based at least in part on the command, a write operation to write the second data to a second die of the memory system and at least a portion of a second programming operation are performed as part of transferring third data from a source data block of the second die to a destination data block of the second die.

20. The method of claim 19, wherein performing at least the portion of the second programming operation comprises: initiating the second programming operation of programming the second data to the destination data block of the second die before receiving the command; suspending the second programming operation based at least in part on initiating the write operation in response to receiving the command; and The second programming operation is resumed after the writing operation is performed.

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