Memory device, operation method and memory system

Abstract

The embodiment of the invention discloses a memory device, an operation method and a memory system. The memory device includes a memory array including a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit coupled to the memory array and configured to: perform a first read operation including: applying a first read voltage to a first word line belonging to a first type among the plurality of word lines; and applying a first pass voltage to word lines other than the first word line in the plurality of word lines; performing a second read operation, the second read operation including: applying a second read voltage to a second word line belonging to a second type among the plurality of word lines; applying a second pass voltage to a word line adjacent to the second word line in the plurality of word lines; and applying the first pass voltage to word lines other than the second word line and word lines adjacent to the second word line among the plurality of word lines.

Description

Technical Field

[0001] This application relates to the technical field of memory, and particularly to a memory device, an operation method, and a memory system. Background Art

[0002] With the development of storage technology, three-dimensional (3D) memory devices have been widely used, such as in computers, tablets, and so on. In fact, to increase the storage density of 3D memory devices, the number of layers they contain is increasing. Such a design results in increasingly serious coupling interference between layers, which seriously affects the threshold voltage distribution of the memory device during programming, reduces the read window margin of the memory device, and seriously affects the read performance of the memory device. Summary of the Invention

[0003] In view of this, embodiments of this application provide a memory device, an operation method, and a memory system.

[0004] To achieve the above object, the technical solution of this application is implemented as follows:

[0005] In a first aspect, an embodiment of this application provides a memory device, including a memory array; the memory array includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and

[0006] a peripheral circuit, coupled to the memory array and configured to:

[0007] perform a first read operation, where the first read operation includes: applying a first read voltage to a first word line of a first type among the plurality of word lines; and applying a first pass voltage to word lines other than the first word line among the plurality of word lines;

[0008] perform a second read operation, where the second read operation includes: applying a second read voltage to a second word line of a second type among the plurality of word lines; applying a second pass voltage to word lines adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to word lines other than the second word line and the word lines adjacent to the second word line among the plurality of word lines; where the second pass voltage is determined according to the threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line.

[0009] In the above solution, the second word line of the second type is between two first word lines of the first type; before performing the first read operation and the second read operation, the peripheral circuit is further configured to:

[0010] perform a programming operation on the plurality of memory cells in a preset programming order;

[0011] Among them, the preset programming sequence includes: sequentially performing programming operations on the memory cells coupled to two first word lines belonging to the first type; and performing a programming operation on the memory cells coupled to the second word line belonging to the second type.

[0012] In the above solution, the programming operation is an incremental step pulse programming, wherein the step size of the incremental voltage corresponding to the programming pulse applied to the first word line belonging to the first type is the same as the step size of the incremental voltage corresponding to the programming pulse applied to the second word line of the second type.

[0013] In the above solution, the word lines adjacent to the second word line include two first word lines belonging to the first type; the peripheral circuit is further configured to:

[0014] Sequentially perform read operations on the memory cells coupled to the two first word lines belonging to the first type, and respectively obtain a first threshold voltage distribution and a second threshold voltage distribution;

[0015] Obtain an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution; and

[0016] Obtain the second pass voltage according to the adjustment voltage and the first pass voltage.

[0017] In the above solution, the memory cells coupled to the second word line are divided into N*N memory groups according to the first threshold voltage distribution and the second threshold voltage distribution; the peripheral circuit is further configured to:

[0018] Determine the adjustment voltage corresponding to each memory group according to a preset mapping relationship, or set the corresponding adjustment voltage for each memory group according to a preset rule.

[0019] In the above solution,

[0020] The first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; wherein, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-memory groups according to the plurality of second data states;

[0021] When the N first sub - storage groups include a first group and a second group, and the N second sub - storage groups include a third group and a fourth group, the N * N storage groups include a first storage group, a second storage group, a third storage group, and a fourth storage group, a total of 2 * 2 storage groups; wherein, the first storage group includes the first group and the third group; the second storage group includes the first group and the fourth group; the third storage group includes the second group and the third group; the fourth storage group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

[0022] In the above - mentioned solution, the adjustment voltage corresponding to the first storage group is less than the adjustment voltage corresponding to the second storage group;

[0023] The adjustment voltage corresponding to the second storage group is less than or equal to the adjustment voltage corresponding to the third storage group;

[0024] The adjustment voltage corresponding to the third storage group is less than the adjustment voltage corresponding to the fourth storage group.

[0025] In the above - mentioned solution, the peripheral circuit is further configured to:

[0026] Obtain a corresponding second passing voltage according to the adjustment voltage corresponding to each storage group and the first passing voltage;

[0027] And perform the second read operation multiple times. Wherein, in each second read operation, the same second read voltage is applied to the second word line; the word lines adjacent to the second word line are applied with second passing voltages corresponding to each adjustment voltage; and the other word lines are applied with the same first passing voltage.

[0028] In a second aspect, an embodiment of the present application further provides an operation method for a memory device. The memory device includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; the operation method includes:

[0029] Perform a first read operation, and the first read operation includes: applying a first read voltage to a first word line belonging to a first type among the plurality of word lines; and applying a first passing voltage to the word lines other than the first word line among the plurality of word lines;

[0030] Perform a second read operation, where the second read operation includes: applying a second read voltage to a second word line of the second type among the multiple word lines; applying a second pass voltage to a word line adjacent to the second word line among the multiple word lines; and applying the first pass voltage to word lines other than the second word line and the word line adjacent to the second word line among the multiple word lines; wherein, the second pass voltage is determined according to the threshold voltage distribution after the storage units coupled to the word line adjacent to the second word line are programmed.

[0031] In the above solution, the second word line of the second type is between two first word lines of the first type; before performing the first read operation and the second read operation; the operation method further includes:

[0032] Performing a programming operation on the multiple storage units according to a preset programming order;

[0033] Wherein, the preset programming order includes: sequentially performing programming operations on the storage units coupled to two first word lines of the first type; and performing a programming operation on the storage units coupled to the second word line of the second type.

[0034] In the above solution, the programming operation is an incremental step pulse programming, wherein the step size of the incremental voltage corresponding to the programming pulse applied to the first word line of the first type is the same as the step size of the incremental voltage corresponding to the programming pulse applied to the second word line of the second type.

[0035] In the above solution, the word lines adjacent to the second word line include two first word lines of the first type; the operation method further includes:

[0036] Sequentially performing read operations on the storage units coupled to two first word lines of the first type to respectively obtain a first threshold voltage distribution and a second threshold voltage distribution;

[0037] Obtaining an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution; and

[0038] Obtaining the second pass voltage according to the adjustment voltage and the first pass voltage.

[0039] In the above solution,

[0040] The obtaining of the adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution includes:

[0041] Dividing the storage units coupled to the second word line into N*N storage groups according to the first threshold voltage distribution and the second threshold voltage distribution;

[0042] Determine the adjustment voltage corresponding to each storage group according to a preset mapping relationship, or set the corresponding adjustment voltage for each storage group according to a preset rule.

[0043] In the above solution, the first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; wherein, the memory cells coupled to the second word line are divided into N first sub-storage groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-storage groups according to the plurality of second data states;

[0044] When the N first sub-storage groups include a first group and a second group, and the N second sub-storage groups include a third group and a fourth group, the N*N storage groups include a first storage group, a second storage state group, a third storage group, and a fourth storage group, a total of 2*2 storage groups; wherein, the first storage group includes the first group and the third group; the second storage group includes the first group and the fourth group; the third storage group includes the second group and the third group; the fourth storage group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group. In the above solution, the adjustment voltage corresponding to the first storage group is less than the adjustment voltage corresponding to the second storage group;

[0045] The adjustment voltage corresponding to the second storage group is less than or equal to the adjustment voltage corresponding to the third storage group; and

[0046] The adjustment voltage corresponding to the third storage group is less than the adjustment voltage corresponding to the fourth storage group.

[0047] In the above solution, obtaining the second passing voltage according to the adjustment voltage and the first passing voltage includes: obtaining the corresponding second passing voltage according to the adjustment voltage corresponding to each storage group and the first passing voltage.

[0048] In the above solution, the operation method further includes: sequentially performing the second read operation multiple times, wherein, in each second read operation, the same second read voltage is applied to the second word line; the second passing voltage corresponding to each adjustment voltage is applied to the word line adjacent to the second word line; the same first passing voltage is applied to other word lines.

[0049] In the above solution, the operation method further includes:

[0050] Obtain the third threshold voltage distribution corresponding to each second read operation;

[0051] Obtain a target threshold voltage distribution corresponding to the memory cells coupled to the second word line according to each third threshold voltage distribution,

[0052] wherein the target threshold voltage distribution is tighter than each third threshold voltage distribution.

[0053] In a third aspect, an embodiment of the present application further provides a memory system, including any one of the foregoing memory devices and a memory controller coupled to and controlling the memory device.

[0054] In the above solution, the memory system is included in a solid-state drive (SSD) or a memory card.

[0055] An embodiment of the present application provides a memory device, an operation method, and a memory system. The memory device includes: a memory array; the memory array includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit, coupled to the memory array and configured to: perform a first read operation, the first read operation including: applying a first read voltage to a first word line of a first type among the plurality of word lines; and applying a first pass voltage to word lines other than the first word line among the plurality of word lines; perform a second read operation, the second read operation including: applying a second read voltage to a second word line of a second type among the plurality of word lines; applying a second pass voltage to word lines adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to word lines other than the second word line and the word lines adjacent to the second word line among the plurality of word lines; wherein the second pass voltage is determined according to a threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line. In the memory device provided by the embodiment of the present application, in the read operation, a first read operation is performed on the memory cells coupled to the first word line of the first type, and a first pass voltage is applied to the remaining unselected word lines; when a second read operation is performed on the memory cells coupled to the first word line of the second type, a second pass voltage determined according to a threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line is applied to the word lines adjacent to the second word line; and the first pass voltage is still applied to the remaining unselected word lines, that is: the word lines included in the memory device are divided into two types, and when read operations are performed on the memory cells coupled to different types of word lines, different pass voltages are applied to the unselected word lines. In this way, the reading of the memory cells coupled to the word lines of the second type is corrected, and the influence of read interference is reduced, so that the memory cells can correctly read data. Description of the Drawings

[0056] In the accompanying drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0057] Figure 1 Schematic diagram of an exemplary system with a memory system provided for an embodiment of the present application;

[0058] Figure 2a Schematic diagram of an exemplary memory card with a memory system provided for an embodiment of the present application;

[0059] Figure 2b Schematic diagram of an exemplary solid-state drive with a memory system provided for an embodiment of the present application;

[0060] Figure 3 Schematic structural diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present application;

[0061] Figure 4 Schematic structural diagram of a memory string, word line, and bit line in a memory device provided for an embodiment of the present application;

[0062] Figure 5 Schematic cross-sectional view of a memory array including NAND-type memory strings provided for an embodiment of the present application;

[0063] Figure 6 Schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present application;

[0064] Figure 7 Schematic diagram of the threshold voltage distribution of a QLC-type storage cell and Esum provided for an embodiment of the present application;

[0065] Figure 8 Schematic structural diagram of a memory device provided for an embodiment of the present application;

[0066] Figure 9 Schematic diagram of a cyclic programming method provided for an embodiment of the present application;

[0067] Figure 10 Flow schematic of an operation method of a memory device provided for an embodiment of the present application Figure 1 ;

[0068] Figure 11 Flow schematic diagram two of an operation method of a memory device provided for an embodiment of the present application;

[0069] Figure 12Flow schematic of an operation method of a memory device provided by an embodiment of the present application Figure 3 。 Detailed implementation manners

[0070] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly understand the present application and to be able to fully convey the scope of the present application to those skilled in the art.

[0071] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some well-known technical features are not described: that is, not all features of the actual embodiments described here are described in detail, and the well-known functions and structures are not described in detail.

[0072] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", "coupled to", or "coupled with" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not mean that the present application necessarily has a first element, component, region, layer, or part.

[0074] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0075] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0076] In order to more fully understand the characteristics and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration purposes only and are not intended to limit the embodiments of the present application.

[0077] Figure 1 A block diagram showing an exemplary system having a memory system provided by an embodiment of the present application. In Figure 1 which, the system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. As Figure 1As shown, the system 100 may include a host 108 and a memory system 102. The host 108 may include a processor, such as a central processing unit (CPU) or a system on chip (SoC), where the system on chip may be, for example, an application processor (AP). The host 108 also includes at least one operating system (OS) that generally manages and controls the functions and operations executed in the host 108. The OS enables interoperability between the host 108 coupled to the memory system 102 and the user who needs and uses the memory system 102. The OS may support functions and operations corresponding to the user's requests. For example, but not limited to, depending on whether the host 108 is a removable host, the OS may be classified into a general operating system and a mobile operating system. The general operating system may include a personal operating system and an enterprise operating system. The personal operating system may be an operating system for general purposes, including Windows and Chrome, to support services. The enterprise operating system may be an operating system dedicated to ensuring and supporting high performance, including Windows Server, Linux, Unix, etc. The mobile operating system may refer to an operating system for mobility services or functions (such as a power-saving function). Generally, the mobile operating system may be an operating system such as Android, iOS, Windows Mobile, etc. In some embodiments, the host 108 may include multiple OSs; correspondingly, the host 108 may run multiple operating systems related to the memory system 102. In other embodiments, the host 108 converts the user's requests into one or more commands and transmits the one or more commands to the memory system 102 to cause the memory system 102 to perform operations related to the one or more commands.

[0078] Among them, the memory system 102 is capable of operating or performing specific functions in response to requests from the host 108 or performing various internal operations. In some embodiments, the memory system 102 is capable of storing data accessed by the host 108. The memory system 102 can be used as the main memory system or the auxiliary memory system of the host 108. The memory system 102 and the host 108 may be electrically connected and communicate according to corresponding protocols.

[0079] Return as Figure 1As shown, the memory system 102 may include one or more memory devices 104 and a memory controller 106. The memory controller 106 may respond to requests from the host 108 and then control the memory devices 104. For example, the memory controller 106 may read data from the memory devices 104 and transfer the read data to the host 108; it may also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. That is, the memory controller 106 can control write (or programming), read, erase, and background operations of the memory devices 104, etc. And the memory system 102 may be implemented and encapsulated in different types of terminal electronic products. Exemplarily, as Figure 2a shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Secure Digital (SD) card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (UFS) device, a Multimedia Card (MMC), an Embedded MMC (eMMC), a Reduced Size MMC (RSMMC), a micro MMC, a Universal Serial Bus (USB) storage device, and a Memory Stick, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 1 the host 108 in Figure 2b ). In another example as shown in Figure 1 , the memory controller 106 and multiple memory devices 104 may be integrated into a Solid State Drive (SSD) 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., Figure 1 the host 108 in

[0080] In some embodiments, the memory system 102 may also be configured to be part of, for example, one of the following devices: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0081] Return Figure 1 As shown, the memory device 104 may include non-volatile memory, which can retain the data stored therein even without power supply. The memory device 104 may also include volatile storage memory. The device 104 may store the data provided from the host 108 through a write operation; the memory device 104 may also provide the stored data to the host 108 through a read operation. In the embodiments of the present application, the memory device 104 may include any memory disclosed, such as volatile memory devices of dynamic random access memory (DRAM) and static RAM (SRAM), or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory (such as three-dimensional NAND flash memory).

[0082] Figure 3 A schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit is shown according to some aspects of the present application. The memory device 300 may be Figure 1An example of the memory device 104. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. Taking the memory array 301 as a three-dimensional NAND-type memory array as an example for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, and each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0083] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states (or data states) and thus can store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a double-level cell (DLC) capable of storing more than one bit of data in four memory states. For example, a DLC can store two bits per memory cell, three bits per memory cell (also known as a trinary-level cell (TLC)), four bits per cell (also known as a quad-level cell (QLC)), or five bits per cell (also known as a penta-level cell (PLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each DLC stores two bits of data, the DLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value can be used for the erased state. That is, the multiple memory states included in the memory cell include an erased state (or erasure state) or multiple programming states (or programming states), and the voltage values included in the voltage range (i.e., the threshold voltage Vt distribution) corresponding to the memory cells in the erased state are less than the threshold voltage distributions corresponding to the memory cells in other programming states.

[0084] As Figure 3As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source extreme and a top select gate (TSG) 312 at its drain extreme. The BSG 310 and the TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a respective bit line (BL) 316, and data may be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG 310 via one or more BSG lines 315.

[0085] As Figure 3 shown, the NAND memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all of the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations.

[0086] Reference Figure 3 and Figure 4, each of the multiple memory cells in the memory cell 306 is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding selection transistor (such as the upper selection transistor (TSG) 312).

[0087] Specifically, referring to Figure 4 , the memory device may include one or more memory strings 308 (refer to Figure 4 as shown by the arrow in), each memory string may include an upper selection transistor SST corresponding to the upper selection transistor gate line SSL, a ground selection transistor GST corresponding to the lower selection transistor gate line GSL, and a plurality of memory cells located between the upper selection transistor and the ground selection transistor. Each memory string is respectively connected to a corresponding bit line BL and a unified common source line. The word line coupled to the selected memory cell is the selected word line (Sel.WL), and the selected word line may be any one of the multiple word lines in the memory device, and the other word lines are unselected word lines (Usel.WL) or dummy word lines (Dummy WL).

[0088] Figure 5 A cross-sectional schematic diagram of an exemplary memory array 301 including a NAND memory string 308 according to some aspects of the present application is shown. As Figure 5 shown, the NAND memory string 308 may include a stacked structure 510, and the stacked structure 510 includes a plurality of gate layers 511 and a plurality of insulating layers 512 that are alternately stacked in sequence, and the memory string 308 vertically penetrates the gate layers 511 and the insulating layers 512. The gate layer 511 and the insulating layer 512 may be alternately stacked, and adjacent two gate layers 511 are separated by one insulating layer 512. The number of pairs of the gate layer 511 and the insulating layer 512 in the stacked structure 510 can determine the number of memory cells included in the memory array 301.

[0089] The constituent material of the gate layer 511 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding the memory cell. The gate layer 511 at the top of the stacked structure 510 may extend horizontally as the upper selection gate line 513, and the gate layer 511 at the bottom of the stacked structure 510 may extend horizontally as the lower selection gate line 514, and the gate layer 511 that extends horizontally between the upper selection gate line and the lower selection gate line may be used as the word line layer 503.

[0090] In some embodiments, the stack structure 510 may be disposed on the substrate 501. The substrate 501 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0091] In some embodiments, the NAND memory string 308 includes a channel structure that extends vertically through the stack structure 510. In some embodiments, the channel structure includes channel holes filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0092] Return reference Figure 3 , the peripheral circuit 302 can be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory array 301 by applying voltage signals and / or current signals to each target storage cell 306 and sensing voltage signals and / or current signals from each target storage cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuits not shown in Figure 6 may also be included.

[0093] The page buffer / sense amplifier 604 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 can store program data (write data) for a page to be programmed to the memory array 301. In another example, the page buffer / sense amplifier 604 can perform a program verification operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 604 can also sense low-power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 606 can be configured to be controlled by the control logic 612 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 610.

[0094] The row decoder / word line driver 608 can be configured to be controlled by the control logic 612 and select / deselect the memory blocks 304 of the memory array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 608 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive the BSG line 315 and the TSG line 313. The row decoder / word line driver 608 can be configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 610 can be configured to be controlled by the control logic 612 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, channel boost voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0095] The control logic 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 614 can be coupled to the control logic 612 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 616 can be coupled to the control logic 612 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 612, and buffer status information received from the control logic 612 and relay it to the host. The interface 616 can also be coupled to the column decoder / bit line driver 606 via the data bus 618 and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory array 301.

[0096] For the storage system and memory described above, the read window margin (RWM) is an important parameter for correctly reading the data of the storage cells. In some embodiments, for a storage cell configured to correspond to multiple data states, the RWM thereof includes multiple readable distributions, and the sum of these multiple readable distributions can be referred to as the edge summary (Esum). Among them, each readable distribution Ei can be a voltage range capable of being used to read the data on a storage cell in a certain data state. Wherein, i is an integer greater than or equal to 0.

[0097] For example, as Figure 7 shown, which shows a schematic diagram of Esum in a QLC type storage cell. In Figure 7 , for a QLC type storage cell, the total readable distributions can include: a total of 30 readable distributions E0, E1,..., E29, which can be denoted as: Esum = E0 + E1 +... + E29. Among them, E0 is the first readable distribution, which is the voltage range between the lower tail of the threshold voltage distribution corresponding to the data state P0 and the voltage Vr1 (read voltage), and it is the voltage range capable of being used to read the data on a storage cell in the erased state. E1 is the second readable distribution, which is the voltage region for reading the data on a storage cell in the P1 state, and it is the voltage range between the minimum voltage value of the threshold voltage distribution corresponding to the data state P0 and the voltage Vr1 (read voltage). For the understanding of other readable distributions, it can be inferred by analogy.

[0098] In the actual application process, when performing a read operation on a memory device, if one wants to correctly read the data of a memory cell, an RWM (i.e., Esum) with sufficient width is required. There are many factors affecting the RWM. Among these factors, as the number of layers of the memory device gradually increases, the distance between layers (i.e., between word lines) decreases, resulting in a relatively serious impact of the coupling between word lines on the RWM.

[0099] To solve one or more of the above technical problems, an embodiment of the present application provides a memory device. During a read operation, different read strategies are adopted for memory cells coupled to different types of word lines. Specifically, when reading a memory cell coupled to a first word line of a first type, a first read voltage is applied to the first word line; a first pass voltage is applied to other word lines; when reading a memory cell coupled to a second word line of a second type, a second read voltage is applied to the second word line, and a second pass voltage determined according to the threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line is applied to the word lines adjacent to the second word line, and the first pass voltage is applied to the remaining word lines. That is, the reading of the memory cells coupled to the word lines of the second type is corrected to reduce the influence of read interference so that the memory cells can correctly read data.

[0100] Specifically, as Figure 8 shown, an embodiment of the present application provides a memory device 800, including:

[0101] A memory array 801; the memory array includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and

[0102] A peripheral circuit 802, coupled to the memory array 801 and configured to:

[0103] Perform a first read operation, the first read operation including: applying a first read voltage to a first word line of a first type among the plurality of word lines; and applying a first pass voltage to the word lines other than the first word line among the plurality of word lines;

[0104] Perform a second read operation, the second read operation including: applying a second read voltage to a second word line of a second type among the plurality of word lines; applying a second pass voltage to the word lines adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to the word lines other than the second word line and the word lines adjacent to the second word line among the plurality of word lines; wherein, the second pass voltage is determined according to the threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line.

[0105] It should be noted that the memory device 800 includes a memory array 801 and a peripheral circuit 802. Among them, the structure of the memory array 801 can be referred to the one described Figure 3 and Figure 4 previously. The peripheral circuit 802 may include the circuit described as Figure 6 . The connection relationship between the multiple memory cells and the multiple word lines coupled to the multiple memory cells can be referred to the descriptions of Figure 3 and Figure 4 . In the embodiment of the present application, the memory device 800 is taken as an example of a 3D NAND flash memory. That is, when there is no special description below, the memory device mentioned is the 3D NAND flash memory.

[0106] Based on the foregoing description, the reading scheme adopted by the memory device in the embodiment of the present application includes:

[0107] Applying a first read voltage to the first word line of the first type; applying a first pass voltage to the other word lines except the first word line to perform a first read operation on the memory cells coupled to the first word line of the first type;

[0108] Applying a second read voltage to the second word line of the second type; applying a second pass voltage determined according to the threshold voltage after programming of the memory cells coupled to the word lines adjacent to the second word line to the word lines adjacent to the second word line; applying a first pass voltage to the other word lines except the second word line and the word lines adjacent to the second word line to perform a second read operation on the memory cells coupled to the second word line of the second type.

[0109] That is, when performing a read operation on the memory device, the multiple word lines are divided into two types. When performing a read operation on the memory cells coupled to different types of word lines, the pass voltages applied to the unselected word lines are different. Specifically, when performing a first read operation on the memory cells coupled to the first word line of the first type, applying a first read voltage to the first word line; applying a first pass voltage to the other word lines in the multiple word lines (word lines other than the first word line); while when performing a second read operation on the memory cells coupled to the second word line of the second type, applying a second read voltage to the second word line; applying a second pass voltage determined according to the threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line to the word lines adjacent to the second word line; applying a first pass voltage to the other word lines in the multiple word lines (word lines other than the word lines adjacent to the second word line and the second word line).

[0110] Here, the descriptions of the first type and the second type are only for distinguishing different types of word lines among multiple word lines, and are not limitations on quantity or order. The descriptions of the first read voltage and the second read voltage are only for distinguishing the read voltages applied to the selected word lines (such as the first word line corresponding to the first read operation; the second word line corresponding to the second read operation) in the first read operation and the second read operation, and are not limitations on quantity. Similarly, the first pass voltage and the second pass voltage can be understood in the same way.

[0111] Moreover, according to the following description, the second pass voltage is obtained by adding an adjustment voltage determined based on the threshold voltage distribution after programming the memory cells coupled to the word lines adjacent to the second word line on the basis of the first pass voltage. That is, the same first pass voltage is applied to the unselected word lines in the first read operation; while in the second read operation, the first pass voltage and the second pass voltage (the second pass voltage is applied to the word lines adjacent to the selected second word line) are applied to the unselected word lines, and the second pass voltage is adjusted on the basis of the first pass voltage. In fact, it is equivalent to that the first read operation is a normal read operation, while the second read operation is a read operation modified by the pass voltage. In this way, by only correcting the read operation performed on the memory cells coupled to some word lines, time can be saved and a tighter threshold voltage distribution can be obtained.

[0112] In 3D NAND flash memory, as the number of layers increases, the coupling interference between word lines is inevitable and is one of the main reasons affecting the threshold voltage distribution of memory cells. Moreover, when programming the above-mentioned multiple memory cells in the forward order (programming from the source line of the memory string to the bit line direction) or the reverse order (programming from the bit line of the memory string to the source line direction), the word line corresponding to the programmed memory cell will cause coupling interference to the word line corresponding to the unprogrammed memory cell, resulting in the broadening of the threshold voltage distribution of the memory cell during reading, thereby reducing the RWM. In the programming situation described above, in order to ensure sufficient RWM, it is necessary to correct the reading operation of the memory cells coupled to each word line to obtain correct read data. However, the correction takes a relatively long time, increasing the reading time and seriously affecting the read / write performance of the memory device. Based on this, the embodiment of the present application adopts a cyclic programming method. During programming, only the second word lines of the second type are affected by the coupling interference of adjacent word lines, and the first word lines of the first type are not affected by the coupling interference of adjacent word lines. Therefore, during the execution of the reading operation, only the memory cells coupled to the second word lines of the second type affected by the coupling interference need to adjust their pass voltages. One implementation manner is as described above. When reading the memory cells coupled to the second word line (i.e., performing the second reading operation), the pass voltage is adjusted. After the adjustment, the threshold voltage distribution of the memory cells coupled to the second word line becomes tighter, that is, the threshold voltage distribution of the memory cells coupled to the second word line has a wider RWM.

[0113] Specifically, for the understanding of the cyclic programming described above, the following description can be referred to: The second word lines of the second type are between two first word lines of the first type; before performing the first reading operation and the second reading operation, the peripheral circuit can also be configured to:

[0114] Perform a programming operation on the multiple memory cells according to a preset programming order;

[0115] Wherein, the preset programming order includes: sequentially performing programming operations on the memory cells coupled to two first word lines of the first type; and performing a programming operation on the memory cells coupled to the second word lines of the second type.

[0116] Here, the so-called preset programming order can be, for example Figure 3 and Figure 4The memory cells on the memory string 308 in the memory array shown are cyclically programmed in the order starting from the memory cells close to the source line SL to the memory cells close to the bit line BL, or in the order starting from the memory cells close to the bit line BL to the memory cells close to the source line SL. Specifically, the preset programming order includes: first, performing programming operations on the memory cells coupled to two first word lines of the first type in sequence; then, performing a programming operation on the memory cells coupled to the second word line of the second type. The second word line of the second type is between the two first word lines of the first type. According to such a cyclic programming method and based on the foregoing description, the word line corresponding to the later-programmed memory cell will be subject to the coupling interference of the word line corresponding to the previously-programmed memory cell, which affects the broadening of its threshold voltage distribution, resulting in a loss of Esum of the threshold voltage distribution. Then, in the cyclic programming method provided by the embodiments of the present application, only the second word line of the second type is subject to the coupling interference caused by the programming of the two first word lines of the first type, and the two first word lines of the first type are not affected by the coupling interference between word lines.

[0117] Based on this, in the memory device programmed according to such a cyclic programming method, the word lines included therein are divided into two types, that is, the first word lines of the first type and the second word lines of the second type. Further, during the read operation, only the reading of the memory cells coupled to the second word lines of the second type is corrected, and the memory cells coupled to the first word lines of the first type can be read normally.

[0118] It should be noted that the preset programming order described in the embodiments of the present application is described according to the programming results. The order in which the memory cells coupled to the two first word lines of the first type complete programming is earlier than the order in which the memory cells coupled to the second word line of the second type complete programming. In other words, the memory cells coupled to the two first word lines of the first type complete programming first, and the memory cells coupled to the second word line of the second type complete programming later. However, during the programming process, the programming of the memory cells coupled to the two first word lines of the first type and the programming of the memory cells coupled to the second word line of the second type are not strictly adjacent.

[0119] Specifically, as Figure 9 shown, it shows a schematic diagram of the cyclic programming provided by the embodiments of the present application. In Figure 9Among them, each square represents a word line WL, and the numbers of the word lines WL are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, ……, 17, …… respectively. Assume that programming starts from word line WL0, and its preset programming sequence can be successively: 0—2—1—4—3—6, etc. Among them, if two first word lines belonging to the first type are WL0 and WL2 respectively, and the second word line belonging to the second type is WL1, at this time, the programming of the three is adjacent. And when two first word lines belonging to the first type are WL2 and WL4 respectively, and the second word line belonging to the second type is WL3, at this time, the programming of the three is not adjacent. Instead, after programming the memory cell coupled to WL2 belonging to the first word line, then the second word line WL1 belonging to the second type is programmed, and then, the memory cell coupled to the first word line WL4 belonging to the first type is programmed, and finally the memory cell coupled to the second word line WL3 belonging to the second type is programmed. Based on this cyclic programming, word lines such as WL1, WL3, WL5, …… are subject to coupling interference from adjacent word lines on both sides, while word lines such as WL0, WL2, WL4, …… are not subject to coupling interference from adjacent word lines. In some embodiments, as Figure 9 shown, word lines numbered 0, 2, 4, 6, …… can be called odd word lines; word lines numbered 1, 3, 5, …… can be called even word lines.

[0120] In the actual application process, regardless of the programming sequence, as long as finally there are formed first word lines of the first type that are not subject to coupling interference; and second word lines of the second type that are subject to coupling interference from adjacent word lines, it is acceptable. For example, in Figure 9 the word line structure shown, programming can also start from a word line with a relatively large number, and be carried out in the order described above Figure 9 ; and for another example, in Figure 9 the word line structure shown, programming can also start from the word line numbered 1, and its sequence can include 1—0—3—2—5—4, etc. In this programming sequence, word line WL0 has only one adjacent word line, and it is only subject to the coupling interference of one adjacent word line. That is to say, in this programming sequence, the edge word lines have only one adjacent word line, and they may only be subject to the coupling interference of one word line. When reading and correcting, they can be processed separately, and the remaining word lines subject to coupling interference are still subject to the coupling interference from two adjacent word lines. It should be noted that the above coding of the word lines does not limit their specific positions in the memory string 308. In other words, as Figure 9Among the word lines shown, the word line WL0 can be the word line close to the bit line in the memory string, that is, the programming starts from the memory cell close to the bit line; the word line WL0 can also be the word line close to the source line in the memory string, that is, the programming starts from the memory cell close to the source line. No matter which direction the programming starts from, the programming logic is the same as the above-described cyclic programming method.

[0121] In some embodiments, the programming operation is incremental step pulse programming, wherein the step size of the incremental voltage corresponding to the programming pulse applied to the first word line of the first type is the same as the step size of the incremental voltage corresponding to the programming pulse applied to the second word line of the second type.

[0122] Here, the programming of multiple memory cells can be performed in a cyclic programming manner by using incremental step pulse programming (ISPP). Moreover, when the cyclic programming method described above is adopted in the embodiments of the present application, the step increments of the programming voltages corresponding to the odd word lines and the even word lines can be the same or different. The ISPP method with the same step increments of the programming voltages corresponding to the odd word lines and the even word lines is adopted in the embodiments of the present application to illustrate the inventive concept of the present application.

[0123] As described above, due to the cyclic programming method provided by the embodiments of the present application, the reading method of the memory device includes two types of reading, that is, the first reading operation and the second reading operation. In this reading method, the first reading operation can be regarded as a conventional reading operation, or a reading operation that does not require correction. The correct reading data can be obtained by using a given first pass voltage and a first reading voltage; the second reading operation can be regarded as a corrective read scheme, or a reading operation that requires correction. A second pass voltage needs to be obtained, and the correct reading data is obtained by using the first pass voltage, the second pass voltage, and the second reading voltage, and the threshold voltage distribution of the memory cell to be read is made denser, and the readable distribution included in the corresponding Esum is larger.

[0124] Before performing the second reading operation, in some embodiments, the word lines adjacent to the second word line include two first word lines of the first type; the peripheral circuit is further configured to:

[0125] Perform reading operations on the memory cells coupled to the two first word lines of the first type in sequence to obtain a first threshold voltage distribution and a second threshold voltage distribution respectively;

[0126] Obtain an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution;

[0127] Obtain the second passing voltage based on the adjusted voltage and the first passing voltage.

[0128] It should be noted that the steps for determining the second passing voltage are described here. Specifically, read operations are sequentially performed on the memory cells coupled to two first word lines of the first type adjacent to the second word line to obtain a first threshold voltage distribution and a second threshold voltage distribution respectively; then, an adjusted voltage relative to the first passing voltage is obtained based on the first threshold voltage distribution and the second threshold voltage distribution; then, the second passing voltage is obtained based on the adjusted voltage and the first passing voltage. That is, an adjustment amount is obtained based on the first threshold voltage distribution and the second threshold voltage distribution, and on the basis of the first passing voltage, an adjustment is made according to the adjustment amount to obtain the second passing voltage.

[0129] Among them, the memory cells coupled to the second word line are divided into N*N memory groups according to the first threshold voltage distribution and the second threshold voltage distribution; the peripheral circuit can also be configured to:

[0130] Determine the adjusted voltage corresponding to each memory group according to a preset mapping relationship, or set the adjusted voltage corresponding to each memory group according to a preset rule.

[0131] Here, the first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; among them, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-memory groups according to the plurality of second data states;

[0132] In the case where the N first sub-memory groups include a first group and a second group, and the N second sub-memory groups include a third group and a fourth group, the N*N memory groups include a first memory group, a second memory state group, a third memory group, and a fourth memory group, a total of 2*2 memory groups; among them, the first memory group includes the first group and the third group; the second memory group includes the first group and the fourth group; the third memory group includes the second group and the third group; the fourth memory group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

[0133] It should be noted that the multiple first data states and the multiple second data states are only descriptions for distinguishing the data states corresponding to the first threshold voltage distribution and the second threshold voltage distribution respectively. In the actual application process, the number of the multiple first data states is the same as the number of the multiple second data states. For example, the multiple first data states include 8 data states; at this time, the multiple second data states include 8 data states. Another example is that the multiple first data states include 16 data states; at this time, the multiple second data states include 16 data states.

[0134] In the actual application process, the memory cells coupled to the second word line are divided into N*N memory groups according to the multiple first data states and the multiple second data states. Specifically, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the multiple first data states; and the memory cells coupled to the second word line are divided into N second sub-memory groups according to the multiple second data states. In this case, N*N memory groups are formed by combining the N first sub-memory groups and the N second sub-memory groups.

[0135] After obtaining the N*N memory groups, various forms can be adopted to obtain the adjustment voltage corresponding to each memory group. An optional implementation method can be as follows: pre-store a preset mapping relationship, and this preset mapping relationship can include the correspondence between the memory group and the adjustment voltage; then, after obtaining the first threshold voltage distribution (corresponding to the multiple first data states) and the second threshold voltage distribution (corresponding to the multiple second data states), the memory cells coupled to the second word line are divided into N first sub-memory groups according to the multiple first data states; and the memory cells coupled to the second word line are divided into N second sub-memory groups according to the multiple second data states; and N*N memory groups are formed according to the N first sub-memory groups and the N second sub-memory groups; then, the adjustment voltage corresponding to each memory group is determined according to the preset mapping relationship. This method, that is: know in advance the relationship between the memory group and the adjustment voltage, and then, after obtaining the first threshold voltage distribution and the second threshold voltage distribution, divide the memory cells coupled to the second word line into N*N memory groups according to the pre-planned method, and then obtain the adjustment voltage corresponding to each memory group according to the mapping relationship.

[0136] Another optional implementation can be as follows: After obtaining the first threshold voltage distribution and the second threshold voltage distribution, the memory cells coupled to the second word line are divided into several groups in real time according to multiple first data states; the memory cells coupled to the second word line are divided into the same number of groups in real time according to multiple second data states. Finally, N*N memory groups are formed. Then, each memory group is assigned a value according to a preset rule. In this way, there is no need to store the mapping relationship, and the adjustment voltage is assigned in real time. Among them, the preset rule can be set according to the following principle: The larger N is, the closer the threshold voltage distribution of the memory cells coupled to the second word line obtained during the read operation is. And the larger the threshold voltages of the N first sub-memory groups included in each of the N*N memory groups are, the larger the corresponding adjustment voltage is; and the larger the threshold voltages of the N second sub-memory groups included in each of the N*N memory groups are, the larger the corresponding adjustment voltage is. In this case, the adjustment voltages corresponding to several memory groups among the N*N memory groups that include data states with threshold voltages in the middle may be equal.

[0137] For example, in some embodiments, the N first sub-memory groups may include a first group and a second group; the N second sub-memory groups may include a third group and a fourth group; the N*N memory groups may include 2*2 memory groups; the 2*2 memory groups include: a first memory group, a second memory group, a third memory group, and a fourth memory group;

[0138] Among them, the first memory group includes the first group and the third group; the second memory group includes the first group and the fourth group; the third memory group includes the second group and the third group; the fourth memory group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

[0139] Here, the multiple first data states divide the memory cells coupled to the second word line into two first sub-memory groups, namely the first group and the second group, and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group. The multiple second data states divide the memory cells coupled to the second word line into two second sub-data states, namely the third group and the fourth group, where the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group. Then, the 2×2 memory group formed according to the two first sub-memory groups and the two second sub-data states includes a total of four memory groups: the first memory group, the second memory group, the third memory group, and the fourth memory group. Moreover, the first memory group includes the first group and the third group; the second memory group includes the first group and the fourth group; the third memory group includes the second group and the third group; and the fourth memory group includes the second group and the fourth group.

[0140] For example, assume that the first threshold voltage distribution includes eight first data states: L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence; the second threshold voltage distribution includes eight second data states: L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence. Then, there can be two first sub-memory groups. For instance, L0, L1, L2, L3, L4 form one first sub-memory group, that is, the first group; L5, L6, L7 form another first sub-memory group, that is, the second group. Similarly, there are also two second sub-data states. For example, L0, L1, L2, L3, L4 form one second sub-data state, that is, the third group; L5, L6, L7 form another second sub-data state, that is, the fourth group. Based on this, the first memory group includes the first group and the third group, that is, it includes the first sub-memory group of L0, L1, L2, L3, L4 and the second sub-data state of L0, L1, L2, L3, L4; the second memory group includes the first group and the fourth group, that is, it includes the first sub-memory group of L0, L1, L2, L3, L4 and the second sub-data state of L5, L6, L7; the third memory group includes the second group and the third group, that is, it includes the first sub-memory group of L5, L6, L7 and the second sub-data state of L0, L1, L2, L3, L4; the fourth memory group includes the second group and the fourth group, that is, it includes the first sub-memory group of L5, L6, L7 and the second sub-data state of L5, L6, L7.

[0141] According to the relationship between the data state and the adjustment voltage described above, in an optional implementation, the adjustment voltage corresponding to the first memory group is less than the adjustment voltage corresponding to the second memory group; the adjustment voltage corresponding to the second memory group is less than or equal to the adjustment voltage corresponding to the third memory group; and the adjustment voltage corresponding to the third memory group is less than the adjustment voltage corresponding to the fourth memory group.

[0142] More specifically, the adjustment voltage corresponding to the first storage group may include a negative adjustment voltage; the adjustment voltage corresponding to the second storage group is equal to the adjustment voltage corresponding to the third storage group, and may include a positive adjustment voltage; the adjustment voltage corresponding to the fourth storage group may include a positive adjustment voltage and is greater than the adjustment voltage corresponding to the second storage group and the adjustment voltage corresponding to the third storage group.

[0143] In some other embodiments, the N first sub-storage groups include a fifth group, a sixth group, and a seventh group; the N second sub-storage groups include an eighth group, a ninth group, and a tenth group; the N*N storage groups include 3*3 storage groups; each of the 3*3 storage groups includes one of the fifth group, the sixth group, and the seventh group and one of the eighth group, the ninth group, and the tenth group;

[0144] Among them, the threshold voltages of the data states included in the fifth group, the sixth group, and the seventh group increase in sequence; the threshold voltages of the data states included in the eighth group, the ninth group, and the tenth group increase in sequence.

[0145] Here, the multiple first data states divide the storage units coupled to the second word line into 3 first sub-storage groups, namely the fifth group, the sixth group, and the seventh group, and the threshold voltages corresponding to the data states of the fifth group, the sixth group, and the seventh group increase in sequence. The multiple second data states divide the storage units coupled to the second word line into 3 second sub-data states, namely the eighth group, the ninth group, and the tenth group. Among them, the threshold voltages corresponding to the data states of the eighth group, the ninth group, and the tenth group increase in sequence. Then, 3*3 storage groups are formed according to the 3 first sub-storage groups and the 3 second sub-storage groups, and each of the 3*3 storage groups includes one of the fifth group, the sixth group, and the seventh group and one of the eighth group, the ninth group, and the tenth group.

[0146] For example, assume that the first threshold voltage distribution includes 8 first data states, which are: L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence; the second threshold voltage distribution includes 8 second data states, which are L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence. Then, the first sub-storage group may include 3. For example, L0, L1, L2, L3 are one first sub-storage group; L4, L5, L6 are one first sub-storage group; L7 is one first sub-storage group. Similarly, the second sub-storage group may include 3. For example, L0, L1, L2, L3 are one second sub-storage group; L4, L5, L6 are one second sub-storage group; L7 is one second sub-storage group. Based on this, each of the 3*3 storage groups includes one of the 3 first sub-storage groups and one of the 3 second sub-storage groups.

[0147] More specifically, the fifth storage group includes the fifth group and the eighth group; the sixth storage group includes the fifth group and the ninth group; the seventh storage group includes the sixth group and the eighth group; the eighth storage group includes the fifth group and the tenth group; the ninth storage group includes the seventh group and the eighth group; the tenth storage group includes the sixth group and the ninth group; the eleventh storage group includes the sixth group and the tenth group; the twelfth storage group includes the seventh group and the ninth group; and the thirteenth storage group includes the seventh group and the tenth group.

[0148] Among these storage groups, an optional way to obtain the adjustment voltage can be: the adjustment voltage corresponding to the fifth digital state group can include a negative adjustment voltage; the adjustment voltages corresponding to the sixth and seventh digital state groups can include zero; the adjustment voltages corresponding to the eighth, ninth, and tenth storage groups can include positive adjustment voltages; and the adjustment voltages corresponding to the eleventh, twelfth, and thirteenth storage groups can include positive adjustment voltages and are greater than the adjustment voltages corresponding to the previous eighth, ninth, and tenth storage groups.

[0149] After determining the adjustment voltage corresponding to each storage group, in some embodiments, the peripheral circuit can also be configured to: obtain a corresponding second passing voltage according to the adjustment voltage corresponding to each storage group and the first passing voltage;

[0150] and perform the second read operation multiple times. Among them, in each second read operation, the same second read voltage is applied to the second word line; the word lines adjacent to the second word line are applied with second passing voltages corresponding to each adjustment voltage; and the other word lines are applied with the same first passing voltage.

[0151] It should be noted that according to the previous description, the storage units coupled to the second word line are grouped according to the threshold voltage distribution coupled to the word lines adjacent to the second word line. For example, they are divided into 2×2 groups or 3×3 groups, etc., and each group corresponds to one of the aforementioned storage groups. Then, the second read operation is performed multiple times on the storage units coupled to the second word line, including: the second read operation performed on each group of storage units among the storage units coupled to the second word line. Among them, in each second read operation, the second passing voltage applied to the word line adjacent to the second word line is the sum of the adjustment voltage corresponding to the storage group corresponding to this group of storage units and the first passing voltage. In other words, the second read operation performed on the storage units coupled to the second word line includes multiple second read operations. In each second read operation, the passing voltage of the word line adjacent to the second word line is adjusted. Thus, the threshold voltage distribution of the second word line coupled storage units that are subjected to the coupling interference of the adjacent word lines is adjusted to obtain a better RWM, that is, read correction.

[0152] For example, assume that the first threshold voltage distribution includes 8 first data states, namely: L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence; the second threshold voltage distribution includes 8 second data states, namely L0, L1, L2, L3, L4, L5, L6, L7, and their threshold voltages increase in sequence. The formed 2×2 memory groups include: the first memory group includes the first group and the third group, that is, it includes: the first sub-memory group of L0, L1, L2, L3, L4 and the second sub-memory group of L0, L1, L2, L3, L4; the second memory group includes the first group and the fourth group, that is, it includes the first sub-memory group of L0, L1, L2, L3, L4 and the second sub-memory group of L5, L6, L7; the third memory group includes the second group and the third group, that is, it includes: the first sub-memory group of L5, L6, L7 and the second sub-memory group of L0, L1, L2, L3, L4; the fourth memory group includes the second group and the fourth group, that is, it includes the first sub-memory group of L5, L6, L7 and the second sub-memory group of L5, L6, L7. At this time, the memory cells coupled to the second word line will also form 2×2 memory groups. Among them, the 2×2 groups include: group A, group B, group C, and group D, which respectively correspond to the first memory group, the second memory group, the third memory group, and the fourth memory group. Then, when performing multiple second read operations, it includes: the second read operation of reading the memory cells included in group A, the second read operation of reading the memory cells included in group B, the second read operation of reading the memory cells included in group C, and the second read operation of reading the memory cells included in group D, a total of 4 second read operations. And when reading the memory cells included in group A, the second pass voltage of the word line adjacent to the second word line is the sum of the first pass voltage and the adjustment voltage corresponding to the first memory group; when reading the memory cells included in group B, the second pass voltage of the word line adjacent to the second word line is the sum of the first pass voltage and the adjustment voltage corresponding to the second memory group; when reading the memory cells included in group C, the second pass voltage of the word line adjacent to the second word line is the sum of the first pass voltage and the adjustment voltage corresponding to the third memory group; when reading the memory cells included in group D, the second pass voltage of the word line adjacent to the second word line is the sum of the first pass voltage and the adjustment voltage corresponding to the fourth memory group. It should be noted that according to the previous description, the adjustment voltage corresponding to the second memory group and the adjustment voltage corresponding to the third memory group are the same. The second read operation of reading the memory cells included in group B and the second read operation of reading the memory cells included in group C can be performed together, that is, a total of 3 second read operations are required. That is to say, in actual situations, the adjustment voltages corresponding to the determined multiple memory groups may be the same. Then, when performing the read operation, the reads can be combined to reduce the number of read operations and save time.

[0153] An embodiment of the present application further provides an operation method for a memory device, where the memory device includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; as Figure 10 shown, the operation method may include:

[0154] Performing a first read operation, where the first read operation includes: applying a first read voltage to a first word line of a first type among the plurality of word lines; and applying a first pass voltage to word lines other than the first word line among the plurality of word lines;

[0155] And performing a second read operation, where the second read operation includes: applying a second read voltage to a second word line of a second type among the plurality of word lines; applying a second pass voltage to word lines adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to word lines other than the second word line and the word lines adjacent to the second word line among the plurality of word lines; where the second pass voltage is determined according to the threshold voltage distribution after programming of the memory cells coupled to the word lines adjacent to the second word line.

[0156] In some embodiments, the second word line of the second type is between two first word lines of the first type; before performing the first read operation and the second read operation; the operation method further includes:

[0157] Performing a programming operation on the plurality of memory cells in a preset programming order;

[0158] Wherein, the preset programming order includes: sequentially performing programming operations on the memory cells coupled to two first word lines of the first type; and performing a programming operation on the memory cells coupled to the second word line of the second type.

[0159] In some embodiments, the programming operation is incremental step pulse programming, where the step size of the incremental voltage corresponding to the programming pulse applied to the first word line of the first type is the same as the step size of the incremental voltage corresponding to the programming pulse applied to the second word line of the second type.

[0160] In some embodiments, as Figure 11 shown, the word lines adjacent to the second word line include two first word lines of the first type; the operation method further includes:

[0161] Sequentially performing read operations on the memory cells coupled to two first word lines of the first type to obtain a first threshold voltage distribution and a second threshold voltage distribution respectively;

[0162] Obtaining an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution;

[0163] And obtaining the second passing voltage based on the adjusted voltage and the first passing voltage.

[0164] In some embodiments, as Figure 12 shown, obtaining the adjusted voltage based on the first threshold voltage distribution and the second threshold voltage distribution may include:

[0165] Dividing the memory cells coupled to the second word line into N*N memory groups according to the first threshold voltage distribution and the second threshold voltage distribution;

[0166] And determining the adjusted voltage corresponding to each memory group according to a preset mapping relationship, or setting the adjusted voltage corresponding to each memory group according to a preset rule.

[0167] In some embodiments, the first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; wherein, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-memory groups according to the plurality of second data states;

[0168] In the case that the N first sub-memory groups include a first group and a second group, and the N second sub-memory groups include a third group and a fourth group, the N*N memory groups include a first memory group, a second memory state group, a third memory group, and a fourth memory group, a total of 2*2 memory groups; wherein, the first memory group includes the first group and the third group; the second memory group includes the first group and the fourth group; the third memory group includes the second group and the third group; the fourth memory group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

[0169] In some embodiments, the adjusted voltage corresponding to the first memory group is less than the adjusted voltage corresponding to the second memory group;

[0170] The adjusted voltage corresponding to the second memory group is less than or equal to the adjusted voltage corresponding to the third memory group; and

[0171] The adjusted voltage corresponding to the third memory group is less than the adjusted voltage corresponding to the fourth memory group.

[0172] In some embodiments,

[0173] Obtaining the second passing voltage based on the adjusted voltage and the first passing voltage includes:

[0174] Obtain a corresponding second passing voltage according to the adjustment voltage corresponding to each storage group and the first passing voltage.

[0175] In some embodiments, the operation method further includes: sequentially performing the second read operation multiple times, wherein, in each second read operation, the same second read voltage is applied to the second word line; a word line adjacent to the second word line is applied with a second passing voltage corresponding to each adjustment voltage; other word lines are applied with the same first passing voltage.

[0176] In some embodiments, the operation method further includes: obtaining a third threshold voltage distribution corresponding to each second read operation; and obtaining a target threshold voltage distribution corresponding to the storage unit coupled to the second word line according to each third threshold voltage distribution,

[0177] wherein the target threshold voltage distribution is tighter than each third threshold voltage distribution.

[0178] It should be noted that the operation method of the memory device provided in the embodiments of the present application is the same as the inventive concept of the memory device described above. The technical features and terms described in this operation method have been described in detail when describing the memory device above, and can be understood by referring to the above description, and will not be repeated here.

[0179] The embodiments of the present application further provide a memory system, including: the memory device described in any one of the foregoing and a memory controller coupled to the memory device and controlling the memory device.

[0180] In some embodiments, the memory system may be included in a solid state drive (SSD) or a memory card.

[0181] It should be noted that this memory system includes the foregoing memory device. Therefore, the two have the same technical features. The terms appearing in this memory system have been explained in detail in the foregoing memory device and are equally applicable here, and will not be repeated one by one. It should be understood that only the structure of the memory system most relevant to the technology of the present application is described here, and other structures may be the structures shown above or other memory system structures. Figures 1 to 6 as shown in the structure, or other memory system structures.

[0182] The foregoing is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A memory device, characterized in that, comprising: a memory array; the memory array includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and a peripheral circuit, coupled to the memory array and configured to: perform a first read operation, the first read operation including: applying a first read voltage to a first word line of a first type among the plurality of word lines; and applying a first pass voltage to word lines other than the first word line among the plurality of word lines; perform a second read operation, the second read operation including: applying a second read voltage to a second word line of a second type among the plurality of word lines; applying a second pass voltage to word lines adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to word lines other than the second word line and the word lines adjacent to the second word line among the plurality of word lines; wherein, the second pass voltage is determined according to a threshold voltage distribution after programming of memory cells coupled to word lines adjacent to the second word line.

2. The memory device according to claim 1, characterized in that, the second word line of the second type is between two first word lines of the first type; before performing the first read operation and the second read operation, the peripheral circuit is further configured to: perform a programming operation on the plurality of memory cells in a preset programming order; wherein, the preset programming order includes: sequentially performing a programming operation on memory cells coupled to two first word lines of the first type; and performing a programming operation on memory cells coupled to the second word line of the second type.

3. The memory device according to claim 2, characterized in that, the programming operation is incremental step pulse programming, wherein a step size of an incremental voltage corresponding to a programming pulse applied to a first word line of the first type is the same as a step size of an incremental voltage corresponding to a programming pulse applied to a second word line of the second type.

4. The memory device according to claim 1, characterized in that, word lines adjacent to the second word line include two first word lines of the first type; the peripheral circuit is further configured to: sequentially perform a read operation on memory cells coupled to two first word lines of the first type, and respectively obtain a first threshold voltage distribution and a second threshold voltage distribution; obtain an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution; and obtain the second pass voltage according to the adjustment voltage and the first pass voltage.

5. The memory device according to claim 4, characterized in that, memory cells coupled to the second word line are divided into N*N memory groups according to the first threshold voltage distribution and the second threshold voltage distribution; the peripheral circuit is further configured to: determine an adjustment voltage corresponding to each memory group according to a preset mapping relationship, or set an adjustment voltage corresponding to each memory group according to a preset rule.

6. The memory device according to claim 5, characterized in that, The first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; wherein, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-memory groups according to the plurality of second data states; In the case that the N first sub-memory groups include a first group and a second group, and the N second sub-memory groups include a third group and a fourth group, the N*N memory groups include a first memory group, a second memory state group, a third memory group, and a fourth memory group, a total of 2*2 memory groups; wherein, the first memory group includes the first group and the third group; the second memory group includes the first group and the fourth group; the third memory group includes the second group and the third group; the fourth memory group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

7. The memory device according to claim 6, wherein, the adjustment voltage corresponding to the first memory group is less than the adjustment voltage corresponding to the second memory group; the adjustment voltage corresponding to the second memory group is less than or equal to the adjustment voltage corresponding to the third memory group; the adjustment voltage corresponding to the third memory group is less than the adjustment voltage corresponding to the fourth memory group.

8. The memory device according to claim 5, wherein, the peripheral circuit is further configured to: obtain a corresponding second pass voltage according to the adjustment voltage corresponding to each memory group and the first pass voltage; and perform the second read operation multiple times, wherein, in each second read operation, the same second read voltage is applied to the second word line; the second pass voltage corresponding to each adjustment voltage is applied to the word line adjacent to the second word line; the same first pass voltage is applied to other word lines.

9. An operation method of a memory device, wherein, the memory device includes a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; the operation method includes: performing a first read operation, the first read operation includes: applying a first read voltage to a first word line belonging to a first type among the plurality of word lines; and applying a first pass voltage to the word lines other than the first word line among the plurality of word lines; performing a second read operation, the second read operation includes: applying a second read voltage to a second word line belonging to a second type among the plurality of word lines; applying a second pass voltage to the word line adjacent to the second word line among the plurality of word lines; and applying the first pass voltage to the word lines other than the second word line and the word line adjacent to the second word line among the plurality of word lines; wherein, the second pass voltage is determined according to the threshold voltage distribution after the memory cells coupled to the word line adjacent to the second word line are programmed.

10. The operation method according to claim 9, wherein, the second word line belonging to the second type is between two first word lines belonging to the first type; before performing the first read operation and the second read operation; the operation method further includes: performing a programming operation on the plurality of memory cells in accordance with a preset programming sequence; wherein, the preset programming sequence includes: sequentially performing a programming operation on the memory cells coupled to two first word lines belonging to the first type; and performing a programming operation on the memory cells coupled to the second word line belonging to the second type.

11. The operation method according to claim 10, wherein, the programming operation is an incremental step pulse programming, wherein the step size of the incremental voltage corresponding to the programming pulse applied to the first word line belonging to the first type is the same as the step size of the incremental voltage corresponding to the programming pulse applied to the second word line belonging to the second type.

12. The operation method according to claim 9, wherein, the word lines adjacent to the second word line include two first word lines belonging to the first type; the operation method further includes: sequentially performing a read operation on the memory cells coupled to two first word lines belonging to the first type to respectively obtain a first threshold voltage distribution and a second threshold voltage distribution; obtaining an adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution; and obtaining the second pass voltage according to the adjustment voltage and the first pass voltage.

13. The operation method according to claim 12, wherein, the obtaining of the adjustment voltage according to the first threshold voltage distribution and the second threshold voltage distribution includes: dividing the memory cells coupled to the second word line into N*N memory groups according to the first threshold voltage distribution and the second threshold voltage distribution; determining the adjustment voltage corresponding to each memory group according to a preset mapping relationship, or setting the adjustment voltage corresponding to each memory group according to a preset rule.

14. The operation method according to claim 13, wherein, the first threshold voltage distribution includes a plurality of first data states; the second threshold voltage distribution includes a plurality of second data states; wherein, the memory cells coupled to the second word line are divided into N first sub-memory groups according to the plurality of first data states; the memory cells coupled to the second word line are divided into N second sub-memory groups according to the plurality of second data states; In the case where the N first sub - storage groups include a first group and a second group, and the N second sub - storage groups include a third group and a fourth group, the N*N storage groups include a first storage group, a second storage group, a third storage group, and a fourth storage group, a total of 2*2 storage groups; wherein, the first storage group includes the first group and the third group; the second storage group includes the first group and the fourth group; the third storage group includes the second group and the third group; the fourth storage group includes the second group and the fourth group; and the threshold voltage in the first threshold voltage distribution corresponding to the first group is less than the threshold voltage in the first threshold voltage distribution corresponding to the second group; the threshold voltage in the second threshold voltage distribution corresponding to the third group is less than the threshold voltage in the second threshold voltage distribution corresponding to the fourth group.

15. The operation method according to claim 14, wherein, the adjustment voltage corresponding to the first storage group is less than the adjustment voltage corresponding to the second storage group; the adjustment voltage corresponding to the second storage group is less than or equal to the adjustment voltage corresponding to the third storage group; and the adjustment voltage corresponding to the third storage group is less than the adjustment voltage corresponding to the fourth storage group.

16. The operation method according to claim 13, wherein, obtaining the second passing voltage according to the adjustment voltage and the first passing voltage includes: obtaining the corresponding second passing voltage according to the adjustment voltage corresponding to each storage group and the first passing voltage.

17. The operation method according to claim 16, wherein, the operation method further includes: performing the second read operation multiple times in sequence, wherein, in each second read operation, the second word line is applied with the same second read voltage; the word lines adjacent to the second word line are applied with the second passing voltage corresponding to each adjustment voltage; and the other word lines are applied with the same first passing voltage.

18. The operation method according to claim 17, wherein, the operation method further includes: obtaining the third threshold voltage distribution corresponding to each second read operation; and obtaining the target threshold voltage distribution corresponding to the storage unit coupled to the second word line according to each third threshold voltage distribution, wherein, the target threshold voltage distribution is tighter than each third threshold voltage distribution.

19. A memory system, wherein, comprising: the memory device according to any one of claims 1 to 8 and a memory controller coupled to the memory device and controlling the memory device.

20. The memory system according to claim 19, wherein, the memory system is included in a solid - state drive SSD or a memory card.

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