Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit comprises a power supply generation circuit; the power supply generating circuit comprises a bias current source which is connected with the current mirror and the transistor adjusting circuit and is configured to receive a first power supply signal and keep the sum of the output current of the current mirror and the control current of the transistor adjusting circuit stable; the current mirror is connected with the transistor adjusting circuit, and is configured to receive and respond to the voltage change of the second power supply signal, and output changed current, so that the control current of the transistor adjusting circuit is changed; the voltage of the first power signal is greater than that of the second power signal; and the transistor adjusting circuit is configured to receive the first power supply signal and generate a driving voltage signal which changes in a certain interval along with the voltage change of the second power supply signal under the adjustment of the change of the control current.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to a memory device, an operation method thereof, and a memory system. Background Art

[0002] With the increase in the storage density of three-dimensional storage devices (such as 3D NAND flash memories), the area available for the peripheral circuit is significantly reduced. How to reduce the circuit area while maintaining the original device process and circuit performance is a challenge in analog power supply design. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a memory device, an operation method thereof, and a memory system.

[0004] In a first aspect, embodiments of the present application provide a memory device, which includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power generation circuit; the power generation circuit includes: a bias current source, connected to both a current mirror and a transistor adjustment circuit, and configured to: receive a first power signal and keep the sum of the output current of the current mirror and the control current of the transistor adjustment circuit stable; the current mirror, connected to the transistor adjustment circuit, and configured to: receive and respond to a voltage change of a second power signal, and output a changing current to make the control current of the transistor adjustment circuit change; the voltage of the first power signal is greater than the voltage of the second power signal; the transistor adjustment circuit, configured to: receive the first power signal and generate a driving voltage signal that varies within a certain range with the voltage change of the second power signal under the adjustment of the changing control current.

[0005] In some embodiments, a first end of the bias current source receives the first power signal, and a second end of the bias current source is coupled to both a second end of the current mirror and a control end of the transistor adjustment circuit; a first end of the current mirror is coupled to an output end of the transistor adjustment circuit, a second end of the current mirror is coupled to the control end of the transistor adjustment circuit, and a third end of the current mirror receives the second power signal; an input end of the transistor adjustment circuit receives the first power signal.

[0006] In some embodiments, the power generation circuit further includes a clamping circuit, coupled between the first end of the current mirror and the output end of the transistor adjustment circuit, and configured to: receive a first control signal at a control end and clamp the voltage of the driving voltage signal at a first voltage when the voltage of the second power signal is less than or equal to a first threshold.

[0007] In some embodiments, the transistor adjustment circuit includes a first transistor. The control terminal of the first transistor is coupled to the second terminal of a bias current source. The input terminal of the first transistor receives a first power signal, and the output terminal of the first transistor outputs a driving voltage signal. The clamping circuit includes a second transistor. The input terminal of the second transistor is coupled to the output terminal of the first transistor, the output terminal of the second transistor is coupled to the first terminal of a current mirror, and the control terminal of the second transistor receives a first control signal. When the voltage of the second power signal is less than or equal to a first threshold, the second transistor is controlled to be in a saturation state through the first control signal so that the voltage of the driving voltage signal is clamped at a first voltage.

[0008] In some embodiments, the current mirror includes a first-stage current mirror and a second-stage current mirror. The input terminal of the first-stage current mirror is coupled to the output terminal of the first transistor through the second transistor, and the output terminal of the first-stage current mirror is coupled to the second terminal of the bias current source and the control terminal of the first transistor. The input terminal and the output terminal of the second-stage current mirror are both coupled to the first-stage current mirror, and the common terminal of the second-stage current mirror receives the second power signal.

[0009] In some embodiments, the first-stage current mirror includes a third transistor and a sixth transistor whose control terminals and drain terminals are connected. The second-stage current mirror includes a fourth transistor and a fifth transistor whose control terminals and drain terminals are connected. The input terminal of the third transistor is coupled to the output terminal of the clamping circuit, and the output terminal of the third transistor is coupled to the input terminal of the fourth transistor. The output terminals of the fourth transistor and the fifth transistor both receive the second power signal. The control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor, and the input terminal of the fifth transistor is coupled to the output terminal of the sixth transistor. The input terminal of the sixth transistor is coupled to the second terminal of the bias current source and the control terminal of the first transistor.

[0010] In some embodiments, the second transistor and the third transistor are PMOS transistors, and the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

[0011] In some embodiments, the memory device further includes a discharge circuit. The first terminal of the discharge circuit is coupled to the output terminal of the first transistor, and the second terminal of the discharge circuit receives a ground voltage signal. The discharge circuit is configured to: receive a second control signal at the control terminal, and when the voltage of the driving voltage signal is greater than a second threshold, discharge to make the voltage of the driving voltage signal drop to a second voltage; when the voltage of the driving voltage signal is less than or equal to the second threshold, stop discharging; wherein the second voltage is greater than the first voltage.

[0012] In some embodiments, the discharge circuit includes a seventh transistor; an input end of the seventh transistor is coupled to an output end of the first transistor, a ground voltage signal is received at an output end of the seventh transistor, a second control signal is received at a control end of the seventh transistor, and when the voltage of the drive voltage signal is greater than a second threshold, the seventh transistor is controlled to be turned on through the second control signal so that the voltage of the drive voltage signal discharges.

[0013] In some embodiments, the discharge circuit further includes an eighth transistor and a ninth transistor; an input end of the eighth transistor is coupled to an output end of the seventh transistor, an output end of the eighth transistor is coupled to an input end of the ninth transistor, and a control end of the eighth transistor is coupled to an input end of the fourth transistor; a control end and a drain end of the ninth transistor are connected, an input end of the ninth transistor is coupled to an output end of the eighth transistor, and a ground voltage signal is received at an output end of the ninth transistor; wherein, the magnitude of the discharge current is adjusted by adjusting the ratio relationship between the sizes of the seventh transistor, the eighth transistor, and the ninth transistor and the sizes of the second transistor, the third transistor, and the fourth transistor.

[0014] In some embodiments, the seventh transistor and the eighth transistor are PMOS transistors, and the ninth transistor is an NMOS transistor; the second transistor and the third transistor are PMOS transistors, and the fourth transistor is an NMOS transistor.

[0015] In some embodiments, the memory cell array includes a plurality of memory blocks; the memory device further includes a control circuit; a first end of the control circuit receives a first power supply signal, a second end of the control circuit is coupled to an output end of the transistor adjustment circuit, and the control circuit is configured to: receive a memory block enable signal, and when the memory block enable signal is in an enabled state, the connection between the output end of the control circuit and the output end of the transistor adjustment circuit is disconnected; when the memory block enable signal is in a disabled state, the output end of the control circuit is connected to the first power supply signal; when the memory block enable signal is in an enabled state, it indicates that the corresponding memory block is the selected memory block.

[0016] In some embodiments, the control circuit includes a tenth transistor; a control end of the tenth transistor receives the memory block enable signal, an input end of the tenth transistor receives the first power supply signal, and an output end of the tenth transistor is coupled to an output end of the first transistor.

[0017] In some embodiments, the tenth transistor is a PMOS transistor.

[0018] In some embodiments, the peripheral circuit further includes a row decoding circuit; the second power supply signal is configured to provide a negative power supply for the row decoding circuit, and the drive voltage signal is configured to provide a positive power supply for the row decoding circuit.

[0019] In some embodiments, the memory device of any one of the above embodiments includes a NAND-type memory.

[0020] In a second aspect, embodiments of the present application provide a memory system, which includes: one or more memory devices as described in any of the embodiments of the first aspect; and a memory controller coupled to and controlling the memory devices.

[0021] In a third aspect, embodiments of the present application provide an operation method for a memory device. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power generation circuit; the power generation circuit includes a bias current source, a current mirror, and a transistor adjustment circuit coupled to each other; the operation method includes: the bias current source receives a first power signal and keeps the sum of the output current of the current mirror and the control current of the transistor adjustment circuit stable; the current mirror receives and responds to a voltage change of a second power signal and outputs a changing current to cause a change in the control current of the transistor adjustment circuit; the voltage of the first power signal is greater than the voltage of the second power signal; the transistor adjustment circuit receives the first power signal and generates a driving voltage signal that varies within a certain range with the voltage change of the second power signal under the adjustment of the changing control current.

[0022] In some embodiments, the power generation circuit further includes a clamping circuit coupled between the first end of the current mirror and the output end of the transistor adjustment circuit. The operation method includes: the control end of the clamping circuit receives a first control signal, and when the voltage of the second power signal is less than or equal to a first threshold, the clamping circuit clamps the voltage of the driving voltage signal at a first voltage.

[0023] In some embodiments, the clamping circuit includes a second transistor; the operation method includes: the control end of the second transistor receives the first control signal, and when the voltage of the second power signal is less than or equal to the first threshold, by controlling the second transistor to be in a saturation state, the voltage of the driving voltage signal is clamped at the first voltage; when the voltage of the second power signal is greater than the first threshold, by controlling the second transistor to be in an amplification state, the voltage of the driving voltage signal increases with the increase of the second power signal; when the voltage of the second power signal is equal to the voltage of the ground voltage signal, the voltage of the driving voltage signal is stabilized at a second voltage; the second voltage is greater than the first voltage.

[0024] In each embodiment of the present application, the power generation circuit forms a negative feedback loop by adopting a local feedback method composed of a bias current source, a current mirror, and a transistor adjustment circuit, formally replacing the functions of the resistor and the operational amplifier in the Low Dropout regulator (LDO) structure. To a certain extent, the output driving voltage signal is stabilized. Moreover, compared with the LDO structure, the area of the power generation circuit is reduced, so that the circuit area is reduced and the cost is lowered while ensuring that the circuit performance meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0026] Figure 2A Schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0027] Figure 2B Schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present application;

[0028] Figure 3 Schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present application;

[0029] Figure 4 Cross-sectional schematic diagram of a memory array including NAND memory strings according to an embodiment of the present application;

[0030] Figure 5 Schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0031] Figure 6 Schematic diagram of a power supply circuit using a classic low dropout linear regulator structure;

[0032] Figure 7 Schematic diagram of a first power generation circuit provided by an embodiment of the present application;

[0033] Figure 8 Schematic diagram of a second power generation circuit provided by an embodiment of the present application;

[0034] Figure 9 Schematic diagram of a third power generation circuit provided by an embodiment of the present application;

[0035] Figure 10 Schematic diagram of a fourth power generation circuit provided by an embodiment of the present application;

[0036] Figure 11 Schematic diagram of a fifth power generation circuit provided by an embodiment of the present application;

[0037] Figure 12 Schematic diagram of a sixth power generation circuit provided by an embodiment of the present application;

[0038] Figure 13 Schematic diagram of a seventh power generation circuit provided by an embodiment of the present application;

[0039] Figure 14AIt is one of the waveform diagrams showing the changes in the driving voltage signal and the second power supply signal provided by the embodiments of the present application;

[0040] Figure 14B It is another waveform diagram showing the changes in the driving voltage signal and the second power supply signal provided by the embodiments of the present application;

[0041] Figure 15 It is the simulation waveform diagram of the changes in the driving voltage signal and the second power supply signal provided by the embodiments of the present application;

[0042] Figure 16 It is the simulation waveform diagram of the changes in the driving voltage signal when the storage block enable signal state switches provided by the embodiments of the present application. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without making creative efforts shall fall within the scope of protection of the present disclosure.

[0044] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0045] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that there must be a first element, component, region, layer, or part in the present disclosure.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0048] To thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other implementation manners.

[0049] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, the three-dimensional NAND type memory is taken as an example for illustration.

[0050] Figure 1A block diagram of an exemplary system 100 with a memory device in accordance with some aspects of the present application is shown. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As Figure 1 shown, system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)). The host 108 can be configured to send data to or receive data from the memory device 104.

[0051] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low-duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0052] In some embodiments, the memory controller 106 is designed to operate in a high-duty cycle environment, a solid state disk (SSD) or an embedded multi media card (eMMC), the SSD or eMMC being used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0053] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process the error correction code (ECC) regarding the data read from or written to the memory device 104.

[0054] The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0055] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0056] In as Figure 2AIn one example as shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 1 the host 108 in

[0057] In another example as shown in Figure 2B , the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., Figure 1 the host 108 in

[0058] Figure 3 FIG. shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present application. The memory device 300 may be an example of the memory device 104 in Figure 1 . The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. Taking the memory cell array 301 as a three-dimensional NAND-type memory cell array as an example for illustration, wherein the storage cell 306 is a NAND-type storage cell, and the storage cells 306 are provided in the form of an array of memory strings 308, and each memory string 308 extends vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of storage cells 306 coupled in series and vertically stacked. Each storage cell 306 may hold a continuous analog value, e.g., a voltage or a charge, which depends on the number of electrons trapped within the region of the storage cell 306. Each storage cell 306 may be a floating-gate type storage cell including a floating-gate transistor, or a charge-trapping type storage cell including a charge-trapping transistor.

[0059] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can thus store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that is capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value can be used for the erased state.

[0060] It should be noted that the storage state mentioned here is the storage state of the memory cell in this application. Different memory cells have different numbers of storage states. For example, an SLC type memory cell has 2 storage states (i.e., two memory states), where these 2 storage states include: a programmed state and an erased state. Another example is that an MLC type memory cell has 4 storage states, where these 4 storage states include: an erased state and three programmed states. Still another example is that a TLC type memory cell has 8 storage states, where these 8 storage states include: an erased state and seven programmed states. In some embodiments, a QLC type memory cell has 16 storage states, where these 16 storage states include: an erased state and fifteen programmed states.

[0061] Such as Figure 3As shown, each memory string 308 may include a bottom select transistor (BSG) 310 (also referred to as a source side select transistor) at its source extreme and a top select transistor (TSG) 312 (also referred to as a drain side select transistor) at its drain extreme. The BSG 310 and TSG 312 may be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all the memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselected voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselected voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0062] As Figure 3 shown, the memory strings 308 may be organized into a plurality of memory blocks 304, and each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 may be coupled through word lines 318, and the word lines 318 select which row of memory cells 306 is affected by read and program operations.

[0063] Referring Figure 3 to, each of the plurality of memory cells, each memory cell 306 is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding select transistor (such as the top select transistor (TSG) 312).

[0064] Figure 4 A cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 exemplified by NAND according to some aspects of the present application is shown. As Figure 4 shown, the NAND memory cell array 301 may include a stacked structure 410, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layer 411 and the insulating layer 412 may be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412.

[0065] The constituent material of the gate layer 411 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend horizontally as an upper select gate line, and the gate layer 411 at the bottom of the stacked structure 410 may extend horizontally as a lower select gate line, and the gate layer 411 extending horizontally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0066] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] In some embodiments, the memory string 308 includes a channel structure that extends vertically through the stack structure 410. In some embodiments, the channel structure includes channel holes filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] Return reference Figure 3 , the peripheral circuit 302 can be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown Figure 5 may also be included.

[0069] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low-power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify the small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0070] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 with word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0071] The control logic 512 may be coupled to each other part of the peripheral circuits described above, and is configured to control the operations of each other part of the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The interface (I / F) 516 may be coupled to the control logic 512, and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and buffer status information received from the control logic 512 and relay it to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 301.

[0072] Reference Figure 6 , the power supply circuit of a memory device such as a 3D NAND flash memory generally adopts a classic low-dropout linear regulator structure, including a structure in which an operational amplifier (OP) 20 and a voltage dividing circuit 30 form a feedback loop. The first input terminal of the operational amplifier 20 receives a reference voltage signal vref, and the output terminal of the operational amplifier 20 feeds back a feedback signal fb to the second input terminal of the operational amplifier 20 after being voltage-divided by the resistor 32 of the voltage dividing circuit 30, so as to obtain a stable voltage output signal vddx at the output terminal of the voltage dividing circuit 30. Although the feedback loop of this structure has a large gain and high output voltage accuracy, both the operational amplifier 20 and the resistor 32 occupy a relatively large area.

[0073] In view of this, embodiments of the present application provide a memory device, an operation method thereof, and a memory system.

[0074] Reference Figure 5 and Figure 7, In a first aspect, an embodiment of the present application provides a memory device 300, which includes: a memory cell array 301 and a peripheral circuit coupled to the memory cell array 301; the peripheral circuit includes a power generation circuit 10; the power generation circuit 10 includes: a bias current source Iref, connected to both a current mirror 14 and a transistor adjustment circuit 12, and configured to: receive a first power signal vcc, and keep the sum of the output current of the current mirror 14 and the control current of the transistor adjustment circuit stable; the current mirror 14, connected to the transistor adjustment circuit 12, and configured to: receive and respond to a voltage change of a second power signal vssx, and output a varying current to cause a change in the control current of the transistor adjustment circuit 12; the voltage of the first power signal vcc is greater than the voltage of the second power signal vssx; the transistor adjustment circuit 12, configured to: receive the first power signal vcc, and generate a drive voltage signal vddx that varies within a certain range with the voltage change of the second power signal under the adjustment of the varying control current.

[0075] Figure 7 The power generation circuit 10 shown can be understood as Figure 5 at least part of the circuit of the voltage generator 510 shown, and is configured to provide a drive voltage signal vddx for the row decoder / word line driver 508. The power generation circuit 10 adopts a local feedback structure composed of a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12. Among them, the bias current source Iref can provide a bias current IDf with a constant current value, and the constant value keeps the sum of the output current of the current mirror 14 and the control current of the transistor adjustment circuit stable; the output current ID2 of the current mirror 14 is a proportional mirror copy of the input current ID1 of the current mirror 14. For example, by setting the size ratio between the fourth transistor M4 and the fifth transistor M5, the ratio between the input current ID1 and the output current ID2 can be adjusted; the output terminal of the transistor adjustment circuit 12 can change under the adjustment of the change of the control current of the transistor adjustment circuit 12. For example, when the control current of the transistor adjustment circuit 12 is larger, the voltage of the output terminal of the transistor adjustment circuit 12 is larger.

[0076] In some embodiments, the transistor adjustment circuit includes a MOS transistor (Metal - Oxide - Semiconductor Field - Effect Transistor, MOSFET) (reference Figure 7)。The MOS transistor belongs to a voltage-controlled device, and the current between the source and drain of the MOS transistor is controlled by the voltage on the gate terminal. The change in the control current of the transistor adjustment circuit 12 should be understood as the change in the voltage of the control terminal of the MOS transistor. When the output current ID2 of the current mirror 14 changes, for example, the current ID2 decreases, and the bias current IDf of the bias current source Iref is greater than the current ID2, the extra current (IDf - ID2) will charge the control terminal of the MOS transistor in the transistor adjustment circuit, and the voltage of the control terminal of the MOS transistor in the transistor adjustment circuit increases.

[0077] In some other embodiments, the transistor adjustment circuit includes a bipolar junction transistor (BJT) ( Figure 7 (not shown). The BJT is a current-controlled device, and the current between the collector and the emitter is controlled by the current on the base. The change in the control current of the transistor adjustment circuit 12 should be understood as the change in the current of the control terminal of the BJT. When the output current ID2 of the current mirror 14 changes, for example, the current ID2 decreases, and the bias current IDf of the bias current source Iref is greater than the current ID2, the extra current (IDf - ID2) will flow to the control terminal of the BJT in the transistor adjustment circuit, and the current of the control terminal of the BJT increases.

[0078] Referring to Figure 7 , in some embodiments, the first end of the bias current source Iref receives the first power supply signal vcc, the second end of the bias current source Iref is coupled to both the second end of the current mirror 14 and the control terminal of the transistor adjustment circuit 12; the first end of the current mirror 14 is coupled to the output terminal of the transistor adjustment circuit 12, the second end of the current mirror 14 is coupled to the control terminal of the transistor adjustment circuit 12, and the third end of the current mirror 14 receives the second power supply signal vssx; the input terminal of the transistor adjustment circuit 12 receives the first power supply signal vcc.

[0079] In some embodiments, the voltage of the second power supply signal vssx varies within a range from zero to a more negative value, and the drive voltage signal vddx varies within a certain positive voltage range. Among them, the first power supply signal vcc serves as the positive power supply, and the voltage of the second power supply signal vssx can vary between the voltage vsn and the voltage vs (the voltage vs of the ground voltage signal vss). Exemplarily, the voltage vs can be zero volts, and the voltage vsn represents a certain negative voltage less than 0. In some embodiments, the drive voltage signal vddx can serve as the positive power supply, and the second power supply signal vssx can serve as the negative power supply.

[0080] In some embodiments, the current mirror 14 is configured such that in response to a first change in the voltage of the second power supply signal, the voltage at the first end of the current mirror 14 undergoes a second change, and in response to the second change, the voltage at the second end of the current mirror 14 undergoes a third change; the bias current source Iref is configured such that in response to the third change, the voltage at the control end of the transistor adjustment circuit 12 undergoes a fourth change; the transistor adjustment circuit 12 is configured such that in response to the fourth change, the voltage at the output end of the transistor adjustment circuit 12 undergoes a fifth change; based on the first to fifth changes, a local feedback manner is formed to ensure that the driving voltage signal vddx varies within a certain positive voltage range.

[0081] Exemplarily, as the voltage vsx of the second power supply signal vssx changes, for example, when the voltage vsx decreases, the current ID1 at the input end of the current mirror 14 increases; since the output current ID2 of the current mirror 14 is a proportional mirror copy of the input current ID1 of the current mirror 14, the output current ID2 of the current mirror 14 increases in a proportional mirror copy manner; the bias current IDf of the bias current source Iref is a constant value, and the control current ID3 of the transistor adjustment circuit 12 is the difference between the bias current IDf of the bias current source Iref and the output current ID2 of the current mirror 14. The control current ID3 of the transistor adjustment circuit 12 decreases as the output current ID2 of the current mirror 14 increases; the increase in the control current ID3 of the transistor adjustment circuit 12 causes the current ID4 at the output end of the transistor adjustment circuit 12 to decrease; through the changes in the current ID1 and the current ID4, the voltage vdx of the driving voltage signal vddx changes to the same extent as the voltage vsx of the second power supply signal vssx changes.

[0082] Compared with Figure 6 the LDO structure shown, the power generation circuit 10 provided in the embodiments of the present application can adopt a local feedback manner composed of a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12 to form a negative feedback loop, which formally replaces the Figure 6 functions of the resistor 32 and the operational amplifier 20 in the LDO structure shown, stabilizes the output driving voltage signal vddx to a certain extent, and the area can be reduced to only Figure 6 1 / 8 of the LDO structure shown, significantly reducing the cost.

[0083] In some specific implementations, when there are process, voltage, and temperature (PVT) variations, the power generation circuit 10 can ensure that the voltage vdx of the output driving voltage signal vddx is stabilized within a certain range.

[0084] In the embodiments of the present application, the power generation circuit 10 can adopt a local feedback method composed of a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12 to generate a driving voltage signal vddx that varies within a certain range with the voltage change of the second power signal, so as to ensure the correct operation of the row decoder / word line driver 508. That is to say, on the premise of ensuring the correct operation of the row decoder / word line driver 508, the power generation circuit 10 can adopt a local feedback method to output an appropriate driving voltage signal vddx for the row decoder / word line driver 508 circuit.

[0085] Reference Figure 8 , in some embodiments, the power generation circuit 10 further includes a clamping circuit 16, coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12, and configured to: receive a first control signal ref_l at the control end, and when the voltage of the second power signal vssx is less than or equal to a first threshold, clamp the voltage of the driving voltage signal vddx at a first voltage.

[0086] Here, the voltage rf_l of the first control signal ref_l is a fixed bias voltage. The first threshold can be understood as the voltage of the second power signal vssx required for the clamping circuit 16 to operate in the saturation state when the voltage rf_l of the first control signal ref_l is a fixed bias voltage. Exemplarily, when the voltage rf_l of the first control signal ref_l is a fixed bias voltage, the voltage vsx of the second power signal vssx varies in the range from zero to a more negative value. When the voltage vsx of the second power signal vssx becomes smaller to the first threshold, the voltage at the drain terminal of the fourth transistor M4 of the current mirror 14 (i.e., the second end of the clamping circuit 16) becomes smaller to the voltage (vsx + vgs4), and the voltage difference between the control end and the second end of the clamping circuit 16 increases to the voltage (rf_l - (vsx + vgs4)), which can make the clamping circuit 16 operate in the saturation state. The clamping circuit 16 bears more voltage drop. Even if the voltage at the second end of the clamping circuit 16 continues to become smaller from the voltage (vsx + vgs4), the voltage vdx of the driving voltage signal vddx will be clamped at the first voltage.

[0087] In some embodiments, the first voltage can be the minimum limit voltage of the positive power supply voltage of the row decoder / word line driver 508. When the voltage of the second power signal vssx varies within a certain range, for example, the voltage of the second power signal vssx varies in the range from zero to a more negative value, the minimum voltage of the voltage vdx of the driving voltage signal vddx is the first voltage. Exemplarily, the first voltage can be 1.5V.

[0088] A clamping circuit 16 is added between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12. When the voltage vsx of the second power supply signal vssx is greater than the first threshold, the clamping circuit 16 operates in the linear region and functions as a switch; when the voltage vsx of the second power supply signal vssx is less than or equal to the first threshold, the clamping circuit 16 operates in the saturation region, clamping the voltage of the driving voltage signal vddx at the first voltage.

[0089] In the embodiment of the present application, the power supply generation circuit 10 can adopt a local feedback method composed of a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12, and a clamping method composed of a clamping circuit 16 coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12 to generate a driving voltage signal vddx that varies within a certain range with the change of the voltage of the second power supply signal, so as to ensure the correct operation of the row decoder / word line driver 508. That is to say, on the premise of ensuring the correct operation of the row decoder / word line driver 508, the power supply generation circuit 10 can adopt the local feedback method and the clamping method to output a suitable driving voltage signal vddx for the row decoder / word line driver 508 circuit.

[0090] Reference Figure 8 , in some embodiments, the transistor adjustment circuit 12 includes a first transistor M1. The control end of the first transistor M1 is coupled to the second end of the bias current source Iref. The input end of the first transistor M1 receives the first power supply signal vcc, and the output end of the first transistor M1 outputs the driving voltage signal vddx; the clamping circuit 16 includes a second transistor M2; the input end of the second transistor M2 is coupled to the output end of the first transistor M1, the output end of the second transistor M2 is coupled to the first end of the current mirror 14, and the control end of the second transistor M2 receives the first control signal ref_l. When the voltage of the second power supply signal vssx is less than or equal to the first threshold, the second transistor M2 is controlled to be in the saturation state through the first control signal ref_l, so that the voltage of the driving voltage signal vddx is clamped at the first voltage.

[0091] Here, the second transistor M2 is coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12, and the gate of the second transistor M2 receives the first control signal ref_l. Among them, the voltage vdx of the driving voltage signal vddx is clamped at a potential smaller than the gate voltage of the second transistor M2 (i.e., the voltage rf_l of the first control signal ref_l) by a gate-source voltage vgs2 of the second transistor M2, that is, the voltage vdx of the driving voltage signal vddx is clamped at the voltage (rf_l - vgs2). That is to say, when the voltage vsx of the second power supply signal vssx is greater than the first threshold, the second transistor M2 operates in the linear region and functions as a switch; when the voltage vsx of the second power supply signal vssx is less than or equal to the first threshold, the second transistor M2 operates in the saturation region, so that the voltage of the driving voltage signal vddx is clamped at the voltage (rf_l - vgs2). In some specific embodiments, the second transistor M2 is a PMOS transistor; the voltage of the driving voltage signal vddx is clamped at the voltage (rf_l - vgs2), where the value of the voltage vgs2 is negative.

[0092] In some embodiments, for example Figure 7 , Figure 8 the current mirror 14 is a first-stage current mirror; the input end of the current mirror 14 is coupled to the output end of the first transistor M1 through the second transistor M2, the output end of the current mirror 14 is coupled to the second end of the bias current source Iref and the control end of the first transistor M1, and the common end of the current mirror 14 receives the second power supply signal vssx.

[0093] Refer to Figure 9 and Figure 10 , in some embodiments, the current mirror 14 includes a first-stage current mirror 146 and a second-stage current mirror 142; the input end of the first-stage current mirror 146 is coupled to the output end of the first transistor M1 through the second transistor M2, the output end of the first-stage current mirror 146 is coupled to the second end of the bias current source Iref and the control end of the first transistor M1; the input end and the output end of the second-stage current mirror 142 are both coupled to the first-stage current mirror 146, and the common end of the second-stage current mirror 142 receives the second power supply signal vssx.

[0094] Refer to Figure 9 and Figure 10, in some embodiments, the first-stage current mirror 146 includes a third transistor M3 and a sixth transistor M6 whose control terminals and drain terminals are connected; the second-stage current mirror 142 includes a fourth transistor M4 and a fifth transistor M5 whose control terminals and drain terminals are connected; the input terminal of the third transistor M3 is coupled to the output terminal of the clamping circuit 16, and the output terminal of the third transistor M3 is coupled to the input terminal of the fourth transistor M4; the output terminals of the fourth transistor M4 and the fifth transistor M5 both receive the second power supply signal vssx; the control terminal of the fifth transistor M5 is coupled to the control terminal of the fourth transistor M4, and the input terminal of the fifth transistor M5 is coupled to the output terminal of the sixth transistor M6; the input terminal of the sixth transistor M6 is coupled to the second terminal of the bias current source Iref and the control terminal of the first transistor M1.

[0095] In some specific embodiments, the voltage vdx of the driving voltage signal vddx ranges from the voltage (rf_l + |vgs2|) to the voltage (vsx + |vgs4| + |vgs3| + vdsat2).

[0096] Reference Figure 9 , in some embodiments, the second transistor M2 is a PMOS transistor; the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors.

[0097] In some specific embodiments, the voltage vdx of the driving voltage signal vddx ranges from the voltage (rf_l - vgs2) to the voltage (vsx + vgs4 + vgs3 + vdsat2). Figure 14A This is one of the waveform schematic diagrams of the driving voltage signal and the second power supply signal provided by the embodiments of the present application. Refer to Figure 9 , Figure 14A, Exemplarily, when the voltage vsx of the second power supply signal vssx is zero, the voltage vdx of the drive voltage signal vddx is stabilized at the voltage (vsx + vgs4 + vgs3 + vdsat2). Wherein, the voltage vgs3 is the gate-source voltage vgs3 of the third transistor M3, the voltage vgs4 is the gate-source voltage vgs4 of the fourth transistor M4, and the voltage vdsat2 is the source-drain voltage vdsat2 when the second transistor M2 operates in the saturation region. When the voltage vsx of the second power supply signal vssx becomes more negative, the voltage vdx of the drive voltage signal vddx decreases linearly accordingly, and always maintains a voltage difference of (vgs4 + vgs3 + vdsat2) with the voltage vsx. When the voltage vdx of the drive voltage signal vddx decreases to a certain extent as the voltage vsx of the second power supply signal vssx decreases, for example, it will exceed the minimum limit of the positive power supply voltage of the row decoder / word line driver 508, the second transistor M2 coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12 clamps the voltage vsx of the second power supply signal vssx. That is to say, when the voltage vsx of the second power supply signal vssx decreases, the source potential of the fourth transistor M4 also decreases. When it decreases to a certain extent, for example, when the voltage vsx of the second power supply signal vssx decreases to the first threshold ( Figure 14A the voltage indicated by character A in

[0098] Reference Figure 10 , in some embodiments, the second transistor M2 and the third transistor M3 are PMOS transistors; the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are NMOS transistors.

[0099] In some specific embodiments, the voltage vdx range of the drive voltage signal vddx is from the voltage (rf_l - vgs2) to the voltage (vsx + vgs4 - vgs3 + vdsat2). Figure 14B This is the second waveform diagram showing the variation of the drive voltage signal and the second power supply signal provided by the embodiments of the present application. Figure 15This is the simulation waveform diagram of the driving voltage signal and the change of the second power supply signal provided by the embodiment of the present application. With reference to Figure 10 , Figure 14B and Figure 15 , for example, when the voltage vsx of the second power supply signal vssx is zero, the voltage vdx of the driving voltage signal vddx is stabilized at the voltage (vsx + vgs4 - vgs3 + vdsat2). Wherein, the voltage vgs3 is the gate-source voltage vgs3 of the third transistor M3 (since the third transistor M3 is a PMOS transistor, the gate-source voltage vgs3 of the third transistor M3 is negative), the voltage vgs4 is the gate-source voltage vgs4 of the fourth transistor M4, and the voltage vdsat2 is the source-drain voltage vdsat2 when the second transistor M2 operates in the saturation region. When the voltage vsx of the second power supply signal vssx becomes more negative, the voltage vdx of the driving voltage signal vddx decreases linearly accordingly, and always maintains a voltage difference of (vgs4 - vgs3 + vdsat2) from the voltage vsx. When the voltage vdx of the driving voltage signal vddx decreases to a certain extent as the voltage vsx of the second power supply signal vssx decreases, for example, when the voltage vsx of the second power supply signal vssx decreases to the first threshold ( Figure 14B the voltage indicated by the character A in

[0100] ), it will exceed the minimum limit of the positive power supply voltage of the row decoder / word line driver 508, and the second transistor M2 coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12 forms a clamp on the voltage vsx of the second power supply signal vssx. That is to say, when the voltage vsx of the second power supply signal vssx decreases, the source potential of the fourth transistor M4 also decreases accordingly. When it decreases to a certain extent, for example, when it exceeds the minimum limit of the positive power supply voltage of the row decoder / word line driver 508, the second transistor M2 enters the saturation region, and the voltage vdx of the driving voltage signal vddx is clamped at the potential of the voltage (rf_l - vgs2), where the voltage vgs2 is the gate-source voltage vgs2 of the second transistor M2. Since the second transistor M2 is a PMOS transistor, the gate-source voltage vgs2 of the second transistor M2 is negative. Among them, the first power supply signal vcc is used as the positive power supply, and the voltage of the second power supply signal vssx can vary between the voltage vsn and the voltage vs (the voltage vs of the ground voltage signal vss). For example, the voltage vs represents zero volts, and the voltage vsn represents a negative voltage less than 0.

[0101] Hereinafter, the current mirror 14 shown in Figure 10 is taken as an example for detailed description. Figure 10The current mirror 14 shown is not used to limit the power generation circuit 10 of the present application.

[0102] Reference Figure 11 , in some embodiments, the memory device further includes a discharge circuit 18; a first end of the discharge circuit 18 is coupled to an output end of the first transistor M1, a second end of the discharge circuit 18 receives a ground voltage signal vss, and the discharge circuit 18 is configured to: receive a second control signal ref_h at a control end, and when a voltage vdx of the driving voltage signal vddx is greater than a second threshold, discharge to make the voltage vdx of the driving voltage signal vddx drop to a second voltage; when the voltage vdx of the driving voltage signal vddx is less than or equal to the second threshold, stop discharging; wherein, the second voltage is greater than the first voltage.

[0103] Here, the voltage vs of the ground voltage signal vss can be zero volts. Here, the voltage rf_h of the second control signal ref_h is a fixed bias voltage. In some specific embodiments, both the voltage rf_l of the first control signal ref_l and the voltage rf_h of the second control signal ref_h are fixed bias voltages; the voltage rf_h of the second control signal ref_h is greater than the voltage rf_l of the first control signal ref_l.

[0104] Exemplarily, when the voltage vdx of the driving voltage signal vddx is higher than a target value (the second threshold) due to certain reasons (such as a working state switch, noise, etc.), the discharge circuit 18 is turned on and discharges quickly through the discharge circuit 18. When approaching the target potential (the second voltage), the discharge circuit 18 is turned off, and the power generation circuit 10 switches to the normal working state.

[0105] Reference Figure 11 , in some embodiments, the discharge circuit 18 includes a seventh transistor M7; an input end of the seventh transistor M7 is coupled to the output end of the first transistor M1, an output end of the seventh transistor M7 receives the ground voltage signal, a control end of the seventh transistor M7 receives the second control signal, and when the voltage of the driving voltage signal vddx is greater than the second threshold, the seventh transistor M7 is controlled to be turned on by the second control signal to discharge the voltage of the driving voltage signal vddx.

[0106] Exemplarily, when the voltage vdx of the driving voltage signal vddx is higher than the second threshold due to certain reasons (such as a working state switch, noise, etc.), the seventh transistor M7 is turned on and discharges quickly through the seventh transistor M7. When approaching the second voltage, the seventh transistor M7 is turned off, and the power generation circuit 10 switches to the normal working state.

[0107] In some specific embodiments, the second threshold may be the voltage (rf_h + |vgs7|), where the voltage rf_h is the voltage rf_h of the second control signal ref_h, and the voltage vgs7 is the gate-source voltage of the seventh transistor M7.

[0108] In some specific embodiments, the voltage rf_h of the second control signal ref_h is greater than the voltage rf_l of the first control signal ref_l. When the voltage of the drive voltage signal vddx is greater than the second threshold, the seventh transistor M7 is turned on, and the second control signal controls the seventh transistor M7 to turn on so that the voltage of the drive voltage signal vddx discharges.

[0109] Reference Figure 12 , in some embodiments, the discharge circuit 18 further includes an eighth transistor M8 and a ninth transistor M9; the input end of the eighth transistor M8 is coupled to the output end of the seventh transistor M7, the output end of the eighth transistor M8 is coupled to the input end of the ninth transistor M9, and the control end of the eighth transistor M8 is coupled to the input end of the fourth transistor M4; the control end and the drain end of the ninth transistor M9 are connected, the input end of the ninth transistor M9 is coupled to the output end of the eighth transistor M8, and the output end of the ninth transistor M9 receives a ground voltage signal; wherein, the magnitude of the discharge current is adjusted by adjusting the proportional relationship between the sizes of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the sizes of the second transistor M2, the third transistor M3, the fourth transistor M4.

[0110] Exemplarily, by setting the transistor sizes of the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 to be in a ratio greater than 1 to the transistor sizes of the second transistor M2, the third transistor M3 and the fourth transistor M4, the discharge current in the discharge path of the discharge circuit 18 can be increased.

[0111] Reference Figure 12 , in some embodiments, the seventh transistor M7 and the eighth transistor M8 are PMOS transistors, and the ninth transistor M9 is an NMOS transistor; the second transistor M2 and the third transistor M3 are PMOS transistors, and the fourth transistor M4 is an NMOS transistor.

[0112] Exemplarily, by setting the transistor size of the seventh transistor M7 to be greater than the transistor size of the second transistor M2, the transistor size of the eighth transistor M8 to be greater than the transistor size of the third transistor M3, and the transistor size of the ninth transistor M9 to be greater than the transistor size of the fourth transistor M4, the discharge current in the discharge path of the discharge circuit 18 can be increased.

[0113] Reference Figure 13, in some embodiments, the memory cell array includes a plurality of memory blocks; the memory device further includes a control circuit 20; a first end of the control circuit 20 receives a first power signal vcc, a second end of the control circuit 20 is coupled to an output end of the transistor adjustment circuit 12, and the control circuit 20 is configured to: receive a memory block enable signal en_c, when the memory block enable signal en_c is in an enabled state, a connection between an output end of the control circuit 20 and the output end of the transistor adjustment circuit 12 is disconnected; when the memory block enable signal en_c is in a disabled state, a connection between an output end of the control circuit 20 and the first power signal vcc is connected; when the memory block enable signal en_c is in an enabled state, it indicates that the corresponding memory block is the selected memory block.

[0114] The function of the control circuit 20 is to determine whether the power generation circuit 10 works or not according to whether the memory block enable signal en_c is in an enabled state or a disabled state. For example, when the memory block enable signal en_c is in a disabled state, a connection between an output end of the control circuit 20 and the first power signal vcc is connected, and the driving voltage signal vddx is pulled up to the first power signal vcc, which can determine that the power generation circuit 10 is in a non-working state.

[0115] Figure 16 This is a simulation waveform diagram of the change of the driving voltage signal when the memory block enable signal state in the embodiment of the present application is switched. With reference to Figure 13 and Figure 16 , in some specific implementations, when the memory block enable signal en_c switches between an enabled state and a disabled state, when the voltage vdx of the driving voltage signal vddx is higher than a second threshold, both the control circuit 20 and the discharge circuit 18 can increase the discharge path for the voltage vdx of the driving voltage signal vddx.

[0116] In some embodiments, the control circuit 20 includes a tenth transistor M10; a control end of the tenth transistor M10 receives the memory block enable signal, an input end of the tenth transistor M10 receives the first power signal vcc, and an output end of the tenth transistor M10 is coupled to an output end of the first transistor M1.

[0117] Exemplarily, when the memory block enable signal en_c is in an enabled state, the tenth transistor M10 is turned off, and a connection between an output end of the tenth transistor M10 and the first power signal vcc is disconnected, determining that the power generation circuit 10 is in a working state; when the memory block enable signal en_c is in a disabled state, the tenth transistor M10 is turned on, and a connection between an output end of the tenth transistor M10 and the first power signal vcc is connected, and the driving voltage signal vddx is pulled up to the first power signal vcc, determining that the power generation circuit 10 is in a non-working state.

[0118] In some embodiments, the tenth transistor M10 is a PMOS transistor.

[0119] Exemplarily, when the storage block enable signal en_c is in a logic high level state (logic state "1"), the tenth transistor M10 is turned off, and the connection between the output terminal of the tenth transistor M10 and the first power supply signal vcc is disconnected, determining that the power generation circuit 10 is in an operating state; when the storage block enable signal en_c is in a logic low level state (logic state "0"), the tenth transistor M10 is turned on, and the connection between the output terminal of the tenth transistor M10 and the first power supply signal vcc is connected, and the driving voltage signal vddx is pulled up to the first power supply signal vcc, determining that the power generation circuit 10 is in a non-operating state.

[0120] In some embodiments, the peripheral circuit further includes a row decoding circuit; the second power supply signal vssx is configured to provide a negative power supply for the row decoding circuit (refer to the row decoder / word line driver 508 shown in Figure 5 ), and the driving voltage signal vddx is configured to provide a positive power supply for the row decoding circuit.

[0121] In the embodiments of the present application, the power generation circuit 10 adopts a local feedback part composed of a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12: the 'ground' (the second power supply signal vssx) of the local feedback part is connected to the negative power supply of the row decoding circuit, and the 'power supply' (the driving voltage signal vddx) of the local feedback part is connected to the positive power supply of the row decoding circuit, so that the voltage vdx of the output driving voltage signal vddx can float up and down with the negative power supply, compensating for the problem that the voltage vdx of the driving voltage signal vddx changes too much, the voltage difference between the positive power supply and the negative power supply is too large, and the row decoding circuit exceeds the specified safe operating area (SOA). In the embodiments of the present application, the power generation circuit 10 adopts a clamping part composed of a clamping circuit 16 coupled between the first end of the current mirror 14 and the output terminal of the transistor adjustment circuit 12: when the negative power supply is too low, the voltage vdx of the driving voltage signal vddx drops significantly with the negative power supply, which will cause the row decoding circuit connected thereto to not flip correctly. The function of the clamping circuit is to ensure the stable output of the driving voltage signal vddx of the power generation circuit 10 when the negative power supply is too low.

[0122] In some embodiments, the memory device of any one of the above embodiments includes a NAND-type memory.

[0123] In the peripheral circuit of a 3D NAND flash memory, due to the limitations of the Erase Program or Read (EPR) operation, the negative power supply of the row decoder circuit varies within the range from zero to a more negative value. Since the row decoder circuit can accept a positive power supply that varies within a certain range, on the premise of ensuring the correct operation of the row decoder circuit, a local feedback method or a method combining local feedback and voltage clamping can be adopted to make the power supply generation circuit generate a driving voltage signal that varies within a certain range with the voltage change of the second power signal, that is, output an appropriate driving voltage.

[0124] Reference Figure 1 , In a second aspect, an embodiment of the present application provides a memory system 102, which includes: one or more memory devices 104 as described in any one of the embodiments of the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0125] Exemplarily, with reference Figure 1 and Figure 13 , the memory device 104 includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power supply generation circuit; the power supply generation circuit includes: a bias current source, connected to both a current mirror and a transistor adjustment circuit, and configured to: receive a first power signal and keep the sum of the output current of the current mirror and the control current of the transistor adjustment circuit stable; a current mirror, connected to the transistor adjustment circuit, and configured to: receive and respond to the voltage change of a second power signal and output a changing current to make the control current of the transistor adjustment circuit change; the voltage of the first power signal is greater than the voltage of the second power signal; a transistor adjustment circuit, configured to: receive the first power signal and generate a driving voltage signal that varies within a certain range with the voltage change of the second power signal under the adjustment of the changing control current.

[0126] Third aspect, embodiments of the present application provide an operation method for a memory device. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power generation circuit; the power generation circuit includes a bias current source Iref, a current mirror 14, and a transistor adjustment circuit 12 that are coupled to each other; the operation method includes: the bias current source Iref receives a first power supply signal vcc and keeps the sum of the output current of the current mirror 14 and the control current of the transistor adjustment circuit 12 stable; the current mirror 14 receives and responds to the voltage change of a second power supply signal vssx, and outputs a varying current to cause the control current of the transistor adjustment circuit 12 to change; the voltage of the first power supply signal vcc is greater than the voltage of the second power supply signal vssx; the transistor adjustment circuit 12 receives the first power supply signal vcc and generates a driving voltage signal vddx that varies within a certain range with the voltage change of the second power supply signal vssx under the adjustment of the changing control current.

[0127] In some embodiments, the power generation circuit 10 further includes a clamping circuit 16 coupled between the first end of the current mirror 14 and the output end of the transistor adjustment circuit 12. The operation method includes: the control end of the clamping circuit 16 receives a first control signal ref_l. When the voltage of the second power supply signal vssx is less than or equal to a first threshold, the clamping circuit 16 clamps the voltage of the driving voltage signal vddx at a first voltage.

[0128] In some embodiments, the clamping circuit 16 includes a second transistor M2. The operation method includes: the control end of the second transistor M2 receives the first control signal ref_l. When the voltage of the second power supply signal vssx is less than or equal to the first threshold, by controlling the second transistor M2 to be in the saturation state, the voltage of the driving voltage signal vddx is clamped at the first voltage; when the voltage of the second power supply signal vssx is greater than the first threshold, by controlling the second transistor M2 to be in the amplification state, the voltage of the driving voltage signal vddx increases with the increase of the second power supply signal vssx; when the voltage of the second power supply signal vssx is equal to the voltage of the ground voltage signal, the voltage of the driving voltage signal vddx is stabilized at a second voltage; the second voltage is greater than the first voltage.

[0129] The memory device used in the operation method for the memory device provided in each embodiment of the third aspect of the present application is the same as or similar to the memory device in each embodiment of the above first aspect. For technical features not detailedly disclosed in the embodiments of the present application, please refer to the memory device in each embodiment of the above first aspect for understanding, and details are not described herein again.

[0130] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0131] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A memory device, characterized in that, it includes: a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power generation circuit; the power generation circuit includes: a bias current source, connected to both a current mirror and a transistor adjustment circuit, and configured to: receive a first power signal and keep the sum of the output current of the current mirror and the control current of the transistor adjustment circuit stable; the current mirror, connected to the transistor adjustment circuit, and configured to: receive and respond to a voltage change of a second power signal, output a varying current to cause the control current of the transistor adjustment circuit to change; the voltage of the first power signal is greater than the voltage of the second power signal; the transistor adjustment circuit, configured to: receive the first power signal and generate a driving voltage signal that varies within a certain range with the voltage change of the second power signal under the adjustment of the changing control current.

2. The memory device according to claim 1, characterized in that, the first end of the bias current source receives the first power signal, and the second end of the bias current source is coupled to both the second end of the current mirror and the control end of the transistor adjustment circuit; the first end of the current mirror is coupled to the output end of the transistor adjustment circuit, the second end of the current mirror is coupled to the control end of the transistor adjustment circuit, and the third end of the current mirror receives the second power signal; the input end of the transistor adjustment circuit receives the first power signal.

3. The memory device according to claim 2, characterized in that, the power generation circuit further includes a clamping circuit, coupled between the first end of the current mirror and the output end of the transistor adjustment circuit, and configured to: receive a first control signal at the control end, and when the voltage of the second power signal is less than or equal to a first threshold, clamp the voltage of the driving voltage signal at a first voltage.

4. The memory device according to claim 3, characterized in that, the transistor adjustment circuit includes a first transistor, the control end of the first transistor is coupled to the second end of the bias current source, the input end of the first transistor receives the first power signal, and the output end of the first transistor outputs the driving voltage signal; the clamping circuit includes a second transistor; the input end of the second transistor is coupled to the output end of the first transistor, the output end of the second transistor is coupled to the first end of the current mirror, the control end of the second transistor receives the first control signal, and when the voltage of the second power signal is less than or equal to the first threshold, the second transistor is controlled to be in a saturation state through the first control signal so that the voltage of the driving voltage signal is clamped at the first voltage.

5. The memory device according to claim 4, characterized in that, the current mirror includes a first-stage current mirror and a second-stage current mirror; The input terminal of the first-stage current mirror is coupled to the output terminal of the first transistor through the second transistor, and the output terminal of the first-stage current mirror is coupled to the second terminal of the bias current source and the control terminal of the first transistor; Both the input terminal and the output terminal of the second-stage current mirror are coupled to the first-stage current mirror, and the common terminal of the second-stage current mirror receives the second power supply signal.

6. The memory device according to claim 5, wherein, The first-stage current mirror includes a third transistor and a sixth transistor with their control terminals and drain terminals connected; the second-stage current mirror includes a fourth transistor and a fifth transistor with their control terminals and drain terminals connected; The input terminal of the third transistor is coupled to the output terminal of the clamping circuit, and the output terminal of the third transistor is coupled to the input terminal of the fourth transistor; the output terminals of the fourth transistor and the fifth transistor both receive the second power supply signal; the control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor, and the input terminal of the fifth transistor is coupled to the output terminal of the sixth transistor; the input terminal of the sixth transistor is coupled to the second terminal of the bias current source and the control terminal of the first transistor.

7. The memory device according to claim 6, wherein, The second transistor and the third transistor are PMOS transistors; the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

8. The memory device according to claim 6, wherein, The memory device further includes a discharge circuit; The first terminal of the discharge circuit is coupled to the output terminal of the first transistor, the second terminal of the discharge circuit receives the ground voltage signal, and the discharge circuit is configured to: receive a second control signal at the control terminal, when the voltage of the drive voltage signal is greater than a second threshold, discharge to make the voltage of the drive voltage signal drop to a second voltage; when the voltage of the drive voltage signal is less than or equal to the second threshold, stop discharging; wherein, the second voltage is greater than the first voltage.

9. The memory device according to claim 8, wherein, The discharge circuit includes a seventh transistor; The input terminal of the seventh transistor is coupled to the output terminal of the first transistor, the output terminal of the seventh transistor receives the ground voltage signal, the control terminal of the seventh transistor receives the second control signal, and when the voltage of the drive voltage signal is greater than the second threshold, the seventh transistor is controlled to conduct by the second control signal to discharge the voltage of the drive voltage signal.

10. The memory device according to claim 9, wherein, The discharge circuit further includes an eighth transistor and a ninth transistor; The input terminal of the eighth transistor is coupled to the output terminal of the seventh transistor, the output terminal of the eighth transistor is coupled to the input terminal of the ninth transistor, and the control terminal of the eighth transistor is coupled to the input terminal of the fourth transistor; The control terminal and the drain terminal of the ninth transistor are connected. The input terminal of the ninth transistor is coupled to the output terminal of the eighth transistor, and the output terminal of the ninth transistor receives the ground voltage signal; Wherein, the magnitude of the discharge current is adjusted by adjusting the ratio relationship between the sizes of the seventh transistor, the eighth transistor, and the ninth transistor and the sizes of the second transistor, the third transistor, and the fourth transistor.

11. The memory device according to claim 10, wherein, the seventh transistor and the eighth transistor are PMOS transistors, and the ninth transistor is an NMOS transistor; the second transistor and the third transistor are PMOS transistors, and the fourth transistor is an NMOS transistor.

12. The memory device according to claim 4, wherein, the memory cell array includes a plurality of memory blocks; the memory device further includes a control circuit; a first end of the control circuit receives the first power signal, a second end of the control circuit is coupled to an output end of the transistor adjustment circuit, and the control circuit is configured to: receive a memory block enable signal. When the memory block enable signal is in an enabled state, the connection between the output end of the control circuit and the output end of the transistor adjustment circuit is disconnected; when the memory block enable signal is in a disabled state, the output end of the control circuit is connected to the first power signal; when the memory block enable signal is in an enabled state, it indicates that the corresponding memory block is the selected memory block.

13. The memory device according to claim 12, wherein, the control circuit includes a tenth transistor; the control terminal of the tenth transistor receives the memory block enable signal, the input terminal of the tenth transistor receives the first power signal, and the output terminal of the tenth transistor is coupled to the output terminal of the first transistor.

14. The memory device according to claim 13, wherein, the tenth transistor is a PMOS transistor.

15. The memory device according to claim 1, wherein, the peripheral circuit further includes a row decoding circuit; the second power signal is configured to provide a negative power supply for the row decoding circuit, and the drive voltage signal is configured to provide a positive power supply for the row decoding circuit.

16. The memory device according to any one of claims 1 to 15, wherein, the memory device includes a NAND type memory.

17. A memory system, wherein, comprises: one or more memory devices according to any one of claims 1 to 16; and a memory controller, which is coupled to the memory device and controls the memory device.

18. An operation method of a memory device, wherein, the memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes a power generation circuit; the power generation circuit includes a bias current source, a current mirror, and a transistor adjustment circuit that are coupled to each other; the operation method includes: The bias current source receives a first power signal and keeps stable the sum of the output current of the current mirror and the control current of the transistor adjustment circuit; The current mirror receives and responds to a voltage change of a second power signal and outputs a varying current to cause a change in the control current of the transistor adjustment circuit; the voltage of the first power signal is greater than the voltage of the second power signal; The transistor adjustment circuit receives the first power signal and, under the adjustment of the changing control current, generates a drive voltage signal that varies within a certain range with the voltage change of the second power signal.

19. The operation method according to claim 18, wherein, the power generation circuit further includes a clamping circuit coupled between a first end of the current mirror and an output end of the transistor adjustment circuit, and the operation method includes: a control end of the clamping circuit receives a first control signal, and when the voltage of the second power signal is less than or equal to a first threshold, the clamping circuit clamps the voltage of the drive voltage signal at a first voltage.

20. The operation method according to claim 19, wherein, the clamping circuit includes a second transistor; the operation method includes: a control end of the second transistor receives the first control signal, and when the voltage of the second power signal is less than or equal to the first threshold, by controlling the second transistor to be in a saturation state, the voltage of the drive voltage signal is clamped at the first voltage; when the voltage of the second power signal is greater than the first threshold, by controlling the second transistor to be in an amplification state, the voltage of the drive voltage signal increases as the second power signal increases; when the voltage of the second power signal is equal to the voltage of the ground voltage signal, the voltage of the drive voltage signal is stabilized at a second voltage; the second voltage is greater than the first voltage.

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