A driving circuit compatible with monostable and magnetic latching relays and its implementation method

Abstract

The present invention relates to a driving circuit and implementation method compatible with monostable and magnetic latching relays, comprising a CPU, a CPLD logic control module and a storage module. The CPU and the storage module are connected to each other via SPI / I2C, the CPU and the CPLD logic control module are connected via a localbus channel, and the CPLD logic control module is connected to multiple relays via different interfaces of a relay driver chip. The control logic version is compatible with the control logic of monostable and magnetic latching relays, and can quickly respond to different customer needs. When using a magnetic latching relay, the user can set the default state of the device relay to be energized or reset and released. For the user-end operating experience, there is no perception of whether the operation is a magnetic latching relay or a monostable relay. A trade-off can be made between reducing the static power consumption of the entire machine and reducing costs, which can effectively reduce the cost of the equipment. On devices with logic devices such as CPLD and FPGA, there is no need to add an additional MCU to control the relay.

Description

Technical Field

[0001] The present invention belongs to the technical field of communication logic control, and in particular relates to a driving circuit compatible with monostable and magnetic latching relays and an implementation method thereof. Background Art

[0002] In the current communications industry and other fields, many devices require relays for signal switching and interface switching. Relay selection requires either a monostable relay, which is relatively low-cost but has high static power consumption, or a more expensive latching relay. Different customers have different requirements (some require latching relays, others require monostable relays), requiring different software control logic versions (the control logic of the two relays differs). This increases version development and management costs, and can hinder timely delivery of the device to customers. Furthermore, most relays currently use an MCU for switching control. Adding an additional MCU specifically for relay switching control to devices already equipped with logic devices undoubtedly increases equipment costs.

[0003] Therefore, the present invention intends to provide a driving circuit and implementation method that is compatible with monostable and magnetic latching relays, using a logic device as the main control of the driving circuit and implementation method that is compatible with monostable and magnetic latching relays, and the control logic uses the same version. Summary of the Invention

[0004] The purpose of the present invention is to provide a driving circuit and implementation method compatible with monostable and magnetic latching relays, which use logic devices as the main control of the driving circuit and implementation method compatible with monostable and magnetic latching relays, and the control logic uses the same version.

[0005] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0006] In a first aspect, a drive circuit compatible with monostable and magnetic latching relays is provided, comprising a CPU, a CPLD logic control module and a storage module, wherein the CPU and the storage module are communicatively connected via SPI / I2C, the CPU and the CPLD logic control module are connected via a Localbus channel, the CPLD logic control module is connected to multiple relays via different interfaces of a relay driver chip, and the CPLD logic control module is further connected to a relay switching indicator light.

[0007] Preferably, it further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a capacitor, the A port and the B port of the relay driver chip are respectively connected to the CPLD-A port and the CPLD-B port of the CPLD logic control module through the first resistor and the second resistor, the OA port and the OB port of the relay driver chip are respectively connected to the two ports of the magnetic latching relay through the fourth resistor and the fifth resistor, the VCC port of the relay driver chip is grounded through the capacitor, the fourth resistor is grounded through the third resistor, and the fifth resistor is grounded through the sixth resistor.

[0008] In the second aspect, a method for implementing a driving circuit compatible with monostable and magnetic latching relays is provided, which includes a magnetic latching relay control implementation method and a monostable relay control implementation method based on the aforementioned driving circuit implementation compatible with monostable and magnetic latching relays.

[0009] Preferably, the magnetic latching relay control implementation method includes four states of the magnetic latching relay, namely release reset, reset hold, energized conduction, and conduction hold. When the power is turned on and switched to the energized state, it can be switched to the energized state hold. When the power is turned off and released and reset, it can be switched to the reset state hold. No matter whether the relay enters the energized hold state or the reset hold state, no current flows through the relay. Current only flows through the relay during action switching, thereby reducing the static power consumption of the equipment.

[0010] Preferably, the restoration maintenance implementation process is:

[0011] After the system is powered on, the magnetic latching relay is set to the reset state or the pull-in conduction state, and the reset state or the pull-in conduction state is written into the storage module external to the CPU as the judgment condition for the relay status light on the next power-on;

[0012] When the reset state is in hold state, the user operates the register of the CPLD logic control module in the operation interface, that is, inputs CPLD A:B=0:1, and the underlying software of the CPLD logic control module writes A:B=0:1 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD, and at the same time backs up A:B=0:1 to the storage medium. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the reset action, and then after a specified delay, the CPLD logic control module executes A:B=0:0 to maintain the reset state; at this time, the power consumption of the relay is 0, and current flows through the two ends of the relay only when the relay is switched; at the same time, the CPLD logic control module The block outputs a low level of 0, and the relay status light is on. Since the reset state is maintained, it will be maintained after power failure, and it will be in the reset state when it is powered on next time. When the software is loaded on the next time, it first reads the relay status value stored last time from the storage module, and then writes the relay status value to the relay control register of the CPLD logic control module when loading. The CPLD logic control module assigns the register value to the CPLD pin to reset all relays. After a specified delay, A:B=0:0 is executed on the CPLD to maintain the reset state. At this time, the relay status lighting judgment condition is directly determined in the logic code to judge the assignment of A and B.

[0013] Preferably, the process of achieving the pull-in conduction state is:

[0014] The user operates the register of the CPLD logic control module in the operation interface and inputs A:B=1:0 into the CPLD logic control module. The underlying software writes A:B=1:0 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD logic control module, and at the same time backs up A:B=1:0 to the storage module. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the pull-in action. Then, after a specified delay, the CPLD executes A:B=1:1 to maintain the pull-in state. At this time, the power consumption of the relay is 0. Current flows through the two ends of the relay only at the moment the relay switches. At the same time, C The PLD logic control module outputs a high level of 1, and the relay status light goes out at this time; since it maintains the energized state, it will remain so even after power failure, and will also be in the energized state when powered on next time. When powered on next time and loaded, the last stored relay status value will be read from the storage medium first, and then the relay status value will be written to the relay control register of the CPLD logic control module when loading. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make all relays energize. After a specified delay, A:B=1:1 is executed on the CPLD logic control module to maintain the energized state. At this time, the relay status lighting judgment condition is directly determined in the logic code to judge the assignment of A and B.

[0015] Preferably, the monostable relay control implementation method is as follows:

[0016] The monostable relay has an armature structure inside. Once the device is powered off, the armature is released and the relay will reset. The default state is the reset state, that is: CPLD A:B=0:0. At this time, the relay status indicator is on. When the user enters the conduction command on the operation interface, that is, the relay is attracted, CPLD A:B=1:0, the relay is attracted and enters the conduction mode. At this time, the relay status indicator is off. Since the control logic is the same as that of the magnetic latching relay, the series resistance of the control B terminal is removed, so that the control B terminal is directly grounded to realize the closing and conducting of the monostable relay.

[0017] The beneficial effects of the present invention include:

[0018] The present invention provides a drive circuit and implementation method that is compatible with monostable and magnetic latching relays, including a CPU, a CPLD logic control module, and a storage module. The CPU and the storage module are connected to each other via SPI / I2C, the CPU and the CPLD logic control module are connected via a Localbus channel, and the CPLD logic control module is connected to multiple relays via different interfaces of a relay driver chip. The control logic version is compatible with the control logic of monostable and magnetic latching relays, and can quickly respond to different customer needs. When using a magnetic latching relay, the user can set the default state of the device relay to be energized or reset and released. For the user-side operating experience, there is no perception of whether the operation is a magnetic latching relay or a monostable relay. A trade-off can be made between reducing the static power consumption of the entire machine and reducing costs, which can effectively reduce the cost of the equipment. On devices with logic devices such as CPLD and FPGA, there is no need to add an additional MCU to control the relay. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the overall architecture of the drive circuit for the compatible monostable and latching relays of the present invention.

[0020] Figure 2 Schematic diagram of the magnetic latching relay driving circuit of the present invention.

[0021] Reference numerals: R1 is a first resistor, R2 is a second resistor, R3 is a third resistor, R4 is a fourth resistor, R5 is a fifth resistor, R6 is a sixth resistor, C is a capacitor, and U is a relay driver chip. DETAILED DESCRIPTION

[0022] The following is combined with Figure 1~Figure 2 The present invention is described in further detail:

[0023] Example 1

[0024] See attached Figure 1 As shown, a drive circuit compatible with monostable and magnetic latching relays includes a CPU, a CPLD logic control module and a storage module. The CPU and the storage module are connected to each other via SPI / I2C, the CPU and the CPLD logic control module are connected via a Localbus channel, the CPLD logic control module is connected to multiple relays via different interfaces of a relay driver chip U, and the CPLD logic control module is also connected to a relay switching indicator light.

[0025] In the current communications industry and other fields, many devices require relays for signal switching and interface switching. Relay selection requires either a monostable relay (lower cost but higher static power consumption) or a more expensive magnetic latching relay. Different customers have different needs, requiring different software control logic versions. This leads to increased version development and management costs, and delays in delivering the device to customers. Furthermore, most relays currently use an MCU for switching control. Adding an additional MCU specifically for relay switching control to devices already equipped with logic devices undoubtedly increases equipment costs.

[0026] Therefore, the present invention provides a driving circuit compatible with monostable and magnetic latching relays, a driving circuit method using a logic device as a master controller compatible with monostable and magnetic latching relays, and a control logic using the same version compatible with monostable and magnetic latching relays. No matter which relay is used, only one version needs to be used, which is convenient for the management and maintenance of subsequent versions. It can meet different customer needs. When using a magnetic latching relay, the user can set the default state of the device relay to be energized or reset and released. For the user-side operation experience, there is no perception of whether the operation is a magnetic latching relay or a monostable relay. A trade-off can be made between reducing the static power consumption of the entire machine and reducing costs, which can effectively reduce the cost of the equipment. On devices with logic devices such as CPLD and FPGA, there is no need to add an additional MCU to control the relay.

[0027] See also Figure 2 The drive circuit compatible with monostable and magnetic latching relays also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a capacitor C. The A port and B port of the relay driver chip U are respectively connected to the CPLD-A port and CPLD-B port of the CPLD logic control module through the first resistor R1 and the second resistor R2, respectively. The OA port and OB port of the relay driver chip U are respectively connected to the two ports of the magnetic latching relay through the fourth resistor R4 and the fifth resistor R5. The VCC port of the relay driver chip U is grounded through the capacitor C, the fourth resistor R4 is grounded through the third resistor R3, and the fifth resistor R5 is grounded through the sixth resistor R6.

[0028] Example 2

[0029] On the basis of Example 1, a method for implementing a drive circuit compatible with a monostable and a magnetic latching relay is provided, based on the aforementioned drive circuit implementation compatible with a monostable and a magnetic latching relay, including a magnetic latching relay control implementation method and a monostable relay control implementation method.

[0030] The magnetic latching relay control implementation method includes four states of the magnetic latching relay, namely, release reset, reset hold, energized conduction, and conduction hold. When the power is switched to the energized state, it can be switched to the energized state hold. When the power is released and reset, it can be switched to the reset state hold. No matter whether the relay enters the energized hold state or the reset hold state, no current flows through the relay. Current only flows through the relay during action switching, thereby reducing the static power consumption of the equipment.

[0031]

[0032] The restoration maintenance implementation process is as follows:

[0033] After the system is powered on, the magnetic latching relay is set to the reset state or the pull-in conduction state, and the reset state or the pull-in conduction state is written into the storage module external to the CPU as the judgment condition for the relay status light on the next power-on;

[0034] When the reset state is in hold state, the user operates the register of the CPLD logic control module in the operation interface, that is, inputs CPLD A:B=0:1, and the underlying software of the CPLD logic control module writes A:B=0:1 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD, and at the same time backs up A:B=0:1 to the storage medium. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the reset action, and then after a specified delay, the CPLD logic control module executes A:B=0:0 to maintain the reset state; at this time, the power consumption of the relay is 0, and current flows through the two ends of the relay only when the relay is switched; at the same time, the CPLD logic control module The block outputs a low level of 0, and the relay status light is on. Since the reset state is maintained, it will be maintained after power failure, and it will be in the reset state when it is powered on next time. When the software is loaded on the next time, it first reads the relay status value stored last time from the storage module, and then writes the relay status value to the relay control register of the CPLD logic control module when loading. The CPLD logic control module assigns the register value to the CPLD pin to reset all relays. After a specified delay, A:B=0:0 is executed on the CPLD to maintain the reset state. At this time, the relay status lighting judgment condition is directly determined in the logic code to judge the assignment of A and B.

[0035] The process of achieving the pull-in conduction state is:

[0036] The user operates the register of the CPLD logic control module in the operation interface and inputs A:B=1:0 into the CPLD logic control module. The underlying software writes A:B=1:0 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD logic control module, and at the same time backs up A:B=1:0 to the storage module. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the pull-in action. Then, after a specified delay, the CPLD executes A:B=1:1 to maintain the pull-in state. At this time, the power consumption of the relay is 0. Current flows through the two ends of the relay only at the moment the relay switches. At the same time, C The PLD logic control module outputs a high level of 1, and the relay status light goes out at this time; since it maintains the energized state, it will remain so even after power failure, and will also be in the energized state when powered on next time. When powered on next time and loaded, the last stored relay status value will be read from the storage medium first, and then the relay status value will be written to the relay control register of the CPLD logic control module when loading. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make all relays energize. After a specified delay, A:B=1:1 is executed on the CPLD logic control module to maintain the energized state. At this time, the relay status lighting judgment condition is directly determined in the logic code to judge the assignment of A and B.

[0037] The monostable relay control is implemented as follows:

[0038] The monostable relay has an armature structure inside. Once the device is powered off, the armature is released and the relay will reset. The default state is the reset state, that is: CPLD A:B=0:0. At this time, the relay status indicator is on. When the user enters the conduction command on the operation interface, that is, the relay is attracted, CPLD A:B=1:0, the relay is attracted and enters the conduction mode. At this time, the relay status indicator is off. Since the control logic is the same as that of the magnetic latching relay, the series resistance of the control B terminal is removed, so that the control B terminal is directly grounded to realize the closing and conducting of the monostable relay.

[0039] In summary, the present invention provides a drive circuit and implementation method that is compatible with monostable and magnetic latching relays, including a CPU, a CPLD logic control module, and a storage module. The CPU and the storage module are connected to each other via SPI / I2C, the CPU and the CPLD logic control module are connected via a Localbus channel, and the CPLD logic control module is connected to multiple relays via different interfaces of the relay driver chip U. The control logic version is compatible with the control logic of monostable and magnetic latching relays, and can quickly respond to different customer needs. When using a magnetic latching relay, the user can set the default state of the device relay to be energized or reset to release. For the user-side operating experience, there is no perception of whether the operation is a magnetic latching relay or a monostable relay. A trade-off can be made between reducing the static power consumption of the entire machine and reducing costs, which can effectively reduce the cost of the equipment. On devices with logic devices such as CPLD and FPGA, there is no need to add an additional MCU to control the relay.

Claims

1. A drive circuit compatible with monostable and magnetic latching relays, characterized in that: The system comprises a CPU, a CPLD logic control module and a storage module. The CPU and the storage module are connected to each other via SPI / I2C communication. The CPU and the CPLD logic control module are connected via a Localbus channel. The CPLD logic control module is connected to multiple relays via different interfaces of a relay driver chip. The CPLD logic control module is also connected to a relay switching indicator light. The drive circuit compatible with the monostable and magnetic latching relays realizes a magnetic latching relay control method and a monostable relay control method. The magnetic latching relay control method includes four states of the magnetic latching relay, namely, release reset, reset hold, pull-in conduction, and conduction hold; The restoration maintenance implementation process is as follows: After the system is powered on, the magnetic latching relay is set to the reset state or the pull-in conduction state, and the reset state or the pull-in conduction state is written into the storage module external to the CPU as the judgment condition for the relay status light on the next power-on; When the reset state is in hold state, the user operates the register of the CPLD logic control module in the operation interface, that is, inputs CPLD A:B=0:1, and the underlying software of the CPLD logic control module writes A:B=0:1 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD, and at the same time backs up A:B=0:1 to the storage medium. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the reset action, and then after a specified delay, the CPLD logic control module executes A:B=0:0 to maintain the reset state; at this time, the power consumption of the relay is 0, and current flows through the two ends of the relay only when the relay is switched; at the same time, the CPLD logic control module The block outputs a low level of 0, and the relay status light is on. Since the reset state is maintained, it will be maintained even after power failure, and will be in the reset state the next time it is powered on. When the software is loaded on the next time, it first reads the relay status value stored last time from the storage module, and then writes the relay status value to the relay control register of the CPLD logic control module when loading. The CPLD logic control module assigns the register value to the CPLD pin to reset all relays. After a specified delay, A:B=0:0 is executed on the CPLD to maintain the reset state. At this time, the relay status light judgment condition is directly determined in the logic code to judge the assignment of A and B. The process of achieving the pull-in conduction state is: The user operates the register of the CPLD logic control module in the operation interface and inputs A:B=1:0 into the CPLD logic control module. The underlying software writes A:B=1:0 to the relay control register of the CPLD logic control module through the Localbus channel from the CPU to the CPLD logic control module, and at the same time backs up A:B=1:0 to the storage module. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make the relay perform the pull-in action. Then, after a specified delay, the CPLD executes A:B=1:1 to maintain the pull-in state. At this time, the power consumption of the relay is 0. Current flows through the two ends of the relay only at the moment the relay switches. At the same time, C The PLD logic control module outputs a high level of 1, and the relay status light goes out at this time. Since the state is maintained, it will be maintained even after power failure, and will be in the energized state the next time the power is turned on. When the power is turned on next time and loaded, the last stored relay state value is first read from the storage medium, and then the relay state value is written to the relay control register of the CPLD logic control module during loading. The CPLD logic control module assigns the register value to the pin of the CPLD logic control module to make all relays energize. After a specified delay, the CPLD logic control module executes A:B=1:1 to maintain the energized state. At this time, the relay status lighting judgment condition is directly determined in the logic code to judge the assignment of A and B. The monostable relay control implementation method is as follows: The interior of the monostable relay is an armature structure. When the device is powered off, the armature is released and the relay is reset. The default state is reset, that is, CPLD A:B=0:

0. At this time, the relay status indicator is on. When the user enters the conduction command in the operation interface, that is, the relay is attracted, CPLD A:B=1:0, the relay is attracted and enters the conduction mode. At this time, the relay status indicator is off. Since the control logic is the same as the magnetic latching relay control method, the series resistance of the control B terminal is removed, so that the control B terminal is directly grounded to realize the closing and conducting of the monostable relay.

2. A driving circuit compatible with monostable and magnetic latching relays according to claim 1, characterized in that: It also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a capacitor. The A port and the B port of the relay driver chip are respectively connected to the CPLD-A port and the CPLD-B port of the CPLD logic control module through the first resistor and the second resistor. The OA port and the OB port of the relay driver chip are respectively connected to the two ports of the magnetic latching relay through the fourth resistor and the fifth resistor. The VCC port of the relay driver chip is grounded through the capacitor, the fourth resistor is grounded through the third resistor, and the fifth resistor is grounded through the sixth resistor.

3. The drive circuit compatible with monostable and magnetic latching relays according to claim 1, characterized in that: When the power is turned on and the relay is switched to the energized state, it can be switched to the maintained energized state. When the power is turned off and the relay is released, it can be switched to the maintained state. No matter the relay enters the energized maintained state or the reset maintained state, no current flows through the relay. When the relay is switched, current flows through the relay, which reduces the static power consumption of the equipment.

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