A method for avoiding delamination in an embedded wafer-level ball grid array bonding process

Abstract

The present invention discloses a method for avoiding delamination in an embedded wafer-level ball grid array bonding process, and the method comprises the following steps: providing a carrier wafer, grinding a first surface of the carrier wafer for carrying chips to make it flat; after cleaning, performing plasma etching on the first surface; and sputtering a stainless steel layer on the first surface after plasma etching; providing a substrate wafer, mounting the chips on the surface of the substrate wafer; and covering all the chips and the surface of the substrate wafer with a resin adhesive; covering the carrier wafer onto the substrate wafer, making the stainless steel layer contact the resin adhesive, and using a pressing device to apply pressure so that the stainless steel layer of the carrier wafer and the resin adhesive of the substrate wafer are bonded; peeling off the substrate wafer to obtain a recombined wafer structure with the active surface of the chips exposed. The method provided by the present invention can greatly improve the bonding force between the carrier wafer and the film-like resin after bonding in the eWLB packaging operation process, and avoid the occurrence of abnormalities in the subsequent operation process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a method for avoiding delamination in an embedded wafer-level ball grid array bonding process. Background Art

[0002] With the development of semiconductor technology, embedded wafer-level ball grid array (eWLB, Embedded Wafer Level Ball Grid Array) has gradually replaced wire bonding packaging as a relatively common packaging method. The embedded wafer-level ball grid array technology is to reposition the chip onto an artificial wafer, then fan out the redistribution lines, implant balls around the chip, and then perform packaging. The size of the packaged chip is exactly the same as that of the bare die, meeting the market requirements for the increasingly light, small, short, thin, and low-cost microelectronic products.

[0003] In the packaging of the embedded wafer-level ball grid array eWLB, a bonding process is used. The wafer bonding process is as follows: First, a group of wafers to be bonded are pretreated, cleaned, and visually aligned, and then the wafers are bonded by different methods.

[0004] In the existing film-type e-WLB packaging, silicon wafers are generally used for bonding during the bonding process, that is, the bonding process is completed by bonding the carrier wafer with the film-type resin glue. However, after the carrier wafer is bonded with the film-type resin glue, delamination problems will occur due to the erosion of chemical agents during the subsequent operation process, such as the water bubble operation with relatively high humidity, which will inevitably affect the subsequent operation.

[0005] Therefore, there is an urgent need to provide a method for avoiding delamination in the embedded wafer-level ball grid array bonding process. Summary of the Invention

[0006] In order to solve the above problems, the present invention provides a method for avoiding delamination in the embedded wafer-level ball grid array bonding process, which can greatly improve the bonding force between the carrier wafer and the film-type resin after bonding in the eWLB packaging operation process and avoid the occurrence of abnormalities during the subsequent operation process.

[0007] In a first aspect, the present invention discloses a method for avoiding delamination in an embedded wafer-level ball grid array bonding process, the method comprising the following steps:

[0008] S1. Provide a carrier wafer for carrying a chip in the bonding process, grind the first surface of the carrier wafer for carrying the chip to make it flat; after cleaning, perform plasma etching on the first surface; and sputter a stainless steel layer on the first surface after plasma etching;

[0009] S2. Provide a substrate wafer for bonding with a carrier wafer, attach multiple chips to the surface of the substrate wafer with the active surfaces of the chips facing the surface of the substrate wafer; and cover all the chips and the surface of the substrate wafer with resin glue.

[0010] S3. Cover the carrier wafer onto the substrate wafer, with the stainless steel layer contacting the resin glue, and use a pressing device to apply pressure to bond the stainless steel layer of the carrier wafer and the resin glue of the substrate wafer.

[0011] S4. Peel off the substrate wafer to obtain a reorganized wafer structure with the active surfaces of the chips exposed.

[0012] In some embodiments, in step S1, a layer of stainless steel is sputtered comprehensively and evenly on the first surface.

[0013] In some embodiments, the thickness of the stainless steel layer is 0.3 ± 0.01 microns.

[0014] In some embodiments, in step S2, first attach a double-sided adhesive to the surface of the substrate wafer, and then attach the chips to the double-sided adhesive on the surface of the substrate wafer. When peeling off the substrate wafer in step S4, the double-sided adhesive is peeled off together.

[0015] In some embodiments, the adhesive force of the double-sided adhesive is greater than or equal to 3 N / 20 mm.

[0016] In some embodiments, in step S3, the pressing device is a vacuum laminating machine, and the working parameters are a temperature of 120 °C, an airbag laminating pressure of 0.11 Mpa, and a laminating time of 60 S.

[0017] In a second aspect, the present invention also discloses another method for avoiding delamination in an embedded wafer-level ball grid array bonding process. This method replaces step S1 of the method described in the first aspect with:

[0018] Provide a carrier wafer for carrying chips in the bonding process, grind the first surface of the carrier wafer for carrying chips to make it flat; after cleaning, perform plasma etching on the first surface; and sputter a titanium layer and a stainless steel layer on the first surface after plasma etching.

[0019] Preferably, the thickness of the titanium layer is 0.1 ± 0.01 microns.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] The present invention adds a stainless steel layer to the surface of the silicon-based carrier wafer. Through the stainless steel layer, sufficient bonding effect with the film-like resin can be achieved after the bonding operation, ensuring that delamination does not occur under the erosion of conventionalizing agents during subsequent operations.

[0022] It is also possible to sputter a titanium layer and a stainless steel layer on the surface of the carrier wafer to achieve the above purpose. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic structural diagram of the carrier wafer in the present invention;

[0024] Figure 2 For Figure 1 Schematic structural diagram of the carrier wafer in

[0025] Figure 3 Schematic structural diagram of the substrate wafer with chips mounted;

[0026] Figure 4 For Figure 3 Schematic structural diagram of the substrate wafer in

[0027] Figure 5 Schematic structural diagram of the carrier wafer and the substrate wafer being pressed together;

[0028] Figure 6 Schematic structural diagram of the reorganized wafer with the active surface of the chip exposed;

[0029] Figures 7 - 11 Schematic diagram of the experimental results of clamping both sides of five groups of components with force.

[0030] Reference numeral description: carrier wafer 1, first surface 101, stainless steel layer 2, resin glue 3, substrate wafer 4, double-sided tape 5, chip 6. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0032] Embodiment 1

[0033] This embodiment discloses a method for avoiding delamination in an embedded wafer-level ball grid array bonding process, and the method includes the following steps:

[0034] S1. As shown in Figure 1 , provide the carrier wafer 1 for carrying the chip 6 in the bonding process, grind the first surface 101 of the carrier wafer 1 for carrying the chip 6 to make it flat; after cleaning, perform plasma etching on the first surface 101; and sputter the stainless steel layer 2 on the first surface 101 after plasma etching. The schematic structural diagram of the carrier wafer 1 with the stainless steel layer 2 sputtered is as shown in Figure 2 .

[0035] The material of the carrier wafer 1 is silicon. Before sputtering the stainless steel layer 2, grinding, cleaning, and plasma etching are performed on the first surface 101 of the carrier wafer 1 to increase the bonding force between the stainless steel layer 2 and the first surface 101 of the carrier wafer 1.

[0036] In specific implementation, a stainless steel layer 2 needs to be sputtered comprehensively and evenly on the first surface 101 of the carrier wafer 1. The thickness of the stainless steel layer 2 is 0.3 ± 0.01 microns. The stainless steel layer 2 with a thickness of 0.3 ± 0.01 microns can increase the bonding force with the first surface 101 of the carrier wafer 1. After the stainless steel layer 2 is greater than this thickness, the cost will increase, and when it is less than this thickness, the bonding force will be affected.

[0037] S2. As Figure 3 shown, a substrate wafer 4 for bonding with the carrier wafer 1 is provided, and multiple chips 6 are mounted on the surface of the substrate wafer 4, and the active surface of the chip 6 faces the surface of the substrate wafer 4. In specific implementation, first, a double-sided adhesive 5 is attached to the surface of the substrate wafer 4, and then the chip 6 is mounted on the double-sided adhesive 5 on the surface of the substrate wafer 4. The adhesive force of the double-sided adhesive 5 is greater than or equal to 3N / 20mm. The key characteristic of the double-sided adhesive 5 in this process is the adhesive force. Glue with a similar effect to the double-sided adhesive 5 can also be used, and the adhesive force needs to reach 3N / 20mm. In this embodiment, the double-sided adhesive 5 of the NWS - TS322F model from the Nitto supplier is used.

[0038] After mounting the chip 6, the resin glue 3 is used to cover the surfaces of all the chips 6 and the substrate wafer 4; the structure as Figure 4 shown is formed.

[0039] S3. The carrier wafer 1 is covered onto the substrate wafer 4, the stainless steel layer 2 contacts the resin glue 3, and a pressing device is used for pressing to bond the stainless steel layer 2 of the carrier wafer 1 and the resin glue 3 of the substrate wafer 4. The schematic diagram of the wafer structure after pressing is as Figure 5 shown.

[0040] The pressing device and process are prior art. The pressing device uses a vacuum laminating machine, and the working parameters are a temperature of 120°C, an airbag laminating pressure of 0.11 Mpa, and a laminating time of 60S.

[0041] S4. The substrate wafer 4 and the double-sided adhesive 5 in step S3 are peeled off to obtain a recombined wafer structure with the active surface of the chip 6 exposed, and its schematic diagram is as Figure 6 shown, and cutting operations are performed as required.

[0042] Example 2

[0043] The method for avoiding delamination in the embedded wafer-level ball grid array bonding process disclosed in this embodiment is different from that in Example 1 only in that step S1 is replaced with:

[0044] S1. Provide a carrier wafer 1 for carrying a chip 6 in a bonding process, grind the first surface 101 of the carrier wafer 1 for carrying the chip 6 to make it flat; after cleaning, perform plasma etching on the first surface 101; and sputter a titanium layer (not shown in the figure) and a stainless steel layer 2 on the plasma-etched first surface 101.

[0045] Among them, the thickness of the titanium layer is 0.1 ± 0.01 microns, and the thickness of the stainless steel layer 2 is 0.3 ± 0.01 microns.

[0046] Example 3

[0047] Comparative experiment:

[0048] Group the carrier wafers 1 into five groups: silicon (the first surface 101 for carrying the chip 6 is made of silicon, without sputtering any metal), silicon + titanium (the first surface 101 for carrying the chip 6 is sputtered with titanium Ti), silicon + stainless steel (the first surface 101 for carrying the chip 6 is sputtered with stainless steel, that is, the solution disclosed in this example), silicon + titanium + copper (the first surface 101 for carrying the chip 6 is sputtered with titanium Ti + copper Cu), and silicon + titanium + stainless steel (the first surface 101 for carrying the chip 6 is sputtered with titanium Ti + stainless steel). Perform the same operation process as described in this example until a reorganized wafer structure with the active surface of the chip 6 exposed after cutting is obtained. After steps such as soaking the cut components in water, observe whether delamination occurs.

[0049] The experimental results of the five groups of components after a thermal process of curing at 200 °C twice and adding one reflow, and then soaking in washing board water for 2 h and 3 h respectively are shown in Table 1.

[0050] Table 1 Experimental results of soaking components in washing board water

[0051]

[0052] The results show that the combination of silicon + stainless steel has no delamination phenomenon compared with other groups.

[0053] Clamp both sides of the five groups of components with force. The Si peeling-off situation is shown in Table 2, and the pictures of Si peeling-off on both sides of the components are as Figures 7 to 11 shown.

[0054] Table 2 Experimental results of clamping both sides of components with force

[0055]

[0056] The above experimental results show that in the e-WLB packaging process, a stainless steel layer 2 or a titanium layer and a stainless steel layer 2 are sputtered on the first surface 101 of the carrier wafer 1 for carrying the chip 6. Through the combination of the stainless steel layer 2 or the titanium layer and the stainless steel layer 2, sufficient adhesion effect between the carrier wafer 1 and the film resin after the bonding operation can be achieved, which can ensure that delamination does not occur under the erosion of the conventionalizing agent during the subsequent operation process.

[0057] The above are only some embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the inventive concept of the present invention, other deformations and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. A method for avoiding delamination in an embedded wafer-level ball grid array bonding process, characterized in that, The method includes the following steps: S1. Provide a carrier wafer for carrying chips in the bonding process, grind the first surface of the carrier wafer for carrying chips to make it flat; after cleaning, perform plasma etching on the first surface; and sputter a stainless steel layer on the first surface after plasma etching; S2. Provide a substrate wafer for bonding with the carrier wafer, mount a plurality of chips on the surface of the substrate wafer, and the active surface of the chips faces the surface of the substrate wafer; and cover all the chips and the surface of the substrate wafer with resin glue; S3. Cover the carrier wafer onto the substrate wafer, the stainless steel layer contacts the resin glue, and use a pressing device to apply pressure to bond the stainless steel layer of the carrier wafer and the resin glue of the substrate wafer; S4. Peel off the substrate wafer to obtain a reorganized wafer structure with the active surface of the chips exposed.

2. The method according to claim 1, wherein In step S1, a stainless steel layer is sputtered comprehensively and uniformly on the first surface.

3. The method according to claim 2, wherein The thickness of the stainless steel layer is 0.3 ± 0.01 microns.

4. The method according to claim 1, wherein In step S2, first attach a double-sided adhesive tape on the surface of the substrate wafer, and then mount the chips on the double-sided adhesive tape on the surface of the substrate wafer.

5. The method according to claim 4, wherein The adhesive force of the double-sided adhesive tape is greater than or equal to 3N / 20mm.

6. The method according to claim 1, wherein In step S3, the pressing device is a vacuum laminating machine, and the working parameters are a temperature of 120 °C, an airbag laminating pressure of 0.11 Mpa, and a laminating time of 60S.

7. The method according to any one of claims 1-6, characterized in that, Replace step S1 with: Provide a carrier wafer for carrying chips in the bonding process, grind the first surface of the carrier wafer for carrying chips to make it flat; after cleaning, perform plasma etching on the first surface; And sputter a titanium layer and a stainless steel layer on the first surface after plasma etching.

8. The method according to claim 7, wherein The thickness of the titanium layer is 0.1 ± 0.01 microns.

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