Power assembly, semiconductor module, and vehicle

Abstract

The application discloses a power assembly, a semiconductor module and a vehicle, and belongs to the technical field of power semiconductors. The power assembly comprises a chip layer and a wiring layer, the chip layer is internally provided with a power chip, the wiring layer is provided with a control electrode and a conduction circuit, the wiring layer and the chip layer are sequentially stacked in a first direction, and the conduction circuit is connected between the power chip and the control electrode. By embedding the power chip into the semiconductor structure, the design space of internal circuits of the semiconductor structure is large and the flexibility is strong, which is beneficial to optimizing the performance of the module on one hand and can reduce the connection terminals and the binding wires on the other hand, the inverter, the charger and the DC / DC unit can be integrated, the volume of the module is effectively reduced, and the power density is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power semiconductors, and particularly relates to a power assembly, a semiconductor module and a vehicle. BACKGROUND

[0002] The high-voltage system of a vehicle mainly includes an inverter module, an OBC (On-Board Charger) module and a DC / DC module, and the layout of the three modules has problems such as large volume and low power density in the related art. The power density of the high-voltage system needs to be further improved. SUMMARY

[0003] The present application aims to at least solve one of the technical problems in the prior art. To this end, the present application provides a power assembly, a semiconductor module and a vehicle, which embeds the power chips of the inverter, the charger and the DC / DC unit into the semiconductor structure, thereby reducing the volume of the module and improving the power density.

[0004] In a first aspect, the present application provides a power assembly, which comprises:

[0005] a chip layer, wherein a power chip is arranged in the chip layer;

[0006] a wiring layer, wherein a control electrode and a conductive circuit are arranged in the wiring layer;

[0007] The wiring layer and the chip layer are stacked in a first direction in sequence, and the conductive circuit is connected between the power chip and the control electrode.

[0008] According to an embodiment of the present application, the surface of the wiring layer away from the chip layer is provided with the control electrode, and the wiring layer is provided with the conductive circuit.

[0009] According to an embodiment of the present application, the chip layer comprises:

[0010] a frame layer, wherein a lead frame is arranged in the frame layer, and the power chip is connected to the lead frame.

[0011] According to an embodiment of the present application, the power chip comprises a plurality of chip groups, the number of the lead frames is a plurality, and each chip group is connected to each lead frame in a one-to-one correspondence.

[0012] According to an embodiment of the present application, the frame layer comprises:

[0013] a laminated plate, wherein a hollow slot is arranged in the laminated plate, the lead frame is arranged in the hollow slot, and the laminated plate is made of an insulating material.

[0014] According to an embodiment of the present application, the chip layer further comprises a thermistor, the thermistor is connected to the lead frame, and is arranged close to the power chip.

[0015] The wiring layer is further provided with a detection electrode on a side surface away from the chip layer, and the wiring layer is further provided with a detection circuit connected between the thermistor and the detection electrode.

[0016] According to an embodiment of the present application, the wiring layer comprises:

[0017] an insulating layer, the insulating layer and the chip layer are sequentially stacked in the first direction, and the insulating layer covers the power chip;

[0018] a control electrode, the control electrode is arranged on a surface of the insulating layer away from the chip layer, and the control electrode is connected to the power chip through a conductive circuit.

[0019] According to an embodiment of the present application, the insulating layer is provided with a via hole in the first direction, and at least part of the conductive circuit is arranged in the via hole.

[0020] According to an embodiment of the present application, the control electrode comprises a power electrode, and the conductive circuit comprises a power connection layer, the power connection layer being connected between the power electrode and the power chip.

[0021] According to an embodiment of the present application, the control electrode comprises a power electrode, and the insulating layer comprises:

[0022] a first insulating layer, the first insulating layer is provided with a power connection layer on a surface thereof away from the chip layer;

[0023] a third insulating layer, the third insulating layer covers the power connection layer, and the third insulating layer is provided with a power electrode on a surface thereof away from the first insulating layer.

[0024] According to an embodiment of the present application, the conductive circuit comprises a power circuit, the first insulating layer and the third insulating layer are provided with a via hole in the first direction, and the power circuit is arranged in the via hole.

[0025] According to an embodiment of the present application, the control electrode comprises a signal electrode, and the conductive circuit comprises a signal connection layer, the signal connection layer being connected between the signal electrode and the power chip.

[0026] According to an embodiment of the present application, the control electrode comprises a signal electrode, and the insulating layer comprises:

[0027] a second insulating layer, the second insulating layer is provided with a signal connection layer on a surface thereof away from the chip layer;

[0028] a third insulating layer, the third insulating layer covers the signal connection layer, and the third insulating layer is provided with the signal electrode on a surface thereof away from the second insulating layer.

[0029] According to an embodiment of the present application, the conductive circuit comprises a signal circuit, the second insulating layer and the third insulating layer are provided with a via hole in the first direction, and the signal circuit is arranged in the via hole.

[0030] According to one embodiment of the present application, the control electrode comprises a signal electrode, the conductive circuit comprises a signal connection layer, and the insulating layer comprises:

[0031] A second insulating layer, the second insulating layer is provided with a signal connection layer away from the surface of the chip layer, and the signal connection layer is connected between the power electrode and the power chip;

[0032] The third insulating layer, the second insulating layer and the first insulating layer are sequentially stacked in the first direction.

[0033] According to one embodiment of the present application, the conductive circuit comprises a power circuit and a signal circuit;

[0034] The first insulating layer is provided with a via hole in the first direction, and the power circuit is arranged in the via hole;

[0035] The second insulating layer is provided with a via hole in the first direction, and the signal circuit is arranged in the via hole.

[0036] According to one embodiment of the present application, the first insulating layer and / or the second insulating layer comprises multiple layers.

[0037] According to one embodiment of the present application, the power assembly further comprises:

[0038] A substrate, the substrate is arranged on the side of the chip layer away from the wiring layer.

[0039] According to one embodiment of the present application, the power assembly further comprises:

[0040] A third insulating layer, the third insulating layer is arranged between the chip layer and the substrate.

[0041] According to one embodiment of the present application, the substrate, the third insulating layer, the laminated plate, the chip layer and the wiring layer are laminated and fused.

[0042] According to one embodiment of the present application, the substrate is an aluminum-based copper-clad plate, and the second insulating layer comprises a pre-impregnated material with adhesive properties.

[0043] According to one embodiment of the present application, the power chip comprises an upper bridge chip and a lower bridge chip, the control electrode comprises a first power electrode, the conductive circuit comprises a first power connection layer and a first power circuit, and the first power connection layer is connected with the first power pin of the upper bridge chip, the first power pin of the lower bridge chip and the first power electrode through the first power circuit.

[0044] According to one embodiment of the present application, the control electrode further comprises a second power electrode, the conductive circuit further comprises a second power connection layer and a second power circuit, the second power connection layer is arranged in the same layer and insulated from the first power connection layer, and the second power connection layer is connected with the second power pin of the lower bridge chip and the second power electrode through the second power circuit.

[0045] According to one embodiment of the present application, the control electrode comprises a third power electrode, and the conductive line comprises a third power line, the third power line being connected between the second power pin of the upper bridge chip and the third power electrode.

[0046] According to one embodiment of the present application, the number of the upper bridge chips and the number of the lower bridge chips are both plural, the first power pin of each upper bridge chip and the first power pin of each lower bridge chip are connected to the same first power connection layer, and the second power pin of each lower bridge chip is connected to the same second power connection layer.

[0047] According to one embodiment of the present application, the orthographic projection of each upper bridge chip on the substrate is located within the orthographic projection range of the first power connection layer on the substrate, and the orthographic projection of each lower bridge chip on the substrate is located within the orthographic projection range of the second power connection layer on the substrate.

[0048] According to one embodiment of the present application, the control electrode comprises a first signal electrode and a second signal electrode, and the conductive line comprises a first signal connection layer, a second signal connection layer, a first signal line and a second signal line, the first signal connection layer being connected to the signal pin of each upper bridge chip and the first signal electrode through the first signal line, and the second signal connection layer being connected to the signal pin of each lower bridge chip and the second signal electrode through the second signal line.

[0049] According to one embodiment of the present application, each of the upper bridge chips and the lower bridge chips comprises a plurality of signal pins, each of the first signal connection layer and the second signal connection layer comprises a plurality of sub signal connection layers, and each sub signal connection layer is connected to each signal pin of each upper bridge chip or each lower bridge chip.

[0050] According to one embodiment of the present application, the number of the upper bridge chips and the number of the lower bridge chips are both plural, and each sub signal connection layer comprises a main connection line and a plurality of branch connection lines, the main connection line being connected to the signal electrode through the signal line, the first end of each branch connection line being connected to the main connection line perpendicularly, the second end of each branch connection line being connected to the signal pin of the upper bridge chip or the lower bridge chip through the signal line, and the lengths of the branch connection lines are the same.

[0051] In a second aspect, the present application provides a semiconductor module, comprising a base plate and a power assembly as described above, and the power assembly is arranged on the base plate.

[0052] According to one embodiment of the present application, the power assembly comprises at least one of a first power assembly, a second power assembly and a third power assembly, the power chips in the first power assembly are used to construct an inverter, the power chips in the second power assembly are used to construct a charger, and the power chips in the third power assembly are used to construct a DC / DC unit.

[0053] According to one embodiment of the present application, the second power assembly and the third power assembly are integrally prepared.

[0054] According to one embodiment of the present application, each power component is welded to the first side of the base plate, and the second side opposite to the first side of the base plate is provided with a heat dissipation structure.

[0055] According to one embodiment of the present application, the plurality of power components includes at least two first power components, at least one first power component is used to build a vehicle motor main drive inverter, and at least one first power component is used to build a vehicle-mounted compressor inverter.

[0056] In a third aspect, the present application provides a vehicle, the vehicle comprising the semiconductor module according to the foregoing.

[0057] According to the power component, the semiconductor module and the vehicle of the present application, the power component can integrate inverters, chargers and DC / DC units, the power chips are embedded into the semiconductor structure, the design space of internal lines of the semiconductor structure is large and the flexibility is strong, which is beneficial to optimize the performance of the module on one hand, and can reduce the wire terminals and the wire binding on the other hand, effectively reduces the volume of the module and improves the power density.

[0058] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0059] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0060] Figure 1 is a cross-sectional schematic view of the power component provided by the embodiment of the present application;

[0061] Figure 2 is an external structure schematic view of the main drive inverter power component provided by the embodiment of the present application;

[0062] Figure 3 is a chip layout schematic view of the main drive inverter power component provided by the embodiment of the present application;

[0063] Figure 4 is a wiring structure schematic view of the main drive inverter power component provided by the embodiment of the present application;

[0064] Figure 5 is a simplified cross-sectional structure schematic view of the main drive inverter power component provided by the embodiment of the present application;

[0065] Figure 6 is a power connection layer wiring schematic view of the main drive inverter power component provided by the embodiment of the present application;

[0066] Figure 7is one of signal connection layer wiring schematic diagrams of the main drive inverter power assembly provided by the embodiment of the present application;

[0067] Figure 8 is the second signal connection layer wiring schematic diagram of the main drive inverter power assembly provided by the embodiment of the present application;

[0068] Figure 9 is the surface electrode layer wiring schematic diagram of the main drive inverter power assembly provided by the embodiment of the present application;

[0069] Figure 10 is the external structure schematic diagram of the vehicle-mounted charger and DC\DC power assembly provided by the embodiment of the present application;

[0070] Figure 11 is the simplified cross-section structure schematic diagram of the vehicle-mounted charger and DC\DC power assembly provided by the embodiment of the present application;

[0071] Figure 12 is the external structure schematic diagram of the vehicle-mounted compressor assembly provided by the embodiment of the present application;

[0072] Figure 13 is the simplified cross-section structure schematic diagram of the vehicle-mounted compressor assembly provided by the embodiment of the present application;

[0073] Figure 14 is the structure schematic diagram of the semiconductor module provided by the embodiment of the present application. DETAILED DESCRIPTION

[0074] The embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings. In the drawings, the size and relative sizes of layers, regions, elements, and the like can be exaggerated for clarity. Identical or similar component elements throughout the drawings are denoted with the same reference numerals, and the description thereof is not repeated. The embodiments described below are examples for explaining the present application, and are not intended to limit the present application.

[0075] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure, and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0076] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0077] In the related art, the integration of the vehicle-mounted power module is mostly to simply arrange the inverter circuit components, the vehicle-mounted charger circuit components and the DC / DC circuit components in a plane, and then encapsulate them as a whole in the same encapsulation shell, but still occupies a large space. In addition, the vehicle-mounted compressor inverter is not integrated, and there is still room for further improving the power density.

[0078] The present application provides a power assembly, a semiconductor module and a vehicle. The power assembly integrates an inverter, a charger and a DC / DC unit, and embeds power chips into a semiconductor structure. The design space of the internal circuit of the semiconductor structure is large and flexible. On the one hand, it is beneficial to optimize the performance of the module. The switching delay of the chip set can be reduced and the overcurrent capacity of the module can be improved by adjusting the connection mode and shape area of the circuit. On the other hand, the number of wire terminals and binding wires can be reduced, the volume of the module can be effectively reduced, and the power density is improved. In addition, the vehicle-mounted compressor inverter can be integrated, the volume change is small, and the power density is further improved.

[0079] Referring toFigure 1 , Figure 1 A cross-sectional structure of a power module is shown, and one embodiment of the present application proposes a power module. In the present embodiment, the power module includes a chip layer 110 and a wiring layer 120, the chip layer 110 is provided with a power chip 111, the wiring layer 120 is provided with a control electrode 130 and a conductive line 140, the wiring layer 120 and the chip layer 110 are stacked in a first direction in sequence, and the conductive line 140 is connected between the power chip 111 and the control electrode 130.

[0080] As shown in Figure 1 , the first direction is the X direction, i.e., the direction from top to bottom. The wiring layer 120 and the chip layer 110 are stacked in a top-to-bottom manner, and the conductive line 140 and the control electrode 130 in the wiring layer 120 realize the signal input and power input and output of the power chip 111.

[0081] As an example, the control electrode 130 can include a power electrode and a signal electrode, and the conductive line 140 includes a power line and a signal line, the power line is connected between the power pin of the power chip and the power electrode, and the signal line is connected between the signal pin of the power chip and the signal electrode.

[0082] The power chip can be an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). Taking the MOSFET as an example, the power pin is the source and the drain, and the signal pin is the gate. Some MOSFETs also have a Kelvin source, which can also be used as a signal pin.

[0083] The power module encapsulates at least one power chip, and the specific number can be determined according to the required circuit topology. For example, the power module can encapsulate an inverter circuit, which can adopt a half-bridge or a full-bridge, wherein each bridge arm can include one, four or eight power chips. The power module can also encapsulate a three-phase full-bridge inverter circuit, which includes three inverter circuits. The chip layer 110 can be provided with an insulating isolation around the power chip, which plays a protective role.

[0084] In some embodiments, the control electrode 130 is arranged on the surface of the wiring layer 120 away from the chip layer 110, and the conductive line 140 is arranged in the wiring layer 120.

[0085] The power lines and the signal lines are used to construct a power loop and a signal loop of the power chip, and realize the power input and output and the signal input and output of the power component by being connected to the power electrode and the signal electrode on the surface. In the case that the power component includes a plurality of power chips, the power lines can also be connected between the power pins of the power chips to realize power distribution, and the signal lines can also be connected between the signal pins of the power chips to realize signal distribution.

[0086] The specific paths of the power loop and the signal loop can be determined according to the required circuit topology to be constructed. For example, the power component can be packaged with a half-bridge or full-bridge inverter circuit, and the power loop and the signal loop need to be implemented according to the power connection relationship and the signal connection relationship of each bridge arm in the half-bridge or full-bridge.

[0087] As an example, the source of the MOSFET tube of the upper bridge arm is connected to the source of the MOSFET tube of the lower bridge arm through the power loop, and the drain of the MOSFET tube of the upper bridge arm is connected to the drain of the MOSFET tube of the lower bridge arm through the power loop to the power electrode. In the case that one bridge arm includes a plurality of MOSFET tubes, the gates of the plurality of MOSFET tubes of the bridge arm can be connected to each other through the signal loop and connected to the signal electrode.

[0088] In some embodiments, the wiring layer 120 includes an insulating layer, the insulating layer is stacked in the first direction in sequence with the chip layer 110, and the insulating layer covers the power chip 111; the control electrode 130 is arranged on the surface of the insulating layer away from the chip layer 110 and connected to the power chip 111 through the conductive line 140.

[0089] The insulating layer can play a protective role in isolating the power chip 111 by covering the power chip 111. The conductive line 140 can pass through or bypass the insulating layer to connect between the control electrodes 130, realizing the input and output of signals and power.

[0090] In some embodiments, the insulating layer is provided with a via hole in the first direction, and at least part of the conductive line 140 is arranged in the via hole.

[0091] Part of the conductive line 140 can extend to both sides of the insulating layer in the via hole to pass through the insulating layer to realize connection on both sides. Directly passing through the insulating layer to realize connection can shorten the length of the line and simplify the line. The control electrode 130 can be located above the insulating layer, the power chip 111 is located below the insulating layer, and part of the conductive line 140 passes through the via hole to connect between the control electrode 130 and the power chip 111.

[0092] In some embodiments, the control electrode 130 includes a power electrode, and the conductive line 140 includes a power connection layer connected between the power electrode and the power chip 111.

[0093] The power electrode is used for power input and output of the power chip 111. If the power chip 111 is a MOS tube, the power electrode can be used as a source electrode and a drain electrode. The power connection layer can be used to collect power of multiple power chips 111, so that power is evenly distributed among the power chips 111.

[0094] In some embodiments, the control electrode 130 includes a power electrode, the insulating layer includes a first insulating layer and a third insulating layer, the first insulating layer is provided with a power connection layer away from the surface of the chip layer, the third insulating layer covers the power connection layer, and the third insulating layer is provided with the power electrode away from the surface of the first insulating layer.

[0095] The first insulating layer is used to isolate the power connection layer and the power chip 111, and plays a protective role. The third insulating layer is used to isolate the power connection layer and the power electrode, and plays a protective role.

[0096] In some embodiments, the conductive circuit 140 includes a power circuit, the first insulating layer and the third insulating layer are provided with a via hole in the first direction, and the power circuit is arranged in the via hole.

[0097] The power circuit is used to realize power connection in the first direction. The power circuit extends in the via hole of the first insulating layer to connect the power chip 111 and the power connection layer on both sides of the first insulating layer. By directly penetrating the first insulating layer, the length of the power circuit can be shortened, and the circuit can be simplified.

[0098] In some embodiments, the control electrode 130 includes a signal electrode, and the conductive circuit 140 includes a signal connection layer connected between the signal electrode and the power chip 111.

[0099] The signal electrode is used for signal input of the power chip 111 to realize control of the power chip 111. If the power chip 111 is a MOS tube, the signal electrode can be used as a gate electrode. The signal connection layer can be used to collect signals of multiple power chips 111, so that signals are synchronized among the power chips 111.

[0100] In some embodiments, the control electrode 130 includes a signal electrode, the insulating layer includes a second insulating layer and a third insulating layer, the second insulating layer is provided with a signal connection layer away from the surface of the chip layer, the third insulating layer covers the signal connection layer, and the third insulating layer is provided with the signal electrode away from the surface of the second insulating layer.

[0101] The first insulating layer is used to isolate the signal connection layer and the power chip 111, and plays a protective role. The third insulating layer is used to isolate the signal connection layer and the signal electrode, and plays a protective role.

[0102] In some embodiments, the conductive circuit 140 includes a signal circuit, the second insulating layer and the third insulating layer are provided with a via hole in the first direction, and the signal circuit is also arranged in the via hole.

[0103] The signal lines are used to realize signal connection in the first direction. The signal lines extend in the via of the second insulating layer to connect the power chips 111 and the signal connection layer on both sides of the second insulating layer. By directly penetrating the second insulating layer to realize the connection, the length of the signal lines can be shortened and the circuit can be simplified.

[0104] In some embodiments, the control electrode 130 includes a power electrode and a signal electrode, the conductive line 140 includes a power connection layer and a signal connection layer, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is provided with the power connection layer away from the surface of the chip layer, the power connection layer is connected between the power electrode and the power chip 111, the second insulating layer is provided with the signal connection layer away from the surface of the chip layer, the signal connection layer is connected between the power electrode and the power chip 111, and the third insulating layer, the second insulating layer and the first insulating layer are stacked in the first direction.

[0105] The power chip 111 is a MOS tube, the power electrode can be used as a source electrode and a drain electrode, and the signal electrode can be used as a gate electrode. The power connection layer can be used to collect the power of multiple power chips 111, and the signal connection layer can be used to collect the signals of multiple power chips 111, so that the power distribution between the power chips 111 is uniform, and the signals are synchronized.

[0106] In some embodiments, the conductive line 140 includes a signal line and a power line, the first insulating layer is provided with a via in the first direction, and the power line is arranged in the via; the second insulating layer is provided with a via in the first direction, and the signal line is arranged in the via.

[0107] The power line is used to realize power connection in the first direction, and the power line extends in the via of the first insulating layer. The signal line is used to realize signal connection in the first direction, and the signal line extends in the via of the second insulating layer. By directly penetrating the first insulating layer and the second insulating layer to realize the connection, the length of the power line and the signal line can be shortened and the circuit can be simplified.

[0108] In the above embodiments, the first insulating layer and / or the second insulating layer includes multiple layers.

[0109] Arranging the first insulating layer and / or the second insulating layer in multiple layers can improve the isolation effect, and can also adapt to different designs of the conductive line 140. For example, the power connection layer and the signal connection layer can also be arranged in multiple layers, and the first insulating layer or the second insulating layer can be arranged between the connection layers (power connection layer or signal connection layer) of adjacent two layers.

[0110] In some embodiments, the power assembly further includes a substrate, and the substrate is arranged on the side of the chip layer 110 away from the wiring layer 120.

[0111] The substrate is, for example,Figure 1 The first substrate 1 in the power component is used to carry the power components, facilitating the preparation and installation of the power components.

[0112] In some embodiments, the power component further comprises a third insulating layer arranged between the chip layer 110 and the substrate.

[0113] An insulating layer can also be arranged between the first substrate 1 and the chip layer 110. The third insulating layer can provide the chip layer 110 with next isolation and protection. In addition, the third insulating layer can also improve the connection reliability between the chip layer 110 and the first substrate 1.

[0114] In this embodiment, the power component can form different circuit topologies by configuring the power chips, power circuits and signal circuits, thereby constructing different devices. For example, the power component with a three-phase full-bridge inverter circuit topology can be used as an inverter, or the power component with a DC / DC circuit topology can be used as a DC / DC unit. Or in application, by connecting with external devices to construct different devices to realize corresponding functions. For example, the power component internally forms multiple AC / DC conversion circuits, and the power electrode connected with the primary side and secondary side of the external transformer can be used as a charger, or connected with the primary side and secondary side of the external transformer can also be used as an isolation type DC / DC unit.

[0115] Referring to Figure 2 , Figure 2 An external structure of a main drive inverter power component 100 is shown. The upper surface of the main drive inverter power component 100 leads out the main electrodes, including a high-voltage DC positive electrode 101, a high-voltage DC negative electrode 102 and a high-voltage AC electrode 103, and the signal electrodes include a first control electrode 104 and a second control electrode 105.

[0116] The main drive inverter power component 100 internally forms a three-phase full-bridge inverter circuit, and the power chips corresponding to each phase bridge arm are arranged along the length direction. The high-voltage DC positive electrode 101 and the high-voltage DC negative electrode 102 are arranged close to one long side, the high-voltage AC electrode 103 is arranged close to the other long side, and the first control electrode 104 and the second control electrode 105 are located at the middle positions of the two long sides. The DC electrodes and the AC electrodes are separated as much as possible to reduce coupling interference and improve electromagnetic compatibility.

[0117] Referring to Figure 3 , Figure 4 and Figure 5 , Figure 3 A chip layout of a main drive inverter power component 100 is shown, Figure 4 A wiring structure of a main drive inverter power component 100 is shown, Figure 5A simplified sectional structure of a main drive inverter power assembly 100 is shown. In some embodiments, the chip layer includes a frame layer 3 provided with a lead frame and an insulating layer 5, the power chips are connected to the lead frame away from the first substrate 1; the insulating layer 5 is arranged on the side of the frame layer 3 away from the first substrate 1 and covers the power chips.

[0118] As an example, the power chips in the main drive inverter power assembly 100 are configured as full-bridge inverter circuits, each bridge arm includes eight power chips, which can be connected to the lead frame as a chip group 4 through silver sintering. The lead frame is used to support the power chips, realize electrical connection and provide a heat dissipation path, and is surrounded by an insulating material to achieve isolation. The thickness of the insulating material can be the same as that of the lead frame to keep the upper surfaces flush.

[0119] In some embodiments, the power chips include multiple chip groups 4, and the number of lead frames is multiple, and each chip group is connected to each lead frame one by one.

[0120] The lead frame can be used to realize the pin extension of the power chip, and the power loop and / or signal loop can be connected to the power chip through the lead frame. Therefore, the power chips connected by one lead frame are suitable to be configured with the same function. For example, each power chip in the main drive inverter power assembly 100 is divided into multiple chip groups 4 according to the bridge arm, and a separate lead frame is used to connect each bridge arm.

[0121] In some embodiments, the chip layer 110 further includes a thermistor 34 connected to the lead frame and arranged close to the power chip; the surface of the wiring layer 120 away from the chip layer 110 is further provided with a detection electrode, and the wiring layer 120 is further provided with a detection circuit connected between the thermistor 34 and the detection electrode.

[0122] The thermistor 34 and the lead frame can be connected by a heat-conducting insulating adhesive to detect the junction temperature of the power chip. The detection electrode is used to connect the control unit, and the detection signal of the thermistor 34 is led out through the detection circuit and transmitted to the control unit through the detection electrode.

[0123] In some embodiments, the frame layer 3 includes a first laminated plate 31 provided with a hollow slot, and the lead frame is arranged in the hollow slot. The frame layer 3 and the upper and lower layers can be fused into one whole through 3-layer pressing, so that the preparation process is simple.

[0124] As Figure 4As shown, the wiring layer 120 includes the first connection layer 7, the second connection layer 10 and the third connection layer 13, each connection layer, power chip and electrode layer are isolated by the insulating layer 8, the insulating layer 11 and the insulating layer 14, the insulating layer is provided with a via and filled with conductive material to form the first via layer 6, the second via layer 9, the third via layer 12 and the fourth via layer 15. Among them, each connection layer and the conductive material in the via can be copper or silver, etc. The following will be described in detail in combination with Figure 5 The first substrate 1 and the first laminated plate 31 are laminated together by the insulating layer 2.

[0125] Taking a half-bridge module as an example, the first laminated plate 31 is provided with two empty slots in the region corresponding to the half-bridge module, respectively embedded with the first lead frame 32 and the second lead frame 33. The thickness of the two lead frames is the same as the thickness of the first laminated plate 31. The chip set 4 includes two groups, one group is the first upper bridge chip 41, and the other group is the first lower bridge chip 42. The first upper bridge chip 41 is connected to the first lead frame 32, and the first lower bridge chip 42 is connected to the second lead frame 33. The first upper bridge chip 41 and the first lower bridge chip 42 are covered by the insulating layer 5 on the side away from the lead frame, realizing insulation and protection.

[0126] In some embodiments, the first substrate 1 and the first laminated plate 31 are provided with the insulating layer 2, and the first substrate 1, the insulating layer 2, the first laminated plate 31, the power chip and the insulating layer 5 are fused after lamination. By one side lamination, the substrate and chip layer 110 are fused into one whole, so that the preparation process is simple.

[0127] In some embodiments, the first substrate 1 is an aluminum-based copper-clad plate, and the insulating layer 2 includes a pre-impregnated material with adhesive properties. The first substrate 1 uses an aluminum plate which is not easy to crack in lamination, and the quality is more reliable. The pre-impregnated material can be FR4 (Flame Retardant Type 4) or BT (Bismaleimide-Triazine). The thickness of the first substrate 1 and the insulating layer 2 can be adjusted according to the actual application and the preparation process requirements.

[0128] In some embodiments, the power electrode includes a first power electrode, the power circuit includes a first power connection layer 71 and a first power circuit, and the first power connection layer 71 is connected with the first power pin of the first upper bridge chip 41, the first power pin of the first lower bridge chip 42 and the first power electrode through the first power circuit.

[0129] The first connection layer 7 is used to realize power connection, which includes the first power connection layer 71, the first via layer 6 includes the first hole 61 and the second hole 62, the fourth via layer 15 includes the tenth hole 153, and the first hole 61, the second hole 62 and the tenth hole 153 are provided with a connecting line to form the first power circuit to realize the power connection of the first power connection layer 71.

[0130] As an example, the first power pin can be a source electrode, and the first power electrode can be the high-voltage alternating current electrode 103. The first power connection layer 71 is connected to the source electrode of the first upper bridge chip 41 through the first hole 61, connected to the source electrode of the first lower bridge chip 42 through the second hole 62, and connected to the high-voltage alternating current electrode 103 through the tenth hole 153 to circulate the main current.

[0131] In the case where the first lower bridge chip 42 is connected to a lead frame, the first power connection layer 71 is connected to the lead frame through the second hole 62 to realize the connection to the source electrode of the first lower bridge chip 42. Of course, the first power connection layer 71 can also be connected to the lead frame through the first hole 61 to realize the connection to the source electrode of the first upper bridge chip 41.

[0132] It can be understood that in the case where the number of the first upper bridge chips 41 and the number of the first lower bridge chips 42 are both plural, the first power pin of each first upper bridge chip 41 and the first power pin of each first lower bridge chip 42 are connected to the same first power connection layer 71. In addition to realizing the power connection between the source electrodes of the first upper bridge chips 41 and the source electrodes of the first lower bridge chips 42, the first power connection layer 71 can also realize the power connection between the source electrodes of the first upper bridge chips 41 and the power connection between the source electrodes of the first lower bridge chips 42 to collect the currents of these pins to the first power connection layer 71 and then to the high-voltage alternating current electrode 103.

[0133] In some embodiments, the power electrode further includes a second power electrode, and the power circuit further includes a second power connection layer 72 and a second power circuit, the second power connection layer 72 is arranged in the same layer and insulated from the first power connection layer 71, and the second power connection layer 72 is connected to the second power pin of the first lower bridge chip 42 and the second power electrode through the second power circuit, respectively.

[0134] The first connection layer 7 further includes a second power connection layer 72, the first via layer 6 further includes a third hole 63, the fourth via layer 15 includes a ninth hole 152, and a connecting line is arranged in the third hole 63 and the ninth hole 152 to form a second power circuit to realize the power connection of the second power connection layer 72. The second power pin can be a drain electrode, and the second power electrode can be the high-voltage direct current negative electrode 102. The second power connection layer 72 is connected to the drain electrode of the first lower bridge chip 42 through the third hole 63 and connected to the high-voltage direct current negative electrode 102 through the ninth hole 152.

[0135] When there are multiple first lower bridge chips 42, the second power pins of each first lower bridge chip 42 are connected to the same second power connection layer 72. The second power connection layer 72 can realize power connection between the drains of each first lower bridge chip 42, so that the current of these pins is collected in the second power connection layer 72 and then led to the high-voltage DC negative electrode 102.

[0136] In some embodiments, the power electrode further includes a third power electrode, the power circuit includes a third power circuit, and the third power circuit is connected between the second power pin of the first upper bridge chip 41 and the third power electrode.

[0137] The fourth via layer 15 also includes an eighth hole 151, which contains a connecting wire forming a third power circuit, enabling power connection to the first upper bridge chip 41. The second power pin can be a drain, and the third power electrode is the high-voltage DC positive electrode 101. The drain of the first upper bridge chip 41 is connected to the high-voltage DC positive electrode 101 through the eighth hole 151. In summary, the power circuit is arranged in an exemplary manner to lead the power pins of the power chip to the power electrode.

[0138] In some embodiments, the orthographic projection of each first upper bridge chip 41 on the first substrate 1 is located within the orthographic projection range of the first power connection layer 71 on the first substrate 1 , and the orthographic projection of each first lower bridge chip 42 on the first substrate 1 is located within the orthographic projection range of the second power connection layer 72 on the first substrate 1 .

[0139] Reference Figure 6 , Figure 6 FIG. 1 shows a power connection layer wiring structure of a main drive inverter power component 100. Figure 6 As shown, the first power connection layer 71 and the second power connection layer 72 can adopt a large-area copper layer structure, which is beneficial to increasing the overcurrent cross-sectional area, improving the module's overcurrent capacity, and reducing stray inductance.

[0140] It should be noted that since the first power connection layer 71 and the second power connection layer 72 cover the first upper bridge chip 41 and the first lower bridge chip 42 respectively, in order to facilitate the arrangement of the remaining power lines and signal lines, the first power connection layer 71 and the second power connection layer 72 can respectively leak out some pins (such as the drain and the gate) of the first upper bridge chip 41 and the first lower bridge chip 42.

[0141] In some embodiments, the signal electrode includes a first signal electrode and a second signal electrode, and the signal circuit includes a first signal connection layer, a second signal connection layer, a first signal line, and a second signal line. The first signal connection layer is connected to the signal pins and the first signal electrodes of each first upper bridge chip 41 through the first signal line, and the second signal connection layer is connected to the signal pins and the second signal electrodes of each first lower bridge chip 42 through the second signal line.

[0142] In the case where the number of the first upper bridge chips 41 and the number of the first lower bridge chips 42 are both plural, the signals of the signal pins of each first upper bridge chip 41 are gathered in the first signal connection layer, and the signals of the signal pins of each first lower bridge chip 42 are gathered in the second signal connection layer, so as to realize common control. The signal pins of the power chips can be gates.

[0143] In some embodiments, the first upper bridge chips 41 and the first lower bridge chips 42 both include a plurality of signal pins, and the first signal connection layer and the second signal connection layer both include a plurality of sub-signal connection layers, each of which is connected to each signal pin of each first upper bridge chip 41 or each first lower bridge chip 42.

[0144] As an example, the signal pins of the first upper bridge chips 41 and the first lower bridge chips 42 both include gates and Kelvin sources, and since the signals of different signal pins need to be isolated, the first signal connection layer and the second signal connection layer both include two sub-signal connection layers.

[0145] Continuing to refer to Figure 5 , the second connection layer 10 and the third connection layer 13 are both used to arrange signal lines. The second connection layer 10 is used to connect the gates of the power chips, and includes a first sub-signal connection layer 107 and a second sub-signal connection layer 108. The third connection layer 13 is used to connect the Kelvin sources of the power chips, and includes a third sub-signal connection layer 131 and a fourth sub-signal connection layer 132. The first sub-signal connection layer 107 and the third sub-signal connection layer 131 are used as the first signal connection layer to lead out the signal pins of the first upper bridge chips 41, and the second sub-signal connection layer 108 and the fourth sub-signal connection layer 132 are used as the second signal connection layer to lead out the signal pins of the first lower bridge chips 42.

[0146] The second via layer 9 includes a fourth hole 91 and a fifth hole 92, and the lower surface of the second connection layer 10 is connected to the upper surface of the insulating layer 8. The gates in the first upper bridge chips 41 are electrically connected to the first sub-signal connection layer 107 through the fourth hole 91, and the gates in the first lower bridge chips 42 are electrically connected to the second sub-signal connection layer 108 through the fifth hole 92. The third via layer 12 includes a sixth hole 121 and a seventh hole 122. The lower surface of the third connection layer 13 is in contact with the upper surface of the insulating layer 11, the Kelvin sources in the first upper bridge chips 41 are electrically connected to the third sub-signal connection layer 131 through the sixth hole 121, and the Kelvin sources in the first lower bridge chips 42 are electrically connected to the fourth sub-signal connection layer 132 through the seventh hole 122.

[0147] Referring to Figure 7 and Figure 8 , Figure 7 one of the signal connection layer wiring of a main drive inverter power assembly 100 is shown,Figure 8 The second wiring of the signal connection layer of the main drive inverter power assembly 100 is shown. It should be noted that, Figure 5 In order to more clearly show the relationship between the wires in the power assembly and the upper and lower layers, the actual positions are simplified. The specific shapes of the second connection layer 10 and the third connection layer 13 are as shown in combination with Figure 7 and Figure 8 .

[0148] In some embodiments, the sub-signal connection layer includes a main connection line and a plurality of sub-connection lines, the main connection line is connected with the signal electrode through the connection hole, the first end of the sub-connection line is connected with the main connection line perpendicularly, and the second end of the sub-connection line is connected with the signal pin of the upper bridge chip or the lower bridge chip through the connection hole, and the lengths of the sub-connection lines are the same.

[0149] From Figure 7 and Figure 8 It can be seen that the main connection line is used to collect signals, and the sub-connection line is connected to each power chip to realize specific distribution of signals. The sub-connection line is connected with the main connection line perpendicularly, which can shorten the length of the sub-connection line; and since the lengths of the sub-connection lines are the same, the path of the current reaching each chip can be made as short and same as possible, which is beneficial to reduce the switching delay of the chip set.

[0150] In some embodiments, in the stacking direction of the power assembly, the first upper bridge chip 41 or the first lower bridge chip 42 corresponds to each sub-signal connection layer partially overlapping and arranged in parallel with each other.

[0151] From Figure 7 and Figure 8 It can be seen that the first sub-signal connection layer 107 and the third sub-signal connection layer 131 partially overlap in the middle part, and the second sub-signal connection layer 108 and the fourth sub-signal connection layer 132 partially overlap in the middle part. Due to the effect of partial overlap and parallel arrangement, signal interference and stray inductance can be reduced.

[0152] Continuing to refer to Figure 5The fourth via layer 15 is mainly used to connect the internal circuit of the power assembly with the surface electrode. The power electrode is as described above, the signal electrode includes the first control electrode 104, the second control electrode 105 and the detection electrode 106, the first control electrode 104 includes the first control source electrode 104a and the first control gate electrode 104b, the second control electrode includes the second control source electrode 105a and the second control gate electrode 105b, and the detection electrode 106 of the thermistor includes the detection resistance positive electrode 106a and the detection resistance negative electrode 106b. The fourth via layer 15 further includes an eleventh hole 154a, a twelfth hole 154b, a thirteenth hole 155a, a fourteenth hole 155b, a fifteenth hole 156a and a sixteenth hole 156b. Among them, the fourth hole 91, the sixth hole 121, the eleventh hole 154a and the twelfth hole 154b are provided with a connecting line, forming a first signal line, realizing the signal connection of the first upper bridge chip 41. The fifth hole 92, the seventh hole 122, the thirteenth hole 155a and the fourteenth hole 155b are provided with a connecting line, forming a second signal line, realizing the signal connection of the first lower bridge chip 42.

[0153] Referring to Figure 9 , Figure 9 The surface electrode layer wiring of the main drive inverter power assembly 100 is shown. The lower surface of each electrode is in contact with the upper surface of the insulating layer 14, the high-voltage direct-current positive electrode 101 is electrically connected with the first lead frame 32 through the eighth hole 151, the high-voltage direct-current negative electrode 102 is electrically connected with the second power connection layer 72 through the ninth hole 152, the high-voltage alternating-current electrode 103 is electrically connected with the first power connection layer 71 through the tenth hole 153, the first control source electrode 104a is electrically connected with the third sub-signal connection layer 131 through the eleventh hole 154a, the first control gate electrode 104b is electrically connected with the first sub-signal connection layer 107 through the twelfth hole 154b, the second control source electrode 105a is electrically connected with the fourth sub-signal connection layer 132 through the thirteenth hole 155a, and the second control gate electrode 105b is electrically connected with the second sub-signal connection layer 108 through the fourteenth hole 155b. The detection resistance positive electrode 106a is connected with the positive electrode of the thermistor through the fifteenth hole 156a, and the detection resistance negative electrode 106b is connected with the negative electrode of the thermistor through the sixteenth hole 156b.

[0154] Referring to Figure 10 , Figure 10An external structure of the vehicle charger and DC\DC power assembly 200 is shown. In some embodiments, the power chips in the second power assembly construct a power factor correction unit, a resonant primary side unit 201 and a resonant secondary side unit 203, and the power chips in the third power assembly construct a DC primary side unit 204 and a DC secondary side unit 205; in a first direction, the resonant secondary side unit 203 is located on a first side of the DC secondary side unit 205, the resonant primary side unit 201 is located on a side of the resonant secondary side unit 203 away from the DC secondary side unit 205, the DC primary side unit 204 is located on a first side of the DC secondary side unit 205, and the power factor correction unit is located on a side of the DC primary side unit 204 away from the DC secondary side unit 205; in a second direction, the DC primary side unit 204 is located on a second side of the resonant secondary side unit 203, and the power factor correction unit is located on a second side of the resonant primary side unit 201, and the first direction is perpendicular to the second direction.

[0155] The power factor correction unit can include a PFC fast tube 206 and a PFC slow tube 202, and the power assembly surface can be provided with a first signal low-voltage electrode 207 and a first high-voltage electrode 208.

[0156] Referring to Figure 11 , Figure 11 A simplified cross-sectional structure of the vehicle charger and DC\DC power assembly 200 is shown. The second laminated board 211 has a plurality of empty slots, and the third lead frame 215 is embedded in the plurality of empty slots of the second laminated board 211, and the thickness of the third lead frame 215 is the same as the thickness of the second laminated board 211. The second laminated board 211 and the third lead frame 215 are connected to the second substrate 209 through the sixth insulating layer 210. The second substrate 209 can be an aluminum-based copper-clad plate, and the sixth insulating layer 210 includes a pre-impregnated material with adhesive properties. The second substrate 209 uses an aluminum plate and is not prone to cracking during lamination, and the quality is more reliable, and the pre-impregnated material can be FR4 or BT. The thickness of the second substrate 209 and the sixth insulating layer 210 can be adjusted according to actual application and preparation process requirements. The third lead frame 215 is provided with a second upper bridge chip 217 and a second lower bridge chip 219, and a seventh insulating layer 212 is provided above the chips. The second substrate 209, the sixth insulating layer 210, the second upper bridge chip 217, the second lower bridge chip 219 and the seventh insulating layer 212 are fused into one whole through one-time lamination, so that the preparation process is simple, the aluminum plate is not prone to cracking during lamination, and the quality is more reliable.

[0157] The power electrode and the signal electrode are arranged on the surface of the vehicle-mounted charger and the DC\DC power assembly 200 to form a first electrode layer 225. The drain of the second upper bridge chip 217 is connected with the power electrode of the first electrode layer 225 through the seventeenth hole 223 and the eighth insulating layer 213, the source is connected with the third power connection layer 224 through the eighteenth hole 220 and the seventh insulating layer 212, and the drain of the second lower bridge chip 219 and the power electrode of the first electrode layer 225 are connected through the nineteenth hole 218 and the twentieth hole 227 and the seventh insulating layer 212 and the eighth insulating layer 213, respectively. The gate and the Kelvin source of the second upper bridge chip 217 are connected with the signal electrode of the first electrode layer 225 through the twenty-first hole 221 and the twenty-second hole 222 and the seventh insulating layer 212 and the eighth insulating layer 213, respectively. The source of the second lower bridge chip 219 is connected with the power electrode of the first electrode layer 225 through the twenty-third hole 226 and the seventh insulating layer 212 and the eighth insulating layer 213. The gate and the Kelvin source of the second lower bridge chip 219 are connected with the signal electrode of the first electrode layer 225 through the twenty-fourth hole 214 and the twenty-fifth hole 216 and the seventh insulating layer 212 and the eighth insulating layer 213, respectively.

[0158] With reference to Figure 12 and Figure 13 , Figure 12 An external structure of a vehicle-mounted compressor assembly 300 is shown, Figure 13 A simplified cross-sectional structure of a vehicle-mounted compressor assembly 300 is shown. The surface of the vehicle-mounted compressor assembly 300 is provided with a second high-voltage electrode 301 and a second signal low-voltage electrode 302. The third laminated plate 305 is provided with a plurality of empty slots, and the fourth lead frame 309 is embedded in the plurality of empty slots of the third laminated plate 305, and the thickness of the fourth lead frame 309 is the same as the thickness of the third laminated plate 305. The third laminated plate 305 and the fourth lead frame 309 are connected with the third substrate 303 through the ninth insulating layer 304. The third substrate 303 can be an aluminum-based copper-clad plate, and the ninth insulating layer 304 includes a pre-impregnated material with adhesive properties. The third substrate 303 adopts an aluminum plate, which is not easy to crack in lamination, and the quality is more reliable. The pre-impregnated material can be FR4 or BT. The thickness of the third substrate 303 and the ninth insulating layer 304 can be adjusted according to actual application and preparation process requirements. The fourth lead frame 309 is provided with a third upper bridge chip 313 and a third lower bridge chip 311, and a tenth insulating layer 306 is arranged above the chips. The third substrate 303, the ninth insulating layer 304, the third upper bridge chip 313, the third lower bridge chip 311 and the tenth insulating layer 306 are fused into one whole through one-time lamination, so that the preparation process is simple, the aluminum plate is not easy to crack in lamination, and the quality is more reliable.

[0159] The second high-voltage electrode 301 and the second signal low-voltage electrode 302 of the surface of the vehicle-mounted compressor assembly 300 can serve as a second electrode layer 319, wherein the second high-voltage electrode 301 is a power electrode, and the second signal low-voltage electrode 302 is a signal electrode. The drain of the third upper bridge chip 313 is electrically connected to the power electrode of the second electrode layer 319 through the twenty-sixth hole 317 and the tenth insulating layer 306 and the eleventh insulating layer 307, the source is connected to the fourth power connection layer 318 through the twentieth-seven hole 314 and the tenth insulating layer 306, and the drain of the third lower bridge chip 311 and the power electrode of the second electrode layer 319 are connected through the twenty-eighth hole 312 and the twenty-ninth hole 321 and the tenth insulating layer 306 and the eleventh insulating layer 307, respectively. The gate and the Kelvin source of the third upper bridge chip 313 are electrically connected to the signal electrode of the second electrode layer 319 through the thirtieth hole 315 and the thirty-first hole 316 and the tenth insulating layer 306 and the eleventh insulating layer 307. The source of the third lower bridge chip 311 is electrically connected to the second electrode layer 319 through the thirty-second hole 320 and the tenth insulating layer 306 and the eleventh insulating layer 307. The gate and the Kelvin source of the third lower bridge chip 311 are electrically connected to the signal electrode of the second electrode layer 319 through the thirty-third hole 308 and the thirty-fourth hole 310 and the tenth insulating layer 306 and the eleventh insulating layer 307.

[0160] Referring to Figure 14 , Figure 14 A structure of a semiconductor module is shown, and one embodiment of the present application also proposes a semiconductor module. In the present embodiment, the semiconductor module includes a base plate 400 and a power assembly as described above, and the power assembly is arranged on the base plate 400.

[0161] The specific structure and principle of the power assembly can refer to the foregoing embodiments, which have corresponding technical effects, and the present embodiment will not be described here.

[0162] In some embodiments, the power assembly includes at least one of a first power assembly, a second power assembly, and a third power assembly, the power chips in the first power assembly are used to build an inverter, the power chips in the second power assembly are used to build a charger, and the power chips in the third power assembly are used to build a DC / DC unit.

[0163] As an example, the plurality of power assemblies can be respectively configured as a main drive inverter power assembly 100, a vehicle-mounted charger, and a DC\DC power assembly 200, and a vehicle-mounted compressor assembly 300, and the main drive inverter power assembly 100, the vehicle-mounted charger, the DC\DC power assembly 200, and the vehicle-mounted compressor assembly 300 are fixed on the base plate 400.

[0164] The main drive inverter power assembly 100, the on-board charger and DC\DC power assembly 200 and the on-board compressor assembly 300 can be welded to the first side of the bottom plate 400, and the second side opposite to the first side of the bottom plate 400 is provided with a heat dissipation structure.

[0165] In the embodiment, the power assembly can be welded to the bottom plate 400 by solder after being made, so as to ensure the connection stability. In addition, the power assembly and the bottom plate 400 can also be connected by other ways, such as bonding. The same side welding leaves space for the second side, so as to facilitate the setting of the heat dissipation structure and improve the reliability of the power assembly.

[0166] The heat dissipation structure can be a heat dissipation rack integrated with the bottom plate 400. The material of the bottom plate 400 can be copper or aluminum, which has high thermal conductivity and improves the heat dissipation effect. Of course, the heat dissipation structure can also be of other types, such as air cooling or liquid cooling.

[0167] In some embodiments, the plurality of power assemblies includes at least two first power assemblies, and at least one first power assembly is used to build a vehicle motor main drive inverter, and at least one first power assembly is used to build an on-board compressor inverter. The power assembly integrates the vehicle motor main drive inverter and the on-board compressor inverter, effectively reduces the volume of the module, and improves the power density.

[0168] As an example, the power chip, power circuit and signal circuit in the first power assembly are configured as a three-phase full-bridge inverter circuit. In the case that the DC side of one of the first power assemblies is connected with the DC bus of the vehicle high-voltage system, and the AC side is connected with the vehicle motor, the first power assembly can be used as a vehicle motor main drive inverter. In the case that the DC side of another first power assembly is connected with the DC bus, and the AC side is connected with the compressor of the vehicle air conditioning system, the first power assembly can be used as a vehicle motor main drive inverter.

[0169] In some embodiments, the second power assembly and the third power assembly are integrally prepared. The second power assembly and the third power assembly can be different regions in a semiconductor structure as a whole. Thus, the connection line between the second power assembly and the third power assembly can be directly realized in the wiring layer 120, reducing the connection terminals and the binding wires, and improving the power density.

[0170] In the preparation process, when the chip layer 110 is formed on a first substrate 1, the power chip meeting the charger and the DC / DC unit is configured at the same time, and then the corresponding power circuit and signal circuit are formed in the wiring layer 120, so as to integrate the charger and the DC / DC unit in a semiconductor structure. The power connection relationship between the charger and the DC / DC unit is realized by the power circuit in the wiring layer 120.

[0171] One embodiment of the present application also provides a vehicle, which comprises the power assembly according to the foregoing. The specific structure and principle of the power assembly can refer to the foregoing embodiments, which also have corresponding technical effects, and will not be described here again.

[0172] In this document, the terms "comprise", "contain", or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or device that includes a list of elements not only includes those elements, but also includes other elements not expressly listed, or inherent to such a process, method, article, or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but can also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted, or combined. In addition, the features described with reference to certain examples can be combined in other examples.

[0173] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements, and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power component, characterized in that: Applied to vehicles, including: A chip layer, wherein the chip layer is provided with a power chip; a wiring layer, wherein the wiring layer is provided with control electrodes and conductive lines; a substrate, the substrate being arranged on a side of the chip layer away from the wiring layer; The wiring layer and the chip layer are stacked sequentially in a first direction, and the conductive line is connected between the power chip and the control electrode; The power chip includes an upper bridge chip and a lower bridge chip, the control electrode includes a first power electrode, a second power electrode, a third power electrode, a first signal electrode, and a second signal electrode, the conductive line includes a first power connection layer, a second power connection layer, a first power line, a second power line, a third power line, a first signal connection layer, a second signal connection layer, a first signal line, and a second signal line, the first power connection layer is respectively connected to the first power pin of the upper bridge chip, the first power pin of the lower bridge chip, and the first power electrode through the first power line, the first signal connection layer is respectively connected to the signal pin of the upper bridge chip and the first signal electrode through the first signal line, the second signal connection layer is respectively connected to the signal pin of the lower bridge chip and the second signal electrode through the second signal line, the second power connection layer is insulated and isolated from the first power connection layer, the second power connection layer is respectively connected to the second power pin and the second power electrode of the lower bridge chip through the second power line, and the third power line is connected between the second power pin of the upper bridge chip and the third power electrode; The chip layer further includes a frame layer, wherein the frame layer is provided with a first lead frame and a second lead frame, the upper bridge chip is connected to the first lead frame, and the lower bridge chip is connected to the second lead frame; The frame layer includes a laminate, the laminate is provided with a slot, the first lead frame and the second lead frame are provided in the slot, and the laminate is made of insulating material; The first power connection layer is connected to the first lead frame through the first power line to achieve connection with the first power pin of the upper bridge chip; and / or the first power connection layer is connected to the second lead frame through the first power line to achieve connection with the first power pin of the lower bridge chip; The power components are used to construct a vehicle motor main drive inverter, an on-board compressor inverter, an on-board charger and an on-board DC / DC unit.

2. The power component according to claim 1, characterized in that: The control electrode is arranged on a surface of the wiring layer away from the chip layer, and the conductive line is arranged in the wiring layer.

3. The power component according to claim 1, characterized in that The chip layer further includes: a thermistor connected to the first lead frame or the second lead frame and arranged close to the power chip; A detection electrode is further provided on a surface of the wiring layer on a side away from the chip layer. A detection circuit is further provided in the wiring layer. The detection circuit is connected between the thermistor and the detection electrode.

4. The power component according to claim 1, characterized in that: The wiring layer includes: an insulating layer, wherein the insulating layer and the chip layer are stacked in sequence in the first direction, and the insulating layer covers the power chip; The control electrode is arranged on a surface of the insulating layer away from the chip layer and is connected to the power chip through the conductive line.

5. The power component according to claim 4, characterized in that: The insulating layer is provided with a via hole in a first direction, and at least a portion of the conducting line is disposed in the via hole.

6. The power component according to claim 4, characterized in that: The insulating layer comprises: a first insulating layer, wherein a surface of the first insulating layer away from the chip layer is provided with the first power connection layer; A third insulating layer covers the power connection layer, and the first power electrode, the second power electrode, and the third power electrode are provided on a surface of the third insulating layer away from the first insulating layer.

7. The power component according to claim 6, characterized in that: The first insulating layer and the third insulating layer are provided with via holes in a first direction, and the first power circuit, the second power circuit, and the third power circuit are provided in the via holes.

8. The power component according to claim 4, characterized in that: The insulating layer comprises: a second insulating layer, wherein the first signal connection layer and the second signal connection layer are provided on a surface of the second insulating layer away from the chip layer; A third insulating layer covers the first signal connection layer and the second signal connection layer. The first signal electrode and the second signal electrode are provided on a surface of the third insulating layer away from the second insulating layer.

9. The power component according to claim 8, characterized in that: The second insulating layer and the third insulating layer are provided with via holes in a first direction, and the first signal line and the second signal line are provided in the via holes.

10. The power component according to claim 7, characterized in that: The insulating layer comprises: a second insulating layer, wherein the first signal connection layer and the second signal connection layer are provided on a surface of the second insulating layer away from the chip layer; The third insulating layer, the second insulating layer, and the first insulating layer are sequentially stacked in a first direction.

11. The power component according to claim 10, characterized in that: The first insulating layer is provided with a via hole in a first direction, and the first power circuit, the second power circuit and the third power circuit are provided in the via hole; The second insulating layer is provided with a via hole in a first direction, and the first signal line and the second signal line are provided in the via hole.

12. The power component according to claim 10, characterized in that The first insulating layer and / or the second insulating layer may include multiple layers.

13. The power component according to claim 1, characterized in that Also includes: A third insulating layer is provided between the chip layer and the substrate.

14. The power component according to claim 13, characterized in that: The substrate, the third insulating layer, the chip layer, and the wiring layer are laminated and fused.

15. The power component according to any one of claims 1 to 14, characterized in that: The number of the upper bridge chips and the number of the lower bridge chips are both multiple, the first power pin of each upper bridge chip and the first power pin of each lower bridge chip are connected to the same first power connection layer, and the second power pin of each lower bridge chip is connected to the same second power connection layer.

16. The power component according to claim 15, characterized in that The orthographic projection of each upper bridge chip on the substrate is located within the orthographic projection range of the first power connection layer on the substrate, and the orthographic projection of each lower bridge chip on the substrate is located within the orthographic projection range of the second power connection layer on the substrate.

17. The power component according to any one of claims 1 to 14, characterized in that: The upper bridge chip and the lower bridge chip each include a plurality of signal pins, the first signal connection layer and the second signal connection layer each include a plurality of sub-signal connection layers, and each sub-signal connection layer is connected to each signal pin of each upper bridge chip or each lower bridge chip.

18. The power component according to claim 17, characterized in that There are multiple upper bridge chips and multiple lower bridge chips, and the sub-signal connection layer includes a main connection line and multiple branch connection lines. The main connection line is connected to the signal electrode through a signal line, and the first end of the branch connection line is vertically connected to the main connection line. The second end of the branch connection line is connected to the signal pin of the corresponding upper bridge chip or the lower bridge chip through a signal line, and the lengths of the branch connection lines are the same.

19. A semiconductor module, characterized in that: include: base plate; The power component according to any one of claims 1 to 18, wherein the power component is arranged on the base plate.

20. The semiconductor module according to claim 19, wherein The power component includes at least one of a first power component, a second power component and a third power component. The power chip in the first power component is used to construct an inverter, the power chip in the second power component is used to construct an on-board charger, and the power chip in the third power component is used to construct an on-board DC / DC unit.

21. The semiconductor module according to claim 20, characterized in that The second power component and the third power component are manufactured integrally.

22. The semiconductor module according to any one of claims 19 to 21, characterized in that The power component is welded to a first side of the base plate, and a heat dissipation structure is provided on a second side of the base plate opposite to the first side.

23. The semiconductor module according to any one of claims 19 to 21, characterized in that The power component includes at least two first power components, at least one of which is used to construct a vehicle motor main drive inverter, and at least one of which is used to construct a vehicle compressor inverter.

24. A vehicle, characterized in that: The vehicle comprises a semiconductor module according to any one of claims 19-23.

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