Fault holding and pulse unlocking circuit and photovoltaic power station

Abstract

The invention provides a fault holding and pulse unlocking circuit and a photovoltaic power station, and the circuit comprises a controller which is provided with a first pin, a second pin, a third pin and a fourth pin, and the third pin is configured to output a low level or a high level according to a signal received by the second pin; the operational amplifier comparison circuit is connected with the first pin and the second pin, and the operational amplifier comparison circuit is configured to compare the sampling voltage and the reference voltage and output a signal to the second pin according to a comparison result; and the AND gate circuit is provided with an input end and an output end, the input end is connected with the third pin and the fourth pin, the output end is suitable for being connected with the inverter unit, and the AND gate circuit is configured to control the inverter unit to stop according to the low level received from the third pin and control the inverter unit to start according to the high level received from the third pin. The fault holding and pulse unlocking circuit and the photovoltaic power station have an autonomous unlocking function.

Description

Technical Field

[0001] This application mainly relates to the field of photovoltaic technology, and particularly relates to a fault holding and pulse unlocking circuit and a photovoltaic power station. Background Art

[0002] The photovoltaic energy storage inverter can not only convert the direct current output by the photovoltaic into alternating current, but also store the excess power through a battery energy storage device for later use. The fault holding and unlocking of the photovoltaic energy storage inverter is a control strategy that can prevent the photovoltaic energy storage inverter from being in abnormal working states such as overvoltage or overcurrent, so as to protect the devices and improve the system stability. When the sampling signal reaches the preset safety limit (such as when the energy storage system detects that the photovoltaic input current is too large, the battery charge and discharge current is too large, the bus voltage is too high, or the grid conditions are not suitable for the normal operation of the photovoltaic energy storage inverter, etc.), the switching pulse of the photovoltaic energy storage inverter is automatically temporarily turned off to stop the internal power conversion, so as to protect the battery pack and the grid from damage. If the fault of the photovoltaic energy storage inverter disappears and a fault unlocking pulse is received, for example, the battery voltage returns to the safe range and the grid condition improves, the pulse block will be released and the photovoltaic energy storage inverter will start working again. However, the existing fault holding and unlocking circuit does not have an autonomous unlocking function. Summary of the Invention

[0003] The technical problem to be solved by this application is to provide a fault holding and pulse unlocking circuit and a photovoltaic power station, and the fault holding and pulse unlocking circuit has an autonomous unlocking function.

[0004] To solve the above technical problem, this application provides a fault holding and pulse unlocking circuit, including: a controller having a first pin, a second pin, a third pin, and a fourth pin, where the third pin is configured to output a low level or a high level according to the signal received by the second pin; an operational amplifier comparison circuit connected to the first pin and the second pin, and the operational amplifier comparison circuit is configured to compare a sampling voltage and a reference voltage, and output a signal to the second pin according to the comparison result; and a AND gate circuit having an input end and an output end, the input end is connected to the third pin and the fourth pin, and the output end is suitable for being connected to an inverter unit, and the AND gate circuit is configured to control the inverter unit to stop operating according to the low level received from the third pin, and control the inverter unit to start operating according to the high level received from the third pin.

[0005] In an embodiment of this application, the operational amplifier comparison circuit includes a first open-drain output operational amplifier and a second open-drain output operational amplifier, and the output end of the first open-drain output operational amplifier and the non-inverting input end of the second open-drain output operational amplifier are respectively connected to the second pin and the first pin.

[0006] In an embodiment of the present application, when a fault occurs in the photovoltaic energy storage inverter, the voltage at the non-inverting input terminal of the first open-drain output operational amplifier is less than the voltage at the inverting input terminal, and the first open-drain output operational amplifier outputs a low level to the controller.

[0007] In an embodiment of the present application, the controller determines whether the sampled voltage has returned to normal. If it has returned to normal, a high level is output to the non-inverting input terminal of the second open-drain output operational amplifier. The output terminal of the second open-drain output operational amplifier outputs a high impedance to the non-inverting input terminal of the first open-drain output operational amplifier, and the first open-drain output operational amplifier outputs a high level to the controller.

[0008] In an embodiment of the present application, the high level output by the first pin is greater than the pull-up voltage, and the pull-up voltage is greater than the reference voltage.

[0009] In an embodiment of the present application, the reference voltage is applied to the inverting input terminal of the second open-drain output operational amplifier.

[0010] In an embodiment of the present application, the sampled voltage includes the bus voltage and / or the chip voltage.

[0011] In an embodiment of the present application, a resistor R1 and a resistor R2 are further included. The resistor R1 is connected in series between the sampled voltage and the inverting input terminal of the first open-drain output operational amplifier, and the resistor R2 is connected in series between the ground terminal and the inverting input terminal of the first open-drain output operational amplifier.

[0012] In an embodiment of the present application, the controller includes a microcontroller unit and a digital signal processor, and the microcontroller unit and the digital signal processor are connected to the input terminals of the AND gate circuit.

[0013] On the other hand, the present application also proposes a photovoltaic power station, including the fault holding and pulse unlocking circuit as described above.

[0014] Compared with the prior art, the present application has the following advantages: If the fault has been resolved or disappeared, when the microcontroller unit inputs a high level to the non-inverting input terminal of the second open-drain output operational amplifier, the output of the second open-drain output operational amplifier to the non-inverting input terminal of the first open-drain output operational amplifier is in a high-impedance state, so that the voltage at the non-inverting input terminal of the first open-drain output operational amplifier returns to the reference voltage. After the microcontroller unit detects the high level of the second pin, the inverter resumes the normal working state, thereby enabling the circuit of the present application to have an autonomous unlocking function. In addition, if the inverter fault still exists, even if the microcontroller unit issues a fault unlocking pulse to restore the voltage at the non-inverting input terminal of the first open-drain output operational amplifier to the reference voltage, the voltage at the inverting input terminal of the first open-drain output operational amplifier is still greater than the reference voltage, and the second pin of the microcontroller unit continuously receives a low level, causing the inverter to remain in the shutdown state, which avoids the system running with faults. Description of the Drawings

[0015] The accompanying drawings are provided to provide a further understanding of the present application, and they are incorporated into and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and, together with this specification, serve to explain the principles of the present application. In the accompanying drawings:

[0016] Figure 1 It is a circuit diagram of a fault holding and pulse unlocking circuit in an embodiment of the present application. Detailed Embodiments

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structure or operation.

[0018] As shown in the present application and the claims, unless the context clearly indicates an exceptional situation, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0019] Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

[0020] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal", and "top, bottom", etc. are usually based on the orientation or positional relationships shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. Without contrary instructions, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as limiting the protection scope of the present application; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0021] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above", etc. may be used here to describe the spatial positional relationship of a device or feature shown in the drawings with other devices or features. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation described in the drawings for the device. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." may include both the orientations of "above..." and "below...". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0022] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is merely for the convenience of distinguishing the corresponding components. Without additional statements, these terms have no special meaning, and thus should not be construed as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of this application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand this application not only through the actual terms used, but also through the meaning implied by each term.

[0023] Next, the fault holding and pulse unlocking circuit and photovoltaic power station of this application will be described through embodiments.

[0024] The fault holding and pulse unlocking circuit of this application includes: a controller, an operational amplifier comparison circuit, and an AND gate circuit. Specifically, as shown in Figure 1 for reference, the controller 110 has a first pin 111, a second pin 112, a third pin 113, and a fourth pin 114. The controller 110 may include a micro control unit (MCU) and a digital signal processor (DSP). The first pin 111 and the third pin 113 are arranged on the micro control unit, and the second pin 112 and the fourth pin 114 are arranged on the digital signal processor. The third pin 113 and the fourth pin 114 are connected to the input terminals of the AND gate circuit (U3) 120. The output terminal of the AND gate circuit 120 is connected to the inverter unit (INV), and the inverter unit may be connected to the power grid (Grid).

[0025] The digital signal processor can continuously output a pulse signal to the AND gate circuit 120 through the fourth pin 114. The third pin 113 is configured to output a low level or a high level to the AND gate circuit 120 according to the signal received by the second pin 112.

[0026] The operational amplifier comparison circuit 130 includes a first open-drain output operational amplifier (U1) 131 and a second open-drain output operational amplifier (U2) 132. The output terminal of the second open-drain output operational amplifier 132 is connected to the non-inverting input terminal of the first open-drain output operational amplifier 131. The output terminal of the first open-drain output operational amplifier 131 is connected to the second pin 112, and a resistor R6 may be connected in series between the output terminal of the first open-drain output operational amplifier 131 and the second pin 112. The non-inverting input terminal of the second open-drain output operational amplifier 132 is connected to the first pin 111, and the micro control unit can input a low level or a high level to the non-inverting input terminal of the second open-drain output operational amplifier 132 through the first pin 111.

[0027] The operational amplifier comparison circuit 130 is configured to compare the sampled voltage V AD and the reference voltage V ref, and output a signal to the second pin 112 according to the comparison result. The sampled voltage includes the bus voltage and / or the voltage of the chip in the photovoltaic energy storage inverter. The output signal is a high level or a low level.

[0028] As Figure 1 shown, the sampled voltage V AD is applied to the inverting input terminal of the first open-drain output operational amplifier 131. A resistor R1 can be connected in series between the sampled voltage V AD and the inverting input terminal. The reference voltage V ref is applied to the non-inverting input terminal of the first open-drain output operational amplifier 131. A resistor R7 can be connected in series between the reference voltage V ref and the non-inverting input terminal. The inverting input terminal of the first open-drain output operational amplifier 131 is grounded through a resistor R2. In addition, the reference voltage V ref is also applied to the inverting input terminal of the second open-drain output operational amplifier 132. A resistor R3 can be connected in series between the reference voltage V ref and the non-inverting input terminal.

[0029] In one embodiment, there is the following magnitude relationship among the voltages of the present application. The high level output by the first pin 111 is greater than the pull-up voltage +VA applied to the second pin 112, and the pull-up voltage +VA is greater than the reference voltage V ref .

[0030] Continuing to refer to Figure 1 shown, the AND gate circuit 120 has an input terminal and an output terminal. The input terminal is connected to the third pin 113 and the fourth pin 114, and the output terminal is connected to the inverter unit. If the third pin 113 outputs a low level to the AND gate circuit 120, the AND gate circuit 120 will output a shutdown signal to the inverter unit to control the shutdown of the inverter unit. The shutdown signal can be a low level, and the low level can block the switching pulse signal output by the fourth pin to the AND gate circuit 120, so that the inverter unit stops working. If the third pin 113 outputs a high level to the AND gate circuit 120, the AND gate circuit 120 will output a startup signal to the inverter unit to control the startup of the inverter unit. The startup signal can be a high level signal.

[0031] The above content makes a basic description of the circuit structure of the present application. To understand the present application more clearly, a non-limiting example is given below.

[0032] Set the magnitude of the high level emitted by the first pin 111 to be V H . As described above, the voltage V H is greater than the pull-up voltage +VA, and the pull-up voltage +VA is greater than the reference voltage V ref . The sampled voltage V AD generates a magnitude of through resistors R1 and R2 at the inverting input terminal of the first open-drain output operational amplifier 131. voltage

[0033] If the photovoltaic energy storage inverter is in a normal operating state, the reference voltage V ref is greater than the voltage The voltage received by the second pin 112 of the microcontroller unit through the resistor R6 is the pull-up voltage +VA, and the voltage at the non-inverting input terminal of the second open-drain output operational amplifier 132 is also the pull-up voltage +VA. Since the pull-up voltage +VA is greater than the reference voltage V ref , the output terminal of the second open-drain output operational amplifier 132 is in a high-impedance state, so it will not affect the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131. The voltage received by the microcontroller unit remains unchanged, the AND gate circuit 120 continuously outputs a high level to the inverter unit, and the inverter unit maintains normal operation.

[0034] If the photovoltaic energy storage inverter is in a fault state (for example, the sampling voltage V AD is too high), the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131, the reference voltage V ref is less than the voltage at its inverting input terminal The first open-drain output operational amplifier 131 outputs a low level to the second pin 112. At this time, the voltage received by the microcontroller unit through the resistor R6 is a low level. The microcontroller unit continuously outputs a low level to the AND gate circuit 120, thereby blocking the switching pulse signal generated by the digital signal processor and causing the inverter unit to stop operating and disconnect from the power grid to reduce related risks.

[0035] Since the voltage at the non-inverting input terminal of the second open-drain output operational amplifier 132 is a low level, which is less than the voltage at its inverting input terminal (i.e., the reference voltage V ref ), the second open-drain output operational amplifier 132 outputs a low level, which makes the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131 continuously remain at a low level. Whether the fault of the photovoltaic energy storage inverter disappears or not, the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131 will remain less than the voltage at its inverting input terminal, and the microcontroller unit continuously receives a low level, causing the inverter to remain in a shutdown state.

[0036] If the fault has been resolved or disappeared (the sampling voltage V AD returns to normal), then when the microcontroller unit inputs a high level V H at the non-inverting input terminal of the second open-drain output operational amplifier 132, the voltage at the non-inverting input terminal of the second open-drain output operational amplifier 132 is greater than the voltage at its inverting input terminal. The output of the second open-drain output operational amplifier 132 to the non-inverting input terminal of the first open-drain output operational amplifier 131 is in a high-impedance state, so that the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131 returns to the reference voltage V refSince the PV energy storage inverter has no fault, the reference voltage V ref is greater than the voltage at the inverting input terminal of the first open-drain output operational amplifier 131 At this time, the voltage received by the microcontroller unit through the resistor R6 is After the microcontroller unit detects the high level of the second pin 112, it outputs a high level to the AND gate circuit 120, thereby enabling the inverter to resume normal operation and having an autonomous unlocking function.

[0037] If the fault of the inverter still exists, even if the microcontroller unit issues a fault unlocking pulse to restore the voltage at the non-inverting input terminal of the first open-drain output operational amplifier 131 to the reference voltage V ref , the voltage at the inverting input terminal of the first open-drain output operational amplifier 131 is still greater than the reference voltage V ref , and the second pin 112 of the microcontroller unit continuously receives a low level, causing the inverter to remain in the shutdown state and avoiding the system running with a fault.

[0038] In one embodiment, the fault can be judged in the following way. The microcontroller unit periodically inputs a high level to the non-inverting input terminal of the second open-drain output operational amplifier 132 through the first pin 111. If the level fed back to the second pin 122 is high, it indicates that the fault has been eliminated. In addition, the microcontroller unit can also directly collect the sampling voltage V AD to judge whether the fault has disappeared.

[0039] On the other hand, the present application also proposes a photovoltaic power station, which includes the fault holding and pulse unlocking circuit as described above.

[0040] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation to the present application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0041] At the same time, the present application uses specific terms to describe the embodiments of the present application. Such as "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the present application can be appropriately combined.

[0042] Similarly, it should be noted that, in order to simplify the description disclosed in this application and thus help the understanding of one or more embodiments of the application, in the foregoing description of the embodiments of this application, multiple features are sometimes merged into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the subject matter of this application are more than those mentioned in the claims. In fact, the features of the embodiments are fewer than all the features of the single embodiments disclosed above.

[0043] In some embodiments, numbers are used to describe components and the quantity of attributes. It should be understood that such numbers used for the description of embodiments are modified by the modifiers "about", "approximate" or "substantially" in some examples. Unless otherwise stated, "about", "approximate" or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and such approximate values may change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used in some embodiments of this application to confirm the breadth of their scope are approximate values, in specific embodiments, the setting of such numerical values is as precise as possible within the feasible range.

[0044] Although this application has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the spirit of this application, they will fall within the scope of the claims of this application.

Claims

1. A fault holding and pulse unlocking circuit, characterized in that: include: A controller having a first pin, a second pin, a third pin and a fourth pin, wherein the third pin is configured to output a low level or a high level according to a signal received by the second pin; an operational amplifier comparison circuit connected to the first pin and the second pin, the operational amplifier comparison circuit being configured to compare the sampled voltage with a reference voltage and output a signal to the second pin according to a comparison result; as well as An AND gate circuit has an input end and an output end, wherein the input end is connected to the third pin and the fourth pin, and the output end is suitable for connecting to an inverter unit. The AND gate circuit is configured to control the inverter unit to shut down according to a low level received from the third pin, and to control the inverter unit to start up according to a high level received from the third pin.

2. The circuit according to claim 1, characterized in that The operational amplifier comparison circuit includes a first open-drain output operational amplifier and a second open-drain output operational amplifier, wherein the output terminal of the first open-drain output operational amplifier and the non-inverting input terminal of the second open-drain output operational amplifier are connected to the second pin and the first pin respectively.

3. The circuit according to claim 2, characterized in that When a fault occurs in the photovoltaic inverter, the voltage at the in-phase input terminal of the first open-drain output operational amplifier is lower than the voltage at the inverting input terminal, and the first open-drain output operational amplifier outputs a low level to the controller.

4. The circuit according to claim 2, characterized in that The controller determines whether the sampling voltage returns to normal. If so, it outputs a high level to the non-inverting input terminal of the second open-drain output operational amplifier. The output terminal of the second open-drain output operational amplifier outputs a high impedance to the non-inverting input terminal of the first open-drain output operational amplifier. The first open-drain output operational amplifier outputs a high level to the controller.

5. The circuit according to claim 2, characterized in that The high level output by the first pin is greater than the pull-up voltage, and the pull-up voltage is greater than the reference voltage.

6. The circuit according to claim 2, characterized in that The reference voltage is applied to the inverting input terminal of the second open-drain output operational amplifier.

7. The circuit according to claim 1, characterized in that The sampled voltage includes a bus voltage and / or a chip voltage.

8. The circuit according to claim 2, characterized in that It also includes a resistor R1 and a resistor R2, wherein the resistor R1 is connected in series between the sampling voltage and the inverting input terminal of the first open-drain output operational amplifier, and the resistor R2 is connected in series between the ground terminal and the inverting input terminal of the first open-drain output operational amplifier.

9. The circuit according to claim 1, characterized in that The controller comprises a micro control unit and a digital signal processor, and the micro control unit and the digital signal processor are connected to the input end of the AND gate circuit.

10. A photovoltaic power station, characterized in that: The invention comprises the fault holding and pulse unlocking circuit as claimed in any one of claims 1 to 9.

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