Integrated circuit with electrostatic discharge protection capability through charging device model

Abstract

The invention provides an integrated circuit with electrostatic discharge protection capability of a charged device model. The integrated circuit comprises a power rail line, a connecting pad, a first internal circuit, a second internal circuit and an electrostatic discharge protection circuit, the first internal circuit is coupled to the connection pad through the first signal wire. The second internal circuit is coupled to the first internal circuit through a second signal wire. The electrostatic discharge protection circuit is coupled between the second signal wire and the power rail line. When the integrated circuit is subjected to electrostatic discharge through the charging device model, the electrostatic discharge protection circuit conducts electrostatic discharge charges on the second signal wire to the power rail line.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to an integrated circuit having the electrostatic discharge (ESD) protection ability of a Charged-Device Model (CDM). Background Art

[0002] Electrostatic discharge (ESD) is an energy release caused by static electricity. Electronic devices may suffer permanent damage when subjected to high ESD voltages. There are three ESD models, namely the Human Body Model (HBM), the Machine Model (MM), and the Charged-Device Model (CDM). For HBM and MM, the source of ESD is outside the integrated circuit (IC). The ESD charge enters the IC from outside the IC via the pins and pads of the IC. To prevent the core circuit of the IC from being damaged by the ESD charge of HBM and MM, a general ESD protection circuit is generally configured beside the input or output bonding pads of the IC to discharge the ESD current nearby. Most of the existing ESD protection circuits are used to protect against ESD events of HBM and MM.

[0003] However, in addition to HBM and MM, there is also the ESD phenomenon of CDM. The situation simulated by CDM is that static charges are first stored in the internal circuit and / or the substrate of the floating IC. The internal circuit of the IC is also called the core circuit or the functional circuit. When a certain pin of the IC is suddenly grounded, the static charges in the IC will discharge through this pin. That is, the source of the ESD current of CDM is not the static electricity outside the IC, but instead the static charges accumulated in the internal circuit and / or the substrate of the IC. Such CDM ESD often causes the gate of the input-stage circuit in the internal circuit of the IC to be punched through. Although a general ESD protection circuit has been configured beside the input or output pads of the IC (i.e., the general ESD protection circuit is configured outside the internal circuit), the general ESD protection circuit may not be able to discharge the CDM ESD charge located inside the internal circuit in time, resulting in the ESD voltage of CDM damaging the electronic devices located inside the internal circuit. How to further prevent the ESD voltage of CDM from damaging electronic devices is one of the many technical issues in the field of electronic circuits. Summary of the Invention

[0004] The present invention provides an integrated circuit having a protection capability against Charged-Device Model (CDM) electrostatic discharge (ESD).

[0005] In an embodiment according to the present invention, the above-mentioned integrated circuit includes a first power rail, a pad, a first internal circuit, a second internal circuit, and a first ESD protection circuit. The first internal circuit is coupled to the pad through a first signal wire. The second internal circuit is coupled to the first internal circuit through a second signal wire. The first ESD protection circuit is coupled between the second signal wire and the first power rail. When CDM ESD occurs in the integrated circuit, the first ESD protection circuit conducts the ESD charge on the second signal wire to the first power rail.

[0006] Based on the above, in embodiments of the present invention, the first ESD protection circuit is configured in the internal circuit of the integrated circuit. A first end of the first ESD protection circuit is coupled to a critical path (such as the second signal wire) of the internal circuit. A second end of the first ESD protection circuit is coupled to the first power rail. When CDM ESD occurs, the first ESD protection circuit can conduct the ESD charge on the critical path to the first power rail in real time. Therefore, the first ESD protection circuit can effectively clamp the ESD voltage on the critical path and avoid the ESD voltage from damaging the electronic devices located in the internal circuit. That is, the integrated circuit has a protection capability against CDM ESD. Description of the Drawings

[0007] Figure 1 is a schematic diagram of a circuit block of an integrated circuit;

[0008] Figure 2 is a schematic diagram of a circuit block of an integrated circuit according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a circuit block of an integrated circuit according to another embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a circuit block of an integrated circuit according to still another embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of a circuit block of an ESD protection circuit arranged in an internal circuit layout area as shown in an embodiment of the present invention.

[0012] Description of the Reference Numerals

[0013] 100, 200, 300, 400: Integrated circuits

[0014] 110, 210, 310, 410: Bond pad layout areas

[0015] 111, 211, 311, 411: ESD clamping circuits

[0016] 112, 113, 212, 213, 312, 313, 412, 413, D51, D52: Diodes

[0017] 120, 220, 320, 420: Internal circuit layout areas

[0018] 121, 122, 221, 222, 321, 322, 421, 422: Internal circuits

[0019] 223, 323, 423, 424, 500: ESD protection circuits

[0020] 510, 520: Diode circuits

[0021] Mn51, Mp51: Transistors

[0022] P1, P2, P3, P4, PVDD1, PVDD2, PVDD3, PVDD4, PVSS1, PVSS2, PVSS3, PVSS4: Bond pads

[0023] PR11, PR12, PR21, PR22, PR31, PR32, PR41, PR42: Power rails

[0024] W11, W12, W21, W22, W31, W32, W41, W42: Signal conductors

[0025] W51, W52: Conductors Detailed implementation manners

[0026] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0027] As used throughout the specification (including the claims) of this case, the term "coupled (or connected)" may refer to any direct or indirect connection means. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means. The terms "first", "second", etc. mentioned throughout the specification (including the claims) of this case are used to name elements or to distinguish different embodiments or scopes, rather than to limit the upper or lower limit of the number of elements, nor to limit the order of the elements. Additionally, wherever possible, components / elements / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / elements / steps with the same reference numerals or the same terms used in different embodiments can be referred to the relevant descriptions.

[0028] Figure 1 is a schematic diagram of a circuit block of an integrated circuit 100. Generally speaking, the integrated circuit 100 includes a connection pad layout area 110 and an internal circuit layout area 120. The pads of the integrated circuit 100 are arranged in the connection pad layout area 110, and the internal circuit (functional circuit, or core circuit) is arranged in the internal circuit layout area 120. Based on the actual design, the pads in the connection pad layout area 110 can be bonding pads or other types of pads. In Figure 1 the illustrated embodiment, connection pad P1, connection pad PVDD1, and connection pad PVSS1 are used as examples of the pads in the connection pad layout area 110, and internal circuit 121 and internal circuit 122 are used as examples of the internal circuits in the internal circuit layout area 120.

[0029] Connection pad P1 can be a signal input pad or a signal output pad. Based on the actual design, connection pad P1 can be a bidirectional transmission signal pad. Internal circuit 121 is coupled to connection pad P1 through signal wire W11. Internal circuit 122 is coupled to internal circuit 121 through signal wire W12. Connection pad PVDD1 is coupled to power rail PR11. Power rail PR11 can transmit the power voltage of connection pad PVDD1 to the internal circuits of the integrated circuit 100 (such as internal circuits 121 and 122). Connection pad PVSS1 is coupled to power rail PR12. Power rail PR12 can transmit the reference voltage (such as ground voltage or other fixed voltage) of connection pad PVSS1 to the internal circuits of the integrated circuit 100 (such as internal circuits 121 and 122).

[0030] An electrostatic discharge (ESD) protection circuit is arranged in the connection pad layout area 110 and is configured near the connection pads of the integrated circuit 100 to discharge the ESD current of the connection pads nearby. Figure 1 In the illustrated embodiment, the ESD protection circuit includes an ESD clamping circuit 111, a diode 112, and a diode 113. The ESD clamping circuit 111 is coupled between the power rail line PR11 and the power rail line PR12. The specific implementation of the ESD clamping circuit 111 is not limited in this embodiment. For example, the ESD clamping circuit 111 may include a well-known ESD clamping circuit or other ESD clamping circuits. The cathode of the diode 112 is coupled to the power rail line PR11. The anode of the diode 112 and the cathode of the diode 113 are coupled to the connection pad P1. The anode of the diode 113 is coupled to the power rail line PR12.

[0031] When an ESD event occurs at the connection pad P1, the ESD protection circuit (ESD clamping circuit 111, diode 112, and diode 113) arranged in the connection pad layout area 110 can conduct the ESD charge at the connection pad P1 to at least one of the power rail line PR11 and the power rail line PR12. For example, when an ESD positive pulse occurs at the connection pad P1 and the connection pad PVDD1 is grounded, the diode 112 can timely conduct the ESD current from the connection pad P1 to the power rail line PR11. When an ESD positive pulse occurs at the connection pad P1 and the connection pad PVSS1 is grounded, the diode 112 can timely conduct the ESD current from the connection pad P1 to the power rail line PR11, and the ESD clamping circuit 111 can timely conduct the ESD current from the power rail line PR11 to the power rail line PR12. When an ESD negative pulse occurs at the connection pad P1 and the connection pad PVSS1 is grounded, the diode 113 can timely conduct the ESD current from the power rail line PR12 to the connection pad P1. When an ESD negative pulse occurs at the connection pad P1 and the connection pad PVDD1 is grounded, the ESD clamping circuit 111 can timely conduct the ESD current from the power rail line PR11 to the power rail line PR12, and the diode 113 can timely conduct the ESD current from the power rail line PR12 to the connection pad P1. Therefore, the ESD clamping circuit 111, the diode 112, and the diode 113 can prevent the ESD voltage or current from damaging the core circuits 121 and 122 located in the internal circuit layout area 120. It should be noted that the specific implementation of the ESD protection circuit located in the connection pad layout area 110 should not be limited to Figure 2 the illustrated circuit diagram. According to the actual design, there may be other ESD circuits in the connection pad layout area 110.

[0032] The ESD protection circuits located in the connection pad layout region 110, such as the ESD clamping circuit 111, the diodes 112 and 113, can effectively prevent ESD events of the Human Body Model (HBM) and / or the Machine Model (MM) from damaging the core circuits located in the internal circuit layout region 120. However, in addition to HBM and MM, there is also the ESD phenomenon of the Charged-Device Model (CDM). The source of the ESD current of CDM is not the static electricity outside the integrated circuit 100, but instead the static charge accumulated by the internal circuits and / or the substrate of the integrated circuit 100. For example, when the integrated circuit 100 is electrically floating, a large amount of static charge may be accumulated in the core circuits 121 and / or 122 due to various factors.

[0033] Although the ESD protection circuits are already configured beside the connection pads (i.e., the ESD protection circuits are configured outside the internal circuit layout region 120), the ESD protection circuits may not be able to discharge the CDM ESD charges located in the internal circuit layout region 120 in time. For example, assume that the signal wire W12 is a critical path and assume that a large amount of static charge is accumulated in the core circuit 122. When the connection pad P1 is suddenly grounded, the static charge (CDM ESD charge) accumulated in the core circuit 122 will be discharged to the connection pad P1 via the signal wire W12, the internal circuit 121, and the signal wire W11. The excessive ESD voltage on the signal wire W12 may damage the electronic devices located in the internal circuit 122 and / or the electronic devices located in the internal circuit 121. The following will illustrate with different embodiments how to further prevent the CDM ESD voltage on the signal wire W12 (critical path) from damaging the electronic devices.

[0034] Figure 2 It is a circuit block diagram of an integrated circuit 200 according to an embodiment of the present invention. Figure 2 The illustrated integrated circuit 200 includes a connection pad layout region 210 and an internal circuit layout region 220. Figure 2 The illustrated integrated circuit 200, the connection pad layout region 210, and the internal circuit layout region 220 can be referred to Figure 1Descriptions of the illustrated integrated circuit 100, connection pad layout region 110, and internal circuit layout region 120 are provided and extended by analogy. Connection pad P2, connection pad PVDD2, connection pad PVSS2, and the ESD protection circuit (ESD clamping circuit 211, diode 212, and diode 213) are arranged in the connection pad layout region 210, while signal wire W22, internal circuit 221, and internal circuit 222 are arranged in the internal circuit layout region 220. Figure 2 The illustrated connection pad P2, connection pad PVDD2, connection pad PVSS2, ESD clamping circuit 211, diode 212, diode 213, power rail line PR21, power rail line PR22, signal wire W21, signal wire W22, internal circuit 221, and internal circuit 222 can be referred to Figure 1 Descriptions of the illustrated connection pad P1, connection pad PVDD1, connection pad PVSS1, ESD clamping circuit 111, diode 112, diode 113, power rail line PR11, power rail line PR12, signal wire W11, signal wire W12, internal circuit 121, and internal circuit 122 are provided and extended by analogy, so they will not be elaborated here.

[0035] In Figure 2 the illustrated embodiment, the integrated circuit 200 further includes an ESD protection circuit 223. The ESD protection circuit 223 is arranged in the internal circuit layout region 220, and the ESD protection circuit 223 is coupled to a critical path within the internal circuit layout region 220. Figure 2 The illustrated signal wire W22 is assumed to be a critical path within the internal circuit layout region 220. The actual critical path within the internal circuit layout region 220 can be determined according to the actual design. The ESD protection circuit 223 is coupled between the signal wire W22 and the power rail line PR22. The power rail line PR22 is used to transmit a reference voltage (such as a ground voltage or other fixed voltage). When the integrated circuit 200 undergoes CDM ESD (Charged Device Model Electrostatic Discharge), the ESD protection circuit 223 can promptly conduct the ESD charge on the signal wire W22 to the power rail line PR22. When the integrated circuit 200 is operating normally, the ESD protection circuit 223 hardly affects the operation of the signal wire W22.

[0036] Figure 3 is a circuit block diagram of an integrated circuit 300 according to another embodiment of the present invention. Figure 3The illustrated integrated circuit 300 includes a connection pad layout region 310 and an internal circuit layout region 320. The connection pads P3, PVDD3, PVSS3, and the ESD protection circuit (ESD clamping circuit 311, diodes 312, and diodes 313) are arranged in the connection pad layout region 310, while the signal wire W32, the internal circuit 321, and the internal circuit 322 are arranged in the internal circuit layout region 320. Figure 3 The illustrated integrated circuit 300, connection pad layout region 310, internal circuit layout region 320, connection pads P3, PVDD3, PVSS3, ESD clamping circuit 311, diodes 312, diodes 313, power rail line PR31, power rail line PR32, signal wire W31, signal wire W32, internal circuit 321, and internal circuit 322 can be referred to Figure 1 the relevant descriptions of the illustrated integrated circuit 100, connection pad layout region 110, internal circuit layout region 120, connection pads P1, PVDD1, PVSS1, ESD clamping circuit 111, diodes 112, diodes 113, power rail line PR11, power rail line PR12, signal wire W11, signal wire W12, internal circuit 121, and internal circuit 122 and analogized, so details are not repeated here.

[0037] In Figure 3 the illustrated embodiment, the integrated circuit 300 further includes an ESD protection circuit 323. The ESD protection circuit 323 is arranged in the internal circuit layout region 320, and the ESD protection circuit 323 is coupled to the critical path within the internal circuit layout region 320. Figure 3 The illustrated signal wire W32 is assumed to be the critical path within the internal circuit layout region 320. The actual critical path within the internal circuit layout region 320 can be determined according to the actual design. The ESD protection circuit 323 is coupled between the signal wire W32 and the power rail line PR31. The power rail line PR31 is used to transmit the power supply voltage. When the integrated circuit 300 undergoes CDM ESD (Charged Device Model Electrostatic Discharge), the ESD protection circuit 323 can promptly conduct the ESD charge on the signal wire W32 to the power rail line PR31. When the integrated circuit 300 is operating normally, the ESD protection circuit 323 hardly affects the operation of the signal wire W32.

[0038] Figure 4 is a circuit block diagram of an integrated circuit 400 according to another embodiment of the present invention. Figure 4The integrated circuit 400 shown includes a connection pad layout region 410 and an internal circuit layout region 420. The connection pad P4, the connection pad PVDD4, the connection pad PVSS4, and the ESD protection circuit (ESD clamping circuit 411, diodes 412, and diodes 413) are arranged in the connection pad layout region 410, while the ESD protection circuit 423, the ESD protection circuit 424, the signal wire W42, the internal circuit 421, and the internal circuit 422 are arranged in the internal circuit layout region 420. Figure 4 The integrated circuit 400, the connection pad layout region 410, the internal circuit layout region 420, the connection pad P4, the connection pad PVDD4, the connection pad PVSS4, the ESD clamping circuit 411, the diodes 412, the diodes 413, the power rail line PR41, the power rail line PR42, the signal wire W41, the signal wire W42, the internal circuit 421, and the internal circuit 422 can be referred to Figure 1 the relevant descriptions of the integrated circuit 100, the connection pad layout region 110, the internal circuit layout region 120, the connection pad P1, the connection pad PVDD1, the connection pad PVSS1, the ESD clamping circuit 111, the diodes 112, the diodes 113, the power rail line PR11, the power rail line PR12, the signal wire W11, the signal wire W12, the internal circuit 121, and the internal circuit 122 shown, and by analogy, Figure 4 the ESD protection circuit 423 shown can be referred to Figure 3 the relevant descriptions of the ESD protection circuit 323 shown, and by analogy, while Figure 4 the ESD protection circuit 424 shown can be referred to Figure 2 the relevant descriptions of the ESD protection circuit 223 shown, and by analogy, so it will not be elaborated here.

[0039] Figure 5 is a circuit block diagram of the ESD protection circuit 500 arranged in the internal circuit layout region as shown in an embodiment of the present invention. Figure 5 The ESD protection circuit 500 shown is coupled between the wire W51 and the wire W52. Figure 5 The ESD protection circuit 500 shown can be used as Figure 2 one of the many embodiments of the ESD protection circuit 223 shown, so Figure 5 the ESD protection circuit 500, the wire W51, and the wire W52 shown can be referred to Figure 2 the relevant descriptions of the ESD protection circuit 223, the signal wire W22, and the power rail line PR22 shown. Or, Figure 5 The ESD protection circuit 500 shown can be used as Figure 3 one of the many embodiments of the ESD protection circuit 323 shown, so Figure 5The ESD protection circuit 500, wire W51, and wire W52 shown can be referred to Figure 3 the relevant descriptions of the ESD protection circuit 323, power rail PR31, and signal wire W32 shown. Alternatively, Figure 5 the ESD protection circuit 500 shown can be used as Figure 4 one of the many embodiments of the ESD protection circuit 423 shown. Therefore, Figure 5 the ESD protection circuit 500, wire W51, and wire W52 shown can be referred to Figure 4 the relevant descriptions of the ESD protection circuit 423, power rail PR41, and signal wire W42 shown. Alternatively, Figure 5 the ESD protection circuit 500 shown can be used as Figure 4 one of the many embodiments of the ESD protection circuit 424 shown. Therefore, Figure 5 the ESD protection circuit 500, wire W51, and wire W52 shown can be referred to Figure 4 the relevant descriptions of the ESD protection circuit 424, signal wire W42, and power rail PR42 shown.

[0040] In Figure 5 the embodiment shown, the ESD protection circuit 500 includes a diode circuit 510 and a diode circuit 520. The cathode of the diode circuit 510 and the anode of the diode circuit 520 are coupled to wire W51 (either a signal wire or a power rail), and the anode of the diode circuit 510 and the cathode of the diode circuit 520 are coupled to wire W52 (the other of the signal wire and the power rail). When there is a positive static charge of CDM on wire W51, the diode circuit 520 can conduct the positive static charge on wire W51 to wire W52. When there is a negative static charge of CDM on wire W51, the diode circuit 510 can conduct the negative static charge on wire W51 to wire W52. When there is a positive static charge of CDM on wire W52, the diode circuit 510 can conduct the positive static charge on wire W52 to wire W51. When there is a negative static charge of CDM on wire W52, the diode circuit 520 can conduct the negative static charge on wire W52 to wire W51.

[0041] This embodiment does not limit the implementation manner of rejecting extraction of the diode circuit 510 and the diode circuit 520. For example, the diode circuit 510 may include a diode D51 and a transistor Mp51, and the diode circuit 520 may include a diode D52 and a transistor Mn51. The cathode of the diode D51 is coupled to the cathode of the diode circuit 510. The first end (e.g., drain) and the control end (e.g., gate) of the transistor Mp51 are coupled to the anode of the diode D51. The second end (e.g., source) of the transistor Mp51 is coupled to the anode of the diode circuit 510. The anode of the diode D52 is coupled to the anode of the diode circuit 520. The first end (e.g., drain) and the control end (e.g., gate) of the transistor Mn51 are coupled to the cathode of the diode D52. The second end (e.g., source) of the transistor Mn51 is coupled to the cathode of the diode circuit 520.

[0042] In summary, the ESD protection circuit 500 is configured in the internal circuit of the integrated circuit. The first end of the ESD protection circuit 500 is coupled to a critical path (e.g., one of the wires W51 and W52) of the internal circuit. The second end of the ESD protection circuit 500 is coupled to the power rail line (e.g., the other of the wires W51 and W52). Static charges may gradually accumulate in the internal circuit to form a voltage difference. When the static charges accumulate enough to activate the diode circuit 510 and / or 520, the ESD protection circuit 500 can immediately conduct the ESD charges in the critical path to the power rail line. Therefore, the ESD protection circuit 500 can effectively clamp the ESD voltage in the critical path and prevent the ESD voltage from damaging the electronic devices located in the internal circuit.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: a first power rail; Connecting pads; a first internal circuit coupled to the connection pad via a first signal wire; a second internal circuit coupled to the first internal circuit via a second signal wire; and A first electrostatic discharge protection circuit is coupled between the second signal conductor and the first power rail, wherein When a charged device model electrostatic discharge occurs to the integrated circuit, the first electrostatic discharge protection circuit guides the electrostatic discharge charge on the second signal conductor to the first power rail.

2. The integrated circuit according to claim 1, characterized in that The first power rail is used to transmit a power voltage or a reference voltage.

3. The integrated circuit according to claim 1, characterized in that The integrated circuit further comprises: The second electrostatic discharge protection circuit is coupled between the second signal conductor and the second power rail, wherein: The first power rail is used to transmit one of a power supply voltage and a reference voltage, and the second power rail is used to transmit the other of the power supply voltage and the reference voltage; and When the CDM electrostatic discharge occurs in the integrated circuit, the second electrostatic discharge protection circuit guides the electrostatic discharge charge on the second signal conductor to the second power rail.

4. The integrated circuit according to claim 1, characterized in that The connection pad is configured in a connection pad layout area of ​​the integrated circuit, and the first internal circuit, the second internal circuit, the two signal wires and the first electrostatic discharge protection circuit are configured in an internal circuit layout area of ​​the integrated circuit.

5. The integrated circuit according to claim 4, characterized in that The integrated circuit further comprises: A second electrostatic discharge protection circuit is configured in the connection pad layout area, wherein the second electrostatic discharge protection circuit is coupled to the connection pad, The first power rail is used to transmit one of a power supply voltage and a reference voltage, the second power rail of the integrated circuit is used to transmit the other of the power supply voltage and the reference voltage, and When an electrostatic discharge event occurs on the connection pad, the second electrostatic discharge protection circuit guides the electrostatic discharge charge on the connection pad to at least one of the first power rail and the second power rail.

6. The integrated circuit according to claim 5, characterized in that The second electrostatic discharge protection circuit comprises: A first diode coupled between the connection pad and the first power rail; and The second diode is coupled between the connection pad and the second power rail.

7. The integrated circuit according to claim 5, characterized in that The second electrostatic discharge protection circuit comprises: The electrostatic discharge clamp circuit is coupled between the first power rail and the second power rail.

8. The integrated circuit according to claim 1, characterized in that The first electrostatic discharge protection circuit comprises: a first diode circuit, wherein a cathode of the first diode circuit is coupled to the second signal conductor and an anode of the first diode circuit is coupled to the first power rail; and A second diode circuit, wherein an anode of the second diode circuit is coupled to the second signal conductor, and a cathode of the second diode circuit is coupled to the first power rail.

9. The integrated circuit according to claim 8, characterized in that The first diode circuit comprises: a diode, wherein a cathode of the diode is coupled to the cathode of the first diode circuit; and A transistor, wherein a first terminal and a control terminal of the transistor are coupled to the anode of the diode, and a second terminal of the transistor is coupled to the anode of the first diode circuit.

10. The integrated circuit according to claim 8, characterized in that The second diode circuit comprises: a diode, wherein an anode of the diode is coupled to the anode of the second diode circuit; and A transistor, wherein a first terminal and a control terminal of the transistor are coupled to a cathode of the diode, and a second terminal of the transistor is coupled to the cathode of the second diode circuit.

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