Power supply end processing circuit and processing method of ARC arc

Abstract

The invention discloses a power supply end processing circuit and a processing method of an ARC arc. A simple hardware circuit is adopted to realize ARC rapid detection. In the power output part, bipolar pulse output is realized by adopting full-bridge control; in the aspect of signal acquisition, the accuracy of voltage and current sampling is improved through a differential circuit. Meanwhile, the invention further provides a solution for eliminating the ARC influence, on one hand, a large number of charged ions gathered when ARC is generated are neutralized in time through a charge neutralization technology, and the problem that a battery piece is stuck and burnt is effectively avoided; on the other hand, energy loss caused by ARC in the technological process is accurately compensated through the energy compensation technology, and the problem that a cell film layer is thin and red due to the fact that a cavity is unstable is solved. According to the rapid detection circuit, the charge neutralization technology and the energy compensation technology are combined, so that the influence of an ARC arc on the yield and the quality of the battery piece caused by the instability of the cavity and the improper loading of the battery piece is reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and particularly to a power supply end processing circuit and a processing method for an ARC arc. Background Art

[0002] In the production of photovoltaic cells, PECVD (Plasma Enhanced Chemical Vapor Deposition) technology is used. During the plasma discharge process, the reaction gas in the cavity is ionized into charged particles (ions and electrons) by applying high-frequency energy. If the charged particles are unevenly distributed, an arc will be formed during the discharge. The generation of the arc will have a great impact on the coating of the cell (such as jamming and burning, and the uniformity of the film thickness of the cell). Therefore, the power supply processing after the generation of the ARC arc is very important. We have a method for rapid detection, but the actions performed after detection are also a very important link. Please refer to Figure 1 , currently, the existing technology is that after detecting the ARC arc, the output is directly turned off for 100 μs, and then the output is performed again. Processing the ARC arc in this way only achieves the result of extinguishing the ARC arc. Although the ARC arc is extinguished, the impact still remains.

[0003] During the starting process (the initial ionization process), as the current climbs, special gas molecules (such as NH 4 , CH 4 , N 2 O and other gases) will be ionized into ions. As the discharge cavity gradually stabilizes, the ions will also reach an equilibrium. When an ARC is generated, this equilibrium will be broken, and charged ions will accumulate at the arc, resulting in uneven conductivity of the cell and jamming and burning at the cell jamming points. Specifically, please refer to Figure 2 , the schematic diagram of the discharge cavity is divided into a left boat leaf and a right boat leaf. The cell is attached to the boat leaf, and the cell is fixed on it by jamming points. The discharge cavity has a special gas, high temperature, and vacuum environment. The special gas is continuously provided, and the flow rate of the special gas in the cavity can also be kept constant. The output of the power supply is connected to the left and right boat leaves. The special gas is between the boat leaves. By applying a bipolar pulse signal to the boat leaves, the special gas between the two boat leaves is ionized. Due to the high temperature and vacuum environment, the ions will undergo chemical reactions, and the alternating magnetic field provides energy to transport the reaction substances to the cell. During ARC, the current will concentrate at a point, and a large number of ionized ions will fill the space between the two boat leaves. At the jamming points, due to direct contact with the side, a large number of charged ions will increase the conductivity of the contact surface. If not removed in time, it will cause the current of a single cell to be too large, resulting in burning of the cell at the jamming points. Jamming and burning of the cell are irreversible and cannot be made to work properly through production rework. Usually, it will be directly scrapped. Therefore, reducing the problem of jamming and burning in cell production is also a technical problem.

[0004] In addition, the impact of ARC is not only the charring at the stuck points. In the production process for automatic control, the process time is fixed. If the ARC causes excessive output shutdowns, the actual reaction time cannot reach the process time, resulting in thinner film coating on the battery wafers. Because the 100 μs of shutdown represents missing energy, as the number of ARC arcs increases, the missing time accumulates. The accumulated time causes the wafers to turn red (when the film coating on the wafers becomes thinner, it is regarded as turning red). The severity of the red wafers is lower than that of the charred wafers at the stuck points, and the red wafers can be reworked by cleaning and then processed again. However, rework will affect the quality of the wafers, possibly downgrading A-grade battery wafers to B-grade battery wafers (the lower the grade of the battery wafers, the lower the selling price), and it also affects the production progress. The energy compensation measures after ARC included in the present invention can solve the problem of missing energy caused by excessive ARC occurrences, resulting in red wafers that need rework, thereby increasing the production efficiency of the battery wafers. Summary of the Invention

[0005] The purpose of the present invention is to provide a power supply terminal processing circuit and method for ARC arcs, which can reduce the impact of ARC arcs on the output and quality of battery wafers.

[0006] The present invention provides a power supply terminal processing circuit for ARC arcs, comprising

[0007] a sampling module, configured to collect voltage signals and current signals in the discharge cavity, and convert the voltage signals and current signals into recognizable voltage signals respectively;

[0008] a frequency-voltage conversion module, configured to convert the recognizable voltage signals into frequency signals;

[0009] an operational amplifier module, configured to perform signal amplification processing on the frequency signals;

[0010] a comparator module, configured to compare the amplified frequency signals with a preset threshold, judge whether the voltage signals and current signals meet the trigger conditions according to the comparison results, and output a trigger signal to the logic module when the voltage signals and the current signals meet the trigger conditions simultaneously;

[0011] the logic module is configured to generate a control signal according to the trigger signal; wherein, the control signal includes a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation;

[0012] a full-bridge output module, configured to perform charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signal.

[0013] Further, the frequency-voltage conversion module includes: a frequency-voltage conversion chip U106, a first operational amplifier chip U110A, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5;

[0014] A first pin of the frequency-voltage conversion chip U106 is connected to an inverting input terminal of the first operational amplifier chip U110A through the first resistor R1, and the first pin is also connected to an output terminal of the first operational amplifier chip U110A through the second resistor R2;

[0015] The fifth capacitor C5 is connected between the inverting input terminal and the output terminal of the first operational amplifier chip U110A;

[0016] A second pin of the frequency-voltage conversion chip U106 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the other end of the fourth resistor R4 is also connected to the first pin of the frequency-voltage conversion chip U106 through the first capacitor C1;

[0017] The third and fourth pins of the frequency-voltage conversion chip U106 are grounded;

[0018] A fifth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the fifth resistor R5 and one end of the second capacitor C2; the other end of the second capacitor C2 is grounded; the other end of the fifth resistor R5 is connected to an eighth pin of the frequency-voltage conversion chip U106;

[0019] A sixth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the sixth resistor R6 and one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the logic module through a frequency input port, and the other end of the sixth resistor R6 is connected to the eighth pin;

[0020] A seventh pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the seventh resistor R7 is connected to the eighth pin; the other end of the eighth resistor R8 is grounded;

[0021] The eighth pin of the frequency-voltage conversion chip U106 is also connected to one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is grounded.

[0022] Further, the operational amplification module includes a second operational amplifier chip U110B, a ninth resistor R9, and a tenth resistor R10;

[0023] The inverting input terminal of the second operational amplifier chip U110B is connected to the output terminal of the first operational amplifier chip U110A through the ninth resistor R9; the non-inverting input terminal of the second operational amplifier chip U110B is grounded, and the output terminal is connected to the input terminal of the comparator module; a tenth resistor R10 is connected between the output terminal and the inverting input terminal of the second operational amplifier chip U110B.

[0024] Further, the comparator module includes a comparator U94A, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15;

[0025] The inverting input terminal of the comparator U94A is connected to the output terminal of the second operational amplifier chip U110B through the eleventh resistor R11, and the inverting input terminal of the comparator U94A is also connected to the sampling signal through the twelfth resistor R12; the non-inverting input terminal of the comparator U94A is grounded through the thirteenth resistor R13 and is also connected to the output terminal of the comparator U94A through the fourteenth resistor R14; the output terminal of the comparator U94A is connected to the power supply voltage through the fifteenth resistor R15.

[0026] Further, the sampling module includes a voltage sampling module;

[0027] The voltage sampling module includes a third operational amplifier chip U1B, a fourth operational amplifier chip U1A, a first terminal block J1, a second terminal block J2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, and a thirty-first resistor R31;

[0028] The voltage signal is input through the first terminal block J1 and the second terminal block J2. One end of the eighteenth resistor R18 is connected to the first terminal block J1, and the other end of the eighteenth resistor R18 is connected to the fifth pin of the third operational amplifier chip U1B through the nineteenth resistor R19. The other end of the nineteenth resistor R19 is also grounded through the sixteenth resistor R16; the other end of the eighteenth resistor R18 is also grounded through the seventeenth resistor R17; the other end of the eighteenth resistor R18 is also connected to the second pin of the fourth operational amplifier chip U1A through the twenty-sixth resistor R26;

[0029] The second terminal J2 is connected to one end of the twenty-eighth resistor R28. The other end of the twenty-eighth resistor R28 is connected to ground through the thirty-first resistor R31. The other end of the twenty-eighth resistor R28 is also connected to the sixth pin of the third operational amplifier chip U1B through the twenty-first resistor R21. The other end of the twenty-eighth resistor R28 is also connected to the third pin of the fourth operational amplifier chip U1A through the twenty-ninth resistor R29. The other end of the twenty-ninth resistor R29 is also grounded through the thirtieth resistor R30;

[0030] The sixth pin of the third operational amplifier chip U1B is also connected to the seventh pin of the third operational amplifier chip U1B through the twenty-second resistor R22;

[0031] The second pin of the fourth operational amplifier chip U1A is also connected to the first pin of the fourth operational amplifier chip U1A through the twenty-fifth resistor R25;

[0032] The seventh pin of the third operational amplifier chip U1B is grounded in sequence through the twentieth resistor R20 and the twenty-third resistor R23. The twentieth resistor R20 is also connected to the first voltage output port;

[0033] The first pin of the fourth operational amplifier chip U1A is grounded in sequence through the twenty-seventh resistor R27 and the twenty-fourth resistor R24. The twenty-seventh resistor R27 is also connected to the second voltage output port.

[0034] Further, the sampling module includes a current sampling module:

[0035] The current sampling module includes: a current transformer LEM1, a thirty-second resistor R32, a first inductor L1, a second inductor L2, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and an eleventh capacitor C11;

[0036] The current signal is input through the third input terminal J3 and the fourth input terminal J4. The third input terminal J3 is connected to the fourth pin, fifth pin, and sixth pin of the current transformer LEM1. The fourth input terminal J4 is connected to the seventh pin, eighth pin, and ninth pin of the current transformer LEM1. The third pin of the current transformer LEM1 outputs the current signal after being grounded through the thirty-second resistor R32;

[0037] The positive working voltage is input to the second pin of the current transformer LEM1 through the first inductor L1, and the second pin is also grounded through the parallel connection of the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8; the negative working voltage is input to the first pin of the current transformer LEM1 through the second inductor L2, and the first pin is also grounded through the parallel connection of the ninth capacitor C9, the tenth capacitor C10, and the eleventh capacitor C11.

[0038] Further, the full-bridge output module includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a twelfth capacitor C12, and a DC source DC;

[0039] The twelfth capacitor C12 is connected in parallel across the DC source DC. The positive pole of the DC source DC is sequentially connected to the source electrodes of the third MOS transistor Q3 and the second MOS transistor Q2, and the negative pole of the DC source DC is sequentially connected to the drain electrodes of the fourth MOS transistor Q4 and the first MOS transistor Q1; the drain electrode of the third MOS transistor Q3 is connected to the source electrode of the fourth MOS transistor Q4, and the connection point is connected to the discharge cavity; the drain electrode of the second MOS transistor Q2 is connected to the source electrode of the first MOS transistor Q1, and the connection point is connected to the discharge cavity; the gate electrodes of the third MOS transistor Q3 and the first MOS transistor Q1 are connected to one path of drive signal, and the gate electrodes of the fourth MOS transistor Q4 and the second MOS transistor Q2 are connected to another path of drive signal.

[0040] Further, the logic module includes: an MCU and a driver;

[0041] The MCU sends two paths of drive signals to the driver. After the driver performs differential processing on the two paths of drive signals, the two paths of drive signals are respectively transmitted into the gate electrodes of the third MOS transistor Q3 and the first MOS transistor Q1 and the gate electrodes of the fourth MOS transistor Q4 and the second MOS transistor Q2 of the full-bridge output module.

[0042] On the other hand, the present invention also provides a method for processing the power supply end of an ARC arc. The method includes the following steps:

[0043] Collect the voltage signal and current signal in the discharge cavity, and respectively convert the voltage signal and current signal into recognizable voltage signals;

[0044] Convert the recognizable voltage signal into a corresponding frequency signal;

[0045] Amplify the frequency signal;

[0046] Compare the amplified frequency signal with a preset threshold value, and judge whether there is an ARC arc according to the comparison result. If there is an ARC arc, generate a trigger signal;

[0047] When receiving the trigger signal, generate corresponding control signals according to different trigger conditions; wherein, the control signals include a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation;

[0048] Perform charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signal.

[0049] Further, generating corresponding control signals according to different trigger conditions, and performing charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signal includes:

[0050] Record the current direction when ARC occurs in the Nth cycle, and send a reverse current control signal for performing charge neutralization in the (N + 1)th cycle, where the reverse current control signal is used to control the current direction output by the full-bridge output module in the (N + 1)th cycle to be opposite to the current direction when ARC occurs in the Nth cycle;

[0051] Or, when the number of times ARC appears in the same conduction cycle exceeds a preset value, calculate the turn-off time of ARC; generate a pulse width modulation signal for performing energy compensation according to the turn-off time, where the pulse width modulation signal is used to control the MOS tube in the full-bridge output module to extend the conduction time.

[0052] Compared with the prior art, the present invention has at least the following technical effects:

[0053] The voltage and current signals in the discharge cavity are converted into recognizable voltage signals through the sampling module, processed and converted into amplified frequency signals through the frequency-voltage conversion module and the operational amplifier module, the comparator module compares the signal with a preset threshold to determine whether the trigger condition is met, when the trigger condition is met, the logic module generates corresponding control signals, and finally the full-bridge output module selectively performs charge neutralization or energy compensation processing according to the control signals, so that the ARC arc in the discharge cavity can be detected and processed quickly and accurately, effectively reducing the influence of the ARC arc on the process. Description of the Drawings

[0054] Figure 1 It is the output waveform diagram of ARC arc processing in the prior art;

[0055] Figure 2 It is the structural schematic diagram of the discharge cavity in the prior art;

[0056] Figure 3 It is the structural schematic diagram of the power supply end processing circuit of the ARC arc in the first embodiment of the present invention;

[0057] Figure 4 Schematic diagram of the circuit structure of the ARC detection module in the first embodiment of the present invention;

[0058] Figure 5 Schematic diagram of the circuit structure of the voltage sampling module in the first embodiment of the present invention;

[0059] Figure 6 Schematic diagram of the circuit structure of the current sampling module in the first embodiment of the present invention;

[0060] Figure 7 Schematic diagram of the structure of the full - bridge output module in the first embodiment of the present invention;

[0061] Figure 8 Schematic diagram of the structure of the logic module in the first embodiment of the present invention;

[0062] Figure 9 Flowchart of the method for processing the power supply terminal of the ARC arc in the second embodiment of the present invention;

[0063] Figure 10 UI waveform diagram during charge neutralization in UI - ARC in the second embodiment of the present invention;

[0064] Figure 11 Waveform diagram of energy compensation processing in the second embodiment of the present invention. Detailed implementation manners

[0065] The following will describe a power supply terminal processing circuit and method for an ARC arc of the present invention in conjunction with the schematic diagrams. Among them, the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as broad guidance for those skilled in the art and not as a limitation to the present invention.

[0066] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0067] Embodiment 1

[0068] Please refer to Figures 3 - 8 , this embodiment provides a power supply terminal processing circuit for an ARC arc. The circuit includes:

[0069] The sampling module is used to collect the voltage signal and current signal in the discharge cavity and convert the voltage signal and current signal into recognizable voltage signals respectively. The frequency-voltage conversion module is used to convert the recognizable voltage signal into a frequency signal. The operational amplifier module is used to amplify the frequency signal. The comparator module is used to compare the amplified frequency signal with a preset threshold, and judge whether there is an ARC arc according to the comparison result. If there is an ARC arc, a trigger signal is generated.

[0070] In this embodiment, the frequency-voltage conversion module, the comparator module and the operational amplifier module together constitute an ARC detection module. The ARC detection module is a fast detection circuit built by using a hardware circuit. Compared with the detection method using software calculation, it avoids the delay caused by software calculation, has the characteristics of fast response speed and strong real-time performance, and can detect and respond at the first time when the ARC arc occurs, so as to effectively reduce the impact of the ARC arc on the production of battery wafers.

[0071] Further, when the logic module receives the trigger signal, corresponding control signals are generated according to different trigger conditions; wherein, the control signals include a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation. The processing circuit further includes a full-bridge output module for performing charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signals.

[0072] In this embodiment, the voltage and current signals in the discharge cavity are converted into recognizable voltage signals by the sampling module, and are processed and converted into an amplified voltage signal by the frequency-voltage conversion module and the operational amplifier module. The comparator module compares the signal with a preset threshold to judge whether the trigger condition is met. When the trigger condition is met, the logic module generates corresponding control signals, and finally the full-bridge output module selectively performs charge neutralization or energy compensation processing according to the control signals, so as to be able to quickly and accurately detect and process the ARC arc in the discharge cavity and effectively reduce the impact of the ARC arc on the process.

[0073] Please refer to Figure 4 In a specific embodiment, the frequency-voltage conversion module includes: a frequency-voltage conversion chip U106, a first operational amplifier chip U110A, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5.

[0074] Specifically, the first pin of the frequency-voltage conversion chip U106 is connected to the inverting input terminal of the first operational amplifier chip U110A through the first resistor R1, and the first pin is also connected to the output terminal of the first operational amplifier chip U110A through the second resistor R2.

[0075] The fifth capacitor C5 is connected between the inverting input terminal (pin 2) and the output terminal (pin 1) of the first operational amplifier chip U110A.

[0076] The second pin of the frequency-voltage conversion chip U106 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the other end of the fourth resistor R4 is also connected to the first pin of the frequency-voltage conversion chip U106 through the first capacitor C1.

[0077] The third and fourth pins of the frequency-voltage conversion chip U106 are grounded.

[0078] The fifth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the fifth resistor R5 and one end of the second capacitor C2; the other end of the second capacitor C2 is grounded; the other end of the fifth resistor R5 is connected to the eighth pin of the frequency-voltage conversion chip U106.

[0079] The sixth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the sixth resistor R6 and one end of the third capacitor C3. The other end of the third capacitor C3 is connected to the logic module through the frequency input port, and the other end of the sixth resistor R6 is connected to the eighth pin.

[0080] The seventh pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the seventh resistor R7 is connected to the eighth pin; the other end of the eighth resistor R8 is grounded.

[0081] The eighth pin of the frequency-voltage conversion chip U106 is also connected to one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is grounded.

[0082] In this embodiment, the frequency-voltage conversion chip U106 is used to convert a voltage signal into a signal of a corresponding frequency; the operational amplifier chip is used to amplify the signal to improve the signal strength; the first to fifth capacitors C5 are used for filtering and stabilizing; the first to eighth resistors R8 are used to set working parameters and divide voltage and limit current. Through the reasonable cooperation of the frequency-voltage conversion chip U106, the operational amplifier chip, the resistors and the capacitors, the frequency-voltage conversion module accurately converts the voltage and current signals into corresponding frequency signals, providing a reliable input for the subsequent ARC arc detection.

[0083] In another specific embodiment, the operational amplifier module includes a second operational amplifier chip U110B, a ninth resistor R9, and a tenth resistor R10.

[0084] Specifically, the inverting input terminal of the second operational amplifier chip U110B is connected to the output terminal of the first operational amplifier chip U110A through the ninth resistor R9; the non-inverting input terminal of the second operational amplifier chip U110B is grounded, and the output terminal is connected to the input terminal of the comparator module; a tenth resistor R10 is connected between the output terminal and the inverting input terminal of the second operational amplifier chip U110B.

[0085] In this embodiment, the signal output by the first operational amplifier is input through the inverting input terminal of the second operational amplifier chip U110B, the non-inverting terminal is grounded to provide a stable reference, and the resistance ratio of the ninth resistor R9 and the tenth resistor R10 is used to set a fixed amplification factor, so as to further amplify the frequency signal. Finally, the amplified signal is transmitted to the comparator module for signal comparison. The circuit structure is simple, easy to implement, and has good linearity and stability.

[0086] In another specific embodiment, the comparator module includes a comparator U94A, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15.

[0087] Specifically, the inverting input terminal of the comparator U94A is connected to the output terminal of the second operational amplifier chip U110B through the eleventh resistor R11, and the inverting input terminal of the comparator U94A is also connected to the sampled signal through the twelfth resistor R12; the non-inverting input terminal of the comparator U94A is grounded through the thirteenth resistor R13 and is also connected to the output terminal of the comparator U94A through the fourteenth resistor R14; the output terminal of the comparator U94A is connected to the power supply voltage through the fifteenth resistor R15.

[0088] In this embodiment, the comparator module respectively inputs the signal amplified by the operational amplifier and the sampled signal through the inverting input terminal of the comparator U94A. The non-inverting input terminal is grounded through the thirteenth resistor R13 to provide a reference potential, and positive feedback is realized through the fourteenth resistor R14. The eleventh resistor R11 and the twelfth resistor R12 are used to set a preset threshold for signal comparison, and the fifteenth resistor R15 is used as a pull-up resistor to pull up the output signal to the power supply level. The circuit structure is simple, has good anti-interference ability and fast response characteristics.

[0089] In this embodiment, the sampling module includes a voltage sampling module and a current sampling module.

[0090] Please refer toFigure 5 , specifically, the voltage sampling module includes a third operational amplifier chip U1B, a fourth operational amplifier chip U1A, a first terminal J1, a second terminal J2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, and a thirty-first resistor R31.

[0091] The voltage signal is input through the first terminal J1 and the second terminal J2. One end of the eighteenth resistor R18 is connected to the first terminal J1, and the other end of the eighteenth resistor R18 is connected to the fifth pin of the third operational amplifier chip U1B through the nineteenth resistor R19. The other end of the nineteenth resistor R19 is also grounded through the sixteenth resistor R16; the other end of the eighteenth resistor R18 is also grounded through the seventeenth resistor R17; the other end of the eighteenth resistor R18 is also connected to the second pin of the fourth operational amplifier chip U1A through the twenty-sixth resistor R26.

[0092] One end of the second terminal J2 is connected to the twenty-eighth resistor R28. The other end of the twenty-eighth resistor R28 is grounded through the thirty-first resistor R31, and the other end of the twenty-eighth resistor R28 is also connected to the sixth pin of the third operational amplifier chip U1B through the twenty-first resistor R21. The other end of the twenty-eighth resistor R28 is also connected to the third pin of the fourth operational amplifier chip U1A through the twenty-ninth resistor R29; the other end of the twenty-ninth resistor R29 is also grounded through the thirtieth resistor R30.

[0093] The sixth pin of the third operational amplifier chip U1B is also connected to the seventh pin of the third operational amplifier chip U1B through the twenty-second resistor R22.

[0094] The second pin of the fourth operational amplifier chip U1A is also connected to the first pin of the fourth operational amplifier chip U1A through the twenty-fifth resistor R25.

[0095] The seventh pin of the third operational amplifier chip U1B is grounded sequentially through the twentieth resistor R20 and the twenty-third resistor R23; the twentieth resistor R20 is also connected to the first voltage output port.

[0096] The first pin of the fourth operational amplifier chip U1A is grounded successively through the twenty-seventh resistor R27 and the twenty-fourth resistor R24; the twenty-seventh resistor R27 is also connected to the second voltage output port.

[0097] Specifically, in this embodiment, the operational amplifier chip serves as the core of the differential amplifier to achieve signal amplification and level conversion. The sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, and nineteenth resistor R19 form the input voltage division of the first path. The twenty-eighth resistor R28, twenty-ninth resistor R29, thirtieth resistor R30, and thirty-first resistor R31 form the input voltage division of the second path. The feedback adjustment resistors (twentieth resistor R20, twenty-third resistor R23, twenty-seventh resistor R27, and twenty-fourth resistor R24) and gain setting resistors (twenty-second resistor R22 and twenty-fifth resistor R25) control the amplification factor; the multi-stage resistor network realizes gain control and impedance matching through different voltage division ratios and feedback configurations; the terminal is used to input high-voltage signals; the voltage output port outputs the processed sampling signal. This circuit adopts a dual-channel design, which not only improves the sampling accuracy but also effectively suppresses the common-mode interference.

[0098] Please refer to Figure 6 , in another specific embodiment, the current sampling module includes: current transformer LEM1, thirty-second resistor R32, third input terminal J3, fourth input terminal J4, first inductor L1, second inductor L2, sixth capacitor C6, seventh capacitor C7, eighth capacitor C8, ninth capacitor C9, tenth capacitor C10, and eleventh capacitor C11.

[0099] The current signal is input through the third input terminal J3 and the fourth input terminal J4. The third input terminal J3 is connected to the fourth, fifth, and sixth pins of the current transformer LEM1; the fourth input terminal J4 is connected to the seventh, eighth, and ninth pins of the current transformer LEM1; the third pin of the current transformer LEM1 outputs the current signal after being grounded through the thirty-second resistor R32.

[0100] The positive working voltage is input to the second pin of the current transformer LEM1 through the first inductor L1, and the second pin is also grounded through the parallel connection of the sixth capacitor C6, seventh capacitor C7, and eighth capacitor C8; the negative working voltage is input to the first pin of the current transformer LEM1 through the second inductor L2, and the first pin is also grounded through the parallel connection of the ninth capacitor C9, tenth capacitor C10, and eleventh capacitor C11.

[0101] In a specific embodiment, the positive working voltage is +15V and the negative working voltage is -15V. It can be understood that those skilled in the art can select working voltages of different magnitudes according to the actual situation.

[0102] In this embodiment, the current sampling module realizes differential acquisition of the current signal through the fourth, fifth, and sixth pins and the seventh, eighth, and ninth pins of the current transformer LEM1, and the standard voltage signal is output after being conditioned by the thirty-second resistor R32 through the third pin; at the same time, the module adopts a dual-power supply design, and the positive and negative working voltages are respectively input to the first pin and the second pin of the current transformer LEM1 through the first inductor L1 and the second inductor L2, and cooperate with the sixth to eleventh capacitors C11 to form an LC filter network for power supply filtering and decoupling. This circuit design not only realizes high-precision isolation sampling of the current signal, but also ensures the stable operation of the sampling circuit through perfect power supply processing, and has the characteristics of strong anti-interference ability and high sampling accuracy.

[0103] Please refer to Figure 7 , in another specific embodiment, the full-bridge output module includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a twelfth capacitor C12, and a DC power source DC.

[0104] Specifically, the twelfth capacitor C12 is connected in parallel across the DC power source DC. The positive pole of the DC power source DC is sequentially connected to the source electrode of the third MOS transistor Q3 and the source electrode of the second MOS transistor Q2. The negative pole of the DC power source DC is sequentially connected to the drain electrode of the fourth MOS transistor Q4 and the drain electrode of the third MOS transistor Q3. The drain electrode of the third MOS transistor Q3 is connected to the source electrode of the fourth MOS transistor Q4, and the connection point is connected to the discharge cavity. The drain electrode of the second MOS transistor Q2 is connected to the source electrode of the first MOS transistor Q1, and the connection point is connected to the discharge cavity. The gate electrodes of the third MOS transistor Q3 and the first MOS transistor Q1 are connected to one path of driving signal, and the gate electrodes of the fourth MOS transistor Q4 and the second MOS transistor Q2 are connected to another path of driving signal.

[0105] In this embodiment, the full-bridge output module is composed of four MOS transistors to form an H-bridge structure and operates under the stable voltage provided by the DC power source DC and the twelfth capacitor C12. The first MOS transistor Q1, the third MOS transistor Q3, the second MOS transistor Q2, and the fourth MOS transistor Q4 are controlled by two complementary drive signals respectively. When the second MOS transistor Q2 and the fourth MOS transistor Q4 are turned on, the first MOS transistor Q1 and the third MOS transistor Q3 are turned off, and the current flows from the second MOS transistor Q2 to the fourth MOS transistor Q4; when the first MOS transistor Q1 and the third MOS transistor Q3 are turned on, the third MOS transistor Q2 and the fourth MOS transistor Q4 are turned off, and the current flows from the third MOS transistor Q3 to the first MOS transistor Q1, thereby forming a bipolar voltage output with a controllable direction at both ends of the discharge cavity.

[0106] In this embodiment, the logic control module is used to control the enabling and disabling of the full-bridge output, is also used to set the frequency on the ARC detection module, and receives the feedback signal of the ARC arc and executes the ARC processing scheme to form a closed-loop system.

[0107] In a specific embodiment, the logic module includes: an MCU and a driver.

[0108] Please refer to Figure 8 , specifically, the MCU sends two drive signals to the driver, and after the driver performs differential processing on the two drive signals, the two drive signals are respectively transmitted into the gates of the third MOS transistor Q3 and the first MOS transistor Q1 of the full-bridge output module and the gates of the fourth MOS transistor Q4 and the second MOS transistor Q2.

[0109] In this embodiment, when the MCU receives a trigger signal, that is, when the MCU detects the existence of an ARC arc, there are two processing logics, and the two processing logics are as follows:

[0110] For charge neutralization processing: The MCU will record the current direction when the ARC occurs in the Nth cycle and send a reverse current control signal for performing charge neutralization in the (N + 1)th cycle. Specifically, if the current flows from the third MOS transistor Q3 to the first MOS transistor Q1 in the Nth cycle, then in the (N + 1)th cycle, the fourth MOS transistor Q4 and the second MOS transistor Q2 are controlled to be turned on, and the third MOS transistor Q3 and the first MOS transistor Q1 are turned off, so that the current flows from the second MOS transistor Q2 to the fourth MOS transistor Q4; conversely, if the current flows from the second MOS transistor Q2 to the fourth MOS transistor Q4 in the Nth cycle, then in the (N + 1)th cycle, the third MOS transistor Q3 and the first MOS transistor Q1 are controlled to be turned on, and the fourth MOS transistor Q4 and the second MOS transistor Q2 are turned off, so that the current flows from the first MOS transistor Q1 to the fourth MOS transistor Q4, realizing the charge neutralization of charged ions.

[0111] For the energy compensation process: When the MCU monitors that the number of ARCs occurring within the same conduction cycle exceeds the preset value, calculate the turn-off time of the ARC; generate a pulse width modulation signal for performing energy compensation according to the turn-off time, and this signal is used to extend the conduction time of the currently conducting MOS transistor pair. That is, if the third MOS transistor Q3 and the first MOS transistor Q1 are conducting, extend their conduction time; if the fourth MOS transistor Q4 and the second MOS transistor Q2 are conducting, extend their conduction time, to achieve energy compensation for charged ions.

[0112] It can be understood that the models, parameters, and values of the electronic components in the above circuit can be adjusted and selected accordingly according to the actual application scenario and process requirements, as long as the same technical functions and effects can be achieved.

[0113] Embodiment 2

[0114] Please refer to Figure 10 , this embodiment discloses a method for processing the power supply end of an ARC arc, using the power supply end processing circuit of the ARC arc disclosed in Embodiment 1. The specific method includes:

[0115] S1. Collect the voltage signal and current signal in the discharge cavity, and convert the voltage signal and current signal into recognizable voltage signals respectively;

[0116] S2. Convert the recognizable voltage signal into a frequency signal

[0117] S3. Perform amplification processing on the frequency signal;

[0118] S4. Compare the amplified frequency signal with a preset threshold, and judge whether there is an ARC arc according to the comparison result. If there is an ARC arc, generate a trigger signal;

[0119] S5. When receiving the trigger signal, generate corresponding control signals according to different trigger conditions; among them, the control signals include a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation;

[0120] S6. Perform charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signal.

[0121] Specifically, in steps S5 and S6, record the current direction when the ARC occurs in the Nth cycle, and send a reverse current control signal for performing charge neutralization in the (N + 1)th cycle. The reverse current control signal is used to control the current direction output by the full-bridge output module in the (N + 1)th cycle to be opposite to the current direction when the ARC occurs in the Nth cycle.

[0122] More specifically, in steps S5 and S6, when the number of ARCs occurring within the same conduction cycle exceeds a preset value, calculate the turn-off time of the ARC; generate a pulse width modulation signal for performing energy compensation according to the turn-off time, and the pulse width modulation signal is used to control the MOS transistors in the full-bridge output module to extend the conduction time.

[0123] Briefly speaking, charge neutralization is performed every time an ARC is detected, and energy compensation is performed when the number of ARCs within the same conduction cycle is too large.

[0124] In a specific embodiment, please refer to Figure 10 , taking UI_ARC as an example, the red is the voltage output curve and the green is the current curve. The MCU sets a fixed frequency for the ARC detection module, and the ARC detection module converts the frequency into the voltage of the comparator U94A to set the voltage and current thresholds. When the voltage and current both meet the trigger conditions, the output is turned off and waits for the next cycle to start. In the above figure, when I reaches the trigger condition at the upper red arrow, the sampling circuit will record the current direction at this time as positive by the MCU. After removing the ARC arc through segmented time, when outputting in the next cycle, the full-bridge output direction will be controlled to make the output current direction opposite to that during the ARC. The opposite current direction will neutralize the charged ions, thereby reducing the impact on the battery cells.

[0125] In another specific embodiment, please refer to Figure 11 , the previous pulse time is 1000 μs. When an ARC occurs in the next cycle and occurs 3 times as shown in the figure, each execution time is 100 μs. Then, power compensation is performed in this Ton section after the last ARC restart, and 300 μs is added later to compensate for the energy during the ARC. If it is concentrated on other Ton sections, it is also not feasible if there are process step jumps, which will cause deviations in the thickness of different film layers of the battery cells.

[0126] In summary, the example of the present invention realizes rapid ARC detection by using a simple hardware circuit, avoiding the delay caused by software calculation. In the power output part, full-bridge control is adopted to achieve bipolar pulse output; in terms of signal acquisition, the accuracy of voltage and current sampling is improved through a differential circuit. At the same time, the present invention also innovatively proposes a solution to eliminate the influence of ARC: on the one hand, a large number of charged ions accumulated during the generation of ARC are neutralized in time through charge neutralization technology, effectively avoiding the problem of the battery chip being stuck and burned; on the other hand, through energy compensation technology, the energy loss caused by ARC during the process is accurately compensated, solving the problem of the film layer of the battery chip being too thin and turning red due to the instability of the cavity. The organic combination of the above rapid detection circuit, charge neutralization technology and energy compensation technology significantly reduces the impact of ARC arcs caused by cavity instability and incomplete loading of battery chips on the output and quality of battery chips, and has important practical value. The present invention has been applied to the production of photovoltaic battery chips, and the film thickness deviation rate, alarm rate, and stuck and burned rate have decreased significantly. The film thickness deviation rate is basically 0, the alarm rate has dropped from 5% to 1%, and the stuck and burned rate has dropped from 1% to one ten-thousandth. It can reduce the scrap rate of silicon wafers, improve the yield and output of production, and has high commercial value.

[0127] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. An ARC power supply end processing circuit, characterized in that: include: A sampling module, used for collecting voltage signals and current signals in the discharge cavity, and converting the voltage signals and current signals into identifiable voltage signals respectively; A frequency-voltage conversion module, used to convert the identifiable voltage signal into a frequency signal; An operational amplifier module, used for performing signal amplification processing on the frequency signal; A comparator module is used to compare the amplified frequency signal with a preset threshold value, determine whether an ARC arc exists according to the comparison result, and generate a trigger signal if an ARC arc exists; When the logic module receives the trigger signal, it generates a corresponding control signal according to different trigger conditions; wherein the control signal includes a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation; The full-bridge output module performs charge neutralization or energy compensation processing on the charged ions gathered in the discharge cavity according to the control signal.

2. The ARC power supply end processing circuit as claimed in claim 1, characterized in that: The frequency-voltage conversion module includes: a frequency-voltage conversion chip U106, a first operational amplifier chip U110A, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5; The first pin of the frequency-voltage conversion chip U106 is connected to the inverting input terminal of the first operational amplifier chip U110A through the first resistor R1, and the first pin is also connected to the output terminal of the first operational amplifier chip U110A through the second resistor R2; The fifth capacitor C5 is connected between the inverting input terminal and the output terminal of the first operational amplifier chip U110A; The second pin of the frequency-voltage conversion chip U106 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the other end of the fourth resistor R4 is also connected to the first pin of the frequency-voltage conversion chip U106 through the first capacitor C1; The third pin and the fourth pin of the frequency-voltage conversion chip U106 are grounded; The fifth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the fifth resistor R5 and one end of the second capacitor C2; the other end of the second capacitor C2 is grounded; the other end of the fifth resistor R5 is connected to the eighth pin of the frequency-voltage conversion chip U106; The sixth pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the sixth resistor R6 and one end of the third capacitor C3, the other end of the third capacitor C3 is connected to the logic module through the frequency input port, and the other end of the sixth resistor R6 is connected to the eighth pin; The seventh pin of the frequency-voltage conversion chip U106 is respectively connected to one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the seventh resistor R7 is connected to the eighth pin; the other end of the eighth resistor R8 is grounded; The eighth pin of the frequency-voltage conversion chip U106 is also connected to one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is grounded.

3. The ARC power supply end processing circuit as claimed in claim 2, characterized in that: The operational amplifier module includes a second operational amplifier chip U110B, a ninth resistor R9 and a tenth resistor R10; The inverting input terminal of the second operational amplifier chip U110B is connected to the output terminal of the first operational amplifier chip U110A through the ninth resistor R9; the non-inverting input terminal of the second operational amplifier chip U110B is grounded, and the output terminal is connected to the input terminal of the comparator module; the tenth resistor R10 is connected between the output terminal and the inverting input terminal of the second operational amplifier chip U110B.

4. The ARC power supply end processing circuit as claimed in claim 2, characterized in that: The comparator module includes a comparator U94A, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a fifteenth resistor R15; The inverting input terminal of the comparator U94A is connected to the output terminal of the second operational amplifier chip U110B through the eleventh resistor R11, and the inverting input terminal of the comparator U94A is also connected to the sampling signal through the twelfth resistor R12; the non-inverting input terminal of the comparator U94A is grounded through the thirteenth resistor R13, and is also connected to the output terminal of the comparator U94A through the fourteenth resistor R14; the output terminal of the comparator U94A is connected to the power supply voltage through the fifteenth resistor R15.

5. The ARC power supply end processing circuit as claimed in claim 2, characterized in that: The sampling module includes a voltage sampling module; The voltage sampling module includes a third operational amplifier chip U1B, a fourth operational amplifier chip U1A, a first wiring terminal J1, a second wiring terminal J2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, and a thirty-first resistor R31; The voltage signal is input through the first wiring terminal J1 and the second wiring terminal J2, the first wiring terminal J1 is connected to one end of the eighteenth resistor R18, the other end of the eighteenth resistor R18 is connected to the fifth pin of the third operational amplifier chip U1B through the nineteenth resistor R19, the other end of the nineteenth resistor R19 is also grounded through the sixteenth resistor R16; the other end of the eighteenth resistor R18 is also grounded through the seventeenth resistor R17; the other end of the eighteenth resistor R18 is also connected to the second pin of the fourth operational amplifier chip U1A through the twenty-sixth resistor R26; The second wiring terminal J2 is connected to one end of the 28th resistor R28, the other end of the 28th resistor R28 is connected to the ground through the 31st resistor R31, the other end of the 28th resistor R28 is also connected to the sixth pin of the third operational amplifier chip U1B through the 21st resistor R21, the other end of the 28th resistor R28 is also connected to the third pin of the fourth operational amplifier chip U1A through the 29th resistor R29; the other end of the 29th resistor R29 is also grounded through the 30th resistor R30; The sixth pin of the third operational amplifier chip U1B is also connected to the seventh pin of the first operational amplifier chip U110A through the twenty-second resistor R22; The second pin of the fourth operational amplifier chip U1A is also connected to the first pin of the second operational amplifier chip U110B through the twenty-fifth resistor R25; The seventh pin of the third operational amplifier chip U1B is connected to ground through the 20th resistor R20 and the 23rd resistor R23 in sequence; the 20th resistor R20 is also connected to the first voltage output port; The first pin of the fourth operational amplifier chip U1A is grounded through the twenty-seventh resistor R27 and the twenty-fourth resistor R24 ​​in sequence; the twenty-seventh resistor R27 is also connected to the second voltage output port.

6. The ARC power supply end processing circuit as claimed in claim 2, characterized in that: The sampling module includes a current sampling module: The current sampling module includes: a current transformer LEM1, a third input terminal J3, a fourth input terminal J4, a thirty-second resistor R32, a first inductor L1, a second inductor L2, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10 and an eleventh capacitor C11; The current signal is input through the third input terminal J3 and the fourth input terminal J4, the third input terminal J3 is connected to the fourth pin, the fifth pin and the sixth pin of the current transformer LEM1; the fourth input terminal J4 is connected to the seventh pin, the eighth pin and the ninth pin of the current transformer LEM1; the third pin of the current transformer LEM1 is grounded through the thirty-second resistor R32 and then outputs the current signal; The positive working voltage is input to the second pin of the current transformer LEM1 through the first inductor L1, and the second pin is also connected in parallel to ground through the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8; the negative working voltage is input to the first pin of the current transformer LEM1 through the second inductor L2, and the first pin is also connected in parallel to ground through the ninth capacitor C9, the tenth capacitor C10 and the eleventh capacitor C11.

7. The ARC power supply end processing circuit as claimed in claim 1, characterized in that: The full-bridge output module includes: a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3, a fourth MOS tube Q4, a twelfth capacitor C12 and a DC source DC; The twelfth capacitor C12 is connected in parallel to both ends of the direct current source DC, the positive electrode of the direct current source DC is connected to the source of the third MOS tube Q3 and the source of the second MOS tube Q2 in sequence, and the negative electrode of the direct current source DC is connected to the drain of the fourth MOS tube Q4 and the drain of the first MOS tube Q1 in sequence; the drain of the third MOS tube Q3 is connected to the source of the fourth MOS tube Q4, and the connection point is connected to the discharge cavity; the drain of the second MOS tube Q2 is connected to the source of the first MOS tube Q1, and the connection point is connected to the discharge cavity; the gates of the third MOS tube Q3 and the fourth MOS tube Q1 are connected to one driving signal, and the gates of the fourth MOS tube Q4 and the second MOS tube Q2 are connected to another driving signal.

8. The ARC power supply end processing circuit as claimed in claim 7, characterized in that: The logic module includes: an MCU and a driver; The MCU sends two drive signals to the driver. After the driver performs differential processing on the two drive signals, the two drive signals are respectively transmitted to the gates of the third MOS tube Q3 and the first MOS tube Q1 of the full-bridge output module and the gates of the fourth MOS tube Q4 and the second MOS tube Q2.

9. A method for processing the power supply end of an ARC arc, characterized in that: The method comprises the following steps: Collecting voltage signals and current signals in the discharge cavity, and converting the voltage signals and current signals into identifiable voltage signals respectively; Converting the identifiable voltage signal into a corresponding frequency signal; amplifying the frequency signal; The amplified frequency signal is compared with a preset threshold value, and whether an ARC arc exists is determined according to the comparison result. If an ARC arc exists, a trigger signal is generated; When the trigger signal is received, a corresponding control signal is generated according to different trigger conditions; wherein the control signal includes a reverse current control signal for performing charge neutralization and a pulse width modulation signal for performing energy compensation; The charged ions gathered in the discharge cavity are subjected to charge neutralization or energy compensation processing according to the control signal.

10. The ARC power end processing method according to claim 9, characterized in that: Generating corresponding control signals according to different trigger conditions, and performing charge neutralization or energy compensation processing on the charged ions accumulated in the discharge cavity according to the control signals includes: Record the current direction when ARC occurs in the Nth cycle, and send a reverse current control signal for performing charge neutralization in the N+1th cycle, wherein the reverse current control signal is used to control the current direction output by the full-bridge output module in the N+1th cycle to be opposite to the current direction when ARC occurs in the Nth cycle; Or, when the number of ARC occurrences in the same conduction cycle exceeds a preset value, the turn-off time of the ARC is calculated; a pulse width modulation signal for performing energy compensation is generated based on the turn-off time, and the pulse width modulation signal is used to control the MOS tube in the full-bridge output module to extend the conduction time.

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