Three-level switching converter and control

Abstract

The invention relates to a three-level switching converter and control. A circuit (200) includes first, second, third, and fourth transistors (206, 208, 210, 212) coupled in series, and a control circuit (204) coupled to the first, second, third, and fourth transistors. The control circuit (204) includes a clock generator (218), a current sense circuit (220), and a zero current zoning (ZCDF) circuit (232). The clock generator (218) is configured to generate first and second clocks. The second clock is orthogonal to the first clock. The current sense circuit (220) is configured to sense a current flowing through the first transistor. The ZCDF circuit (232) is configured to define a ZCDF interval that starts at an edge of the second clock and ends when the fourth transistor is turned on. The control circuit (204) is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and in DCM, in response to the current flowing through the first transistor (206) being negative, turn off the first transistor (206) during the ZCDF interval.

Description

Technical Field

[0001] This application relates to DC-DC converters, and more particularly, to three-level switching converters and control. Background Art

[0002] A DC-DC converter is an electronic circuit that converts an input direct current (DC) voltage into one or more DC output voltages that are higher or lower in magnitude than the input DC voltage. A DC-DC converter that generates an output voltage lower than the input voltage is called a buck or step-down converter. A DC-DC converter that generates an output voltage higher than the input voltage is called a boost or step-up converter.

[0003] Some DC-DC converter topologies include drive / power switches coupled to an energy storage inductor / transformer at a switching node. By alternately opening and closing the switches in accordance with a switching signal, electrical energy is transferred through the energy storage inductor / transformer to a load. The amount of electrical energy transferred to the load depends on the on / off duty cycle of the switches and the frequency of the switching signal. DC-DC converters are widely used in electronic devices, particularly battery-powered devices such as portable cellular telephones, laptop computers, and other electronic systems where efficient use of electrical power is required. Summary of the Invention

[0004] In one example, a circuit includes first, second, third, and fourth transistors, and a control circuit. The first, second, third, and fourth transistors are coupled in series. The control circuit is coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a current sensing circuit, and a zero current discrimination zone (ZC_DF) circuit. The clock generator is configured to generate a first and a second clock. The second clock is orthogonal to the first clock. The current sensing circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval that begins at an edge of the second clock and ends when the fourth transistor is turned on. The control circuit is configured to operate the first, second, third, and fourth transistors in discontinuous conduction mode (DCM), and in DCM, turn off the first transistor during the ZC_DF interval in response to the current flowing through the first transistor being negative.

[0005] In another example, a circuit includes first, second, third, and fourth transistors, and a control circuit. The first, second, third, and fourth transistors are coupled in series. The control circuit is coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a first current sensing circuit, and a second current sensing circuit. The clock generator is configured to generate a first and a second clock. The second clock is orthogonal to the first clock. The first current sensing circuit is configured to sense a current flowing through the first transistor. The second current sensing circuit is configured to sense a current flowing through the fourth transistor. The control circuit is configured to operate the first, second, third, and fourth transistors in a pulse frequency modulation (PFM) mode, and define a pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the second clock. In the pre-PFM region, the control circuit is configured to inhibit turning on of the fourth transistor, and exit the pre-PFM region in response to the current flowing through the fourth transistor not being zero at the edge of the second clock.

[0006] In another example, a backlight system includes a light emitting diode (LED) and a three-level switched converter. The three-level switched converter is coupled to the LED. The three-level switched converter includes first, second, third, and fourth transistors and a control circuit. The first, second, third, and fourth transistors are coupled in series. The control circuit is coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a first current sensing circuit, a second current sensing circuit, and a zero current distinguish region (ZC_DF) circuit. The clock generator is configured to generate a first and a second clock. The second clock is orthogonal to the first clock. The first current sensing circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval that starts at an edge of the second clock and ends when the fourth transistor turns on. The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM). In DCM, the controller is configured to turn off the first transistor in response to the current flowing through the first transistor being negative during the ZC_DF interval, and turn off the second transistor in response to the current flowing through the fourth transistor being negative during the ZC_DF interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an example backlight system including a three-level boost converter.

[0008] Figure 2 is a block diagram of an example three-level boost converter including an optical load control circuitry.

[0009] Figure 3 Is an illustration Figure 2 of the example operation of a three-level boost converter in continuous conduction mode (CCM) with a low input voltage.

[0010] Figure 4 Is an illustration Figure 2 of the example operation of a three-level boost converter in CCM with a high input voltage.

[0011] Figure 5 Is an illustration Figure 2 of the example operation of a three-level boost converter in discontinuous conduction mode (DCM) with a low input voltage.

[0012] Figure 6 Is an illustration Figure 2 of the example operation of a three-level boost converter in DCM with a high input voltage.

[0013] Figure 7 Is an illustration Figure 2 of the example operation of a three-level boost converter transitioning to pulse frequency modulation (PFM) mode with a high input voltage.

[0014] Figure 8 Is an illustration Figure 2 of the example operation of a three-level boost converter transitioning to PFM mode with a low input voltage.

[0015] Figure 9 Is an illustration Figure 2 of the example operation of a three-level boost converter simultaneously transitioning to PFM mode with a low input voltage in the pre-PFM region. DETAILED DESCRIPTION

[0016] Figure 1 Is a block diagram of an example backlight system 100. The backlight system 100 can be applied in a liquid crystal display (LCD) system to provide light emitted from the display. The backlight system 100 can also be applied in other lighting applications. The backlight system 100 includes a three-level switching converter 102 and light emitting diodes (LEDs) 104. The LEDs 104 can include any number of LEDs arranged in series and / or parallel to emit light behind the LCD panel. For example, strings of series-coupled LEDs can be coupled in parallel to form a two-dimensional array of LEDs.

[0017] The three-level switched converter 102 can provide several advantages over a two-level converter. The three-level converter generates the output voltage in two voltage steps (three levels - input voltage, intermediate voltage, and output voltage) instead of the single voltage step (two levels - input voltage and output voltage) used in a two-level converter. Generating the output voltage in two steps reduces the voltage across the switching device, which enables the use of smaller, lower-voltage devices and increases efficiency. Compared to a two-level boost converter, the three-level switched converter 102 may be more complex (controlling more switching devices), but can provide higher efficiency, a higher boost ratio, lower electromagnetic interference, and / or a smaller overall size.

[0018] The LED 104 is coupled to the three-level switched converter 102. The three-level switched converter 102 provides power (VOUT) to forward bias the LED 104. The three-level switched converter 102 can be a three-level boost converter that provides a wide boost ratio for a wide range of input voltages (VIN). For example, the three-level switched converter 102 can operate at a VIN in the range of 3 volts to 24 volts for use with various power sources (batteries, universal serial bus, etc.).

[0019] To provide efficient operation over a wide range of loads, the three-level switched converter 102 can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse frequency modulation (PFM) mode. Switching control in DCM and PFM presents many challenges in a three-level boost converter. For example, in DCM, improper synchronous rectifier control may increase rectifier losses. The PFM operating region varies over a wide VIN range, and improper control can increase switching losses. The three-level switched converter 102 controls DCM operation to reduce rectifier losses and controls PFM operation to reduce switching losses.

[0020] Figure 2is a block diagram of an example three-level boost converter 200 that includes an optical load control circuit system. The three-level boost converter 200 is an example of the three-level switching converter 102. The three-level boost converter 200 includes a power stage 202 and a controller 204 (also referred to as a control circuit). The power stage 202 includes transistors 206, 208, 210, and 212 coupled in series, and a capacitor 216. The transistors 206, 208, 210, and 212 can be n-type field effect transistors (NFETs). A first current terminal (e.g., drain) of the transistor 206 is coupled to the output terminal for providing VOUT to an external circuit system (e.g., LED 104). A second current terminal (e.g., drain) of the transistor 206 is coupled to a first current terminal (e.g., drain) of the transistor 208. A second current terminal (e.g., source) of the transistor 208 is coupled to a first current terminal (e.g., drain) of the transistor 210. A second current terminal (e.g., source) of the transistor 210 is coupled to a first current terminal (e.g., drain) of the transistor 212. A second current terminal (e.g., source) of the transistor 212 is coupled to a reference voltage terminal (e.g., ground).

[0021] The capacitor 216 is coupled across the transistors 208 and 210. A first terminal (e.g., top plate) of the capacitor 216 is coupled to the first current terminal of the transistor 208, and a second terminal (e.g., bottom plate) of the capacitor 216 is coupled to the second current terminal of the transistor 210.

[0022] An inductor 214 is coupled between the input voltage terminal and the second current terminal of the transistor 208. The inductor 214 can be provided external to the power stage 202, and the power stage 202 and the controller 204 can be provided as an integrated circuit. The transistors 206, 208, 210, and 212 are turned on or off to charge or discharge the inductor 214 and the capacitor 216, and to generate VOUT.

[0023] The transistors 206, 208, 210, and 212 have control terminals (e.g., gates) coupled to the controller 204. As four different states, the controller 204 controls the turning on and off of the transistors 206, 208, 210, and 212 to generate VOUT from VIN. In state 1, the controller 204 turns on the transistors 210 and 212 and turns off the transistors 206 and 208 to charge the inductor 214. In state 2, the controller 204 turns on the transistors 208 and 212 and turns off the transistors 206 and 210 to charge the capacitor 216. In state 3, the controller 204 turns on the transistors 206 and 210 and turns off the transistors 208 and 212 to discharge the capacitor 216. In state 4, the controller 204 turns on the transistors 206 and 208 and turns off the transistors 210 and 212 to discharge the inductor 214. These states will be further described in Figure 3 , 4 , 5, and 6.

[0024] The controller 204 includes a clock generation circuit 218, current sensing circuits 220 and 222, valley current detection circuits 224 and 230, zero current detection circuits 226 and 228, a valley / zero current discrimination circuit 232, a DCM control circuit 234, a PFM control circuit 236, a high-side turn-on circuit 238, a high-side turn-off circuit 240, a low-side turn-on circuit 242, a low-side turn-off circuit 244, and a gate control circuit 246. The gate control circuit 246 has outputs coupled to the control terminals of the transistors 206, 208, 210, and 212 and generates signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM to control the turning on and off of the transistors 206, 208, 210, and 212. The gate control circuit 246 may include level shifting, driving, and signal generation circuitry to generate the signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM based on on / off control signals received from the high-side turn-on circuit 238, the high-side turn-off circuit 240, the low-side turn-on circuit 242, and the low-side turn-off circuit 244.

[0025] The high-side turn-on circuit 238 is coupled to the gate control circuit 246. The high-side turn-on circuit 238 provides control signals HS1_ON and HS2_ON to the gate control circuit 246 to turn on the transistors 206 and 208, respectively. The high-side turn-on circuit 238 generates HS1_ON and HS2_ON based on the clock signals CLK_1 and CLK_2 received from the clock generation circuit 218 and the signals LS1_ON and LS2_ON received from the low-side turn-on circuit 242. The logic implemented by the circuitry of the high-side turn-on circuit 238 will be explained using Figure 3-9 .

[0026] The high-side turn-off circuit 240 is coupled to the gate control circuit 246. The high-side turn-off circuit 240 provides control signals HS1_OFF and HS2_OFF to the gate control circuit 246 to turn off the transistor 206 and the transistor 208 respectively. The high-side turn-off circuit 240 generates HS1_OFF and HS2_OFF based on the signal VZC_DF received from the valley / zero current discrimination circuit 232, the signal HS1_VALLEY received from the valley current detection circuit 224, the signal LS1_VALLEY received from the valley current detection circuit 230, and the signals HS1_DCM_OFF and HS2_DCM_OFF received from the DCM control circuit 234. Will use Figure 3-9 Explain the logic implemented by the circuitry of the high-side turn-on circuit 238.

[0027] The low-side turn-on circuit 242 is coupled to the gate control circuit 246. The low-side turn-on circuit 242 provides control signals LS1_ON and LS2_ON to the gate control circuit 246 to turn on the transistor 210 and the transistor 212 respectively. The low-side turn-on circuit 242 generates LS1_ON and LS2_ON based on the signal VZC_DF received from the valley / zero current discrimination circuit 232, the signal HS1_VALLEY received from the valley current detection circuit 224, the signal LS1_VALLEY received from the valley current detection circuit 230, and the signals LS1_ON_SKIP and LS2_ON_SKIP received from the PFM control circuit 236. Will use Figure 3-9 Explain the logic implemented by the circuitry of the low-side turn-on circuit 242.

[0028] The low-side turn-off circuit 244 is coupled to the gate control circuit 246. The low-side turn-off circuit 244 provides control signals LS1_OFF and LS2_OFF to the gate control circuit 246 to turn off the transistor 210 and the transistor 212 respectively. The low-side turn-off circuit 244 generates LS1_OFF and LS2_OFF based on the clock signals CLK_1 and CLK_2 received from the clock generation circuit 218 and the signals LS1_ON_SKIP and LS2_ON_SKIP received from the PFM control circuit 236. Will use Figure 3-9 Explain the logic implemented by the circuitry of the low-side turn-off circuit 244.

[0029] The DCM control circuit 234 is coupled to the high-side turn-off circuit 240. The DCM control circuit 234 generates the signals HS1_DCM_OFF and HS2_DCM_OFF based on the signals HS1_ZERO, LS1_ZERO, and VZC_DF received from the valley / zero current discrimination circuit 232. Will use Figure 5-6 Explain the logic implemented by the circuitry of the DCM control circuit 234.

[0030] The PFM control circuit 236 is coupled to the low-side turn-on circuit 242 and the low-side turn-off circuit 244. The PFM control circuit 236 generates signals LS1_ON_SKIP and LS2_ON_SKIP based on the clock signals CLK_1 and CLK_2 received from the clock generation circuit 218 and the signal LS1_ZERO received from the zero-current detection circuit 228. The logic implemented by the circuitry of the PFM control circuit 236 will be explained using Figure 9 to explain the logic implemented by the circuitry of the PFM control circuit 236.

[0031] The valley / zero-current discrimination circuit 232 is coupled to the DCM control circuit 234. The valley / zero-current discrimination circuit 232 generates a signal VZC_DF based on the clock signal CLK_2 received from the clock generation circuit 218 and the signal LS1_ON received from the low-side turn-on circuit 242. The logic implemented by the circuitry of the valley / zero-current discrimination circuit 232 will be explained using Figure 5 and 6 to explain the logic implemented by the circuitry of the valley / zero-current discrimination circuit 232.

[0032] The current sensing circuit 220 is coupled across the transistor 206. A first terminal of the current sensing circuit 220 is coupled to a first current terminal of the transistor 206, and a second terminal of the current sensing circuit 220 is coupled to a second current terminal of the transistor 206. The current sensing circuit 220 senses the current flowing through the transistor 206, e.g., senses the current based on the voltage across the transistor 206. The current sensing circuit 220 generates a signal HS1_CS that represents the current flowing through the transistor 206.

[0033] The valley current detection circuit 224 is coupled to the current sensing circuit 220. The valley current detection circuit 224 detects the valley in the current flowing through the transistor 206 based on HS1_CS. The signal HS1_VALLEY represents the detection of the valley in the current flowing through the transistor 206. The valley current detection circuit 224 may include a comparator that compares HS1_CS with a valley current threshold to detect the valley current.

[0034] The zero-current detection circuit 226 is coupled to the current sensing circuit 220. The zero-current detection circuit 226 detects the zero current flowing through the transistor 206 based on HS1_CS. The signal HS1_ZERO represents the detection of the zero current flowing through the transistor 206. The valley current detection circuit 224 may include a comparator that compares HS1_CS with a zero-current threshold to detect the zero current.

[0035] The current sensing circuit 222 is coupled across the transistor 212. A first terminal of the current sensing circuit 222 is coupled to a first current terminal of the transistor 212, and a second terminal of the current sensing circuit 222 is coupled to a second current terminal of the transistor 212. The current sensing circuit 222 senses the current flowing through the transistor 212, for example, based on the voltage across the transistor 212. The current sensing circuit 222 generates a signal LS1_CS, which signal represents the current flowing through the transistor 212.

[0036] The valley current detection circuit 230 is coupled to the current sensing circuit 222. The valley current detection circuit 230 detects a valley in the current flowing through the transistor 212 based on LS1_CS. The signal LS1_VALLEY represents the detection of the valley in the current flowing through the transistor 212. The valley current detection circuit 230 may include a comparator that compares LS1_CS with a valley current threshold to detect the valley current.

[0037] The zero current detection circuit 228 is coupled to the current sensing circuit 220. The zero current detection circuit 228 detects a zero current flowing through the transistor 212 based on LS1_CS. The signal LS1_ZERO represents the detection of the zero current flowing through the transistor 212. The zero current detection circuit 228 may include a comparator that compares LS1_CS with a zero current threshold to detect the zero current.

[0038] The clock generation circuit 218 generates clock signals CLK_1 and CLK_2 as sawtooth or ramp signals at a fixed frequency (e.g., a selected switching frequency of 200). CLK_1 and CLK_2 have the same frequency, and CLK_2 is phase-shifted 90° relative to CLK_1. CLK_1 and CLK_2 are orthogonal (phases offset 90° relative to each other).

[0039] Figure 3 is a timing diagram illustrating an example operation of the three-level boost converter 200 in CCM with a low input voltage. A low input voltage refers to an input voltage VIN that is less than half of VOUT. A high input voltage refers to an input voltage VIN that is greater than half of VOUT. Figure 3 Shows the clock signals CLK_1 and CLK_2, the current sensing signals HS1_CS and LS1_CS, and the transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM. The transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM control the on / off of the transistors 206, 208, 210, and 212, respectively.

[0040] At the falling edge of CLK_1 (start of state 2), the high-side turn-on circuit 238 sets HS1_ON to logic one, which sets HS1_PWM to logic one and turns on transistor 206. Similarly, at the falling edge of CLK_1, the low-side turn-off circuit 244 sets LS1_OFF to logic one, which sets LS1_PWM to logic zero and turns off transistor 212. With transistor 206 turned on, the valley current detection circuit 224 monitors the current flowing through transistor 206 to detect the valley. When the valley is detected (start of state 1 after state 2), the high-side turn-off circuit 240 sets HS1_OFF to logic one, which sets HS1_PWM to logic zero and turns off transistor 206. Similarly, when the valley is detected, the low-side turn-on circuit 242 sets LS1_ON to logic one, which sets LS1_PWM to logic one and turns on transistor 212.

[0041] At the falling edge of CLK_2 (start of state 3), the high-side turn-on circuit 238 sets HS2_ON to logic one, which sets HS2_PWM to logic one and turns on transistor 208. Similarly, at the falling edge of CLK_2, the low-side turn-off circuit 244 sets LS2_OFF to logic one, which sets LS2_PWM to logic zero and turns off transistor 210. With transistor 208 turned on, the valley current detection circuit 230 monitors the current flowing through transistor 212 to detect the valley. When the valley is detected (start of state 1 after state 3), the high-side turn-off circuit 240 sets HS2_OFF to logic one, which sets HS2_PWM to logic zero and turns off transistor 208. Similarly, when the valley is detected, the low-side turn-on circuit 242 sets LS2_ON to logic one, which sets LS2_PWM to logic one and turns on transistor 210.

[0042] Thus, in CCM with a low input voltage, the three-level boost converter 200 transitions between states of 1, 2, 1, 3 to generate VOUT.

[0043] Figure 4 is a timing diagram illustrating the example operation of the three-level boost converter 200 in CCM with a high input voltage. Figure 4 Shows the clock signals CLK_1 and CLK_2, the current sensing signals HS1_CS and LS1_CS, and the transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM. The transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM control the turn-on / turn-off of transistors 206, 208, 210, and 212, respectively.

[0044] At the falling edge of CLK_1 (start of state 4 after state 3), the high-side turn-on circuit 238 sets HS1_ON to logic one, which sets HS1_PWM to logic one and turns on transistor 206. Similarly, at the falling edge of CLK_1, the low-side turn-off circuit 244 sets LS1_OFF to logic one, which sets LS1_PWM to logic zero and turns off transistor 212. With transistor 206 turned on, the valley current detection circuit 224 monitors the current flowing through transistor 206 to detect the valley. When the valley is detected (start of state 2), the high-side turn-off circuit 240 sets HS2_OFF to logic one, which sets HS2_PWM to logic zero and turns off transistor 208. Similarly, when the valley is detected, the low-side turn-on circuit 242 sets LS2_ON to logic one, which sets LS2_PWM to logic one and turns on transistor 210.

[0045] At the falling edge of CLK_2 (start of state 4 after state 2), the high-side turn-on circuit 238 sets HS2_ON to logic one, which sets HS2_PWM to logic one and turns on transistor 208. Similarly, at the falling edge of CLK_2, the low-side turn-off circuit 244 sets LS2_OFF to logic one, which sets LS2_PWM to logic zero and turns off transistor 210. The valley current detection circuit 224 monitors the current flowing through transistor 206 to detect the valley. When the valley is detected (start of state 3), the high-side turn-off circuit 240 sets HS1_OFF to logic one, which sets HS1_PWM to logic zero and turns off transistor 206. Similarly, when the valley is detected, the low-side turn-on circuit 242 sets LS1_ON to logic one, which sets LS1_PWM to logic one and turns on transistor 212.

[0046] Therefore, in CCM with a high input voltage, the three-level boost converter 200 transitions between states 2, 4, 3, and 4 to generate VOUT.

[0047] Figure 5 is a timing diagram illustrating the example operation of the three-level boost converter 200 in DCM with a low input voltage. Figure 5 Shows the clock signals CLK_1 and CLK_2, the current sense signals HS1_CS and LS1_CS, and the transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM. The transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM control the turn-on / turn-off of transistors 206, 208, 210, and 212, respectively. Figure 5Also shown is a zero current discrimination zone (ZC_DF) defined by a signal VZC_DF generated by a valley / zero current discrimination circuit 232. ZC_DF defines a time interval in DCM during which transistors 206 and 208 turn off with a different timing than in CCM. ZC_DF is active (e.g., VZC_DF is logic one) starting from the falling edge of CLK_2 until LS1_ON is set to logic one (LS1_PWM is set to logic one and transistor 212 is turned on), as Figure 5 shown in

[0048] At the falling edge of CLK_1 (start of state 2), a high side turn-on circuit 238 sets HS1_ON to logic one, which sets HS1_PWM to logic one and turns on transistor 206. Similarly, at the falling edge of CLK_1, a low side turn-off circuit 244 sets LS1_OFF to logic one, which sets LS1_PWM to logic zero and turns off transistor 212. When the current flowing through transistor 206 is zero in the zero current discrimination zone (detected by a zero current detection circuit 226), a DCM control circuit 234 sets HS1_DCM_OFF to logic one. Based on HS1_DCM_OFF, a high side turn-off circuit 240 sets HS1_OFF to logic one, which sets HS1_PWM to logic zero and turns off transistor 206. In contrast, in CCM, transistor 206 may remain on until HS1_CS is equal to CLK_1. When HS1_CS is equal to CLK_1 (start of state 1 after state 2), a low side turn-on circuit 242 sets LS1_ON to logic one, which sets LS1_PWM to logic one and turns on transistor 212.

[0049] At the falling edge of CLK_2 (start of state 3), the high-side turn-on circuit 238 sets HS2_ON to logic one, which sets HS2_PWM to logic one and turns on transistor 208. Similarly, at the falling edge of CLK_2, the low-side turn-off circuit 244 sets LS2_OFF to logic one, which sets LS2_PWM to logic zero and turns off transistor 210. The falling edge of CLK_2 starts the zero-current discrimination period, and when the current flowing through transistor 212 is zero (detected by the zero-current detection circuit 228), the DCM control circuit 234 sets HS2_DCM_OFF to logic one. Based on HS2_DCM_OFF, the high-side turn-off circuit 240 sets HS2_OFF to logic one, which sets HS2_PWM to logic zero and turns off transistor 208. In contrast, in CCM, transistor 208 can remain on until LS1_CS equals CLK_2. When LS1_CS equals CLK_2 (start of state 1 after state 3), the low-side turn-on circuit 242 sets LS2_ON to logic one, which sets LS2_PWM to logic one and turns on transistor 210.

[0050] Thus, in DCM with a low input voltage, the three-level boost converter 200 transitions between states of 1, 2, 1, 3, and:

[0051] ZC_DF = 1, starting from the edge of CLK_2 until LS1_ON == 1; (1)

[0052] HS1_OFF = (HS1_CS < CLK_1) || (HS1_CS < 0) && ZC_DF == 1); and (2)

[0053] HS2_OFF = (LS1_CS < CLK_2) || (HS1_CS < CLK_2) || (3)

[0054] (LS1_CS < 0) && ZC_DF == 1) || (HS1_CS < 0) && ZC_DF == 0).

[0055] Figure 6 is a timing diagram illustrating the example operation of the three-level boost converter 200 in DCM with a high input voltage. Figure 6 Shows the clock signals CLK_1 and CLK_2, the current sensing signals HS1_CS and LS1_CS, and the transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM. The transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM control the turn-on / off of transistors 206, 208, 210, and 212, respectively.Figure 6 Also shown is a zero current discrimination zone (ZC_DF) defined by a signal VZC_DF generated by a valley / zero current discrimination circuit 232. ZC_DF is active (e.g., VZC_DF is logic one) starting from the falling edge of CLK_2 until LS1_ON is set to logic one (transistor 212 is turned on), as Figure 6 shown therein. Figure 6 The operations described therein are according to equations (1)-(3).

[0056] At the falling edge of CLK_1 (start of state 4 after state 3), the high side turn-on circuit 238 sets HS1_ON to logic one, which sets HS1_PWM to logic one and turns on transistor 206. Additionally, at the falling edge of CLK_1, the low side turn-off circuit 244 sets LS1_OFF to logic one, which sets LS1_PWM to logic zero and turns off transistor 212. After the falling edge of CLK_1, the three-level boost converter 200 does not operate in the zero current discrimination zone, and transistor 206 is not turned off when the current flowing through transistor 206 is zero. However, when the current flowing through transistor 206 is zero, HS2_DCM_OFF is set to logic one, which sets HS2_OFF to logic one and HS2_PWM to logic zero, thereby turning off transistor 208.

[0057] When HS1_CS is equal to CLK_2 (start of state 2 after state 4), the low side turn-on circuit 242 sets LS2_ON to logic one, which sets LS2_PWM to logic one and turns on transistor 210. At the falling edge of CLK_2 (start of state 4 after state 2), the high side turn-on circuit 238 sets HS2_ON to logic one, which sets HS2_PWM to logic one and turns on transistor 208. Additionally, at the falling edge of CLK_2, the low side turn-off circuit 244 sets LS2_OFF to logic one, which sets LS2_PWM to logic zero and turns off transistor 210. The zero current discrimination zone starts from the falling edge of CLK_2.

[0058] When HS1_CS is equal to zero (after the falling edge of CLK_2), in the zero current discrimination zone, the DCM control circuit 234 sets HS_1_DCM_OFF to logic one, which sets HS1_OFF to logic one and HS1_PWM to logic zero, thereby turning off transistor 206. When HS1_CS is equal to CLK_1 (start of state 3 after state 4), the low side turn-on circuit 242 sets LS1_ON to logic one, which sets LS1_PWM to logic one and turns on transistor 212.

[0059] Figure 7It is a timing diagram illustrating an example operation of the three-level boost converter 200 transitioning to the PFM mode with a high input voltage. Figure 7 The clock signals CLK_1 and CLK_2 are shown, and line 702 representing the sensed current as the output current of the three-level boost converter 200 decreases (e.g., because the current flowing through the load coupled to the three-level boost converter 200 decreases). Figure 7 It shows that when the current provided by the three-level boost converter 200 decreases, the three-level boost converter 200 directly transitions from operation in CCM or DCM to PFM. In CCM and DCM, the sensed current intersects with CLK_1 and CLK_2, and the three-level boost converter 200 switches the transistors 206, 208, 210, and transistor 212, as Figure 3-6 shown. In the PFM mode, the sensed current does not intersect with CLK_1 or CLK_2, and there is no switching of the transistors 206, 208, 210, and 212 based on such intersections.

[0060] Figure 8 It is a timing diagram illustrating an example operation of the three-level boost converter 200 transitioning to the PFM mode with a low input voltage. Figure 8 The clock signals CLK_1 and CLK_2 are shown, and line 802 representing the sensed current as the output current of the three-level boost converter 200 decreases (e.g., because the current flowing through the load coupled to the three-level boost converter 200 decreases). Figure 8 It shows that when the current provided by the three-level boost converter 200 decreases, the three-level boost converter 200 transitions from operation in CCM or DCM to PFM through a pre-PFM region. In CCM and DCM, the sensed current intersects with CLK_1 and CLK_2, and the three-level boost converter 200 switches the transistors 206, 208, 210, and 212, as Figure 3-6 shown. In the pre-PFM region, the sensed current also intersects with CLK_1 and CLK_2, but the switching in the pre-PFM region may result in an unwanted state transition. For example, the three-level boost converter 200 may turn on transistors 206 and 208 in state 4, which is unwanted when operating with a low input voltage.

[0061] In the three-level boost converter 200, the PFM control circuit 236 identifies the operation in the pre-PFM region and prohibits the switching of the transistors 206, 208, 210, and 212 based on the comparison of the sensed current with CLK_1 and CLK_2.

[0062] Figure 9 It is a timing diagram illustrating an example operation of the three-level boost converter 200 in the pre-PFM region. Figure 9Shows clock signals CLK_1 and CLK_2, current sense signals HS1_CS and LS1_CS, and transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM. The transistor control signals HS1_PWM, HS2_PWM, LS1_PWM, and LS2_PWM control the on / off of transistors 206, 208, 210, and 212, respectively. Figure 9 Also shows an LS1_ON_SKIP region defined by a signal LS1_ON_SKIP generated by the PFM control circuit 236 and an LS2_ON_SKIP region defined by a signal LS2_ON_SKIP generated by the PFM control circuit 236.

[0063] The PFM control circuit 236 identifies a pre-PFM region based on the sensed current LS1_CS at the edge of CLK_1 or CLK_2. If LS1_CS is zero at the falling edge of CLK_2, the three-level boost converter 200 operates in the pre-PFM region. If LS1_CS is zero at the falling edge of CLK_2, the PFM control circuit 236 defines the LS1_ON_SKIP region to start at the edge of CLK_2 and end at the edge of CLK_1. Similarly, if LS1_CS is zero at the falling edge of CLK_1, the three-level boost converter 200 operates in the pre-PFM region. If LS1_CS is zero at the falling edge of CLK_1, the PFM control circuit 236 defines the LS2_ON_SKIP region to start at the edge of CLK_1 and end at the edge of CLK_2. In the LS1_ON_SKIP region, the low-side turn-on circuit 242 prohibits the generation of LS1_ON and the turning on of transistor 212. In the LS2_ON_SKIP region, the low-side turn-on circuit 242 prohibits the generation of LS2_ON and the turning on of transistor 210. The pre-PFM region can be defined as either the LS1_ON_SKIP region or the LS2_ON_SKIP region.

[0064] Additionally, if LS1_ON and LS2_ON are logic zero, the high-side turn-on circuit 238 prohibits the generation of HS1_ON and HS2_ON (prohibits turning on transistor 206 and transistor 208).

[0065] In this description, the term "coupled" can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A through the control signal generated by device A.

[0066] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components or their ends.

[0067] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture to form the described structure.

[0068] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little change to the rest of the circuit system. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) (n-type transistors) or p-channel FETs (PFETs) (p-type transistors)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used instead of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0069] The control input and current terminals of a transistor may be referenced in the claims. In the case of an FET, the control input (or transistor control terminal) is the gate, and the current terminals are the drain and source. In the case of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0070] Reference herein to an FET being "on" means that there is a conducting channel in the FET and a drain current can flow through the FET. Reference herein to an FET being "off" means that the conducting channel does not exist, and thus the drain current does not flow through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0071] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0072] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0073] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially", or "essentially" in front of a parameter means within + / - 10% of the stated parameter, or, if the parameter is zero, means within a reasonable value around approximately zero.

[0074] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A circuit comprising: first, second, third and fourth transistors coupled in series; as well as a control circuit coupled to the first, second, third and fourth transistors, the control circuit comprising a clock generator, a current sensing circuit and a zero current zone division (ZC_DF) circuit, wherein: The clock generator is configured to generate first and second clocks, wherein the second clock is orthogonal to the first clock; The current sensing circuit is configured to sense a current flowing through the first transistor; The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at the turning-on of the fourth transistor; and The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and in the DCM, in response to the current flowing through the first transistor being negative, turning off the first transistor during the ZC_DF interval.

2. The circuit according to claim 1, wherein: The current sensing circuit is a first current sensing circuit; The control circuit includes a second current sensing circuit configured to detect a current flowing through the fourth transistor; and The control circuit is configured to, in DCM, turn off the second transistor during the ZC_DF interval in response to the current flowing through the fourth transistor being negative. 3 . The circuit of claim 2 , wherein the control circuit is configured to, in DCM, turn off the second transistor outside the ZC_DF interval in response to the current flowing through the first transistor being negative.

4. The circuit of claim 2, wherein: The first current sensing circuit is configured to generate a first sensing signal representative of the current flowing through the first transistor; the second current sensing circuit being configured to generate a second sensing signal representative of the current flowing through the fourth transistor; and The control circuit is configured to turn off the second transistor in response to the first sensing signal being less than the second clock or the second sensing signal being less than the second clock.

5. The circuit of claim 1, wherein: The current sensing circuit is configured to generate a sense signal representative of the current flowing through the first transistor; and The control circuit is configured to turn off the first transistor in response to the sense signal being less than the first clock.

6. The circuit of claim 1 , wherein the control circuit is configured to: operating the first, second, third and fourth transistors in a pulse frequency modulation (PFM) mode; defining a pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the second clock; as well as In the pre-PFM region: prohibiting the fourth transistor from being turned on; and In response to the current flowing through the fourth transistor being non-zero at an edge of the second clock, exiting the pre-PFM region.

7. The circuit of claim 6, wherein the control circuit is configured to: defining the pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the first clock; In the pre-PFM region: prohibiting the third transistor from being turned on; and In response to the current flowing through the fourth transistor being non-zero at an edge of the first clock, exiting the pre-PFM region.

8. The circuit of claim 6, wherein the control circuit is configured to: In the pre-PFM region: turning on of the first transistor and the second transistor is prohibited based on turning on of the third and fourth transistors being prohibited.

9. A circuit comprising: first, second, third and fourth transistors coupled in series; as well as a control circuit coupled to the first, second, third and fourth transistors, the control circuit comprising a clock generator, a first current sensing circuit and a second current sensing circuit, wherein: The clock generator is configured to generate first and second clocks, wherein the second clock is orthogonal to the first clock; The first current sensing circuit is configured to sense a current flowing through the first transistor; The second current sensing circuit is configured to sense a current flowing through the fourth transistor; and The control circuit is configured to: operating the first, second, third and fourth transistors in a pulse frequency modulation (PFM) mode; defining a pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the second clock; and In the pre-PFM region: prohibiting the fourth transistor from being turned on; and In response to the current flowing through the fourth transistor being non-zero at an edge of the second clock, exiting the pre-PFM region.

10. The circuit of claim 9, wherein the control circuit is configured to: defining the pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the first clock; In the pre-PFM region: prohibiting the third transistor from being turned on; and In response to the current flowing through the fourth transistor being non-zero at an edge of the first clock, exiting the pre-PFM region.

11. The circuit of claim 9, wherein the control circuit is configured to: In the pre-PFM region: turning on of the first transistor and the second transistor is prohibited based on turning on of the third and fourth transistors being prohibited.

12. The circuit of claim 9, wherein: The control circuit comprises: a zero current zone division (ZC_DF) circuit configured to define a ZC_DF interval starting at an edge of the second clock and ending at the turning-on of the fourth transistor; and The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and in the DCM, in response to the current flowing through the first transistor being negative, turning off the first transistor during the ZC_DF interval. 13 . The circuit of claim 12 , wherein the control circuit is configured to, in DCM, turn off the second transistor during the ZC_DF interval in response to the current flowing through the fourth transistor being negative. 14 . The circuit of claim 13 , wherein the control circuit is configured to, in DCM, turn off the second transistor outside the ZC_DF interval in response to the current flowing through the first transistor being negative.

15. The circuit of claim 13, wherein: The first current sensing circuit is configured to generate a first sensing signal representative of the current flowing through the first transistor; the second current sensing circuit being configured to generate a second sensing signal representative of the current flowing through the fourth transistor; and The control circuit is configured to turn off the second transistor in response to the first sensing signal being less than the second clock or the second sensing signal being less than the second clock.

16. The circuit of claim 13, wherein: The first current sensing circuit is configured to generate a sense signal representative of the current flowing through the first transistor; and The control circuit is configured to turn off the first transistor in response to the sense signal being less than the first clock.

17. A backlight system, comprising: Light emitting diode LED; as well as A three-level switching converter is coupled to the LED, the three-level switching converter comprising: first, second, third and fourth transistors coupled in series; as well as a control circuit coupled to the first, second, third and fourth transistors, the control circuit comprising a clock generator, a first current sensing circuit, a second current sensing circuit and a zero current zone division (ZC_DF) circuit, wherein: The clock generator is configured to generate first and second clocks, wherein the second clock is orthogonal to the first clock; The first current sensing circuit is configured to sense a current flowing through the first transistor; The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at the turning-on of the fourth transistor; and The control circuit is configured to operate the first, second, third and fourth transistors in a discontinuous conduction mode (DCM), and in the DCM: In response to the current flowing through the first transistor being negative, turning off the first transistor during the ZC_DF interval; and In response to the current flowing through the fourth transistor being negative, the second transistor is turned off during the ZC_DF interval.

18. The backlight system of claim 17, wherein the control circuit is configured to, in DCM, turn off the second transistor outside the ZC_DF interval in response to the current flowing through the first transistor being negative.

19. The backlight system according to claim 17, wherein: The first current sensing circuit is configured to generate a first sensing signal representative of the current flowing through the first transistor; the second current sensing circuit being configured to generate a second sensing signal representative of the current flowing through the fourth transistor; The control circuit is configured to: In response to the first sensing signal being smaller than the second clock or the second sensing signal being smaller than the second clock, turning off the second transistor; and In response to the first sensing signal being smaller than the first clock, the first transistor is turned off.

20. The backlight system of claim 17, wherein the control circuit is configured to: operating the first, second, third and fourth transistors in a pulse frequency modulation (PFM) mode; defining a pre-PFM region based on the current flowing through the fourth transistor being zero at an edge of the second clock or the current flowing through the fourth transistor being zero at an edge of the first clock; as well as In the pre-PFM region: prohibiting the fourth transistor from being turned on; In response to the current flowing through the fourth transistor being zero at an edge of the second clock, the pre-PFM region is initiated, and in response to the current flowing through the fourth transistor being not zero at an edge of the second clock, the pre-PFM region is exited; prohibiting the third transistor from being turned on; In response to the current flowing through the fourth transistor being zero at an edge of the first clock, the pre-PFM region is initiated, and in response to the current flowing through the fourth transistor being not zero at an edge of the first clock, the pre-PFM region is exited; and Turning on of the first transistor and the second transistor is prohibited based on turning on of the third and fourth transistors being prohibited.

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