Power adapter power transfer

Abstract

In an embodiment, a method for operating a USB-PD power adapter includes operating a first step-down circuit based on a first target voltage and a supply voltage at a supply voltage terminal, the first step-down circuit including a first switch connected between the supply voltage terminal and a first USB port, in response to the first target voltage being less than the supply voltage plus the offset voltage, the first step-down circuit is operated in a variable step-down input mode to control the first switch according to a first duty cycle based on the first target voltage and the supply voltage to generate the first target voltage at the first USB port, and in response to the first target voltage being equal to the supply voltage plus the offset voltage, operating the first buck circuit in a buck bypass mode to maintain an on state of the first switch to generate the first target voltage at the first USB port.

Description

Technical Field

[0001] The present disclosure generally relates to power transfer, and more particularly, to a universal serial bus (USB) power transfer power adapter. Background Art

[0002] Various electronic devices (e.g., smartphones, tablets, laptops, notebooks, hubs, chargers, adapters, etc.) are configured to transfer power through a USB connector according to a USB power transfer (USB-PD) protocol defined in various versions of the universal serial bus (USB) power transfer specification. An alternating current to direct current (AC-DC) converter converts power from an alternating current (AC) source into a direct current (DC) source at a specific voltage level. Summary of the Invention

[0003] The Summary of the Invention is provided to introduce a series of concepts further described below in the Detailed Description in a simplified form. The Summary of the Invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] In an embodiment of the technology presented herein, a universal serial bus (USB) power transfer (USB-PD) power adapter includes: a first USB port; a flyback converter operable to receive a first voltage and convert it to a second voltage; a first buck circuit including a first switch connected between the flyback converter and the first USB port; and a USB-PD controller connected to the flyback converter and configured to: receive a first target voltage of the first USB port; determine a value of the second voltage of the flyback converter; in response to the first target voltage being less than the second voltage plus an offset voltage, operate the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the second voltage to generate the first target voltage at the first USB port; and in response to the first target voltage being equal to the second voltage plus the offset voltage, operate the first buck circuit in a buck bypass mode to maintain the on state of the first switch to generate the first target voltage at the first USB port.

[0005] In an implementation of the technology presented in this document, a system for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: means for operating a first buck circuit based on a first target voltage of a first USB port and a power supply voltage at a power supply voltage terminal, the first buck circuit including a first switch connected between the power supply voltage terminal and the first USB port, wherein, in response to the first target voltage being less than the power supply voltage plus an offset voltage, means for operating the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the power supply voltage to generate the first target voltage at the first USB port, and in response to the first target voltage being equal to the power supply voltage plus the offset voltage, operating the first buck circuit in a buck bypass mode to maintain the first switch in an on state to generate the first target voltage at the first USB port.

[0006] In an implementation of the technology presented in this document, a method for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: operating a first buck circuit based on a first target voltage of a first USB port and a power supply voltage at a power supply voltage terminal, the first buck circuit including a first switch connected between the power supply voltage terminal and the first USB port, wherein, in response to the first target voltage being less than the power supply voltage plus an offset voltage, operating the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the power supply voltage to generate the first target voltage at the first USB port, and in response to the first target voltage being equal to the power supply voltage plus the offset voltage, operating the first buck circuit in a buck bypass mode to maintain the first switch in an on state to generate the first target voltage at the first USB port.

[0007] In an implementation of the technology presented herein, a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: a USB port; a flyback converter operable to receive a first voltage and convert it to a second voltage; a buck circuit connected between the flyback converter and the USB port; and a USB-PD controller connected to the flyback converter and configured to: receive a target voltage of the USB port; determine a value of the second voltage of the flyback converter based on the largest of the target voltages; in response to the target voltage of a first selected buck circuit in the buck circuit being less than the second voltage plus an offset voltage, operate the first selected buck circuit in a variable buck input mode according to a duty cycle based on the target voltage of the first selected buck circuit and the second voltage to generate the target voltage of the first selected buck circuit at a first USB port in the USB port associated with the first selected buck circuit; and in response to the target voltage of a second selected buck circuit in the buck circuit being less than the second voltage plus the offset voltage, operate the second selected buck circuit in a buck bypass mode according to a 100% duty cycle to generate the target voltage of the second selected buck circuit at a second USB port in the USB port associated with the second selected buck circuit.

[0008] To achieve the foregoing and related purposes, the following description and drawings set forth certain illustrative aspects and implementations. These illustrative aspects and implementations only indicate some of the various ways in which one or more aspects may be employed. When considered in conjunction with the drawings, other aspects, advantages, and novel features of the present disclosure will become apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a block diagram of a multi-port Universal Serial Bus (USB) Power Delivery (USB-PD) power adapter according to some implementations.

[0010] Figure 1B is a schematic block diagram of a flyback converter according to some implementations.

[0011] Figure 1C is a schematic block diagram of a buck circuit in a USB power adapter according to some implementations.

[0012] Figure 1D is a schematic block diagram of a first buck circuit operating in a buck bypass mode and a second buck circuit operating in a variable buck input mode according to some implementations.

[0013] Figure 2 is a flowchart showing a method of operating a USB power adapter in a buck bypass mode according to some implementations.

[0014] Figure 3A diagram of an on-chip integrated circuit (IC) USB controller according to some embodiments.

[0015] Figure 4 A block diagram of a system 400 for a USB device according to some embodiments. Detailed embodiments

[0016] The claimed subject matter is now described with reference to the accompanying drawings, in which like reference numerals are always used to refer to like elements. In the following description, numerous specific details are set forth for purposes of illustration in order to provide a thorough understanding of the claimed subject matter. It is evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0017] It should be understood that the following description of the embodiments should not be considered limiting. The scope of the present disclosure is not intended to be limited to the embodiments or drawings described hereinafter which are only considered illustrative. The drawings should be considered as schematic representations and the elements shown in the drawings are not necessarily drawn to scale. Instead, the various elements are represented such that their function and general purpose become apparent to those skilled in the art.

[0018] All numerical values in the detailed embodiments herein and in the claims are modified by the term "about" or "approximately" indicating the value, and account for experimental error and variations that would be expected by a person of ordinary skill in the art.

[0019] Figure 1A A block diagram of an embodiment of a multi-port USB power adapter 100, which includes a flyback converter 102, buck circuits 104A, 104B, and a USB controller 106. The USB controller 106 includes a buck controller 108 and a USB-PD subsystem 110. The buck controller 108 can be integrated as part of a DC / DC controller or subsystem in the USB controller 106 (also referred to as a USB-PD controller) as shown, or the buck controller 108 can be external to the USB controller 106. In some embodiments, the multi-port USB power adapter 100 includes two USB ports 112A, 112B corresponding to the buck circuits 104A, 104B. However, any number of USB ports and buck circuits 104A, 104B can be provided. Each of the USB ports 112A, 112B is connected to the output of the flyback converter 102 through one of the buck circuits 104A, 104B and is connected to the USB controller 106 through one or more CC lines and DP / DM lines.

[0020] The flyback converter 102 is configured to receive an input AC or DC voltage and convert the input AC or DC voltage into a second DC voltage. Each of the step-down circuits 104A, 104B connected between the power voltage terminal of the flyback converter 102 and one of the USB ports 112A, 112B can be configured by the step-down controller 108 to receive the input voltage (V IN ) from the flyback converter 102 at the power voltage terminal and output a target voltage (V OUT_C1 or V OUT_C2 ) to one of the USB ports 112A, 112B. More specifically, the step-down controller 108 is operable to independently control each of the step-down circuits 104A, 104B to provide the requested or target V OUT_C1 or V OUT_C2 on the associated USB ports 112A, 112B. In some embodiments, the output voltages V OUT_C1 and V OUT_C2 do not need to be the same, and both of the USB ports 112A, 112B do not need to be active simultaneously with the devices connected to the USB ports 112A, 112B. The USB controller 106 is coupled to the flyback converter 102, the step-down circuits 104A, 104B, and the USB ports 112A, 112B. The USB-PD subsystem 110 in the USB controller 106 is configured to control or operate the flyback converter 102 and cooperate with the step-down controller 108 to operate the multi-port USB power adapter 100 in a variable step-down input mode or a step-down bypass mode.

[0021] In the variable step-down input mode, the USB-PD subsystem 110 controls the flyback converter 102 to generate the input voltage (V IN ) to the step-down circuits 104A, 104B, and the input voltage (V IN ) is determined by the higher of the offset voltage (V OS ) and the highest requested output voltage (V OUT_C1 or V OUT_C2 ), or a voltage determined according to the power (W C1 , W C2 ) in watts drawn on the two ports relative to the maximum current (I max ) supported by the multi-port USB power adapter 100. If only one of the USB ports 112A is active or connected to the first device, the USB-PD subsystem 110 operates the flyback converter 102 to generate a V OS equal to the sum of V OUT_C1 and the requested V INIf the second USB port 112B is also connected to a second device, the USB-PD subsystem 110 operates the flyback converter 102 to generate a voltage equal to V OS With V OUT_C1 or V OUT_C2 The larger of the sum of V IN and coupled to the first buck circuit 104A and the second buck circuit 104B, and the buck circuits 104A and 104B are enabled and operated to convert V OUT_C1 output to the first USB port 112A, and V OUT_C2 Output to the second USB port 112B.

[0022] In the buck bypass mode where a single USB port 112A is active, the USB-PD subsystem 110 of the USB controller 106 controls the flyback converter 102 to generate a voltage equal to V OUT_C1 V IN By configuring the first buck circuit 104A in the buck bypass mode, the V IN is passed to the first USB port 112A. If the second USB port 112B is also connected to a second device, the USB-PD subsystem 110 operates the flyback converter 102 to generate V IN and coupled to the first buck circuit 104A and the second buck circuit 104B. IN Equal to V OUT_C1 、V OUT_C2 The larger of the two ports or the power drawn in watts (W C1 , W C2 ) relative to the maximum current (I max ) and the voltage determined by the request for a lower output voltage (V OUT_C1 or V OUT_C2 The buck circuits 104A, 104B associated with the USB ports 112A, 112B of the 200A and 200B are then operated in a variable buck input mode to generate the requested lower output voltage. If both USB ports 112A, 112B are connected to devices and have the same requested voltage, then V IN is set equal to V OUT_C1 / V OUT_C2 Add V OS , and both buck circuits 104A, 104B operate in buck bypass mode.

[0023] In some embodiments, the requested output voltage (V OUT_C1 or V OUT_C2 ) may include one of 5V, 9V, 12V, 15V, or 20V (e.g., in accordance with the USB-PD specification). Where applicable, the offset voltage (VOS ) Compensate for the expected voltage drop across the buck circuits 104A, 104B and typically depends on the maximum duty cycle of the buck circuits 104A, 104B. For example, if the offset voltage V OS is 1V, then V IN in the variable buck input mode can include 6V, 10V, 13V, 16V or 21V.

[0024] A more detailed description of an embodiment of the multi-port USB power adapter 100 will now be made with reference to Figure 1B FIG. Figure 1B is a schematic diagram showing an embodiment of the USB power adapter of Figure 1A FIG. In the illustrated embodiment, the multi-port USB power adapter 100 is a dual-port USB power adapter that includes a first USB Type-C port 112A and a second USB Type-C port 112B and an AC-DC flyback converter 102.

[0025] Figure 1B is a schematic block diagram of the flyback converter 102 according to some embodiments. In some embodiments, the flyback converter 102 includes a transformer 114 that has a primary winding electrically connected or coupled to the input terminal on the primary side 144P and a secondary winding coupled to the output terminal on the secondary side 114S. On the primary side 114P, a rectifying circuit such as a bridge rectifier 116 and one or more input filters 118, 120 are connected to a first terminal of the transformer 114 to rectify the AC input voltage AC IN and provide input power to the primary winding of the transformer 114. The flyback converter 102 also includes a power switch (PS122), such as a primary field effect transistor (PRFET), that has a drain node coupled to a second terminal of the transformer 114, a gate node coupled to the primary side controller 124, and a source node coupled to the primary side controller, and the source node is coupled to ground through a current sensing element (such as a resistive element (RCS)) to sense the primary side current (I PR ) flowing through the primary winding when PS122 is closed or turned on. In some embodiments, the primary side controller 124 is also connected to the first terminal of the transformer 114 through a resistive element (R IN ) to receive a voltage or signal equal to or proportional to the rectified AC input voltage.

[0026] On the secondary side 114S, the flyback converter 102 includes a synchronous rectifier (SR) such as an SR field effect transistor (SRFET) 126, an SR controller 128 coupled to the gate of the SRFET 126, and an output capacitor 130. The flyback converter 102 also includes an isolation circuit or barrier 132 to electrically isolate the secondary side 114S from the AC input voltage present on the primary side 114P. Since the transformer 114 is a step-down transformer, it is considered part of the isolation barrier 132. The isolation barrier 132 also includes an opto-isolator 134 to provide electrical isolation with the USB-PD subsystem 110 of the USB controller 106 and the primary side controller 124 on the flyback or feedback path. In some embodiments, the opto-isolator 134 includes a light emitting element such as a light emitting diode (LED), and a photosensitive element 136 such as a phototransistor. The opto-isolator 134 has an anode coupled to the drain of the SR_FET 126 through a first voltage divider including a first resistor element R1 and a second resistor element R2, and a cathode coupled to ground through a shunt regulator 138. The cathode of the opto-isolator 134 and the shunt regulator 138 are also coupled to the feedback (FB) pin 140 of the USB controller 106 through a second voltage divider including resistor elements R3 and R4 and through an enhancement mode n-channel transistor 142 to receive a pulse width modulation (PWM) feedback signal, which enables the secondary side control of the flyback converter 102. The photosensitive element 136 may include a bipolar NPN transistor and is coupled to the primary side controller 124 through the FB_INPUT pin 144. Alternatively, the shunt regulator 138, the transistor 142, and the resistors R3, R4 may be integrated in the USB-PD subsystem 110 of the USB controller 106, and for some highly integrated flyback controller designs, the USB controller 106 may control the flyback converter 102 through a digital interface such as an internal integrated circuit (I2C) or a serial peripheral interface (SPI). In some embodiments, a pulse transformer that magnetically transmits the PWM signal may be used to transmit the PWM signal between the SR controller 128 and the primary side controller 124, where the pulse transformer provides the isolation barrier.

[0027] In operation, the SR controller 128 senses the voltage on SR_DRAIN and turns the SRFET 126 on and off in response to sensed voltage peaks, negative crossings, and zero crossings. The primary side controller 124 receives signals from the SR_FET 126 or the SR controller 128 via a feedback or flyback path. During the time when PS122 is turned on or closed and the SR_FET 126 is turned off or open, the flyback converter 102 is considered to be operating in the flyback mode, and a magnetic field is established in the transformer 114 while the current on the primary side 114P linearly increases. When PS122 is turned off or open and the SR_FET 126 is turned on or closed, the flyback converter 102 transfers power to the secondary side 114S, where the magnetic field begins to decay and the secondary side current steadily decreases, but gradually decreases as power is transferred to the capacitor 130 connected to the output terminal until a point where there is substantially zero current flow in the secondary side 114S is reached.

[0028] Figure 1C is a schematic diagram of an embodiment of the buck circuits 104A, 104B according to some embodiments. Each of the buck circuits 104A, 104B includes an input capacitor 150, an input resistor 151, a first switching element 152, a second switching element 154, an inductor 156, a capacitor 158, a current sensing resistor 160, and an output capacitor 162. In some embodiments, a transistor 164 is provided that uses the VBUS_CTRL signal to control the switching rate of the buck circuits 104A, 104B.

[0029] In the variable buck input mode, the USB controller 106 operates to switch the buck circuits 104A, 104B between a mode of storing energy in the inductor 156 while the capacitor 158 provides the output and a mode of releasing the stored energy to recharge the capacitor 158. When the switching element 152 is turned on and the switching element 154 is turned off, energy is stored in the inductor 156. When the switching element 152 is turned off and the switching element 154 is turned on, energy is sent to the capacitor 158 to generate the output voltage. The PWM duty cycle of the buck circuits 104A, 104B is determined based on the ratio of the output voltage to the input voltage.

[0030] In the buck bypass mode, the USB controller 106 operates to keep the switching element 152 in the on state and the switching element 154 in the off state, thereby charging the output capacitor 158 with the input voltage V IN to generate the output voltage. In some embodiments, the switching element 152 is kept in the on state by setting the PWM duty cycle to 100%. In some embodiments, a bootstrap circuit such as a charge pump generates a bootstrap signal to keep the switching element 152 in the on state.

[0031] Figure 2 is a flowchart of a method 200 for operating a USB power adapter in a step-down bypass operation mode. The USB controller 106 operates the step-down circuits 104A, 104B according to a contract established with the load devices on the USB ports 112A, 112B. At 202, the input voltage V of the flyback converter 102 is set. IN . In some embodiments, V IN is set to the lowest supported output voltage from one of the multiple USB ports 112A, 112B, for example, V IN = 5V. In some embodiments, the supported output voltages may include 5V, 9V, 12V, 15V, or 20V (e.g., according to the USB-PD specification). At 204, it is determined whether at least the first USB port 112A among the multiple USB ports 112A, 112B is active (i.e., whether a device is connected to the first USB port 112A). If no device is detected at 204, the USB port 112A is disabled at 206. If a device is connected at 204, it is determined at 208 whether the second USB port 112B among the multiple USB ports 112A, 112B is active and whether a device is connected. If the second USB port 112B is not active at 208, the USB-PD subsystem 110 enables the bypass mode of the step-down circuit 104A at 210 and controls V IN to be equal to the target voltage V of the first USB port 112A OUT_C1 .

[0032] If it is detected at 208 that a second device is connected to the second USB port 112B, it is determined at 214 whether the requested voltage or target voltage V of the second USP port 112B OUT_C2 is the same as the target voltage V of the first USB port 112A OUT_C1 . If the requested voltage or target voltage V at 214 OUT_C2 and V OUT_C1 are the same, then at 216, the USB-PD subsystem 110 enables the bypass mode of both the step-down circuits 104A, 104B and controls V IN to be equal to the target voltages V of the USB ports 112A, 112B OUT_C1 , V OUT_C2 .

[0033] If at 214, the requested voltage or target voltage V OUT_C2 and V OUT_C1 are not the same, then at 220, the USB-PD subsystem 110 enables the one with the highest target voltage V OUT_CThe bypass mode of the buck circuits 104A and 104B, and controls V at 222 IN equal to the highest target voltage V OUT_C . At 224, the USB-PD subsystem 110 enables the buck mode of the buck circuits 104A and 104B with the lowest target V OUT_C .

[0034] Figure 1D Shows the buck circuit 104A operating in the buck bypass mode and the buck circuit 104B operating in the variable buck input mode. In the buck circuit 104A, the PWM of the switching element 152 is set to 100% (represented by a solid line), and the PWM of the switching element 154 is set to zero (represented by a double line). The input voltage generated by the flyback converter 102 is set to V IN = +V OUT_C1 +V OS . In the buck circuit 104B, the PWM of the switching element 152 is set to PWM = V OUT_C2 / V IN (represented by a dotted line).

[0035] Figure 2 The method 200 in can be applied to any number of buck circuits 104A, 104B and associated USB ports 112A, 112B. The USB-PD subsystem 110 sets V IN equal to the highest target voltage V OUT_C across all active USB ports 112A, 112B, and enables the bypass mode of the buck circuits 104A, 104B with that highest target voltage V OUT_C . The USB-PD subsystem 110 enables the buck mode of the buck circuits 104A, 104B for any USB port in USB ports 112A, 112B having a lower requested voltage or target voltage.

[0036] In some embodiments, the USB-PD subsystem 110 uses a feedback loop or mechanism that monitors the output voltage (V max , V OUT_C1 , V OUT_C2 ) and the load current (I out_C1 , I out_C2 ) relative to the maximum current (I max ) supported by the multi-port USB power adapter 100, and switches the operation between the buck bypass mode and the variable buck input mode based on the total wattage drawn on the USB ports 112A, 112B. When the total current drawn on the USB ports 112A, 112B relative to I maxWhen it is small, the multi-port USB power adapter 100 can continue to operate in the buck bypass mode. When the current drawn on the USB ports 112A, 112B increases, the USB-PD subsystem 110 increases V IN to a higher voltage (limited by I max ) and operates the buck circuits 104A, 104B in the variable buck input mode. In some embodiments, the current limit occurs when the maximum target output voltage V OUT_C is less than 15V. When the target output voltage V OUT_C is 15V (optional) or 20V, the USB-PD subsystem 110 can continue to operate in the buck bypass mode for the USB ports 112A, 112B that request 15V (optional) or 20V.

[0037] Figure 3 is a block diagram of the USB controller 106 according to some embodiments. The USB controller 106 includes a sensing unit 302 and a gate driver 304. The gate driver 304 is coupled to the gate node of the switching element 152 through the HG1 pin and to the gate node of the switching element 154 through the LG1 pin. The sensing unit 302 is coupled to the drain node of the switching element 152 through the SNS pin and to the source node of the switching element 152 through the SVSS pin. The sensing unit 302 includes a zero-crossing detector (ZCD) block for sensing or detecting zero-crossing, a negative sensing detection (NSN) block for sensing the negative voltage in the SNS pin, a line feed-forward (LFF) block for sensing the feed-forward operation, and a peak detector for detecting the peak voltage on the SNS pin. One or more output terminals of the sensing unit 302 are coupled to the gate driver 304 and the pulse width modulation (PWM) circuit 306 to generate switching signals for controlling the switching elements 152, 154.

[0038] The USB controller 106 further includes: a secondary switching unit 308, which includes a conversion rate control gate driver for driving the provided transistor 164; a low dropout (LDO) regulator; a high voltage (HV) regulator; a VBUS_C discharge circuit for discharging V OUT_C1 , V OUT_C2 ; and a CSNO discharge unit for discharging the VBUS_CTRL line.

[0039] The interface circuit 310 switch includes circuits or blocks for communicating with the devices powered or charged by the USB controller 106 to support various charging protocols. These circuits or blocks may include: a VCONN block for reusing the CC pins to power the electronic device in the USB Type-C power delivery mode; and a bi-phase mark code (BMC) and a physical layer (PHY) for communicating with the device using certain charging protocols and a charger detection module.

[0040] The USB controller 106 includes a microcontroller unit (MCU) subsystem 312, and the microcontroller unit (MCU) subsystem 312 includes: logic and a microprocessor or controller for executing a program stored in the memory of the MCU subsystem; an analog-to-digital converter (ADC); a multi-purpose timer counter pulse width modulator (TCPWM) capable of performing multiple functions required for the operation of the MCU; a plurality of general-purpose input / outputs (GPIO); and a serial communication bus (SCB).

[0041] The USB controller 106 includes a feedback circuit 314 coupled to a feedback pin to provide error correction to the PWM unit 306. In some embodiments, the feedback circuit 314 includes a constant voltage (CV) reference, a constant current (CC) reference, one or more error amplifiers such as a constant voltage (CV) error amplifier or a constant current (CC) error amplifier, a digital-to-analog converter (IDAC), and a current sense amplifier (CSA).

[0042] In the bypass mode, the USB controller 106 maintains the on state of the switching element 152 and the off state of the switching element 154 to charge the output capacitor 158 with the input voltage V IN to generate an output voltage. In some embodiments, the on state of the switching element 152 is maintained by setting the PWM duty cycle in the PWM unit 306 to 100%. In some embodiments, a bootstrap circuit generates a bootstrap signal to maintain the on state of the switching element 152. In some embodiments, the bootstrap unit includes a charge pump 316 and a diode 318.

[0043] Figure 4FIG. 0 is a block diagram of a system 400 for a USB device according to some embodiments. In some embodiments, system 400 includes a peripheral subsystem 402, a peripheral interconnect 404, a CPU subsystem 408, a DC / DC controller 409 including a buck controller 409B, and system resources 410. In some embodiments, peripheral subsystem 402 includes a plurality of components used in USB Power Delivery (USB-PD). Peripheral subsystem 402 may include a peripheral interconnect 404, which includes a Peripheral Clock Module (PCLK) 406 for providing a clock signal to various components of peripheral subsystem 402. Peripheral interconnect 404 may be a peripheral bus, such as a single-stage or multi-stage Advanced High-Performance Bus (AHB), and may provide a data and control interface between peripheral subsystem 402 and CPU subsystem 408. Peripheral interconnect 404 may include controller circuitry, such as a Direct Memory Access (DMA) controller, which may be programmed to transfer data between peripheral blocks without input from CPU subsystem 408, without control from CPU subsystem 408, or without imposing the same transfer.

[0044] Peripheral interconnect 404 may be used to couple peripheral subsystem 402 components to other components of system 400. A plurality of General-Purpose Input / Output (GPIO) 412 may be coupled to peripheral interconnect 404 for sending and receiving signals. GPIO 412 may include circuitry configured to implement various functions, such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single multiplexing, and so on. Other functions may also be implemented by GPIO 412. One or more Timer / Counter / Pulse-Width Modulator (TCPWM) 414 may also be coupled to the peripheral interconnect and may include circuitry that implements a timing circuit (timer), counter, pulse-width modulator (PWM), decoder, and other digital functions associated with working with I / O signals, and may provide digital signals to system components of system 400. Peripheral subsystem 402 may also include one or more Serial Communication Blocks (SCB) 416 for implementing serial communication interfaces, such as I2C, Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), Controller Area Network (CAN), CXPI (Clock eXtended Peripheral Interface), etc.

[0045] For USB power delivery applications, the peripheral subsystem 402 may include a USB power delivery subsystem 418 coupled to the peripheral interconnect 404, and the USB power delivery subsystem 418 includes a set of USB PD modules 420 for use with USB power delivery. The USB PD modules 420 may be coupled to the peripheral interconnect 404 via a USB-PD interconnect 422. The USB PD modules 420 may include: one or more analog-to-digital converters (ADCs) for converting various analog signals into digital signals; a VCONN unit; an error amplifier (ERROR AMP) for controlling the power voltage applied to the VBUS line according to a PD contract; a high-voltage regulator (HV REG) for converting the power voltage into the precise voltage required by the USB controller 106 (e.g., 3V to 5V); a current sense amplifier (CSA); an overvoltage protection (OVP) circuit; an overcurrent protection (OCP) circuit; a pulse width modulator (PWM); one or more gate drivers (GATE DRIVER) for controlling the power switches that turn on and off the power supply on the VBUS line; a low-side gate driver (LSDR); a high-side gate driver (HSDR); a charge protocol detection block (CHG DET) for detecting and supporting different types of proprietary charging standards; at least two on-die discharge (VBUS DISCH) circuits that can discharge the VBUS line voltage to any range of programmable voltage levels; and a communication channel PHY (CC BB PHY) logic for supporting communication on a Type-C communication channel (CC), including the requested V OUT_C level.

[0046] The USB power delivery subsystem 418 may also include pads 424 for external connection and an electrostatic discharge (ESD) suppression circuitry 426 that may be required on a Type-C port. The USB PD modules 420 may also include a communication module for retrieving and sending information such as control signals from, for example, the USB controller 106 and the SR controller 128.

[0047] The GPIO 412, TCPWM 414, and SCB 416 may be coupled to an input / output (I / O) subsystem 428, and the input / output (I / O) subsystem 428 may include a high-speed (HS) I / O matrix 430 connected to a plurality of GPIOs 432. The GPIO 412, TCPWM 414, and SCB 416 may be coupled to the GPIOs 432 via the HS-I / O matrix 430.

[0048] The central processing unit (CPU) subsystem 408 is used to process instructions, store program information, and data. The CPU subsystem 408 may include one or more processing units 434 for executing instructions and reading from and writing to memory locations in multiple memories. The processing unit 434 may be a processor adapted to operate in an integrated circuit (IC) or system-on-chip (SOC) device. In some embodiments, the processing unit 434 may be optimized for low-power operation using a large amount of clock gating. In this embodiment, different internal control circuits may be implemented for the operation of the processing unit in different power states. For example, the processing unit 434 may include a single-wire debug (SWD) module, a terminal count (TC) module, a wake-up interrupt controller (WIC) configured to wake up the processing unit from a sleep state (which may turn off the power when the IC or SOC is in the sleep state), a fast multiplier, a nested vector interrupt controller (NVIC), and an interrupt multiplexer (IRQMUX). The CPU subsystem 408 may include one or more memories, including flash memory 436, static random access memory (SRAM) 438, and read-only memory (ROM) 440. The flash memory 436 may be non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. The flash memory 436 may include a system performance controller interface (SPCIF) register and a read accelerator, and improve the access times by being integrated into the CPU subsystem 408. The SRAM 438 may be volatile memory configured to store data and firmware instructions accessible by the processing unit 434. The ROM 440 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during the operation of the system 400. The SRAM 438 and the ROM 440 may have associated control circuitry. The processing unit 434 and the memory modules 436, 438, 440 may be coupled to a system interconnect 442 to route signals to various components of the CPU subsystem 408 and route signals from various components of the CPU subsystem 408 to other blocks or modules of the system 400. The system interconnect 442 may be implemented as a system bus, such as a single-level or multi-level AHB. The system interconnect 442 may be configured as an interface for coupling various components of the CPU subsystem 408 together. The system interconnect 442 may be coupled to a peripheral interconnect 404 to provide a signal path between the components of the CPU subsystem 408 and the components of the peripheral subsystem 402.

[0049] System resources 410 may include a power module 444, a clock module 446, a reset module 448, and a test module 450. The power module 444 may include a sleep control module, a wake interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a PWRSYS module. In some embodiments, the power module 444 may include circuitry that enables system 400 to draw power from and / or supply power to an external source at different voltage levels and / or current levels, and to control operation in different power states such as active, low power, or sleep. In various embodiments, more power states may be implemented as system 400 throttles operation to achieve a desired power consumption or power output. For example, the secondary side controller 104 may access secondary electrical parameters on the secondary side. The clock module 446 may include a clock control module, a watchdog timer (WDT), an internal low oscillator (ILO), and an internal master oscillator (IMO). The reset module 448 may include a reset control module and an external reset module (XRES module). The test module 450 may include a module for controlling and entering a test mode, and a test control module for simulating functional and digital functions (digital test and analog DFT).

[0050] System 400 may be implemented in a single (e.g., monolithic) semiconductor die. In other embodiments, different portions or modules of system 400 may be implemented on different semiconductor dies. For example, the memory modules 436, 438, 440 of the CPU subsystem 408 may be on-chip or off-chip. In other embodiments, circuitry with separate dies may be packaged in a single "chip", or remain separate and arranged as separate components on a circuit board (or in a USB cable connector).

[0051] System 400 can be implemented in multiple application environments to provide USB PD functionality. In any application environment, an electronic device (e.g., a USB-enabled device) can have an IC controller or an SOC implementation implemented by System 400, which is arranged and configured to perform operations according to the techniques described herein. In one embodiment, System 400 can be arranged and configured in a personal computer (PC) power adapter for a laptop computer, notebook computer, etc. In another embodiment, System 400 can be housed in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smartphone, a tablet, etc.). In another embodiment, System 400 can be set and configured in a wall socket that is configured to provide power via a USB Type-A port and / or a USB Type-C port. In another embodiment, System 400 can be arranged and configured in a vehicle charger that is configured to provide power via a USB Type-A port and / or a USB Type-C port. In yet another embodiment, System 400 can be arranged and configured in a power bank that can be charged via a USB Type-A port and / or a USB Type-C port and then supply power to another electronic device. In other embodiments, a system such as System 400 can be configured with the power switch gate control circuitry described herein and can be incorporated into various other USB-enabled electronic devices or electromechanical devices.

[0052] It should be understood that a system (such as System 400) implemented on or as an IC controller can be placed in various applications that vary according to the type of power used and the power supply direction. For example, in the case of a vehicle charger, the power source is a vehicle battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall socket. Additionally, in the case of a PC power adapter, the flow of power input is from the provider device to the consumer device, while in the case of a power bank, the flow of power input can be in either direction, depending on whether the power bank is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., allowing itself to be charged). For these reasons, the various applications of System 400 should be considered illustrative rather than restrictive in nature.

[0053] In an embodiment of the technology presented herein, a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: a first USB port; a flyback converter operable to receive a first voltage and convert it to a second voltage; a first buck circuit including a first switch connected between the flyback converter and the first USB port; and a USB-PD controller connected to the flyback converter and configured to: receive a first target voltage of the first USB port; determine a value of the second voltage of the flyback converter; in response to the first target voltage being less than the second voltage plus an offset voltage, operate the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the second voltage to generate the first target voltage at the first USB port; and in response to the first target voltage being equal to the second voltage plus the offset voltage, operate the first buck circuit in a buck bypass mode to maintain the first switch in an on state to generate the first target voltage at the first USB port.

[0054] In an embodiment of the technology presented herein, the USB-PD power adapter includes: a second USB port; and a second buck circuit including a second switch connected between the flyback converter and the second USB port, wherein the USB-PD controller is configured to: receive a second target voltage of the second USB port; determine a value of the second voltage of the flyback converter based on a larger value of the first target voltage and the second target voltage; in response to the second target voltage being less than the second voltage plus the offset voltage, operate the second buck circuit in a variable buck input mode to control the second switch according to a second duty cycle based on the second target voltage and the second voltage to generate the second target voltage at the second USB port; and in response to the second target voltage being equal to the second voltage plus the offset voltage, operate the second buck circuit in a buck bypass mode to maintain the second switch in an on state to generate the second target voltage at the second USB port.

[0055] In an embodiment of the technology presented herein, the USB-PD controller includes a bootstrap circuit connected to a gate input of the first switch to maintain the first switch in an on state in the buck bypass mode.

[0056] In an embodiment of the technology presented herein, the bootstrap circuit includes a charge pump.

[0057] In an embodiment of the technology presented herein, the USB-PD controller includes a Pulse Width Modulation (PWM) circuit connected to a gate input of the first switch to switch the first switch according to the first duty cycle in the variable buck input mode and maintain the first switch in an on state in the buck bypass mode.

[0058] In an embodiment of the technology presented herein, the first buck circuit includes a second switch connected between the first USB port and ground, and the USB-PD controller is configured to keep the second switch off in the buck bypass mode.

[0059] In an embodiment of the technology presented herein, the first buck circuit includes an inductor connected between the first switch and the first USB port, and the offset voltage depends on the voltage drops across the first switch and the inductor.

[0060] In an embodiment of the technology presented herein, a method for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter includes: operating a first buck circuit based on a first target voltage of a first USB port and a power voltage at a power voltage terminal, the first buck circuit including a first switch connected between the power voltage terminal and the first USB port; in response to the first target voltage being less than the power voltage plus an offset voltage, operating the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the power voltage to generate the first target voltage at the first USB port; and in response to the first target voltage being equal to the power voltage plus the offset voltage, operating the first buck circuit in the buck bypass mode to keep the first switch on to generate the first target voltage at the first USB port.

[0061] In an embodiment of the technology presented herein, the method includes: operating a second buck circuit based on a second target voltage of a second USB port and a power voltage at a power voltage terminal, the second buck circuit including a second switch connected between the power voltage terminal and the second USB port, wherein in response to the second target voltage being less than the power voltage plus the offset voltage, operating the second buck circuit in a variable buck input mode to control the second switch according to a second duty cycle based on the second target voltage and the power voltage to generate the second target voltage at the second USB port; and in response to the second target voltage being equal to the power voltage plus the offset voltage, operating the second buck circuit in the buck bypass mode to keep the second switch on to generate the second target voltage at the second USB port.

[0062] In an embodiment of the technology presented herein, the method includes configuring a flyback converter to generate a power voltage at the power voltage terminal based on the larger of the first target voltage and the second target voltage.

[0063] In an embodiment of the technology presented herein, the method includes enabling a bootstrap circuit connected to the gate input of the first switch to keep the first switch on in the buck bypass mode.

[0064] In an embodiment of the technology presented herein, enabling the bootstrap circuit includes enabling a charge pump connected to the gate input of the first switch.

[0065] In an embodiment of the technology presented herein, the method includes configuring a pulse width modulation (PWM) circuit connected to the gate input of the first switch to switch the first switch according to a first duty cycle in a variable buck input mode and to keep the first switch in an on state in a buck bypass mode.

[0066] In an embodiment of the technology presented herein, the first buck circuit includes a second switch connected between the first USB port and ground, and the method includes keeping the second switch in an off state in a buck bypass mode.

[0067] In an embodiment of the technology presented herein, the first buck circuit includes an inductor connected between the first switch and the first USB port, and the method includes configuring an offset voltage based on the voltage drops across the first switch and the inductor.

[0068] In an embodiment of the technology presented herein, a universal serial bus power delivery (USB-PD) power adapter includes: a USB port; a flyback converter operable to receive a first voltage and convert it to a second voltage; a buck circuit connected between the flyback converter and the USB port; and a USB-PD controller connected to the flyback converter and configured to: receive a target voltage of the USB port; determine a value of the second voltage of the flyback converter based on the maximum of the target voltages; in response to the target voltage of a first selected buck circuit in the buck circuit being less than the second voltage plus the offset voltage, operate the first selected buck circuit in a variable buck input mode according to a duty cycle based on the target voltage of the first selected buck circuit and the second voltage to generate the target voltage of the first selected buck circuit at a first USB port in the USB port associated with the first selected buck circuit; and in response to the target voltage of a second selected buck circuit in the buck circuit being less than the second voltage plus the offset voltage, operate the second selected buck circuit in a buck bypass mode according to a 100% duty cycle to generate the target voltage of the second selected buck circuit at a second USB port in the USB port associated with the second selected buck circuit.

[0069] In an embodiment of the technology presented herein, the first selected buck circuit includes a switch, and the USB-PD controller is configured to control the switch based on the duty cycle.

[0070] In an embodiment of the technology presented herein, the USB-PD controller includes a bootstrap circuit connected to the gate input of the switch to keep the switch in an on state in a buck bypass mode.

[0071] In an implementation of the technology presented herein, the second selected buck circuit includes a second switch, and the USB-PD controller includes a pulse width modulation (PWM) circuit that is connected to the gate input of the second switch to switch the second switch according to a duty cycle in a variable buck input mode.

[0072] In an implementation of the technology presented herein, the USB-PD controller includes a pulse width modulation (PWM) circuit that is connected to the gate input of the switch to keep the switch on in a buck bypass mode.

[0073] Various operations of the implementations are provided herein. In one implementation, one or more of the described operations may constitute computer-readable instructions stored on one or more computer-readable media that, if executed by a computing device, will cause the computing device to perform the described operations. The order of some or all of the described operations should not be construed as implying that these operations must be order-dependent. Those skilled in the art who benefit from this specification will understand alternative orderings. In addition, it should be understood that not all operations must be present in every implementation provided herein. Further, it will be understood that in some implementations, not all operations are required.

[0074] In addition, unless otherwise specified, "first", "second", etc. are not intended to imply any aspect of time, space, order, etc. Instead, these terms are only used as identifiers, names, etc. for features, elements, items, etc. For example, a first object and a second object generally correspond to object A and object B or two different or two identical objects or the same object.

[0075] In addition, terms such as "exemplary" used herein are meant to be used as examples, instances, illustrations, etc. and are not necessarily advantageous. As used herein, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Further, as used in this application, "a" and "an" can generally be construed to mean "one or more" unless otherwise stated or clearly meant to be in the singular form according to the context. Further, with respect to the use of "comprising", "having", "has", "containing", and / or variants thereof in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "including".

[0076] In addition, although the present disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the present disclosure may be disclosed with respect to only one of several implementations, such a feature may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application.

Claims

1. A universal serial bus power transmission USB-PD power adapter, comprising: First USB port; a flyback converter operable to receive a first voltage and convert the first voltage into a second voltage; a first buck circuit comprising a first switch connected between the flyback converter and the first USB port; and A USB-PD controller is connected to the flyback converter and is configured to: receiving a first target voltage of the first USB port; determining a value of the second voltage of the flyback converter; in response to the first target voltage being less than the second voltage plus an offset voltage, operating the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the second voltage to generate the first target voltage at the first USB port; as well as In response to the first target voltage being equal to the second voltage plus the offset voltage, operating the first buck circuit in a buck bypass mode to maintain an on state of the first switch to generate the first target voltage at the first USB port.

2. The USB-PD power adapter according to claim 1, comprising: Second USB port; as well as A second buck circuit includes a second switch connected between the flyback converter and the second USB port, wherein: The USB-PD controller is configured to: receiving a second target voltage from the second USB port; determining a value of the second voltage of the flyback converter based on the greater of the first target voltage and the second target voltage; in response to the second target voltage being less than the second voltage plus the offset voltage, operating the second buck circuit in a variable buck input mode to control the second switch according to a second duty cycle based on the second target voltage and the second voltage to generate the second target voltage at the second USB port; and In response to the second target voltage being equal to the second voltage plus the offset voltage, operating the second buck circuit in a buck bypass mode to maintain an on state of the second switch to generate the second target voltage at the second USB port.

3. The USB-PD power adapter according to claim 1, wherein: The USB-PD controller includes: A bootstrap circuit is connected to a gate input terminal of the first switch to maintain an on state of the first switch in the buck bypass mode.

4. The USB-PD power adapter according to claim 3, wherein: The bootstrap circuit includes a charge pump.

5. The USB-PD power adapter according to claim 1, wherein: The USB-PD controller includes: A pulse width modulation (PWM) circuit is connected to the gate input terminal of the first switch to switch the first switch according to the first duty cycle in the variable buck input mode and to maintain the on state of the first switch in the buck bypass mode.

6. The USB-PD power adapter according to claim 1, wherein: The first step-down circuit includes a second switch connected between the first USB port and ground; and The USB-PD controller is configured to maintain an off state of the second switch in the buck bypass mode.

7. The USB-PD power adapter according to claim 1, wherein: The first step-down circuit includes an inductor connected between the first switch and the first USB port; and The offset voltage depends on a voltage drop across the first switch and the inductor.

8. A method for operating a Universal Serial Bus Power Delivery (USB-PD) power adapter, comprising: Based on a first target voltage of a first USB port and a power voltage at a power voltage terminal, a first buck circuit is operated, the first buck circuit comprising a first switch connected between the power voltage terminal and the first USB port, wherein: in response to the first target voltage being less than the power supply voltage plus an offset voltage, operating the first buck circuit in a variable buck input mode to control the first switch according to a first duty cycle based on the first target voltage and the power supply voltage to generate the first target voltage at the first USB port; and In response to the first target voltage being equal to the power supply voltage plus the offset voltage, the first buck circuit is operated in a buck bypass mode to maintain an on state of the first switch to generate the first target voltage at the first USB port.

9. The method according to claim 8, comprising: Based on a second target voltage of a second USB port and the power voltage at the power voltage terminal, a second buck circuit is operated, the second buck circuit comprising a second switch connected between the power voltage terminal and the second USB port, wherein: in response to the second target voltage being less than the power supply voltage plus an offset voltage, operating the second buck circuit in a variable buck input mode to control the second switch according to a second duty cycle based on the second target voltage and the power supply voltage to generate the second target voltage at the second USB port; and In response to the second target voltage being equal to the power supply voltage plus the offset voltage, the second buck circuit is operated in a buck bypass mode to maintain an on state of the second switch to generate the second target voltage at the second USB port.

10. The method according to claim 9, comprising: A flyback converter is configured to generate the supply voltage at the supply voltage terminal based on a greater of the first target voltage and the second target voltage.

11. The method according to claim 8, comprising: A bootstrap circuit is enabled, the bootstrap circuit being connected to a gate input of the first switch to maintain the on state of the first switch in the buck bypass mode.

12. The method according to claim 11, wherein: Enabling the bootstrap circuit includes enabling a charge pump connected to a gate input of the first switch.

13. The method according to claim 8, comprising: A pulse width modulation (PWM) circuit is configured, and the pulse width modulation (PWM) circuit is connected to the gate input terminal of the first switch to switch the first switch according to the first duty cycle in the variable buck input mode and to keep the first switch in the on state in the buck bypass mode.

14. The method of claim 8, wherein: The first step-down circuit includes a second switch connected between the first USB port and ground; and The method includes maintaining an off state of the second switch in the buck bypass mode.

15. The method of claim 8, wherein: The first step-down circuit includes an inductor connected between the first switch and the first USB port; and The method includes configuring the offset voltage based on a voltage drop across the first switch and the inductor.

16. A universal serial bus power transmission USB-PD power adapter, comprising: USB port; a flyback converter operable to receive a first voltage and convert the first voltage into a second voltage; a step-down circuit connected between the flyback converter and the USB port; as well as A USB-PD controller is connected to the flyback converter and is configured to: Receiving a target voltage of the USB port; determining a value of the second voltage of the flyback converter based on a maximum of the target voltages; in response to a target voltage of a first selected buck circuit of the buck circuits being less than the second voltage plus an offset voltage, operating the first selected buck circuit in a variable buck input mode according to a duty cycle based on the target voltage of the first selected buck circuit and the second voltage to generate the target voltage of the first selected buck circuit at a first USB port of the USB ports associated with the first selected buck circuit; as well as In response to a target voltage of a second selected buck circuit among the buck circuits being less than the second voltage plus the offset voltage, operating the second selected buck circuit in a buck bypass mode according to a 100% duty cycle to generate the target voltage of the second selected buck circuit at a second USB port among the USB ports associated with the second selected buck circuit.

17. The USB-PD power adapter according to claim 16, wherein: The first selected step-down circuit includes a switch; and The USB-PD controller is configured to control the switch based on the duty cycle.

18. The USB-PD power adapter according to claim 17, wherein: The USB-PD controller includes: A bootstrap circuit is connected to the gate input terminal of the switch to keep the switch in the on state in the buck bypass mode.

19. The USB-PD power adapter according to claim 17, wherein: The second selected buck circuit includes a second switch; and The USB-PD controller includes a pulse width modulation (PWM) circuit connected to a gate input terminal of the second switch to switch the second switch according to the duty cycle in the variable buck input mode.

20. The USB-PD power adapter according to claim 17, wherein: The USB-PD controller includes: A pulse width modulation (PWM) circuit is connected to the gate input terminal of the switch to keep the switch in the on state in the buck bypass mode.

Images