Amplification circuit and control method thereof

Abstract

The invention discloses an amplifying circuit and a control method thereof. The filter circuit receives the first input signal, the second input signal and the adjusting signal and generates a first amplification signal and a second amplification signal according to the first input signal, the second input signal and the adjusting signal, and the first input signal and the second input signal are differential signals; the PWM circuit receives the first amplified signal and the second amplified signal and generates a first output signal and a second output signal according to the first amplified signal and the second amplified signal, and the first output signal and the second output signal are differential signals; the adjusting circuit is used for receiving the first output signal and the second output signal, generating an adjusting signal according to the first output signal and the second output signal, and representing a common mode value of the first output signal and the second output signal; when the common mode value of the first output signal and the second output signal is larger than a first preset threshold value, the adjusting signal is reduced, and when the common mode value of the first output signal and the second output signal is smaller than a second preset threshold value, the adjusting signal is increased.

Description

Technical Field

[0001] This application relates to the technical field of amplifier circuits, and particularly to an amplifier circuit and a control method thereof. Background Art

[0002] Class-D amplifiers are a type of high-efficiency audio power amplifier that uses Pulsewidth Modulation (PWM) or Pulse Density Modulation (PDM) techniques to drive speakers. Compared with traditional Class-A, Class-B, or Class-AB amplifiers, Class-D amplifiers have higher efficiency and lower heat dissipation requirements, so they are very suitable for portable devices and applications that require high power output. However, for Class-D amplifiers used in in-vehicle systems, due to the strong jitter and ripple of the output power supply voltage in the in-vehicle system, higher requirements are put forward for the Power Supply Rejection Ratio (PSRR) of the Class-D amplifiers in the in-vehicle system.

[0003] For common Class-D amplifiers in the prior art, their PSRR is usually jointly affected by the input resistance, feedback resistance, and the common mode rejection ratio (CMRR) of the loop filter. To improve the power supply rejection ratio, some Class-D amplifiers will increase the area of the input resistance and feedback resistance in the Class-D amplifier to reduce the resistance mismatch, and increase the power consumption of the loop filter and other ways to improve the common mode rejection ratio CMRR. However, this solution requires a large cost for the increased resistance area and the power consumption of the filtering area, which will bring new problems. Summary of the Invention

[0004] This application provides an amplifier circuit and a control method thereof, aiming to solve the problem of low power supply rejection ratio of Class-D amplifiers in the prior art. To achieve the above technical objectives, this application adopts the following technical solutions:

[0005] According to the first aspect of the present application, an embodiment of the present application provides a filtering circuit, which has a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, a third input terminal for receiving an adjustment signal, a first output terminal for providing a first amplified signal, and a second output terminal for providing a second amplified signal. The filtering circuit generates the first amplified signal and the second amplified signal according to the first input signal, the second input signal, and the adjustment signal, wherein the first input signal and the second input signal are differential signals; a PWM circuit, which has a first input terminal for receiving the first amplified signal, a second input terminal for receiving the second amplified signal, a first output terminal for providing a first output signal, and a second output terminal for providing a second output signal. The PWM circuit generates the first output signal and the second output signal according to the first amplified signal and the second amplified signal, wherein the first output signal and the second output signal are differential signals; an adjustment circuit, which has a first input terminal for receiving the first output signal, a second input terminal for receiving the second output signal, and an output terminal for providing an adjustment signal. The adjustment circuit generates the adjustment signal according to the first output signal and the second output signal, and the adjustment signal represents the common-mode value of the first output signal and the second output signal; when the common-mode value of the first output signal and the second output signal is greater than a first preset threshold, the adjustment signal decreases, and when the common-mode value of the first output signal and the second output signal is less than a second preset threshold, the adjustment signal increases.

[0006] According to the second aspect of the present application, an embodiment of the present application further provides a control method for an amplification circuit, which is applicable to the amplification circuit described in any one of the above first aspects, and includes: receiving a first input signal and a second input signal, and generating a first amplified signal and a second amplified signal according to the first input signal, the second input signal, and the adjustment signal, wherein the first input signal and the second input signal are differential signals; receiving the first amplified signal and the second amplified signal, and generating a first output signal and a second output signal according to the first amplified signal and the second amplified signal, wherein the first output signal and the second output signal are differential signals; receiving the first output signal and the second output signal, and generating an adjustment signal according to the first output signal and the second output signal; when the common-mode value of the first output signal and the second output signal is greater than a first preset threshold, the adjustment signal decreases, and when the common-mode value of the first output signal and the second output signal is less than a second preset threshold, the adjustment signal increases.

[0007] Through one or more embodiments in the above embodiments of the present application, at least the following technical effects can be achieved:

[0008] In the embodiment of the present application, the adjustment circuit generates an adjustment signal representing the common-mode value of the first output signal and the second output signal according to the first output signal and the second output signal, and feeds it back to the filtering circuit as a negative feedback adjustment of the output common mode of the amplification circuit. Compared with the amplification circuit without the adjustment circuit, the amplification circuit in the present application reduces the output common-mode interference of the amplification circuit in the prior art (the ripple and jitter of the power supply voltage can be equivalent to the output common-mode interference) by adding the above adjustment circuit, enhances the power supply rejection ratio of the amplification circuit, and has a simple circuit, low cost, and wide application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0010] Figure 1 FIG. 1 shows a schematic structural diagram of an amplification circuit according to an embodiment of the present application;

[0011] Figure 2 FIG. 2 shows a schematic circuit diagram of an amplification circuit according to an embodiment of the present application;

[0012] Figure 3 FIG. 3 shows a schematic circuit diagram of an amplification circuit according to an embodiment of the present application;

[0013] Figure 4 FIG. 4 shows a schematic circuit diagram of a filtering circuit according to an embodiment of the present application;

[0014] Figure 5 FIG. 5 shows a schematic circuit diagram of a PWM circuit according to an embodiment of the present application;

[0015] Figure 6 FIG. 6 shows a signal waveform diagram of a PWM circuit according to an embodiment of the present application;

[0016] Figure 7 FIG. 7 shows a signal waveform diagram of a PWM circuit according to an embodiment of the present application;

[0017] Figure 8 FIG. 8 shows a schematic circuit diagram of a driving circuit according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In the description of the present application, it should be noted that throughout the specification and claims, the term "coupled" is defined as directly or indirectly connecting in an electrical or non-electrical manner. When an element is described as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be one or more intermediate elements. In contrast, when an element is described as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Throughout the specification, references to "one embodiment", "an embodiment", "one example", or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present application. Thus, the phrases "in one embodiment", "in an embodiment", "one example", or "an example" that appear throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the particular features, structures, or characteristics can be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. Like reference numerals indicate like components. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] The typical architecture of a class-D amplifier circuit mainly includes the following modules: an input signal processing module (gain, filtering, etc.); a modulation module (modulating an analog signal into a PWM signal); a power amplification module (driving a load using switching elements); a low-pass filter (smoothing the PWM signal output); and a feedback module (ensuring the accuracy and stability of the output signal). In a class-D amplifier circuit, the Power Supply Rejection Ratio (PSRR) is an important performance indicator. The power supply rejection ratio refers to the ability of the amplifier circuit to suppress power supply noise, reflecting how much power supply noise in the input signal (such as an audio input signal) is transmitted to the output. A high power supply rejection ratio means that the amplifier can effectively suppress the noise or fluctuations in the power supply and reduce the interference of these noises on the output signal. For a class-D amplifier circuit with a typical architecture, its power supply rejection ratio is mainly affected by the jitter or ripple △VBAT of the power supply voltage VBAT. This part can be equivalent to the common-mode noise or non-linearity in the circuit. When the electronic components in the feedback loop are symmetric, it will not affect the power supply rejection ratio PSRR of the class-D amplifier. However, due to the mismatch of the theoretically matched components in the feedback loop in the actual application environment, the jitter of the power supply voltage will be directly amplified by the mismatch. Intuitively, the power supply rejection ratio PSRR is limited by the common-mode rejection ratio CMRR of the input resistance, feedback resistance, and loop filter. If the resistance values of the input resistance and feedback resistance are taken too large to reduce the mismatch, it will affect the noise performance of the feedback path; if the method of increasing the resistance area is used to reduce the mismatch and the unit resistance width of the input resistance and feedback resistance is taken too large, it will affect the area cost of the circuit (the mismatch of the resistance is related to the resistance value and area), and the common-mode rejection ratio CMRR of the loop filter is directly related to the circuit power consumption and cannot be too large either.

[0020] Figure 1The structural schematic diagram of an amplifier circuit according to an embodiment of the present application is given. The amplifier circuit includes a filter circuit 10, a PWM circuit 20, and an adjustment circuit 30. The filter circuit 10 has a first input terminal for receiving a first input signal Vin1, a second input terminal for receiving a second input signal Vin2, a third input terminal for receiving an adjustment signal Vtrcl, a first output terminal for providing a first amplified signal Vs1, and a second output terminal for providing a second amplified signal Vs2. The filter circuit 10 generates the first amplified signal Vs1 and the second amplified signal Vs2 according to the first input signal Vin1, the second input signal Vin2, and the adjustment signal Vtrcl, where the first input signal Vin1 and the second input signal Vin2 are differential signals. The PWM circuit 20 has a first input terminal for receiving the first amplified signal Vs1, a second input terminal for receiving the second amplified signal Vs2, a first output terminal for providing a first output signal Vout1, and a second output terminal for providing a second output signal Vout2. The PWM circuit 20 generates the first output signal Vout1 and the second output signal Vout2 according to the first amplified signal Vs1 and the second amplified signal Vs2, where the first output signal Vout1 and the second output signal Vout2 are differential signals. The adjustment circuit 30 has a first input terminal for receiving the first output signal Vout1, a second input terminal for receiving the second output signal Vout2, and an output terminal for providing the adjustment signal Vtrcl. The adjustment circuit 30 generates the adjustment signal Vtrcl according to the first output signal Vout1 and the second output signal Vout2, and the adjustment signal Vtrcl represents the common-mode value of the first output signal Vout1 and the second output signal Vout2. When the common-mode value of the first output signal Vout1 and the second output signal Vout2 is greater than a first preset threshold, the adjustment signal Vtrcl decreases; when the common-mode value of the first output signal Vout1 and the second output signal Vout2 is less than a second preset threshold, the adjustment signal Vtrcl increases. The first preset threshold and the second preset threshold are determined based on the common-mode value of the first output signal Vout1 and the second output signal Vout2 during the actual application process.

[0021] In the embodiment of the present application, generating the adjustment signal Vtrcl according to the first output signal Vout1 and the second output signal Vout2 and inputting it into the filter circuit 10 realizes the negative feedback adjustment of the output common mode of the amplifier circuit. By adding the above adjustment circuit 30, the output common-mode interference of the amplifier circuit in the prior art is reduced (the ripple and jitter of the power supply voltage can be equivalent to the output common-mode interference), the power supply rejection ratio of the amplifier circuit is enhanced, and the circuit is simple, with low cost and applicable to many scenarios.

[0022] Figure 2The structural schematic diagram of an amplifier circuit according to an embodiment of the present application is given. The adjustment circuit 30 includes a sampling circuit 31 and a first operational amplifier Amp1. The sampling circuit 31 has a first input terminal for receiving a first output signal Vout1, a second input terminal for receiving a second output signal Vout2, and an output terminal for providing a sampling signal Vsam. The sampling circuit 31 generates the sampling signal Vsam according to the first output signal Vout1 and the second output signal Vout2. The first operational amplifier Amp1 has a first input terminal for receiving the sampling signal Vsam, a second input terminal for receiving a common-mode reference signal VCM, and an output terminal for providing an adjustment signal Vtrcl. The first operational amplifier Amp1 generates the adjustment signal Vtrcl according to the sampling signal Vsam and the common-mode reference signal VCM.

[0023] In some embodiments, the voltage value ranges of the first output signal Vout1 and the second output signal Vout2 are between 4.5 - 30V.

[0024] In Figure 2 In the illustrated embodiment, the sampling circuit 31 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end for receiving the first output signal Vout1, and a second end coupled to the first input terminal of the first operational amplifier Amp1 to provide the sampling signal Vsam. The second resistor R2 has a first end for receiving the second output signal Vout2, and a second end coupled to the first input terminal of the first operational amplifier Amp1 to provide the sampling signal Vsam.

[0025] In Figure 2 In the illustrated embodiment, the adjustment circuit 30 further includes a common-mode reference circuit 33 and a first capacitor C1. The common-mode reference circuit 33 has an output terminal for providing the common-mode reference signal VCM. The common-mode reference signal VCM is determined based on the common-mode value of the first output signal Vout1 and the second output signal Vout2. The first end of the first capacitor C1 is coupled to the first input terminal of the first operational amplifier Amp1, and the second end is coupled to the output terminal of the first operational amplifier Amp1. The first capacitor C1 connected across the first output terminal and the output terminal of the first operational amplifier Amp1, together with the first operational amplifier Amp1 and the sampling circuit 31, form a filter H_PSRR(S), which has an inhibitory effect on the common-mode jitter and ripple of the overall amplifier circuit. Its calculation formula is

[0026]

[0027] where, △mismatch is the common-mode ripple caused by the mismatch of the matching elements in the loop, △VBAT is the jitter of the power supply voltage, and H_PSRR(S) is the transfer function of the filter.

[0028] In an embodiment of the present application, the common-mode values of the first output signal Vout1 and the second output signal Vout2 are sampled through the first resistor R1 and the second resistor R2 to generate a sampling signal Vsam. The sampling signal Vsam and the common-mode reference signal VCM generated by the common-mode reference circuit 33 are respectively input to the first input terminal and the second input terminal of the first operational amplifier Amp1. Exemplarily, the first input terminal may be an inverting input terminal, and the second input terminal may be a non-inverting input terminal. The first operational amplifier Amp1 generates an adjustment signal Vtrcl according to the sampling signal Vsam and the common-mode reference signal VCM, and outputs it to the filter circuit 10 to change the first amplified signal Vs1 and the second amplified signal Vs2 and output them to the PMM circuit, thereby feedback-adjusting the values of the first output signal Vout1 and the second output signal Vout2. The magnitude of the common-mode reference signal VCM is determined based on the magnitude of the first preset threshold. For different first preset thresholds, the voltage value of the common-mode reference signal VCM provided by the common-mode reference circuit 33 is also different.

[0029] Figure 3 FIG. shows a schematic structural diagram of an amplification circuit according to an embodiment of the present application. The adjustment circuit 30 includes a voltage division circuit 32, a sampling circuit 31, and a first operational amplifier Amp1. The voltage division circuit 32 has a first input terminal for receiving the first output signal Vout1, a second input terminal for receiving the second output signal Vout2, a first output terminal for providing a third output signal Vout3, a second output terminal for providing a fourth output signal Vout4, a third output terminal coupled to the reference ground, and a fourth output terminal coupled to the reference ground. The voltage division circuit 32 generates the third output signal Vout3 and the fourth output signal Vout4 according to the first output signal Vout1 and the second output signal Vout2. The sampling circuit 31 has a first input terminal for receiving the third output signal Vout3, a second input terminal for receiving the fourth output signal Vout4, and an output terminal for providing a sampling signal Vsam. The sampling circuit 31 generates the sampling signal Vsam according to the third output signal Vout3 and the fourth output signal Vout4. The first operational amplifier Amp1 has a first input terminal for receiving the sampling signal Vsam, a second input terminal for receiving the common-mode reference signal VCM, and an output terminal for providing an adjustment signal Vtrcl. The first operational amplifier Amp1 generates the adjustment signal Vtrcl according to the sampling signal Vsam and the common-mode reference signal VCM.

[0030] In Figure 3In the illustrated embodiment, the sampling circuit 31 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end receiving the third output signal Vout3 and a second end coupled to the first input terminal of the first operational amplifier Amp1 to provide a sampling signal Vsam. The second resistor R2 has a first end receiving the fourth output signal Vout4 and a second end coupled to the first input terminal of the first operational amplifier Amp1 to provide the sampling signal Vsam. The voltage dividing circuit 32 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first transistor M1, and a second transistor M2. The third resistor R3 has a first end and a second end, and the first end receives the first output signal Vout1. The fourth resistor R4 has a first end and a second end, and the first end receives the second output signal Vout2. The first transistor M1 has a first end coupled to the second end of the third resistor R3, a second end receiving an enable signal, and a third end coupled to the first input terminal of the sampling circuit 31 to provide the third output signal Vout3. The second transistor M2 has a first end coupled to the second end of the fourth resistor R4, a second end receiving the enable signal, and a third end coupled to the second input terminal of the sampling circuit 31 to provide the fourth output signal Vout4. The fifth resistor R5 has a first end coupled to the third end of the first transistor M1 and a second end coupled to the reference ground. The sixth resistor R6 has a first end coupled to the third end of the second transistor M2 and a second end coupled to the reference ground.

[0031] In Figure 3 the illustrated embodiment, the adjustment circuit 30 further includes a common-mode reference circuit 33 and a first capacitor C1. The common-mode reference circuit 33 has an output terminal providing a common-mode reference signal VCM, and the common-mode reference signal VCM is determined based on the common-mode value of the first output signal Vout1 and the second output signal Vout2. The first end of the first capacitor C1 is coupled to the first input terminal of the first operational amplifier Amp1, and the second end is coupled to the output terminal of the first operational amplifier Amp1.

[0032] In the embodiment of the present application, since the first output signal Vout1 and the second output signal Vout2 are in a higher voltage domain, the first output signal Vout1 and the second output signal Vout2 are first converted into a third output signal Vout3 and a fourth output signal Vout4 in a lower voltage domain through voltage-dividing resistors. In some embodiments, the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4, and the resistance value of the fifth resistor R5 is equal to the resistance value of the sixth resistor R6. Therefore, the conversion ratio of the voltage-dividing circuit 32 is β = R3 / (R3 + R5), or equal to R4 / (R4 + R6), and the values of the two are equal. The first resistor R1 and the second resistor R2 sample the common-mode values of the third output signal Vout3 and the fourth output signal Vout4 to generate a sampling signal Vsam. The common-mode values of the third output signal Vout3 and the fourth output signal Vout4 are the common-mode values of the first output signal Vout1 and the second output signal Vout2 multiplied by the conversion ratio β. The sampling signal Vsam and the common-mode reference signal VCM generated by the common-mode reference circuit 33 are respectively input to the first input terminal and the second input terminal of the first operational amplifier Amp1. The common-mode reference signal VCM generated by the common-mode reference circuit 33 is input to the first input terminal and the second input terminal of the first operational amplifier Amp1. Exemplarily, the first input terminal can be the inverting input terminal, and the second input terminal can be the non-inverting input terminal. The first operational amplifier Amp1 generates an adjustment signal Vtrcl according to the sampling signal Vsam and the common-mode reference signal VCM, and outputs it to the filtering circuit 10 to change the first amplified signal Vs1 and the second amplified signal Vs2 and output them to the PMM circuit 20, so as to feedback and adjust the values of the first output signal Vout1 and the second output signal Vout2. The magnitude of the common-mode reference signal VCM is the common-mode value of the first output signal Vout1 and the second output signal Vout2 multiplied by a preset proportional threshold. The preset proportional threshold is determined according to the resistance values in the voltage-dividing circuit 32 and the sampling circuit 31. When the preset proportional threshold is different, the voltage value of the common-mode reference signal VCM provided by the common-mode reference circuit 33 is also different. The first transistor M1 and the second transistor M2 are used as a clamping circuit, and their gate terminals both receive the enable signal EN and are automatically turned on after the amplifier circuit is powered on to clamp the voltage at the second ends of the third resistor R3 and the fourth resistor R4 within a preset range.

[0033] Figure 4The circuit structure diagram of the filtering circuit 10 according to an embodiment of the present application is shown. The filtering circuit 10 includes a first filtering circuit 11, a compensation circuit 12, and a second filtering circuit 13. The first filtering circuit 11 has a first input terminal for receiving a first input signal Vin1, a second input terminal for receiving a second input signal Vin2, a first output terminal for providing a third amplified signal Vs3, and a second output terminal for providing a fourth amplified signal Vs4. The first filtering circuit 11 generates the third amplified signal Vs3 and the fourth amplified signal Vs4 according to the first input signal Vin1 and the second input signal Vin2. The compensation circuit 12 has a first input terminal for receiving the third amplified signal Vs3, a second input terminal for receiving the fourth amplified signal Vs4, a first output terminal for providing a fifth amplified signal Vs5, and a second output terminal for providing a sixth amplified signal Vs6. The compensation circuit 12 generates the fifth amplified signal Vs5 and the sixth amplified signal Vs6 according to the third amplified signal Vs3 and the fourth amplified signal Vs4. The second filtering circuit 13 has a first input terminal for receiving the fifth amplified signal Vs5, a second input terminal for receiving the sixth amplified signal Vs6, a first output terminal for providing a first amplified signal Vs1, and a second output terminal for providing a second amplified signal Vs2. The compensation circuit 12 generates the first amplified signal Vs1 and the second amplified signal Vs2 according to the fifth amplified signal Vs5 and the sixth amplified signal Vs6.

[0034] In Figure 4 In the illustrated embodiment, the first filtering circuit 11 includes a second operational amplifier Amp2, a second capacitor C2, and a third capacitor C3. The second operational amplifier Amp2 has a first input terminal for receiving the first input signal Vin2, a second input terminal for receiving the second input signal Vin1, a first output terminal for providing the third amplified signal Vs3, and a second output terminal for providing the fourth amplified signal Vs4. Exemplarily, the first input terminal of the second operational amplifier Amp2 may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal. The second capacitor C2 has a first end coupled to the first input terminal of the second operational amplifier Amp2, and a second end coupled to the first output terminal of the second operational amplifier Amp2. The third capacitor C3 has a first end coupled to the second input terminal of the second operational amplifier Amp2, and a second end coupled to the second output terminal of the second operational amplifier Amp2.

[0035] In Figure 4In the illustrated embodiment, the compensation circuit includes a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, and a fifth capacitor C5. The seventh resistor R7 has a first end receiving a third amplified signal Vs3 and a second end providing a fifth amplified signal Vs5. The fourth capacitor C4 has a first end coupled to the first end of the seventh resistor R7 and a second end coupled to the second end of the seventh resistor R7. The eighth resistor R8 has a first end receiving a fourth amplified signal Vs4 and a second end providing a sixth amplified signal Vs6. The fifth capacitor C5 has a first end coupled to the first end of the eighth resistor R8 and a second end coupled to the second end of the eighth resistor R8.

[0036] In Figure 4 In the illustrated embodiment, the second filter circuit 13 includes a third operational amplifier Amp3, a sixth capacitor C6, and a seventh capacitor C7. The third operational amplifier Amp3 has a first input terminal receiving the fifth amplified signal Vs5, a second input terminal receiving the sixth amplified signal Vs6, a first output terminal providing a first amplified signal Vs1, and a second output terminal providing a second amplified signal Vs2. Exemplarily, the first input terminal of the third operational amplifier Amp2 may be an inverting input terminal, and the second input terminal may be a non-inverting input terminal. The sixth capacitor C6 has a first end coupled to the second input terminal of the third operational amplifier Amp3 and a second end coupled to the first output terminal of the third operational amplifier Amp3. The seventh capacitor C7 has a first end coupled to the first input terminal of the third operational amplifier Amp3 and a second end coupled to the second output terminal of the third operational amplifier Amp3.

[0037] In an embodiment of the present application, the filter circuit 10 is a second-order loop filter for stabilizing the amplifier circuit by controlling the frequency response of the loop and eliminating noise. The first filter circuit 11 is the first-stage fully differential amplifier of the second-order loop filter, the second filter circuit 13 is the second-stage fully differential amplifier of the second-order loop filter, and the compensation circuit 12 serves as the compensation loop of the second-order loop filter to provide a circuit zero for the second-order loop filter. The filter loop of the feedback resistor Rfb1, the second capacitor C2, the seventh resistor R7, and the sixth capacitor C6 determines the circuit poles of the second-order loop filter (similarly for the feedback resistor Rfb2, the third capacitor C3, the eighth resistor R8, and the seventh capacitor C7).

[0038] Figure 5The schematic diagram of the circuit structure of a PWM circuit according to an embodiment of the present application is shown. The PWM circuit 20 includes a PWM modulation circuit 21 and a driving circuit 22. The PWM modulation circuit 21 has a first input terminal for receiving a first amplified signal Vs1, a second input terminal for receiving a second amplified signal Vs2, a first output terminal for providing a first driving signal PWMP, and a second output terminal for providing a second driving signal PWMN. The PWM modulation circuit 21 generates the first driving signal PWMP and the second driving signal PWMN according to the first amplified signal Vs1 and the second amplified signal Vs2. The driving circuit 22 has a first input terminal for receiving the first driving signal PWMP, a second input terminal for receiving the second driving signal PWMN, a first output terminal for providing a first output signal Vout1, and a second output terminal for providing a second output signal Vout2. The driving circuit 22 generates the first output signal Vout1 and the second output signal Vout2 according to the first driving signal PWMP and the second driving signal PWMN. The first driving signal PWMP and the second driving signal PWMN are PWM signals. When the adjustment signal Vtrcl decreases, the duty cycles of the first driving signal PWMP and the second driving signal PWMN decrease. When the adjustment signal Vtrcl increases, the duty cycles of the first driving signal PWMP and the second driving signal PWMN increase.

[0039] In Figure 5 the illustrated embodiment, the PWM modulation circuit 21 includes a first comparator coml and a second comparator com2. The first comparator coml has a first input terminal for receiving the first amplified signal Vs1, a second input terminal for receiving a triangular wave signal Vramp, and an output terminal for providing the first driving signal PWMP. The first comparator coml generates the first driving signal PWMP according to the first amplified signal Vs1 and the triangular wave signal Vramp. Exemplarily, the first input terminal of the first comparator coml is the positive input terminal, and the second input terminal is the negative input terminal. The second comparator com2 has a first input terminal for receiving the second amplified signal Vs2, a second input terminal for receiving the triangular wave signal Vramp, and an output terminal for providing the second driving signal PWMN. The second comparator com2 generates the second driving signal PWMN according to the second amplified signal Vs2 and the triangular wave signal Vramp. Exemplarily, the first input terminal of the second comparator com2 is the positive input terminal, and the second input terminal is the negative input terminal. In some embodiments, the triangular wave signal Vramp is generated by an external reference circuit and is used as a comparison reference signal. The frequency of the triangular wave signal Vramp can be between 384 kHz and 2.1 MHz, and the amplitude is about half of the power supply voltage of the comparator.

[0040] Figure 6 , Figure 7 The signal waveform diagram of the PWM circuit according to an embodiment of the present application is shown. Figure 6 , Figure 7The signal waveforms in two different cases are shown, where Vs_PN1 is the common-mode value of the first amplified signal Vs1 and the second amplified signal Vs2 in the first case, and Vs_PN2 is the common-mode value of the first amplified signal Vs1 and the second amplified signal Vs2 in the second case. PWM_PN1 is the waveform of the first driving signal PWMP and the second driving signal PWMN in the first case (the waveforms of the two are the same), and PWM_PN2 is the waveform of the first driving signal PWMP and the second driving signal PWMN in the second case. Vout_PN1 is the common-mode value of the first output signal Vout1 and the second output signal Vout2 in the first case, and Vout_PN2 is the common-mode value of the first output signal Vout1 and the second output signal Vout2 in the second case.

[0041] When the common-mode value Vs_PN of the first amplified signal Vs1 and the second amplified signal Vs2 is greater than the triangular wave signal Vramp, the first driving signal PWMP and the second driving signal PWMN output by the first comparator com1 and the second comparator com2 are at a high level. When the common-mode value Vs_PN of the first amplified signal Vs1 and the second amplified signal Vs2 is less than the triangular wave signal, the first driving signal PWMP and the second driving signal PWMN output by the first comparator com1 and the second comparator com2 are at a low level. After passing through the driving circuit 22, the common-mode value of the first output signal Vout1 and the second output signal Vout2 is obtained.

[0042] Reference Figure 2 、 3 and Figure 5 In the embodiments shown, when the common-mode value Vs_PN of the first amplified signal Vs1 and the second amplified signal Vs2 output by the filter circuit 10 is equal to the common-mode value of the triangular wave signal Vramp, the first driving signal PWMP output by the first comparator com1 and the second driving signal PWMN output by the second comparator com2 are both PWM signals with a duty cycle of 50%. After being output to the driving circuit 22, the common-mode value of the first output signal Vout1 and the second output signal Vout2 is 1 / 2VBAT. When the common-mode value of the first output signal Vout1 and the second output signal Vout2 is greater than 1 / 2VBAT, the sampling voltage input to the inverting input terminal of the first operational amplifier Amp1 in the adjustment circuit 30 increases, so that the adjustment signal Vtrcl provided by the output terminal of the first operational amplifier Amp1 decreases. After the filter circuit 10 receives this decreased adjustment signal Vtrcl, the common-mode value of the first amplified signal Vs1 and the second amplified signal Vs2 output decreases. The PWM modulation circuit generates the first driving signal PWMP and the second driving signal PWMN with a decreased duty cycle, which are output to the driving circuit 22, so that the common-mode value of the first output signal Vout1 and the second output signal Vout2 decreases, thus playing a role of negative feedback adjustment.

[0043] Figure 8 The circuit structure diagram of the driving circuit 22 according to an embodiment of the present application is shown. The driving circuit 22 includes a logic control circuit 221, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor M4. In Figure 8 the embodiment shown, the first switching transistor M1 to the fourth switching transistor M4 are all N-type field effect transistors. The drain terminal of the first switching transistor M1 is coupled to the power supply voltage VBAT, the source terminal is coupled to the drain terminal of the second switching transistor M2, the source terminal of the second switching transistor M2 is coupled to the reference ground, the gate terminals of the first switching transistor M1 and the second switching transistor M2 are both coupled to the logic control circuit 221. The drain terminal of the third switching transistor M3 is coupled to the power supply voltage VBAT, the source terminal is coupled to the drain terminal of the fourth switching transistor M4, the source terminal of the fourth switching transistor M4 is coupled to the reference ground, and the gate terminals of the third switching transistor M3 and the fourth switching transistor M4 are both coupled to the logic control circuit 221. The full-bridge circuit composed of the first switching transistor M1 to the fourth switching transistor M4 amplifies the signal under the control of the control switching signal generated by the logic control circuit based on the first driving signal PWMP and the second driving signal PWMN, and generates a first output signal Vout1 and a second output signal Vout2 and outputs them to the subsequent load (when the output signal is an audio signal, the load can be a speaker).

[0044] In Figure 2 or Figure 3 the embodiment shown, the amplifier circuit further includes a first feedback resistor Rfb1 and a second feedback resistor Rfb2. The first feedback resistor Rfb1 has a first end coupled to the first input terminal of the filter circuit 10 and a second end coupled to the first output terminal of the PWM circuit 20. The second feedback resistor Rfb2 has a first end coupled to the second input terminal of the filter circuit 10 and a second end coupled to the second output terminal of the PWM circuit 20.

[0045] In Figure 2 or Figure 3 the embodiment shown, the amplifier circuit further includes a first input resistor Rin1 and a second input resistor Rin2. The first input resistor Rin1 has a first end receiving a first external input signal and a second end coupled to the first input terminal of the filter circuit 10 to provide a first input signal Vin1. The second input resistor Rin2 has a first end receiving a second external input signal and a second end coupled to the second input terminal of the filter circuit 10 to provide a second input signal Vin2. Exemplarily, the first external input signal and the second external input signal can be audio analog signals.

[0046] The present application provides a control method for an amplifier circuit, which is applicable to the above amplifier circuit. The control method includes steps 101 to 103.

[0047] Step 101: Receive a first input signal Vin1 and a second input signal Vin2, and generate a first amplified signal Vs1 and a second amplified signal Vs2 according to the first input signal Vin1, the second input signal Vin2, and an adjustment signal Vtrcl, where the first input signal Vin1 and the second input signal Vin2 are differential signals.

[0048] Step 102: Receive the first amplified signal Vs1 and the second amplified signal Vs2, and generate a first output signal Vout1 and a second output signal Vout2 according to the first amplified signal Vs1 and the second amplified signal Vs2, where the first output signal Vout1 and the second output signal Vout2 are differential signals.

[0049] Step 103: Receive the first output signal Vout1 and the second output signal Vout2, and generate an adjustment signal Vtrcl according to the first output signal Vout1 and the second output signal Vout2. When the common-mode value of the first output signal Vout1 and the second output signal Vout2 is greater than a first preset threshold, the adjustment signal Vtrcl decreases; when the common-mode value of the first output signal Vout1 and the second output signal Vout2 is less than a second preset threshold, the adjustment signal Vtrcl increases.

[0050] Although the present application has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present application can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be construed broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An amplifier circuit, comprising: A filter circuit, comprising a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, a third input terminal for receiving an adjustment signal, a first output terminal for providing a first amplified signal, and a second output terminal for providing a second amplified signal, wherein the filter circuit generates a first amplified signal and a second amplified signal according to the first input signal, the second input signal and the adjustment signal, wherein the first input signal and the second input signal are differential signals; A PWM circuit, comprising a first input terminal for receiving a first amplified signal, a second input terminal for receiving a second amplified signal, a first output terminal for providing a first output signal, and a second output terminal for providing a second output signal, wherein the PWM circuit generates a first output signal and a second output signal according to the first amplified signal and the second amplified signal, wherein the first output signal and the second output signal are differential signals; A regulating circuit, comprising a first input terminal for receiving a first output signal, a second input terminal for receiving a second output signal, and an output terminal for providing a regulating signal, wherein the regulating circuit generates a regulating signal according to the first output signal and the second output signal, and the regulating signal represents a common mode value of the first output signal and the second output signal; When the common mode value of the first output signal and the second output signal is greater than a first preset threshold, the adjustment signal decreases; when the common mode value of the first output signal and the second output signal is less than a second preset threshold, the adjustment signal increases.

2. The amplifier circuit according to claim 1, characterized in that: The regulating circuit comprises: A sampling circuit having a first input terminal for receiving a first output signal, a second input terminal for receiving a second output signal, and an output terminal for providing a sampling signal, wherein the sampling circuit generates the sampling signal according to the first output signal and the second output signal; The first operational amplifier has a first input terminal for receiving a sampling signal, a second input terminal for receiving a common-mode reference signal, and an output terminal for providing an adjustment signal. The first operational amplifier generates the adjustment signal according to the sampling signal and the common-mode reference signal.

3. The amplifier circuit according to claim 1, characterized in that: The voltage values ​​of the first output signal and the second output signal range from 4.5V to 30V.

4. The amplifier circuit according to claim 2, characterized in that: The sampling circuit comprises: A first resistor having a first end for receiving a first output signal and a second end coupled to a first input end of the first operational amplifier to provide a sampling signal; The second resistor has a first end for receiving the second output signal and a second end coupled to the first input end of the first operational amplifier to provide a sampling signal.

5. The amplifier circuit according to claim 1, characterized in that: The regulating circuit also includes: A voltage divider circuit has a first input terminal for receiving a first output signal, a second input terminal for receiving a second output signal, a first output terminal for providing a third output signal, a second output terminal for providing a fourth output signal, the third output terminal is coupled to a reference ground, and the fourth output terminal is coupled to a reference ground, and the voltage divider circuit generates a third output signal and a fourth output signal according to the first output signal and the second output signal; A sampling circuit, having a first input terminal for receiving a third output signal, a second input terminal for receiving a fourth output signal, and an output terminal for providing a sampling signal, wherein the sampling circuit generates the sampling signal according to the third output signal and the fourth output signal; The first operational amplifier has a first input terminal for receiving a sampling signal, a second input terminal for receiving a common-mode reference signal, and an output terminal for providing an adjustment signal. The first operational amplifier generates the adjustment signal according to the sampling signal and the common-mode reference signal.

6. The amplifier circuit according to claim 5, characterized in that: The sampling circuit comprises: A first resistor having a first end for receiving the third output signal and a second end coupled to the first input end of the first operational amplifier to provide a sampling signal; The second resistor has a first end for receiving the fourth output signal and a second end coupled to the first input end of the first operational amplifier to provide a sampling signal.

7. The amplifier circuit according to claim 5, characterized in that: The voltage divider circuit comprises: A third resistor has a first end and a second end, wherein the first end receives the first output signal; a fourth resistor having a first end and a second end, wherein the first end receives the second output signal; A first transistor having a first terminal coupled to the second terminal of the third resistor, a second terminal receiving an enable signal, and a third terminal coupled to the first input terminal of the sampling circuit to provide a third output signal; A second transistor having a first end coupled to the second end of the fourth resistor, a second end receiving an enable signal, and a third end coupled to the second input end of the sampling circuit to provide a fourth output signal; a fifth resistor having a first end coupled to the third end of the first transistor and a second end coupled to the reference ground; The sixth resistor has a first end coupled to the third end of the second transistor and a second end coupled to the reference ground.

8. The amplifier circuit according to claim 2 or 5, characterized in that: The regulation circuit further includes a common mode reference circuit having an output terminal for providing a common mode reference signal, wherein the common mode reference signal is determined based on a common mode value of the first output signal and the second output signal.

9. The amplifier circuit according to claim 2 or 5, characterized in that: The regulating circuit further includes a first capacitor, wherein a first end of the first capacitor is coupled to a first input end of the first operational amplifier, and a second end of the first capacitor is coupled to an output end of the first operational amplifier.

10. The amplifier circuit according to claim 1, characterized in that: The filtering circuit comprises: a first filter circuit, having a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, a first output terminal for providing a third amplified signal, and a second output terminal for providing a fourth amplified signal, wherein the first filter circuit generates the third amplified signal and the fourth amplified signal according to the first input signal and the second input signal; a compensation circuit, comprising a first input terminal receiving a third amplified signal, a second input terminal receiving a fourth amplified signal, a first output terminal providing a fifth amplified signal, and a second output terminal providing a sixth amplified signal, wherein the compensation circuit generates the fifth amplified signal and the sixth amplified signal according to the third amplified signal and the fourth amplified signal; The second filtering circuit has a first input end for receiving the fifth amplified signal, a second input end for receiving the sixth amplified signal, a first output end for providing the first amplified signal, and a second output end for providing the second amplified signal. The second filtering circuit generates the first amplified signal and the second amplified signal according to the fifth amplified signal and the sixth amplified signal.

11. The amplifier circuit according to claim 10, characterized in that: The first filtering circuit comprises: A second operational amplifier having a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, a first output terminal for providing a third amplified signal, and a second output terminal for providing a fourth amplified signal; A second capacitor having a first end coupled to the first input end of the second operational amplifier and a second end coupled to the first output end of the second operational amplifier; The third capacitor has a first end coupled to the second input end of the second operational amplifier and a second end coupled to the second output end of the second operational amplifier.

12. The amplifier circuit according to claim 10, characterized in that: The compensation circuit comprises: a seventh resistor, having a first end for receiving the third amplified signal and a second end for providing a fifth amplified signal; a fourth capacitor having a first end coupled to the first end of the seventh resistor and a second end coupled to the second end of the seventh resistor; an eighth resistor, having a first end receiving the fourth amplified signal and a second end providing a sixth amplified signal; The fifth capacitor has a first end coupled to the first end of the eighth resistor and a second end coupled to the second end of the eighth resistor.

13. The amplifier circuit according to claim 10, characterized in that: The second filtering circuit comprises: a third operational amplifier having a first input terminal for receiving the fifth amplified signal, a second input terminal for receiving the sixth amplified signal, a first output terminal for providing the first amplified signal, and a second output terminal for providing the second amplified signal; a sixth capacitor having a first end coupled to the second input end of the third operational amplifier and a second end coupled to the first output end of the third operational amplifier; The seventh capacitor has a first terminal coupled to the first input terminal of the third operational amplifier, and a second terminal coupled to the second output terminal of the third operational amplifier.

14. The amplifier circuit according to claim 1, characterized in that: The PWM circuit comprises: A PWM modulation circuit, comprising a first input terminal for receiving a first amplified signal, a second input terminal for receiving a second amplified signal, a first output terminal for providing a first drive signal, and a second output terminal for providing a second drive signal, wherein the PWM modulation circuit generates a first drive signal and a second drive signal according to the first amplified signal and the second amplified signal; The driving circuit has a first input terminal for receiving a first driving signal, a second input terminal for receiving a second driving signal, a first output terminal for providing a first output signal, and a second output terminal for providing a second output signal. The driving circuit generates a first output signal and a second output signal according to the first driving signal and the second driving signal.

15. The amplifier circuit according to claim 14, characterized in that: The first drive signal and the second drive signal are PWM signals. When the adjustment signal decreases, the duty cycle of the first drive signal and the second drive signal decreases. When the adjustment signal increases, the duty cycle of the first drive signal and the second drive signal increases.

16. The amplifier circuit according to claim 14, characterized in that: The PWM modulation circuit comprises: A first comparator, having a first input terminal for receiving a first amplified signal, a second input terminal for receiving a triangular wave signal, and an output terminal for providing a first drive signal, wherein the first comparator generates a first drive signal according to the first amplified signal and the triangular wave signal, wherein the triangular wave signal is generated by an external reference circuit and is used as a comparison reference signal; The second comparator has a first input terminal receiving the second amplified signal, a second input terminal receiving the triangular wave signal, and an output terminal providing a second drive signal. The second comparator generates a second drive signal according to the second amplified signal and the triangular wave signal.

17. The amplifier circuit according to claim 16, characterized in that: The frequency of the triangle wave signal is between 384 kHz and 2.1 MHz.

18. The amplifier circuit according to claim 1, characterized in that: The amplifying circuit further comprises: A first feedback resistor having a first end coupled to the first input end of the filter circuit and a second end coupled to the first output end of the PWM circuit; The second feedback resistor has a first end coupled to the second input end of the filter circuit and a second end coupled to the second output end of the PWM circuit.

19. The amplifier circuit according to claim 1, characterized in that: The amplifying circuit further comprises: A first input resistor having a first end for receiving a first external input signal and a second end coupled to the first input end of the filter circuit to provide the first input signal; The second input resistor has a first end for receiving a second external input signal and a second end coupled to the second input end of the filter circuit to provide a second input signal.

20. A control method for an amplifier circuit, applicable to the amplifier circuit according to any one of claims 1 to 19, characterized in that: include: receiving a first input signal and a second input signal, and generating a first amplified signal and a second amplified signal according to the first input signal, the second input signal and the adjustment signal, wherein the first input signal and the second input signal are differential signals; receiving a first amplified signal and a second amplified signal, and generating a first output signal and a second output signal according to the first amplified signal and the second amplified signal, wherein the first output signal and the second output signal are differential signals; receiving a first output signal and a second output signal, and generating an adjustment signal according to the first output signal and the second output signal; When the common mode value of the first output signal and the second output signal is greater than a first preset threshold, the adjustment signal decreases; when the common mode value of the first output signal and the second output signal is less than a second preset threshold, the adjustment signal increases.

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