Power amplification circuit with mode conversion, power amplifier and design method thereof

Abstract

The invention discloses a power amplification circuit with a mode conversion function, a power amplifier and a design method of the power amplifier. The power amplification circuit with the mode conversion function comprises a main power amplifier input matching network; the auxiliary power amplifier is input into the matching network; the input end of the power divider is connected with the radio frequency input; the delay line is connected with the power divider and the auxiliary power amplifier input matching network; the grid electrode of the main transistor is connected with the output end of the main power amplifier input matching network; the grid electrode of the auxiliary transistor is connected with the output end of the auxiliary power amplifier input matching network; a main path output matching network; the first bonding wire is connected with the drain electrode of the main transistor and the main path output matching network; and the second bonding wire is connected with the drain electrode of the auxiliary transistor and the output end of the radio frequency output and main path output matching network. According to the power amplification circuit with the mode conversion function, under any phase shift of the main path output matching network, higher bandwidth can be achieved, and high rollback efficiency can be kept.

Description

Technical Field

[0001] The present invention relates to the technical field of microwave power amplifiers, and in particular, to a power amplification circuit with mode conversion, a power amplifier, and a design method thereof. Background Art

[0002] In recent years, a new broadband back-off efficiency enhancement technology - Switchless Class G amplifier has been developed, which provides enhanced back-off efficiency and bandwidth simultaneously. This technology adopts a dual-path power amplifier architecture, in which two transistors are biased at different drain voltages. In the high-efficiency region, the main transistor in the low DC bias state will be affected by the high-biased auxiliary transistor, and then its operating state will gradually enter the third quadrant from the first quadrant. This two-quadrant impedance modulation can not only eliminate the bandwidth limitation caused by the traditional impedance inversion, but also realize the soft switching of the power source, avoiding problems such as gain discontinuity and poor linearity caused by the hard switching of the traditional switched Class G amplifier.

[0003] Although the existing SLCG (Switchless Class G) technology can provide high back-off efficiency in a broadband range up to four octaves, in the traditional SLCG circuit, a complete main amplifier main path output matching network and an auxiliary amplifier main path output matching network are required to achieve the operation in the SLCG mode over the entire frequency band. One disadvantage of this circuit is that due to the existence of the matching elements in the auxiliary branch, a certain phase shift will be generated in the auxiliary branch. And since the matching network of the auxiliary branch is a frequency-dependent element, the greater the frequency deviation from the center frequency point, the greater the impact. Specifically, it is reflected as the increase in the drain node voltage of the auxiliary transistor at the back-off point, further causing the auxiliary transistor to reach saturation prematurely at the edge frequency points, thus reducing the performance at the edge frequency points.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the object of the present invention is to provide a power amplification circuit with mode conversion, a power amplifier, and a design method thereof, so as to solve the problem that in the existing SLCG circuit, the drain node voltage of the auxiliary transistor at the back-off point increases, further causing the auxiliary transistor to reach saturation prematurely at the edge frequency points, thus reducing the performance at the edge frequency points.

[0006] The technical solution adopted by the present invention to solve its technical problems is: to provide a power amplification circuit with mode conversion, including:

[0007] A main amplifier input matching network;

[0008] An auxiliary amplifier input matching network;

[0009] A power splitter for distributing the power of an input radio frequency signal, with the input end of the power splitter connected to a radio frequency input;

[0010] A delay line, with one end of the delay line connected to the output end of the power splitter and the other end of the delay line connected to the input end of the auxiliary power amplifier input matching network;

[0011] A main transistor with parasitic parameters, with the gate of the main transistor connected to the output end of the main power amplifier input matching network;

[0012] An auxiliary transistor with parasitic parameters, with the gate of the auxiliary transistor connected to the output end of the auxiliary power amplifier input matching network;

[0013] A main path output matching network for impedance transformation and absorbing the parasitic parameters of the main transistor;

[0014] A first bonding wire for absorbing the parasitic parameters of the main transistor, with one end of the first bonding wire connected to the drain of the main transistor and the other end of the first bonding wire connected to the main path output matching network;

[0015] A second bonding wire for absorbing the parasitic parameters of the auxiliary transistor, with one end of the second bonding wire connected to the drain of the auxiliary transistor and the other end of the second bonding wire connected to the radio frequency output and the output end of the main path output matching network.

[0016] A further setting of the present invention, the main path output matching network includes: a first series transmission line, a first parallel short - circuit line, a second series transmission line, a first series capacitor;

[0017] One end of the first series transmission line is connected to the other end of the first bonding wire, and the other end of the first series transmission line is connected to one end of the first series capacitor and the first parallel short - circuit line;

[0018] The other end of the first parallel short - circuit line is grounded;

[0019] One end of the second series transmission line is connected to the first series capacitor, and the other end of the second series transmission line is connected to the other end of the second bonding wire and the radio frequency output.

[0020] A further setting of the present invention further includes: an output matching adjustment resistor, with one end of the output matching adjustment resistor connected to the output end of the main path output matching network and the other end of the second bonding wire, and the other end of the output matching adjustment resistor is grounded.

[0021] A further arrangement of the present invention is that the power divider is used to equally distribute the input radio frequency signal.

[0022] A further arrangement of the present invention is that the power divider equally distributes power within the frequency range of radio frequency signals from 0.6 GHz to 3.6 GHz.

[0023] A further arrangement of the present invention is that the power divider is an equal - division Wilkinson power divider.

[0024] A further arrangement of the present invention is that the parasitic parameters of the main transistor include an output first parasitic capacitance.

[0025] A further arrangement of the present invention is that the parasitic parameters of the auxiliary transistor include an output second parasitic capacitance.

[0026] The present invention also provides a power amplifier, including: a dielectric substrate and the power amplification circuit with mode conversion as described above, and the power amplification circuit with mode conversion is integrated on the dielectric substrate.

[0027] The present invention also provides a design method for the power amplification circuit with mode conversion as described above. The design method includes:

[0028] Extracting the parasitic parameters of the main transistor and the parasitic parameters of the first bonding wire;

[0029] Determining the optimal impedance of the main transistor;

[0030] Based on the parasitic parameters of the main transistor, the parasitic parameters of the first bonding wire, and the main - path output matching network, a composite matching network is formed, and based on the composite matching network, a transmission line with a characteristic impedance equal to the optimal impedance of the main transistor and an electrical length of θ is equivalent;

[0031] Calculating the A parameter of the composite matching network based on the electrical length of the transmission line;

[0032] Calculating the B parameter of the composite matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor;

[0033] Calculating the C parameter of the composite matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor;

[0034] Calculating the D parameter of the composite matching network based on the electrical length of the transmission line;

[0035] Based on the A parameter, the B parameter, the C parameter, and the D parameter, the output matching network is equivalent through a band - pass matching network, and by adjusting the electrical length of the transmission line and the parameters of the capacitor in the band - pass matching network, the absorption of the parasitic parameters of the main transistor and impedance transformation are achieved.

[0036] Determine the gate voltage ratio of the main transistor and the auxiliary transistor;

[0037] Determine the main power amplifier input matching network and the auxiliary power amplifier input matching network according to the gate voltage ratio of the main transistor and the auxiliary transistor.

[0038] The beneficial effects of the present invention:

[0039] The power amplifier circuit with mode conversion not only has the ability to absorb parasitic parameters, but also only retains the main path output matching network in the SLCG circuit structure, without the auxiliary output matching network, avoiding the performance degradation at the edge frequency points caused by the phase shift of the auxiliary path. At the same time, the parasitic parameters of the main transistor, the parasitic parameters of the first bonding wire, and the main path output matching network are equivalent to a transmission line with a characteristic impedance of RoptM and an electrical length of θ. When the phase shift of the main path output matching network is 0°, the operating mode of the power amplifier circuit with mode conversion is the SLCG mode. When the phase shift of the main path output matching network is 90°, the power amplifier circuit with mode conversion corresponds to the operating mode of the Doherty amplifier. When the phase shift of the main path output matching network gradually transitions from 0° to 90°, the power amplifier circuit with mode conversion can gradually transition from the SLCG mode to the Doherty mode, and the delay line can keep the connection position between the main path output matching network and the second bonding wire in phase, enabling the power amplifier circuit with mode conversion to maintain the optimal output power. Therefore, it can be seen that the power amplifier circuit with mode conversion can not only achieve a higher bandwidth but also maintain a high back-off efficiency under any phase shift of the main power amplifier input matching network. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0041] Figure 1 It is the structure diagram of the power amplifier circuit with mode conversion of the present invention.

[0042] Figure 2 It is the equivalent circuit structure diagram of the power amplifier circuit with mode conversion of the present invention.

[0043] Figure 3 It is the circuit diagram of the main path output matching network in an embodiment of the present invention.

[0044] Figure 4It is the test result of the output power and efficiency of the power amplifier circuit with mode conversion of the present invention varying with frequency in the range of 0.6 - 3.6 GHz.

[0045] Figure 5 It is the flowchart of the design method of the power amplifier circuit with mode conversion of the present invention.

[0046] Figure 6 It is the circuit structure diagram based on which the voltage ratio of the gate voltage of the main transistor to the gate voltage of the auxiliary transistor is calculated.

[0047] Marks in the attached drawings: 100, power splitter; 200, delay line; 300, main power amplifier input matching network; 400, auxiliary power amplifier input matching network; 500, output matching network; M1, main transistor; M2, auxiliary transistor; T1, first bonding wire; T2, second bonding wire; TL M1 , first series transmission line; TL M2 , first parallel short - circuit line; TL M3 , second series transmission line; C m , first series capacitor; R L , output matching adjustment resistor; C outM , first parasitic capacitor; C outA , second parasitic capacitor. Detailed implementation manners

[0048] For a clearer understanding of the technical features, objectives and effects of the present invention, the detailed implementation manners of the present invention are now described with reference to the attached drawings. In the following description, it should be understood that the orientation or positional relationships indicated by "front", "rear", "upper", "lower", "left", "right", "longitudinal", "transverse", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail", etc. are based on the orientation or positional relationships shown in the attached drawings, and are constructed and operated in a specific orientation. This is only for the convenience of describing the technical solution, rather than indicating that the indicated devices or elements must have a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0049] The demand for high-speed data transmission in the new generation of wireless communication systems has gradually evolved into the pursuit of higher spectral efficiency and wider transmission bandwidths. This trend requires that base station communication circuits be able to support the transmission of broadband modulation signals with high peak-to-average power ratios. This poses more stringent requirements for the efficiency and operating bandwidth of the core device in the RF system - the power amplifier. On the one hand, the base station power amplifier needs to maintain high efficiency even at a large power back-off; on the other hand, it needs to transmit broadband modulation signals in multiple different frequency bands. In addition, the emergence of new mobile communication base stations, such as base station systems based on drones, may need to adapt to different regions, different frequency bands, and different communication standards. Therefore, power amplifier technologies that support improved back-off efficiency and have ultra-wideband operation are receiving extensive attention.

[0050] Currently, the Doherty technology is one of the most common techniques for enhancing back-off efficiency. Traditional Doherty power amplifiers use a 1 / 4 wavelength transmission line to combine two sub-power amplifiers, with a narrow bandwidth. In recent years, researchers have proposed a variety of new techniques to expand the bandwidth of Doherty power amplifiers. However, due to the bandwidth limitation of the impedance reflector itself, there is still a trade-off between the back-off efficiency and the operating bandwidth of Doherty power amplifiers, and it is difficult to maintain high back-off efficiency simultaneously within a bandwidth range exceeding an octave. To overcome this limitation, some new impedance modulation techniques have emerged successively. These techniques reduce the dependence on impedance inversion while improving the back-off efficiency by introducing more complex combining network structures and multiple sub-power amplifiers, thereby providing a wider frequency response. However, these techniques have increased the circuit complexity, which in turn has led to more complex trade-offs for the power amplifier in terms of cost, volume, and performance.

[0051] In recent years, a new broadband back-off efficiency enhancement technology - switched-less class-G amplifier (SLCG) has been developed, providing enhanced back-off efficiency and bandwidth simultaneously. This technology adopts a dual-path power amplifier architecture, in which two transistors are biased at different drain voltages. In the high-efficiency region, the main transistor in a low DC bias state will be affected by the auxiliary transistor with a high bias, and then its operating state will gradually enter the third quadrant from the first quadrant. This two-quadrant impedance modulation can not only eliminate the bandwidth limitation caused by the traditional impedance inversion, but also achieve the soft switching of the power source, avoiding problems such as discontinuous gain and poor linearity caused by the hard switching of the traditional switched class-G amplifier. Although the existing SLCG technology can provide a high back-off efficiency in a broadband range up to four octaves, the further expansion of its bandwidth still faces the following challenges. First, the SLCG technology requires the main and auxiliary transistors to have exactly equal drain AC voltages. However, when the frequency increases, this requirement is difficult to achieve due to the phase change caused by parasitic parameters such as the connecting wire inductance. Second, although the existing SLCG technology can roughly maintain the voltage amplitude consistency of the main and auxiliary transistors by adding an external matching network to absorb the parasitic parameters of the transistors, the phase shift caused by the auxiliary matching element will cause the voltage of the auxiliary transistor to continuously increase when the frequency deviates from the center frequency, and lead to the decrease of the saturated output power at the edge frequency.

[0052] To address the above technical problems, the present invention provides a power amplifier circuit with mode conversion. As Figure 1 shown, the power amplifier circuit with mode conversion may include a main power amplifier input matching network 300, an auxiliary power amplifier input matching network 400, a delay line 200, a power splitter 100, a main transistor M1 with parasitic parameters, an auxiliary transistor M2 with parasitic parameters, a main path output matching network 500, a first bonding wire T1, and a second bonding wire T2.

[0053] Among them, the main power amplifier input matching network 300 is used for impedance matching between the output end of the power splitter 100 and the gate of the main transistor M1; the auxiliary power amplifier input matching network 400 is used for impedance matching between the output end of the power splitter 100 and the gate of the auxiliary transistor M2; the power splitter 100 is used for power distribution of the input radio frequency signal, and the input end of the power splitter 100 is connected to the radio frequency input ( Figure 1The RFIN) connection in; One end of the delay line 200 is connected to the output end of the power splitter 100, and the other end of the delay line 200 is connected to the input end of the auxiliary power amplifier input matching network 400; The gate of the main transistor M1 is connected to the output end of the main power amplifier input matching network 300; The gate of the auxiliary transistor M2 is connected to the output end of the auxiliary power amplifier input matching network 400; The main path output matching network 500 is used for impedance transformation and absorbing the parasitic parameters of the main transistor M1; The first bonding wire T1 is used for absorbing the parasitic parameters of the main transistor M1. One end of the first bonding wire T1 is connected to the drain of the main transistor M1, and the other end of the first bonding wire T1 is connected to the main path output matching network 500; The second bonding wire T2 is used for absorbing the parasitic parameters of the auxiliary transistor M2. One end of the second bonding wire T2 is connected to the drain of the auxiliary transistor M2, and the other end of the second bonding wire T2 is connected to the radio frequency output ( Figure 1 in the RFOUT) and the output end of the main path output matching network 500.

[0054] Specifically, the main transistor M1 is packaged with a first parasitic capacitance C outM , and the first parasitic capacitance C outM is packaged in parallel in the main transistor M1. The parasitic parameters of the main transistor M1 include the output first parasitic capacitance C outM . The auxiliary transistor M2 is packaged with a second parasitic capacitance C outA , and the second parasitic capacitance C outA is packaged in parallel in the auxiliary transistor M2. The parasitic parameters of the auxiliary transistor M2 include the output second parasitic capacitance C outA . The main power amplifier input matching network 300, the main transistor M1, the first bonding wire T1, and the main path output matching network 500 form the main power amplifier branch; The delay line 200, the auxiliary power amplifier input matching network 400, the auxiliary transistor M2, and the second bonding wire T2 form the auxiliary power amplifier branch. It can be seen that compared with the traditional SLCG circuit, the power amplification circuit with mode conversion saves the auxiliary path output matching network 500 in the auxiliary power amplifier branch and minimizes the phase shift influence of the auxiliary power amplifier branch.

[0055] The delay line 200 adopts a low-pass - band-pass hybrid circuit structure and is arranged in the auxiliary power amplifier branch to achieve broadband phase synchronization at the synthesis point between the main path of the main power amplifier and the auxiliary power amplifier branch. Among them, the position of the synthesis point is the connection end of the second bonding wire T2 and the output end of the main path output matching network 500.

[0056] The first parasitic capacitance C outM , the second parasitic capacitance C outAThe first bonding wire T1 and the second bonding wire T2 are all low-pass elements. The main output matching network 500 is a bandpass circuit network to absorb the parasitic parameters of the main transistor M1 and realize the mode conversion of the power amplifier circuit with mode conversion at different frequency points.

[0057] like Figure 2 As shown, the parasitic parameters of the main transistor M1, the parasitic inductance L of the first bonding line T1 band The main output matching network 500 is equivalent to a characteristic impedance of R optM , a transmission line with an electrical length of θ, where R optM The electrical length θ is the optimal impedance of the main transistor M1 and reflects the phase shift of the main output matching network 500 . θ will change with the frequency.

[0058] Specifically, when the phase shift of the main output matching network 500 is 0°, the working mode of the power amplifier circuit with mode conversion is the SLCG mode, which is equivalent to the direct coupling of the drain nodes of the main transistor M1 and the auxiliary transistor M2. Based on the theory of the SLCG circuit, it can be known that at high power, the main transistor M1 will gradually enter the third quadrant, at which time it can be equivalent to an impedance, and the main output power of the circuit at high power is provided by the auxiliary transistor M2; and at the center frequency of the frequency offset, the phase shift of the main output matching network 500 will increase from 0°. In the process of the phase shift gradually changing from 0° to 90°, the main transistor M1 will gradually leave the working mode of the third quadrant at high power, and provide the output power of the overall circuit together with the auxiliary transistor M2. At this time, the working mode of the power amplifier circuit with mode conversion is a Doherty-SLCG hybrid mode; when the phase shift is 90°, the power amplifier circuit with mode conversion corresponds to the working mode of the Doherty amplifier, and can achieve the same performance as the Doherty amplifier, that is, high back-off efficiency.

[0059] It should be noted that the power amplifier circuit with mode conversion is at low power (before the back-off point), and the auxiliary amplification branch is not turned on. Therefore, the working mode of the power amplifier circuit with mode conversion is equivalent to a single main transistor M1 working at each frequency point. At this time, the drain of the main transistor M1 must see the optimal impedance, that is, the power amplifier circuit with mode conversion works under the optimal conditions.

[0060] In this embodiment, the power amplifier circuit with mode conversion not only has the ability to absorb parasitic parameters, but also only retains the main path output matching network 500 in the SLCG circuit structure, eliminating the need for the auxiliary output matching network 500, thus avoiding the performance degradation at the edge frequency points caused by the phase shift of the auxiliary path. At the same time, the parasitic parameters of the main transistor M1, the parasitic parameters of the first bonding wire T1, and the main path output matching network 500 are equivalent to a transmission line with a characteristic impedance of RoptM and an electrical length of θ. When the phase shift of the main path output matching network 500 is 0°, the working mode of the power amplifier circuit with mode conversion is the SLCG mode. When the phase shift of the main path output matching network 500 is 90°, the power amplifier circuit with mode conversion corresponds to the working mode of the Doherty amplifier (DPA mode). When the phase shift of the main path output matching network 500 gradually transitions from 0° to 90°, the power amplifier circuit with mode conversion can gradually transition from the SLCG mode to the Doherty mode, and the delay line 200 can keep the connection position between the main path output matching network 500 and the second bonding wire T2 in phase, enabling the power amplifier circuit with mode conversion to maintain the optimal output power. Therefore, it can be seen that the power amplifier circuit with mode conversion can not only achieve a higher bandwidth but also maintain a high back-off efficiency under any phase shift of the main power amplifier input matching network 300.

[0061] In some embodiments, as Figure 1 shown, the power amplifier circuit with mode conversion further includes an output matching adjustment resistor R L , where one end of the output matching adjustment resistor R L is connected to the output end of the main path output matching network 500 and the other end of the second bonding wire T2, and the other end of the output matching adjustment resistor R L is grounded.

[0062] Specifically, the output matching adjustment resistor R L is an adjustable resistor. By designing the output matching adjustment resistor R L , the degree of freedom of the power amplifier circuit with mode conversion is improved to achieve impedance matching of the entire power amplifier circuit with mode conversion, enabling the main transistor M1 and the auxiliary transistor M2 to operate at the optimal impedance and thus achieving the optimal performance.

[0063] In some embodiments, as Figure 3 shown, the main path output matching network 500 may include a first series transmission line T LM1 , a first parallel short - circuit line T LM2 , a second series transmission line T LM3 , and a first series capacitor C m ; where the first series transmission line T LM1One end thereof is connected to the other end of the first bonding wire T1, and the first series transmission line T LM1 The other end of is connected to the first series capacitor C m And the first parallel short - circuit wire T LM2 One end of is connected; the other end of the first parallel short - circuit wire T LM2 The other end is grounded; one end of the second series transmission line T LM3 Is connected to the first series capacitor C m The other end of the second series transmission line T LM3 Is connected to the other end of the second bonding wire T2 and the RF output.

[0064] Specifically, when connected, the other end of the second series transmission line T LM3 Is connected to the other end of the second bonding wire T2 and the RF output ( LM3 RFOUT in), and the other end of the second series transmission line T Figure 1 Is also connected to one end of the output matching adjustment resistor R LM3 L L One end of is connected.

[0065] In this embodiment, the first series transmission line T LM1 , the first parallel short - circuit wire T LM2 , the second series transmission line T LM3 And the first series capacitor C m Form a band - pass matching network on the main power amplifier branch to achieve impedance transformation of the main power amplifier branch. Further, the first series transmission line T LM1 , the first parallel short - circuit wire T LM2 , the second series transmission line T LM3 And the first series capacitor C m Are all high - pass elements, so that the output matching network 500 can simultaneously absorb the parasitic parameters of the main transistor M1.

[0066] In some embodiments, the power divider 100 performs equal - power distribution on the input RF signal.

[0067] Specifically, the power divider 100 performs equal - power distribution within the frequency range of RF signals from 0.6 - 3.6 GHz. Among them, the power divider 100 can be, but is not limited to, an equal - division Wilkinson power divider.

[0068] In order to verify the superiority of the power amplifier circuit with mode conversion, a test experiment was conducted on the power amplifier circuit with mode conversion, and the test results are as Figure 4As shown, specifically, during the test experiment, continuous wave testing is used for large signal testing. During the testing process, the drain voltage of the main transistor M1 is set to 13.5V, the drain voltage of the auxiliary transistor M2 is set to 28V, the gate voltage of the main transistor M1 is set to -2.9V, and the drain voltage of the auxiliary transistor M2 is set to -4.7V, so as to keep the corresponding drain static bias current at 32mA. From Figure 4 it can be found that in the range of 0.6 - 3.6 GHz, the power amplifier circuit with mode conversion can provide a low power gain of 7.79 to 13.77 dB, a saturated output power of 38.7 - 40.1 dBm, and maintain a saturated drain efficiency of 43.4 - 69.3%, a 6 dB back-off efficiency of 42.7 - 60.5%, and a 7.5 dB back-off efficiency of 40 - 57%.

[0069] In some embodiments, the present invention also provides a power amplifier, which includes a dielectric substrate and the power amplifier circuit with mode conversion as described above, and the power amplifier circuit with mode conversion is integrated on the dielectric substrate.

[0070] Specifically, the dielectric substrate can be a commercially available dielectric substrate with the model of RO5880. The power amplifier circuit with mode conversion is integrated on this dielectric substrate, and the area of the power amplifier made of this dielectric substrate is 10.7×5.8 square centimeters.

[0071] In some embodiments, as Figure 5 shown, the present invention also provides a design method for the power amplifier circuit with mode conversion as described above. The design method includes the steps:

[0072] S1. Extract the parasitic parameters of the main transistor and the parasitic parameters of the first bonding wire;

[0073] S2. Determine the optimal impedance of the main transistor;

[0074] S3. Based on the parasitic parameters of the main transistor, the parasitic parameters of the first bonding wire, and the main path output matching network, form a composite matching network, and based on the composite matching network, equivalent a transmission line with a characteristic impedance of the optimal impedance of the main transistor and an electrical length of θ;

[0075] S4. Calculate the A parameters of the composite matching network based on the electrical length of the transmission line;

[0076] S5. Calculate the B parameters of the composite matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor;

[0077] S6. Calculate the C parameters of the composite matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor;

[0078] S7. Calculate the D parameters of the synthetic matching network based on the electrical length of the transmission line;

[0079] S8. Equivalent the output matching network through the band-pass matching network based on the A parameters, B parameters, C parameters, and D parameters, and adjust the electrical length of the transmission line and the parameters of the capacitor in the band-pass matching network to absorb the parasitic parameters of the main transistor and perform impedance transformation;

[0080] S9. Determine the gate voltage ratio of the main transistor and the auxiliary transistor;

[0081] S10. Determine the input matching network of the main power amplifier and the input matching network of the auxiliary power amplifier according to the gate voltage ratio of the main transistor and the auxiliary transistor.

[0082] Specifically, simulation can be performed through the simulation software on the computer terminal to extract the parasitic parameters of the main transistor and the parasitic parameters of the first bonding wire. Among them, the parasitic parameters of the main transistor are the output first parasitic capacitance, and the first bonding wire outputs the parasitic inductance L band .

[0083] After determining the parasitic parameters of the main transistor and the parasitic parameters of the first bonding wire, determine the optimal impedance of the main transistor through load-pull. Among them, the load refers to the impedance seen by the drain node of the main transistor.

[0084] It should be noted that load-pull is a commonly used method in power amplifier design to find the optimal impedance of the transistor. Specifically, in an ideal situation, the circuit performance that can be obtained with different loads (impedances) can be simulated through the simulation software on the computer terminal to determine the load corresponding to the best output power and efficiency that the transistor can provide.

[0085] Furthermore, determine the characteristics of the main path output matching network through the phase shift θ of the main power amplifier branch. Specifically, combine the parasitic parameters of the main transistor (the main transistor outputs the first parasitic capacitance), the parasitic parameters of the first bonding wire (the first bonding wire outputs the parasitic inductance L band ) and the main path output matching network to form a synthetic matching network. According to this synthetic matching network, a transmission line with a characteristic impedance equal to the optimal impedance of the main transistor and an electrical length of θ is equivalent. At different frequency points, the transmission line will generate different phase shifts on the main power amplifier branch. Based on this characteristic, the A parameters, B parameters, C parameters, and D parameters of the synthetic matching network can be calculated. The A parameters, B parameters, C parameters, and D parameters are expressed as:

[0086]

[0087] Among them, A m is the A parameter, B m is the B parameter, C mis the C parameter, D m is the D parameter, R optM is the optimal impedance of the main transistor, and θ is the electrical length of the transmission line.

[0088] After the A parameter, B parameter, C parameter, and D parameter are calculated and determined, the main path output matching network is equivalent through the band-pass matching network. By adjusting the electrical length of the transmission line and the parameters of the capacitor in the band-pass matching network, the parasitic parameters of the main transistor are absorbed and impedance transformation is achieved, so that the combined matching network composed of the parasitic parameters of the main transistor, the parasitic parameters of the first bonding wire, and the main path output matching network in the power amplifier circuit with mode conversion is equivalent to the above A parameter, B parameter, C parameter, and D parameter.

[0089] Further, after the main path output matching network is equivalent through the band-pass matching network, the voltage ratio of the gates of the main transistor and the auxiliary transistor is determined. Specifically, as Figure 6 shown, the designed main path output matching network is applied to the Figure 6 output terminal in. The voltage of the drain of the main transistor is set to 13.5V, the voltage of the drain of the auxiliary transistor is set to 28V, the voltage configured for the gate of the main transistor is -3V, and the corresponding drain static current is 30mA. In the Figure 6 setting of the input terminal in, the self-using power of the two power sources ( Figure 6 P in inm and P ina ) are set to be equal to facilitate the implementation of the broadband power divider. Among them, Z SM is the source impedance of the main power amplifier branch, Z SA is the source impedance of the auxiliary power amplifier branch. The initial values of the source impedance of the main power amplifier branch and the source impedance of the auxiliary power amplifier branch can be obtained through the simulation of a broadband input matching network; subsequently, the source impedance of the main power amplifier branch, the source impedance of the auxiliary power amplifier branch, the phase difference θ Δ of the power source, and the gate bias voltage of the auxiliary transistor are adjusted to obtain the optimal large-signal performance that conforms to the theoretical characteristics in the range of 0.6 - 3.6GHz; finally, record the fundamental wave gate voltage ratio (the ratio of the gate voltage of the main transistor to the gate voltage of the auxiliary transistor, that is, V GA in the figure) that generates the optimal large-signal performance when V gsm / V gsa ) with V GA fixed at -4.4V. After the ratio of the gate voltage of the main transistor to the gate voltage of the auxiliary transistor is determined, the main power amplifier input matching network and the auxiliary power amplifier input matching network are designed, so as to achieve the corresponding drain current characteristics and enable the power amplifier circuit with mode conversion to switch from the SLCG mode to the Doherty mode (when the phase shift of the main path output matching network is from 0° - 90°).

[0090] Further, the main path output matching network may include a first series transmission line, a first parallel short - circuit line, a second series transmission line, and a first series capacitor; wherein, one end of the first series transmission line is connected to the other end of the first bonding wire, and the other end of the first series transmission line is connected to one end of the first series capacitor and the first parallel short - circuit line; the other end of the first parallel short - circuit line is grounded; one end of the second series transmission line is connected to the first series capacitor, and the other end of the second series transmission line is connected to the other end of the second bonding wire and the RF output.

[0091] In this embodiment, by adjusting the values of the first series transmission line, the first parallel short - circuit line, the second series transmission line, and the first series capacitor, the A - parameter, B - parameter, C - parameter, and D - parameter required for the theoretical synthesis matching network are achieved. Among them, when adjusting the values of the first series transmission line, the first parallel short - circuit line, the second series transmission line, and the first series capacitor, it can be carried out in the simulation software of the computer terminal.

[0092] Further, the power amplifier circuit with mode conversion further includes an output matching adjustment resistor, wherein one end of the output matching adjustment resistor is connected to the output end of the main path output matching network and the other end of the second bonding wire, and the other end of the output matching adjustment resistor is grounded.

[0093] When the output matching adjustment resistor is specifically applied, fine - tuning is required. Specifically, the output matching adjustment resistor is determined by the following calculation formula:

[0094]

[0095] wherein, Z in is the impedance seen from the drain of the main transistor; in the ideal state, the impedance of R L is equal to the optimal impedance of the main transistor; R opt represents the optimal impedance of the main transistor; θ is the electrical length of the transmission line.

[0096] In the ideal state, the impedance of Z in is equal to the optimal impedance of the main transistor. At this time, the power amplifier circuit with mode conversion can achieve the best performance. However, since the main path output matching network, the parasitic parameters of the main transistor, and the first bonding wire need to be equivalent to a transmission line with a characteristic impedance equal to the optimal impedance of the main transistor, and under broadband conditions, this equivalence is not necessarily completely consistent. Therefore, when setting the impedance of R L to be equal to the optimal impedance of the main transistor, the impedance of Z in is not necessarily equal to the optimal impedance of the main transistor. Therefore, it is necessary to fine - tune the value of the output matching adjustment resistor to achieve the required impedance conversion.

[0097] In some embodiments, the main path output matching network may include a first series transmission line, a first parallel short circuit line, a second series transmission line, and a first series capacitor; wherein, one end of the first series transmission line is connected to the other end of the first bonding wire, and the other end of the first series transmission line is connected to one end of the first series capacitor and the first parallel short circuit line; the other end of the first parallel short circuit line is grounded; one end of the second series transmission line is connected to the first series capacitor, and the other end of the second series transmission line is connected to the other end of the second bonding wire and the RF output.

[0098] Specifically, when the second series line is connected, the other end of the second series line is connected to the other end of the second bonding wire and the RF output terminal, and the other end of the second series line is also connected to one end of the output matching adjustment resistor.

[0099] In this embodiment, the first series transmission line, the first parallel short circuit line, the second series transmission line, and the first series capacitor form a band-pass matching network on the main power amplifier branch to achieve impedance transformation of the main power amplifier branch. Further, the first series transmission line, the first parallel short circuit line, the second series transmission line, and the first series capacitor are all high-pass elements, so that the output matching network can also absorb the parasitic parameters of the main transistor.

[0100] In summary, the present invention provides a power amplification circuit with mode conversion, a power amplifier, and a design method thereof, having the following beneficial effects:

[0101] The power amplification circuit with mode conversion not only has the ability to absorb parasitic parameters, but also only retains the main path output matching network in the SLCG circuit structure, without the auxiliary output matching network, avoiding the performance degradation at the edge frequency points caused by the phase shift of the auxiliary path. At the same time, the parasitic parameters of the main transistor, the parasitic parameters of the first bonding wire, and the main path output matching network are equivalent to a transmission line with a characteristic impedance of R optM , an electrical length of θ. When the phase shift of the main path output matching network is 0°, the working mode of the power amplification circuit with mode conversion is the SLCG mode. When the phase shift of the main path output matching network is 90°, the power amplification circuit with mode conversion corresponds to the working mode of the Doherty amplifier. When the phase shift of the main path output matching network gradually transitions from 0° to 90°, the power amplification circuit with mode conversion can gradually transition from the SLCG mode to the Doherty mode, and the delay line can keep the connection position of the main path output matching network and the second bonding wire in phase, so that the power amplification circuit with mode conversion maintains the optimal output power. Therefore, it can be seen that the power amplification circuit with mode conversion can not only achieve a higher bandwidth, but also maintain a high back-off efficiency under any phase shift of the main power amplifier input matching network.

[0102] It can be understood that the above embodiments only represent the preferred embodiments of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can also be made, which all fall within the protection scope of the present invention. Therefore, all equivalent transformations and modifications made to the scope of the claims of the present invention shall fall within the scope covered by the claims of the present invention.

Claims

1. A power amplifier circuit with mode conversion, characterized in that: include: Main amplifier input matching network; Auxiliary amplifier input matching network; A power divider, used for distributing power of the incoming radio frequency signal, wherein the input end of the power divider is connected to the radio frequency input; A delay line, one end of which is connected to the output end of the power divider, and the other end of which is connected to the input end of the auxiliary power amplifier input matching network; A main transistor having parasitic parameters, wherein a gate of the main transistor is connected to an output end of an input matching network of the main power amplifier; An auxiliary transistor having parasitic parameters, wherein a gate of the auxiliary transistor is connected to an output end of the auxiliary power amplifier input matching network; A main output matching network, used for impedance transformation and absorbing parasitic parameters of the main transistor; A first bonding line, used for absorbing parasitic parameters of the main transistor, one end of the first bonding line is connected to the drain of the main transistor, and the other end of the first bonding line is connected to the main output matching network; The second bonding line is used to absorb the parasitic parameters of the auxiliary transistor. One end of the second bonding line is connected to the drain of the auxiliary transistor, and the other end of the second bonding line is connected to the RF output and the output end of the main output matching network.

2. The power amplifier circuit with mode conversion according to claim 1, characterized in that: The main output matching network includes: a first series transmission line, a first parallel short-circuit line, a second series transmission line, and a first series capacitor; One end of the first series transmission line is connected to the other end of the first bonding line, and the other end of the first series transmission line is connected to the first series capacitor and one end of the first parallel short-circuit line; The other end of the first parallel short-circuit line is grounded; One end of the second series transmission line is connected to the first series capacitor, and the other end of the second series transmission line is connected to the other end of the second bonding line and the RF output.

3. The power amplifier circuit with mode conversion according to claim 1, characterized in that: Also includes: An output matching adjustment resistor, one end of which is connected to the output end of the main output matching network and the other end of the second bonding line, and the other end of which is grounded.

4. The power amplifier circuit with mode conversion according to claim 1, characterized in that: The power divider is used to distribute the received radio frequency signals with equal power.

5. The power amplifier circuit with mode conversion according to claim 4, characterized in that: The power divider performs equal power distribution within the frequency range of the radio frequency signal of 0.6-3.6 GHz.

6. The power amplifier circuit with mode conversion according to claim 5, characterized in that: The power divider is an equal-division Wilkinson power divider.

7. The power amplifier circuit with mode conversion according to claim 1, characterized in that: The parasitic parameters of the main transistor include an output first parasitic capacitance.

8. The power amplifier circuit with mode conversion according to claim 1, characterized in that: The parasitic parameters of the auxiliary transistor include an output second parasitic capacitance.

9. A power amplifier, characterized in that: include: A dielectric board and a power amplifier circuit with mode conversion as claimed in any one of claims 1 to 7, wherein the power amplifier circuit with mode conversion is integrated on the dielectric board.

10. A design method for a power amplifier circuit with mode conversion according to any one of claims 1 to 8, characterized in that: The design method comprises: Extracting parasitic parameters of the main transistor and parasitic parameters of the first bonding line; Determine the optimum impedance of the main transistor; A synthetic matching network is formed based on the parasitic parameters of the main transistor, the parasitic parameters of the first bonding line and the main output matching network, and a transmission line having a characteristic impedance equal to the optimal impedance of the main transistor and an electrical length of θ is equivalent to the synthetic matching network; Calculating an A parameter of the synthetic matching network based on the electrical length of the transmission line; Calculating a B parameter of the synthetic matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor; Calculating a C parameter of the synthetic matching network based on the electrical length of the transmission line and the optimal impedance of the main transistor; Calculating a D parameter of the synthetic matching network based on the electrical length of the transmission line; Based on the A parameter, the B parameter, the C parameter and the D parameter, the output matching network is equivalent through a bandpass matching network, and the electrical length of the transmission line and the parameters of the capacitance in the bandpass matching network are adjusted to achieve absorption of the parasitic parameters of the main transistor and impedance transformation; determining a gate voltage ratio of the main transistor and the auxiliary transistor; The main power amplifier input matching network and the auxiliary power amplifier input matching network are determined according to the gate voltage ratio of the main transistor and the auxiliary transistor.

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