Class-D amplifier capable of preventing wave chopping

Abstract

The invention discloses a D-type amplifier capable of preventing wave chopping. The class D amplifier generates an output signal with pulse width modulation based on a DC voltage according to an input signal in a normal mode, and comprises: a first-stage integrating circuit for integrating a difference between the input signal and a feedback signal in the normal mode to generate a first integrated signal; the final-stage integrating circuit is used for generating a final-stage integrating signal according to the first integrating signal in a normal mode; the superposition circuit is used for buffering the last-stage integral signal to generate a loop filtering signal in a normal mode; and the modulation and driving circuit is used for generating an output signal according to the comparison of the loop filtering signal and the triangular wave. In the chopping mode, the first-stage integrating circuit enters a reset or maintenance state, the last-stage integrating circuit enters a maintenance state, and the superposition circuit is used for superposing the last-stage integrating signal and the feed-forward signal to generate a loop filtering signal.

Description

Technical Field

[0001] The present invention relates to a class D amplifier, and particularly to a class D amplifier capable of preventing clipping. Background Art

[0002] Prior cases related to the present application are: "Data processing system for clipping correction" (US8081022B2), "Pulse-width modulation amplifier and suppression of clipping therefor" (US7315202B2), "Amplifier apparatus" (US7088177B2).

[0003] Figure 1 The block diagram of a prior art class D amplifier is shown. As Figure 1 shown, in a prior art class D amplifier 900, an integration circuit 180 includes a first integration circuit 181 and a second integration circuit 182. The first integration circuit 181 integrates the difference between an input signal and a feedback signal to generate a first integration signal, where the input signal includes a positive input signal Vip and a negative input signal Vin, the feedback signal includes a negative feedback signal Sfbn and a positive feedback signal Sfbp, and the first integration signal includes a negative first integration signal S8in and a positive first integration signal S8ip. The second integration circuit 182 integrates the first integration signal S8in to generate a second integration signal, where the second integration signal includes a negative second integration signal S8ifn and a positive second integration signal S8ifp. A modulation and drive circuit 1062 performs, for example, pulse-width modulation on the second integration signal (negative second integration signal S8ifn and positive second integration signal S8ifp), thereby controlling a plurality of switches in the modulation and drive circuit 1062 to generate a positive output signal Vop and a negative output signal Von having pulse-width modulation characteristics. The above positive output signal Vop and negative output signal Von respectively pass through a feedback circuit 1041 and a feedback circuit 1042 to respectively generate a negative feedback signal Sfbn and a positive feedback signal Sfbp.

[0004] The disadvantage of the above prior art is that when the amplitude of the input signal of the class D amplifier is too large, it will cause the sine wave of the integration signal generated by at least one integration circuit in the integration circuit 180 to be clipped and saturated, thereby causing noise or unpleasant popping in the output signal (such as the above positive output signal Vop and negative output signal Von) of the class D amplifier.

[0005] In view of the above, the present invention aims at the deficiencies of the above-mentioned prior art and provides a class-D amplifier that can prevent clipping. Through the operations of resetting and / or maintaining the state of the integration circuit and the operation of the feedforward architecture, the class-D amplifier can prevent the generation of clipping as in the above-mentioned prior art, making the output signal (such as sound) of the class-D amplifier closer to the ideal and avoiding the generation of popping sounds. Summary of the Invention

[0006] In one aspect, the present invention provides a class-D amplifier for generating an output signal with pulse-width modulation based on a DC voltage according to an input signal in a normal mode, comprising: a primary integration circuit for integrating the difference between the input signal and a feedback signal to generate a first integration signal in the normal mode, wherein the feedback signal is related to the output signal; a final integration circuit for integrating and generating a final integration signal according to the first integration signal in the normal mode; a superimposing circuit for buffering the final integration signal to generate a loop filter signal in the normal mode; and a modulation and driving circuit for generating the output signal according to the comparison between the loop filter signal and a triangular wave; wherein in a clipping mode, the primary integration circuit enters a reset state or a maintaining state, the final integration circuit enters a maintaining state, and the superimposing circuit is used to superimpose the final integration signal and a feedforward signal to generate the loop filter signal; wherein the feedforward signal is related to the input signal.

[0007] In a preferred embodiment, the class-D amplifier further comprises at least one intermediate integration circuit for generating a corresponding at least one intermediate integration signal according to the first integration signal, wherein the final integration circuit is used to integrate and generate the final integration signal according to the intermediate integration signal in the normal mode; wherein in the clipping mode, the intermediate integration circuit enters a reset state or a maintaining state.

[0008] In a preferred embodiment, the class-D amplifier further comprises a feedforward switch for conducting in the clipping mode to electrically connect the feedforward signal to the superimposing circuit, and for turning off the electrical connection between the feedforward signal and the superimposing circuit in the normal mode.

[0009] In a preferred embodiment, in the normal mode, the superimposing circuit is further used to superimpose the final integration signal and the feedforward signal to generate the loop filter signal.

[0010] In a preferred embodiment, the class-D amplifier further comprises a clipping detection circuit for judging whether the input signal will cause clipping according to the final integration signal, the loop filter signal or the output signal, and for generating a clipping control signal to control the class-D amplifier to enter the clipping mode when it is judged that the input signal will cause clipping.

[0011] In a preferred embodiment, the first-stage integration circuit and / or the last-stage integration circuit includes: an amplifier, an integration capacitor, and at least one state control switch, wherein the integration capacitor and the amplifier are coupled to each other for performing corresponding integration operations; wherein one of the at least one state control switch is connected in parallel with the integration capacitor and is turned on in the chopping mode to reset the integration capacitor to enter the corresponding reset state; and / or wherein one of the at least one state control switch is connected in series before an input terminal of the amplifier and is turned off in the chopping mode to open the signal received by the input terminal, thereby maintaining the state of the integration capacitor to enter the corresponding holding state.

[0012] In a preferred embodiment, each of the first-stage integration circuit, the intermediate integration circuit, and the last-stage integration circuit includes: a digital integration circuit for performing corresponding integration operations, wherein each of the input signal, the feedback signal, the feedforward signal, the last-stage integration signal, and the loop filter signal is a digital signal.

[0013] In a preferred embodiment, the class D amplifier further includes a digital enable circuit for enabling the superposition of the feedforward signal and the last-stage integration signal in the chopping mode and prohibiting the superposition of the feedforward signal and the last-stage integration signal in the normal mode.

[0014] The following is a detailed description through specific embodiments to more easily understand the object, technical content, features, and achieved effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Displays a block diagram of a prior art class D amplifier.

[0016] Figure 2 Displays a block diagram of an embodiment of the class D amplifier of the present invention.

[0017] Figure 3 Displays a block diagram of an embodiment of the class D amplifier of the present invention.

[0018] Figure 4 Displays a block diagram of an embodiment of the class D amplifier of the present invention.

[0019] Figure 5 Displays a schematic diagram of a specific embodiment of the class D amplifier of the present invention.

[0020] Figure 6 Displays a schematic diagram of a specific embodiment of the integration circuit with a reset state in the class D amplifier of the present invention.

[0021] Figure 7Schematic diagram of a specific embodiment of an integrating circuit with a holding state in the Class D amplifier of the present invention.

[0022] Figure 8 Schematic diagram of a specific embodiment of an integrating circuit with a reset state and / or a holding state in the Class D amplifier of the present invention.

[0023] Figure 9 Schematic diagram of a specific embodiment of the Class D amplifier of the present invention.

[0024] Figure 10 Schematic diagram of an embodiment of an intermediate integrating circuit in the Class D amplifier of the present invention.

[0025] Figure 11 Schematic diagram of a specific embodiment of a modulation and drive circuit in the Class D amplifier of the present invention.

[0026] Figure 12 Operating waveform diagram of an embodiment of a prior art Class D amplifier compared to the Class D amplifier of the present invention.

[0027] Figure 13 Schematic diagram of another specific embodiment of the Class D amplifier of the present invention.

[0028] Symbol description in the figure

[0029] 101, 101’, 1011, 1012, 1013: Loop filter circuit

[0030] 102, 1021, 1022: Multistage integrating circuit

[0031] 103, 103’: Feedforward path

[0032] 1031, 1032, 1033: Integrating circuit

[0033] 104: Feedback circuit

[0034] 104’: Buffer

[0035] 1041, 1042: Feedback circuit

[0036] 105, 105a, 105b: Clipping detection circuit

[0037] 106, 1062, 121: Modulation and drive circuit

[0038] 107: Feedforward switch

[0039] 107n: Negative terminal feedforward switch

[0040] 107p: Positive terminal feedforward switch

[0041] 107D: AND gate

[0042] 108, 109: Buffer

[0043] 11: Amplifier

[0044] 111, 1111: Summing circuit

[0045] 12, 13: Feedback network

[0046] 1211: Full-bridge power stage circuit

[0047] 180: Integrating circuit

[0048] 181: First integrating circuit

[0049] 182: Second integrating circuit

[0050] 2002, 2003, 2004, 2005, 2009, 2013: Class-D amplifier

[0051] 201: Amplifier

[0052] 21: First-stage integrating circuit

[0053] 211: Positive input terminal

[0054] 212: Negative input terminal

[0055] 213: Negative output terminal

[0056] 214: Positive output terminal

[0057] 22, 2M, 2n: Intermediate-stage integrating circuit

[0058] 2F: Final-stage integrating circuit

[0059] 401~408: Waveform

[0060] 90: Load

[0061] 900: Class-D amplifier

[0062] Cip, Cin: Integrating capacitor

[0063] QHp, QHn: Upper-bridge switch

[0064] QLp, QLn: Lower-bridge switch

[0065] S8ifn: Negative second integration signal

[0066] S8ifp: Positive second integration signal

[0067] S8in: Negative first integration signal

[0068] S8ip: Positive first integration signal

[0069] Sclpi, Sclpia, Sclpib: Carrier cut-off detection signal

[0070] Sclpo, Sclpoa, Sclpob: Carrier cut-off control signal

[0071] Sfbn: Negative feedback signal

[0072] Sfbp: Positive feedback signal

[0073] Sfb: Feedback signal

[0074] Sff: Feedforward signal

[0075] Sffn: Negative feedforward signal

[0076] Sffp: Positive feedforward signal

[0077] Shp, Shn: State control switch

[0078] Si1n: First negative integration signal

[0079] Si1p: First positive integration signal

[0080] Sif: Final-stage integration signal

[0081] Sifn: Final-stage negative integration signal

[0082] Sifp: Final-stage positive integration signal

[0083] Simn: Negative intermediate-stage integration signal

[0084] Simp: Positive intermediate-stage integration signal

[0085] Sin: Negative input integration signal

[0086] Sip: Positive input integration signal

[0087] Slf: Loop filter signal

[0088] Slfn: Negative loop filter signal

[0089] Slfp: Positive loop filter signal

[0090] Son: Negative output integration signal

[0091] Sop: Positive output integration signal

[0092] Spwp: Positive modulation signal

[0093] Spwn: Negative modulation signal

[0094] Srp, Srn: Status control switches

[0095] VDD: DC high-level voltage

[0096] Vi: Input signal

[0097] Vin: Negative input signal

[0098] Vip: Positive input signal

[0099] Vo: Output signal

[0100] Von: Negative output signal

[0101] Vop: Positive output signal

[0102] Vpp: DC voltage

[0103] VSS: DC low-level voltage

[0104] Vtri: Triangular wave Detailed implementation manners

[0105] The drawings in the present invention are all schematic, mainly intended to show the coupling relationship between each circuit and the relationship between each signal waveform. As for the circuits, signal waveforms and frequencies, they are not drawn according to scale.

[0106] Figure 2 Show a block diagram of an embodiment of the class D amplifier of the present invention. In one embodiment, as Figure 2 shown, the class D amplifier 2002 is used to generate an output signal Vo with pulse width modulation based on the input signal Vi according to the DC voltage Vpp in the normal mode. The output signal Vo is used to drive a load 90, where the load 90 can be, for example but not limited to, a speaker or a linear resonant actuator (LRA). In one embodiment, the class D amplifier 2002 includes: a loop filter circuit 101 and a modulation and drive circuit 106. The loop filter circuit 101 is used to generate a loop filter signal Slf according to the input signal Vi and the output signal Vo. The modulation and drive circuit 106 is used to control the switches in the modulation and drive circuit 106 according to the comparison between the loop filter signal Slf and the triangular wave Vtri, and convert the DC voltage Vpp to generate an output signal Vo with pulse width modulation. Details about the switches in the modulation and drive circuit 106 and the DC voltage Vpp will be described in detail later.

[0107] In one embodiment, the loop filter circuit 101 includes: a multi-stage integration circuit 102, a feedback circuit 104, and a superposition circuit 111. In one embodiment, in a normal mode, the multi-stage integration circuit 102 is used to integrate the difference between the input signal Vi and the feedback signal Sfb to generate a final-stage integration signal Sif, and the superposition circuit 111 is used to buffer the final-stage integration signal Sif to generate a loop filter signal Slf. In one embodiment, in a clipping mode, the multi-stage integration circuit 102 enters a reset state or a hold state, and the superposition circuit 111 is used to superimpose the final-stage integration signal Sif and the feedforward signal Sff to generate a loop filter signal Slf, thereby keeping the final-stage integration signal Sif, the loop filter signal Slf, and the output signal Vo within a linear bias range to avoid clipping noise in the output signal Vo. In one embodiment, the feedback circuit 104 generates a feedback signal Sfb according to the output signal Vo. In one embodiment, the feedforward signal Sff is related to the input signal Vi. In one embodiment, the input signal Vi generates the feedforward signal Sff via a feedforward path 103. In other words, the input signal Vi is the feedforward signal Sff.

[0108] In one embodiment, as Figure 2 shown, the class-D amplifier 2002 further includes a clipping detection circuit 105. In one embodiment, the clipping detection circuit 105 is used to determine whether the input signal Vi will cause clipping of the integration signal or the output signal Vo according to the signal on any node in the signal path, and when it is determined that the input signal Vi will cause clipping, a clipping control signal Sclpo is generated to control the class-D amplifier 2002 to enter the clipping mode. In this embodiment, the clipping detection circuit 105 is used to determine whether the input signal Vi will cause clipping according to the clipping detection signal Sclpi, and when it is determined that the input signal Vi will cause clipping, a clipping control signal Sclpo is generated to control the class-D amplifier 2002 to enter the clipping mode. In this embodiment, the clipping detection signal Sclpi is, for example, related to the final-stage integration signal Sif, the loop filter signal Slf, or the output signal Vo in the signal path. It should be noted that the operation details in the above clipping mode will be described in detail later.

[0109] Figure 3 Showing a block diagram of an embodiment of the class-D amplifier of the present invention. Figure 3 The class-D amplifier 2003 is similar to Figure 2 the class-D amplifier 2002, the difference being that in Figure 3In an embodiment, the class D amplifier 2003 further includes a feedforward switch 107. In one embodiment, the feedforward switch 107 is configured to conduct in the clipping mode to electrically connect the feedforward signal Sff to the summing circuit 111, and in the normal mode, the feedforward switch 107 is configured to turn off the electrical connection between the feedforward signal Sff and the summing circuit 111. In other words, in this embodiment, in the normal mode, the feedforward switch 107 is turned off, thereby disconnecting the electrical connection between the feedforward signal Sff and the summing circuit 111. At this time, the summing circuit 111 is only used to buffer the final-stage integrated signal Sif to generate the loop filter signal Slf. On the other hand, in the clipping mode, the clipping control signal Sclpo controls the feedforward switch 107 to conduct. At this time, the summing circuit 111 is used to add the final-stage integrated signal Sif and the feedforward signal Sff via the feedforward path 103' to generate the loop filter signal Slf.

[0110] It should be noted that, in Figure 2 the embodiment, in the normal mode, the summing circuit 111 is also used to add the final-stage integrated signal Sif and the feedforward signal Sff to generate the loop filter signal Slf. In Figure 3 the embodiment, since the feedforward switch 107 conducts only in the clipping mode, the summing circuit 111 adds the final-stage integrated signal Sif and the feedforward signal Sff to generate the loop filter signal Slf only in the clipping mode. In other words, from one perspective, the class D amplifier of this embodiment does not perform modulation according to the feedforward signal in the normal mode. It should also be noted that the above Figure 2 and Figure 3 embodiments of both have the effect of preventing clipping of the present invention. The following will take the Figure 3 embodiment including the feedforward switch as an example to further illustrate the operation details of the specific embodiment.

[0111] Figure 4 FIG. shows a block diagram of an embodiment of the class D amplifier of the present invention. Figure 4 The class D amplifier 2004 of Figure 3 is similar to the class D amplifier 2003 of Figure 4 . The difference is that, in the embodiment of Figure 4 , the feedback circuit 104 is configured as a buffer 104', and the class D amplifier 2004 further includes a buffer 108 and a buffer 109. In one embodiment, the buffer 104' is used to buffer the output signal Vo to generate the feedback signal Sfb, and the buffers 108 and 109 are used to buffer the input signal Vi.

[0112] Figure 5 FIG. shows a schematic diagram of a specific embodiment of the class D amplifier of the present invention. In one embodiment, at Figure 5In the class D amplifier 2005, the input signal Vi includes a positive input signal Vip and a negative input signal Vin, the output signal Vo includes a positive output signal Vop and a negative output signal Von, and the feedforward switch includes a positive terminal feedforward switch 107p and a negative terminal feedforward switch 107n. In Figure 5 In an embodiment, the feedback circuits in the loop filter circuit 1011 include a feedback circuit 1041 and a feedback circuit 1042, which are respectively used to generate a negative feedback signal Sfbn and a positive feedback signal Sfbp according to the positive output signal Vop and the negative output signal Von. In Figure 5 In an embodiment, the multi-stage integration circuit 1021 includes a first-stage integration circuit 21 and a last-stage integration circuit 2F, and the superposition circuit 1111 includes an amplifier 11, a feedback network 12, and a feedback network 13.

[0113] As Figure 5 shown, in a specific embodiment, in the normal mode, the first-stage integration circuit 21 is used to integrate the difference between the positive input signal Vip and the negative feedback signal Sfbn to generate a first negative integration signal Si1n, and is used to integrate the difference between the negative input signal Vin and the positive feedback signal Sfbp to generate a first positive integration signal Si1p. Then, the last-stage integration circuit 2F is used to integrate according to the first integration signal to generate a last-stage integration signal, where the first integration signal includes the first negative integration signal Si1n and the first positive integration signal Si1p, and the last-stage integration signal includes a last-stage positive integration signal Sifp and a last-stage negative integration signal Sifn. From one perspective, the last-stage integration circuit 2F is used to integrate according to the first negative integration signal Si1n to generate a last-stage negative integration signal Sifn, and is used to integrate according to the first positive integration signal Si1p to generate a last-stage positive integration signal Sifp.

[0114] In this embodiment, in the normal mode, the positive terminal feedforward switch 107p and the negative terminal feedforward switch 107n are both turned off. At this time, the superposition circuit 1111 is used to buffer the last-stage negative integration signal Sifn and the last-stage positive integration signal Sifp to generate a negative loop filter signal Slfn and a positive loop filter signal Slfp. In this embodiment, the modulation and drive circuit 106 is used to generate a positive output signal Vop according to the comparison between the negative loop filter signal Slfn and the triangular wave Vtri, and generate a negative output signal Von according to the comparison between the positive loop filter signal Slfp and the triangular wave Vtri.

[0115] In an embodiment, the modulation and drive circuit may include, for example, a half-bridge or full-bridge power stage circuit. Please also refer to Figure 11 , Figure 11FIG. 0 shows a schematic diagram of a specific embodiment of the modulation and drive circuit in the class D amplifier of the present invention. In this embodiment, the modulation and drive circuit 121 is configured to generate a positive modulation signal Spwp according to the comparison between the positive loop filter signal Slfp and the triangular wave Vtri, and generate a negative modulation signal Spwn according to the comparison between the negative loop filter signal Slfn and the triangular wave Vtri. In addition, in this embodiment, the modulation and drive circuit 121 further includes a full-bridge power stage circuit 1211, which includes an upper-bridge switch QHp, QHn and a lower-bridge switch QLp, QLn. Specifically, these switches in the full-bridge power stage circuit 1211 are configured to switch according to the positive modulation signal Spwp and the negative modulation signal Spwn, so as to convert the DC high-level voltage VDD and the DC low-level voltage VSS into a positive output signal Vop and a negative output signal Von. The aforementioned DC voltage Vpp corresponds to the DC high-level voltage VDD and the DC low-level voltage VSS, for example.

[0116] Please continue to refer to Figure 5 , in an embodiment, in the clipping mode, the first-stage integration circuit 21 enters the reset state or the hold state, and the last-stage integration circuit 2F enters the hold state (detailed later). The clipping control signal Sclpoa controls the positive-terminal feedforward switch 107p and the negative-terminal feedforward switch 107n to conduct. At this time, the summing circuit 1111 is configured to sum the last-stage integration signal and the feedforward signal related to the input signal to generate a loop filter signal, where the feedforward signal includes a positive feedforward signal Sffp and a negative feedforward signal Sffn, and the loop filter signal includes a positive loop filter signal Slfp and a negative loop filter signal Slfn. From one perspective, the summing circuit 1111 is configured to sum the last-stage negative integration signal Sifn and the positive feedforward signal Sffp related to the positive input signal Vip to generate a negative loop filter signal Slfn, and is configured to sum the last-stage positive integration signal Sifp and the negative feedforward signal Sffn related to the negative input signal Vin to generate a positive loop filter signal Slfp.

[0117] Please continue to refer to Figure 5 , in an embodiment, the clipping detection circuit 105a in the class D amplifier 2005 is configured to determine whether the positive input signal Vip or the negative input signal Vin will cause clipping according to the clipping detection signal Sclpia, and generate a clipping control signal Sclpoa when it is determined that the positive input signal Vip or the negative input signal Vin will cause clipping, so as to control the class D amplifier 2005 to enter the clipping mode. In this embodiment, the clipping detection signal Sclpia is related to the first negative integration signal Si1n, the first positive integration signal Si1p, the last-stage negative integration signal Sifn, the last-stage positive integration signal Sifp, the negative loop filter signal Slfn, the positive loop filter signal Slfp, the positive output signal Vop or the negative output signal Von.

[0118] Figure 6 FIG. shows a schematic diagram of a specific embodiment of an integrating circuit with a reset state in the class D amplifier of the present invention. In one embodiment, the integrating circuit of the present invention includes: an amplifier, an integrating capacitor, and a state control switch. In one embodiment, Figure 5 The primary integrating circuit 21 of Figure 6 is configured as the integrating circuit 1031 of Figure 6 As shown, the integrating circuit 1031 includes an amplifier 201, an integrating capacitor Cip, an integrating capacitor Cin, a state control switch Srp, and a state control switch Srn. In one embodiment, the integrating capacitor and the amplifier are coupled to each other for corresponding integration operations. Specifically, in one embodiment, the integrating capacitor Cip is coupled between the positive input terminal and the negative output terminal of the amplifier 201, and the integrating capacitor Cin is coupled between the negative input terminal and the positive output terminal of the amplifier 201. In this embodiment, the state control switch Srp and the state control switch Srn are respectively connected in parallel to the integrating capacitor Cip and the integrating capacitor Cin, and are configured to conduct in the clipping mode to reset the integrating capacitor Cip and / or the integrating capacitor Cin to enter the corresponding reset state.

[0119] Please also refer to Figure 5 and Figure 6 . In a specific embodiment, in the normal mode, the state control switches Srp and Srn are turned off, and the amplifier 201 is configured to integrate the integrating capacitor Cip and the integrating capacitor Cin according to the positive input integration signal Sip and the negative input integration signal Sin respectively to generate a negative output integration signal Son and a positive output integration signal Sop. When the clipping detection circuit 105a determines that the positive input signal Vip or the negative input signal Vin will cause clipping, it enters the clipping mode, and the clipping control signal Sclpoa controls the state control switches Srp and Srn to conduct to reset the integrating capacitor Cip and / or the integrating capacitor Cin, thereby entering the corresponding reset state.

[0120] It should be noted that when the aforementioned Figure 5 The primary integrating circuit 21 of Figure 6When the integrating circuit 1031 is concerned, the positive input integrating signal Sip and the negative input integrating signal Sin respectively correspond to the positive input signal Vip and the negative input signal Vin, the negative output integrating signal Son and the positive output integrating signal Sop respectively correspond to the first negative integrating signal Si1n and the first positive integrating signal Si1p, the positive input terminal and the negative input terminal of the amplifier 201 respectively correspond to the positive input terminal 211 and the negative input terminal 212 of the integrating circuit 1031 (i.e., the first-stage integrating circuit 21), and the negative output terminal and the positive output terminal of the amplifier 201 respectively correspond to the negative output terminal 213 and the positive output terminal 214 of the integrating circuit 1031 (i.e., the first-stage integrating circuit 21).

[0121] It should also be noted that in Figure 6 the embodiment, by resetting the integrating capacitor Cip and / or the integrating capacitor Cin in the chopping mode, when the amplitudes of the input signals (such as the positive input signal Vip and the negative input signal Vin) of the class-D amplifier are too large, the saturation of the sine waves of the negative output integrating signal Son and the positive output integrating signal Sop can be avoided, thereby avoiding the generation of noise or pop sound in the output signals (such as the positive output signal Vop and the negative output signal Von) of the class-D amplifier.

[0122] Figure 7 Shows a schematic diagram of a specific embodiment of the integrating circuit with a holding state in the class-D amplifier of the present invention. In one embodiment, Figure 5 the first-stage integrating circuit 21 and / or the last-stage integrating circuit 2F of Figure 7 is configured as the integrating circuit 1032 of Figure 7 In one embodiment, the difference between the integrating circuit 1032 of Figure 6 and the integrating circuit 1031 of Figure 7 is that the integrating circuit 1032 includes a state control switch Shp and a state control switch Shn. In one embodiment, the state control switch Shp and the state control switch Shn are respectively connected in series before the positive input terminal and the negative input terminal of the amplifier 201, and are used to conduct in the normal mode, so that the integrating capacitors Cip and Cin are integrated, and are used to turn off according to the control of the chopping control signal Sclpoa in the chopping mode, so as to open the signals (such as the positive input integrating signal Sip and the negative input integrating signal Sin) received by the positive input terminal and the negative input terminal of the amplifier 201, thereby maintaining the states of the integrating capacitors Cip and Cin to enter the corresponding holding states. Figure 6 The remaining operation details of the integrating circuit 1032 of

[0123] It should be noted that when the above-mentioned Figure 5 the first-stage integrating circuit 21 is configured as Figure 7When the integrating circuit 1032 is concerned, the positive input integrating signal Sip and the negative input integrating signal Sin respectively correspond to the positive input signal Vip and the negative input signal Vin, and the negative output integrating signal Son and the positive output integrating signal Sop respectively correspond to the first negative integrating signal Si1n and the first positive integrating signal Si1p. The remaining corresponding relationships are similar to Figure 6 , which will not be elaborated here.

[0124] In addition, it should be noted that when the Figure 5 final-stage integrating circuit 2F is configured as Figure 7 the integrating circuit 1032, the positive input integrating signal Sip and the negative input integrating signal Sin respectively correspond to the first negative integrating signal Si1n and the first positive integrating signal Si1p, the negative output integrating signal Son and the positive output integrating signal Sop respectively correspond to the final-stage negative integrating signal Sifn and the final-stage positive integrating signal Sifp. One end of the state control switch Shp and one end of the state control switch Shn respectively correspond to the positive input terminal 211 and the negative input terminal 212 of the integrating circuit 1032 (i.e., the final-stage integrating circuit 2F), and the negative output terminal and the positive output terminal of the amplifier 201 respectively correspond to the negative output terminal 213 and the positive output terminal 214 of the integrating circuit 1032 (i.e., the final-stage integrating circuit 2F).

[0125] Figure 8 The figure shows a schematic diagram of a specific embodiment of the integrating circuit with a reset state and / or a holding state in the class D amplifier of the present invention. In one embodiment, Figure 5 the first-stage integrating circuit 21 and / or the final-stage integrating circuit 2F is configured as Figure 8 the integrating circuit 1033. In one embodiment, as Figure 8 shown, the integrating circuit 1033 includes Figure 6 the state control switch Srp and the state control switch Srn of the embodiment, and includes Figure 7 the state control switch Shp and the state control switch Shn of the embodiment. In this embodiment, when Figure 5 the first-stage integrating circuit 21 is configured as Figure 8 the integrating circuit 1033, in the normal mode, the state control switch Shp and the state control switch Shn are turned on, and the state control switch Srp and the state control switch Srn are turned off to perform mechanical integration on the integrating capacitors Cip and Cin; on the other hand, in the clipping mode, the state control switch Shp and the state control switch Shn become non-conductive, and the state control switch Srp and the state control switch Srn are turned off to enter the corresponding holding state, or, in the clipping mode, the state control switch Srp and the state control switch Srn become conductive, and the state control switch Shp and the state control switch Shn remain conductive to enter the corresponding reset state.

[0126] On the other hand, in this embodiment, when Figure 5 the final-stage integrating circuit 2F of Figure 8 is configured as the integrating circuit 1033 of Figure 8 the remaining operation details of the integrating circuit 1033 of Figure 6 and Figure 7 the embodiments of

[0127] Figure 9 shows a schematic diagram of a specific embodiment of the class-D amplifier of the present invention. Figure 9 The class-D amplifier 2009 of Figure 5 is similar to the class-D amplifier 2005 of Figure 9 The difference is that in the embodiment of

[0128] In Figure 9 the embodiment of Figure 5 the multi-stage integrating circuit 1022 in the loop filter circuit 1012 further includes at least one intermediate integrating circuit 2M for generating at least one corresponding intermediate integration signal according to the first integration signal. Specifically, in this embodiment, at least one intermediate integrating circuit 2M includes an intermediate integrating circuit 22, and the intermediate integrating circuit 22 is used to generate a corresponding negative intermediate integration signal Simn and a positive intermediate integration signal Simp according to the first negative integration signal Si1n and the first positive integration signal Si1p. In this embodiment, the final-stage integrating circuit 2F is used to integrate and generate a final-stage negative integration signal Sifn according to the negative intermediate integration signal Simn and to integrate and generate a final-stage positive integration signal Sifp according to the positive intermediate integration signal Simp in the normal mode, and in the clipping mode, the intermediate integrating circuit 22 enters the reset state or the hold state. The reset state and the hold state of the intermediate integrating circuit 22 can be referred to the description of the foregoing embodiments.

[0128] In Figure 9 the embodiment of Figure 5 the clipping detection circuit 105b is used to judge whether the positive input signal Vip or the negative input signal Vin will cause clipping according to the clipping detection signal Sclpib, and when it is judged that the positive input signal Vip or the negative input signal Vin will cause clipping, a clipping control signal Sclpob is generated to control the class-D amplifier 2009 to enter the clipping mode. Compared with the embodiment of Figure 5 in this embodiment, the clipping detection signal Sclpib is also related to the negative intermediate integration signal Simn or the positive intermediate integration signal Simp. Figure 9 The remaining operation details of the class-D amplifier 2009 ofFigure 5 Inferred from the embodiments of

[0129] Figure 10 A schematic diagram of an embodiment of an intermediate integration circuit in a class-D amplifier of the present invention is shown. In one embodiment, as Figure 10 shown Figure 9 At least one intermediate integration circuit 2M of includes intermediate integration circuits 22 to 2n, where n is a positive integer greater than or equal to 2. In other words, the intermediate integration circuit 2M may include one or more intermediate integration circuits. In this embodiment, the intermediate integration circuit 22 is used to generate corresponding negative and positive intermediate integration signals according to the first negative integration signal Si1n and the first positive integration signal Si1p. After the integration of the intermediate integration circuits between the intermediate integration circuit 22 and the intermediate integration circuit 2n, finally, the intermediate integration circuit 2n generates corresponding negative intermediate integration signal Simn and positive intermediate integration signal Simp to the final-stage integration circuit 2F according to the negative and positive intermediate integration signals generated by the previous-stage intermediate integration circuit. In one embodiment, in the chopping mode, the intermediate integration circuits in at least one intermediate integration circuit 2M all enter the reset state or the hold state.

[0130] It should be noted that the present invention controls the feedforward signal, and in the chopping mode, the first-stage integration circuit (such as the first-stage integration circuit 21) and at least one intermediate integration circuit 2M (such as the intermediate integration circuit 22) operate in the reset state or the hold state, and the final-stage integration circuit 2F operates in the hold state to reset or maintain the potential of the integration capacitor in the integration circuit, thereby avoiding the situation that the sine wave of the integration signal generates chopping (saturation), and further avoiding unnecessary noise or popping in the output signal (such as the positive output signal Vop and the negative output signal Von) of the class-D amplifier.

[0131] Figure 12 An operation waveform diagram of an embodiment of a class-D amplifier of the prior art compared with the class-D amplifier of the present invention is shown. Waveform 401 is the output signal waveform diagram of the class-D amplifier of the prior art, waveforms 402 to 404 are the integration signal waveform diagrams of multiple stages of the integration circuit in the class-D amplifier of the prior art, waveform 405 is the output signal waveform diagram of the class-D amplifier of the present invention, and waveforms 406 to 408 are the integration signal waveform diagrams of multiple stages of the integration circuit in the class-D amplifier of the present invention. From Figure 12As can be seen from the waveform diagram, in the prior art, when the amplitude of the input signal of the class D amplifier is too large, it will cause the multi-stage integration signals to saturate to the positive power supply or the negative power supply (such as waveforms 402-404), and cause the output signal to generate clipping, noise and pop (as marked in the figure); however, in the present invention, by operating the integration circuit in the reset state or the hold state in the clipping mode to reset or hold the potential of the integration capacitor in the integration circuit, so that each integration signal does not saturate (such as waveforms 406-408), thereby avoiding the generation of noise and pop in the output signal.

[0132] Figure 13 Schematic diagram showing another specific embodiment of the class D amplifier of the present invention. Figure 13 The class D amplifier 2013 is similar to Figure 3 the class D amplifier 2003, the difference is that in Figure 13 this embodiment, the loop filter circuit 1013 of the class D amplifier 2013 is implemented by a digital circuit. Specifically, in this embodiment, the input signal Vi, the feedback signal Sfb, the feedforward signal Sff, the final-stage integration signal Sif and the loop filter signal Slf are all corresponding digital signals, and the feedback circuit 104 and the multi-stage integration circuit 102 are also digital circuits, used to perform the corresponding feedback and integration functions in a digital manner. Specifically, Figure 13 the multi-stage integration circuit 102 can also correspond to Figure 5 , Figure 9 and Figure 10 the multi-stage integration circuits in, that is, corresponding to Figure 13 the multi-stage integration circuit, in which the first-stage integration circuit, the intermediate-stage integration circuit and the final-stage integration circuit also all perform the integration function in a digital manner. In this embodiment, the feedforward path 103' includes an enable logic circuit (such as the AND gate 107D correspondingly), used to enable or disable the superposition of the feedforward signal Sff and the final-stage integration signal Sif according to the clipping control signal Sclpo.

[0133] The present invention has been described above with reference to the preferred embodiments. However, the above description is only for the purpose of making those skilled in the art easily understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. Each of the described embodiments is not limited to being applied alone, and can also be applied in combination. For example, two or more embodiments can be combined and used, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or operating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or operating according to the converted signal to generate a certain output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A class D amplifier for generating an output signal with pulse width modulation based on a DC voltage according to an input signal in a normal mode, comprising: A primary integration circuit for integrating the difference between the input signal and a feedback signal in the normal mode to generate a first integration signal, wherein the feedback signal is related to the output signal; A final integration circuit for integrally generating a final integration signal according to the first integration signal in the normal mode; An addition circuit for buffering the final integration signal to generate a loop filter signal in the normal mode; And A modulation and drive circuit for generating the output signal according to the comparison between the loop filter signal and a triangular wave; Wherein in a clipping mode, the primary integration circuit enters a reset state or a hold state, the final integration circuit enters a hold state, and the addition circuit is used to add the final integration signal and a feedforward signal to generate the loop filter signal; Wherein the feedforward signal is related to the input signal.

2. The class D amplifier according to claim 1, Wherein, It further comprises: At least one intermediate integration circuit for generating a corresponding at least one intermediate integration signal according to the first integration signal, wherein the final integration circuit is used to integrally generate the final integration signal according to the intermediate integration signal in the normal mode; Wherein in the clipping mode, the intermediate integration circuit enters a reset state or a hold state.

3. The class D amplifier according to claim 1, Wherein, It further comprises a feedforward switch for conducting in the clipping mode to electrically connect the feedforward signal to the addition circuit, and in the normal mode, turning off the electrical connection between the feedforward signal and the addition circuit.

4. The class D amplifier according to claim 1, Wherein, In the normal mode, the addition circuit is further used to add the final integration signal and the feedforward signal to generate the loop filter signal.

5. The class D amplifier according to claim 1, Wherein, It further comprises a clipping detection circuit for judging whether the input signal will cause clipping according to the final integration signal, the loop filter signal or the output signal, and when judging that the input signal will cause clipping, generating a clipping control signal to control the class D amplifier to enter the clipping mode.

6. The class D amplifier according to claim 1, Wherein, The primary integration circuit and / or the final integration circuit includes: An amplifier, an integration capacitor and at least one state control switch, wherein the integration capacitor and the amplifier are coupled to each other for corresponding integration operations; Wherein one of the at least one state control switch is connected in parallel with the integration capacitor for conducting in the clipping mode to reset the integration capacitor to enter the corresponding reset state; and / or Wherein one of the at least one state control switch is connected in series before an input end of the amplifier for turning off in the clipping mode to open the signal received by the input end, thereby maintaining the state of the integration capacitor to enter the corresponding hold state.

7. The class D amplifier according to claim 2, Wherein, Each of the first-stage integration circuit, the intermediate-stage integration circuit, and the final-stage integration circuit includes: a digital integration circuit for performing corresponding integration operations, wherein each of the input signal, the feedback signal, the feedforward signal, the final-stage integration signal, and the loop filter signal is a digital signal.

8. The class D amplifier according to claim 7, wherein, it further includes a digital enabling circuit for enabling the superposition of the feedforward signal and the final-stage integration signal in the chopping mode, and prohibiting the superposition of the feedforward signal and the final-stage integration signal in the normal mode.

Images