Differential signal processing circuit, differential operational amplifier and operational amplifier chip

Abstract

The invention relates to the field of integrated circuits, in particular to a differential signal processing circuit, a differential operational amplifier and an operational amplifier chip. The differential signal processing circuit comprises a high-voltage cross-coupled switch circuit which is provided with two first input ends and two first output ends, and the high-voltage cross-coupled switch circuit is configured to receive high-voltage differential signals through the two first input ends respectively and output the high-voltage differential signals according to low-voltage domain clock signals. A high-voltage differential signal is selectively output through the two first output ends; and the level shifting circuit is provided with two second input ends and two second output ends, and is configured to receive the high-voltage differential signal through the two second input ends, transfer the high-voltage differential signal into a low-voltage differential signal according to the low-voltage domain clock signal, and output the low-voltage differential signal through the two second output ends. According to the technical scheme, high-voltage direct-current common-mode signals can be isolated, and high-voltage differential signals are transferred into low-voltage differential signals to be output.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and particularly to a differential signal processing circuit, a differential operational amplifier, and an operational amplifier chip. Background Art

[0002] In many measurement situations, the signal of interest is very small, possibly in the range of dozens of microvolts, and is superimposed on a much larger DC common-mode (CM) signal, possibly in the range of several volts or even hundreds of volts. Processing such a large DC common-mode signal while accurately measuring such a small signal is a great challenge for a differential signal processing circuit. For example, in high-side current sensing, as Figure 1 shown, where the load current of a battery is monitored by inserting a small sensing resistor Rsense in series with the battery. Thus, the current can be determined by the DC voltage drop Vsense across the resistor. To minimize its power consumption, the sensing resistor Rsense is usually very small, and thus the DC voltage drop Vsense is also very small, usually between dozens of microvolts and hundreds of millivolts. At this time, the DC voltage drop Vsense is accompanied by a large DC common-mode voltage, which can be as high as 30V under normal circumstances, far exceeding the supply voltage of a normal CMOS circuit.

[0003] In the prior art, magnetic coupling and optical coupling are usually adopted to solve the DC common-mode voltage problem. Magnetic coupling consists of an input and output modulator, a transformer, and a readout amplifier. In this case, the modulator is implemented as a chopper, that is, the polarity inversion is driven by a digital clock signal with a fixed frequency. The input chopper converts the DC differential voltage into a square wave, and the output chopper converts the amplified square wave back into direct current. In this way, the high-voltage differential signal is first modulated to a high frequency by the input chopper, and thus can be coupled to the input of the readout differential operational amplifier through the transformer. However, the DC common-mode voltage is not modulated and thus is not coupled to the readout differential operational amplifier. In addition, the bias and 1 / f noise of the readout differential operational amplifier will be up-modulated by the output chopper and thus can be filtered out. However, a major drawback of this method is that it is difficult to integrate the transformer on the chip. Although integrated micro-transformers can be realized in some processes, they often occupy a large amount of chip area.

[0004] Optical coupling involves optically isolating the DC CM voltage, for example, using an optical isolator. Although there are many types of optical isolators, the most common type consists only of an LED and a photodiode. The LED is connected to the input signal and converts it into an optical signal, which is then picked up by the photodiode and the readout amplifier and converted back into an electrical signal. In this way, the input DC common-mode voltage is completely isolated from the differential operational amplifier. However, the main disadvantage of this method is the lack of accuracy. The signal transfer function between the LED and the photodiode depends on several parameters, such as the voltage-to-light transfer function of the LED, the intensity of the light picked up by the photodiode, and the light-voltage transfer function of the photodiode. These parameters are difficult to control and accurately reproduce in mass production. Therefore, the measurement accuracy, especially the total gain of the system, is not well defined. In addition, the linearity of the signal is usually very low, which requires an additional feedback circuit. Summary of the Invention

[0005] Based on this, it is necessary to provide a differential signal processing circuit and an operational amplifier chip for the above technical problems to isolate the high-voltage DC common-mode signal and transfer the high-voltage differential signal into a low-voltage differential signal for output.

[0006] In a first aspect, an embodiment of the present application provides a differential signal processing circuit, including:

[0007] A high-voltage cross-coupled switch circuit having two first input terminals and two first output terminals, the high-voltage cross-coupled switch circuit being configured to receive a high-voltage differential signal through the two first input terminals respectively and select to output the high-voltage differential signal through the two first output terminals according to a low-voltage domain clock signal;

[0008] A level shift circuit having two second input terminals and two second output terminals, configured to receive the high-voltage differential signal through the two second input terminals and transfer the high-voltage differential signal into a low-voltage differential signal for output through the two second output terminals according to the low-voltage domain clock signal.

[0009] In some embodiments, the high-voltage cross-coupled switch circuit includes: a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit. One end of the first switch unit is connected to one of the first input terminals, and the other end is connected to one of the first output terminals. One end of the second switch unit is connected to one of the first input terminals, and the other end is connected to the other first output terminal. One end of the third switch unit is connected to the other first input terminal, and the other end is connected to the first output terminal. One end of the fourth switch unit is connected to the other first input terminal, and the other end is connected to the other first output terminal.

[0010] In some embodiments, the high-voltage cross-coupled switch circuit further includes: a first clock signal control circuit and a second clock signal control circuit. The first clock signal control circuit receives the low-voltage domain clock signal and controls the first switch unit and the fourth switch unit. The second clock signal control circuit receives the low-voltage domain clock signal and controls the second switch unit and the third switch unit.

[0011] In some embodiments, the first switch unit includes PMOS transistor MP3 and NMOS transistor MN5. The second switch unit includes PMOS transistor MP1 and NMOS transistor MN1. The third switch unit includes PMOS transistor MP2 and NMOS transistor MN2. The fourth switch unit includes PMOS transistor MP4 and NMOS transistor MN6.

[0012] The gate of PMOS transistor MP3 is connected to the first clock signal control circuit, its source is connected to the drain of NMOS transistor MN5, and its drain is connected to one of the first output terminals. The gate of NMOS transistor MN5 is connected to the first clock signal control circuit, and its source is connected to the first high-voltage differential signal.

[0013] The gate of NMOS transistor MN1 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of PMOS transistor MP1. The gate of PMOS transistor MP1 is connected to the second clock signal control circuit, and its drain is connected to one of the first output terminals.

[0014] The gate of NMOS transistor MN2 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal, and its drain is connected to the source of PMOS transistor MP2. The gate of NMOS transistor MN2 is connected to the second clock signal control circuit, and its drain is connected to the other first output terminal.

[0015] The gate of PMOS transistor MP4 is connected to the first clock signal control circuit, its source is connected to the drain of NMOS transistor MN6, and its drain is connected to the other first output terminal. The gate of NMOS transistor MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal.

[0016] In some embodiments, the first clock signal control circuit includes NMOS transistors MN7, MN8, PMOS transistors MP7, MP8, capacitors Cp3, Cp4, Cp7, Cp8. The second clock signal control circuit includes NMOS transistors MN3, MN4, PMOS transistors MP5, MP6, capacitors Cp1, Cp2, Cp5, Cp6.

[0017] The source of the NMOS transistor MN7 is connected to the first high-voltage differential signal, its gate is connected to the drain of the NMOS transistor MN8, its drain is connected to one end of the capacitor Cp3 and the gate of the NMOS transistor MN8, and the other end of the capacitor Cp3 is connected to the second low-voltage domain clock signal; the source of the NMOS transistor MN8 is connected to the first high-voltage differential signal, its drain is connected to one end of the capacitor Cp4, and the other end of the capacitor Cp4 is connected to the first low-voltage domain clock signal;

[0018] The source of the PMOS transistor MP7 is connected to the first high-voltage differential signal, its gate is connected to the drain of the PMOS transistor MP8, its drain is connected to one end of the capacitor Cp7 and the gate of the PMOS transistor MP8, and the other end of the capacitor Cp7 is connected to the fourth low-voltage domain clock signal; the source of the PMOS transistor MP8 is connected to the first high-voltage differential signal, its drain is connected to one end of the capacitor Cp8, and the other end of the capacitor Cp8 is connected to the third low-voltage domain clock signal;

[0019] The source of the NMOS transistor MN3 is connected to the second high-voltage differential signal, its gate is connected to the drain of the NMOS transistor MN4, its drain is connected to one end of the capacitor Cp1 and the gate of the NMOS transistor MN4, and the other end of the capacitor Cp1 is connected to the first low-voltage domain clock signal; the source of the NMOS transistor MN4 is connected to the second high-voltage differential signal, its drain is connected to one end of the capacitor Cp2, and the other end of the capacitor Cp2 is connected to the second low-voltage domain clock signal;

[0020] The source of the PMOS transistor MP5 is connected to the second high-voltage differential signal, its gate is connected to the drain of the PMOS transistor MP6, its drain is connected to one end of the capacitor Cp5 and the gate of the PMOS transistor MP6, and the other end of the capacitor Cp5 is connected to the third low-voltage domain clock signal; the source of the PMOS transistor MP6 is connected to the second high-voltage differential signal, its drain is connected to one end of the capacitor Cp6, and the other end of the capacitor Cp6 is connected to the fourth low-voltage domain clock signal.

[0021] In some embodiments, the third low-voltage domain clock signal is a delayed signal of the first low-voltage domain clock signal; the fourth low-voltage domain clock signal is a delayed signal of the second low-voltage domain clock signal.

[0022] In some embodiments, the first high-voltage differential signal is greater than or equal to or less than the second high-voltage differential signal.

[0023] In some embodiments, the level shift circuit includes a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a ninth switch unit, a tenth switch unit, capacitor C1, capacitor C2, capacitor C3, and capacitor C4;

[0024] One end of the fifth switch unit is connected to one end of capacitor C3, and the other end is connected to the common ground. The other end of capacitor C3 is connected to one of the second output terminals;

[0025] One end of the sixth switch unit is connected to one end of capacitor C3, and the other end is connected to the reference voltage signal;

[0026] One end of the seventh switch unit is connected to one end of capacitor C4, and the other end is connected to the reference voltage signal. The other end of capacitor C4 is connected to the other second output terminal;

[0027] One end of the eighth switch unit is connected to one end of capacitor C4, and the other end is connected to the common ground;

[0028] One end of the ninth switch unit is connected to one of the second output terminals, and the other end is connected to one end of the tenth switch unit. The other end of the tenth switch unit is connected to the other second output terminal;

[0029] One end of capacitor C1 is connected to one of the second input terminals, and the other end is connected to one of the second output terminals; one end of capacitor C2 is connected to the other second input terminal, and the other end is connected to the other second output terminal.

[0030] In a second aspect, an embodiment of the present application provides a differential operational amplifier, including the differential signal processing circuit as described in the first aspect.

[0031] In a third aspect, an embodiment of the present application provides an operational amplifier chip, including the differential operational amplifier as described in the second aspect.

[0032] The above differential signal processing circuit, differential operational amplifier, and operational amplifier chip have the following technical effects: The high-voltage cross-coupled switch circuit receives high-voltage differential signals through the two first input terminals, and selects and outputs high-voltage differential signals through the two first output terminals according to the low-voltage domain clock signal. The level shift circuit receives the high-voltage differential signals through the two second input terminals, and transfers the high-voltage differential signals into low-voltage differential signals and outputs them through the two second output terminals according to the low-voltage domain clock signal. This technical solution can isolate the high-voltage DC common-mode signal and transfer the high-voltage differential signal into a low-voltage differential signal for output on the premise of a small integration area and high precision. Description of the Drawings

[0033] Figure 1Schematic diagram of the differential signal processing circuit in an embodiment provided by the present application;

[0034] Figure 2 Specific schematic diagram of the differential signal processing circuit in an embodiment provided by the present application;

[0035] Figure 3 Equivalent circuit diagram of the differential signal processing circuit in an embodiment provided by the present application;

[0036] Figure 4 Schematic diagram of the high - voltage cross - coupled switch circuit in an embodiment provided by the present application. Detailed implementation manners

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described and explained below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.

[0038] Referring to "embodiments" in the present application means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0039] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "comprise", "include", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means greater than or equal to two. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0040] Figure 1 The structural schematic diagram of the differential signal processing circuit in an embodiment provided for this application is as follows. As Figure 1 shown, the differential signal processing circuit includes: a high-voltage cross-coupled switch circuit 10, having two first input terminals and two first output terminals, the high-voltage cross-coupled switch circuit 10 being configured to receive high-voltage differential signals through the two first input terminals respectively and select and output high-voltage differential signals through the two first output terminals according to a low-voltage domain clock signal; a level shift circuit 20, having two second input terminals and two second output terminals, being configured to receive the high-voltage differential signals through the two second input terminals and transfer the high-voltage differential signals into low-voltage differential signals and output them through the two second output terminals according to the low-voltage domain clock signal.

[0041] Among them, the high-voltage differential signal refers to a differential signal above 70V, but the specific voltage range is not limited in this embodiment.

[0042] In this embodiment, the high-voltage cross-coupled switch circuit 10 receives high-voltage differential signals through the two first input terminals respectively, and selects and outputs high-voltage differential signals through the two first output terminals according to the low-voltage domain clock signal. The level shift circuit 20 receives the high-voltage differential signals through the two second input terminals, and transfers the high-voltage differential signals into low-voltage differential signals according to the low-voltage domain clock signal and outputs them through the two second output terminals. This technical solution can isolate the high-voltage DC common-mode signal and transfer the high-voltage differential signal into a low-voltage differential signal for output on the premise of a small integration area and high accuracy.

[0043] Figure 2 It is a schematic structural diagram of a differential signal processing circuit in an embodiment provided by this application. As Figure 2 shown, the high-voltage cross-coupled switch circuit 10 includes: a first switch unit S1, a second switch unit S2, a third switch unit S3, and a fourth switch unit S4. One end of the first switch unit S1 is connected to one of the first input terminals, and the other end is connected to one of the first output terminals. One end of the second switch unit S2 is connected to one of the first input terminals, and the other end is connected to the other first output terminal. One end of the third switch unit S3 is connected to the other first input terminal, and the other end is connected to the first output terminal. One end of the fourth switch unit S4 is connected to the other first input terminal, and the other end is connected to the other first output terminal.

[0044] Among them, a first high-voltage differential signal V H is input to one first input terminal, and a second high-voltage differential signal V L is input to the other first input terminal.

[0045] In some embodiments, the level shift circuit 20 includes a fifth switch unit S5, a sixth switch unit S6, a seventh switch unit S7, an eighth switch unit S8, a ninth switch unit S9, a tenth switch unit S10, capacitors C1, C2, C3, and C4.

[0046] One end of the fifth switch unit S5 is connected to one end of the capacitor C3, and the other end is connected to the common ground. The other end of the capacitor C3 is connected to one of the second output terminals. One end of the sixth switch unit S6 is connected to one end of the capacitor C3, and the other end is connected to the reference voltage signal V REF ; One end of the seventh switch unit S7 is connected to one end of the capacitor C4, and the other end is connected to the reference voltage signal V REF, the other end of the capacitor C4 is connected to the other second output terminal; one end of the eighth switch unit S8 is connected to one end of the capacitor C4, and the other end is connected to the common ground; one end of the ninth switch unit S9 is connected to one second output terminal, and the other end is connected to one end of the tenth switch unit S10, and the other end of the tenth switch unit S10 is connected to the other second output terminal; one end of the capacitor C1 is connected to one second input terminal, and the other end is connected to one second output terminal; one end of the capacitor C2 is connected to the other second input terminal, and the other end is connected to the other second output terminal.

[0047] Among them, one second output terminal outputs the first low-voltage differential signal V ON , and the other second output terminal outputs the second low-voltage differential signal V OP .

[0048] In the above embodiment, the capacitances of the capacitors C1, C2, C3, and C4 are the same.

[0049] In the above embodiment, the first switch unit S1, the fourth switch unit S4, the fifth switch unit S5, the seventh switch unit S7, the ninth switch unit S9, and the tenth switch unit S10 are controlled by the first low-voltage domain clock signal , and the second switch unit S2, the third switch unit S3, the sixth switch unit S6, and the eighth switch unit S8 are controlled by the second low-voltage domain clock signal . The first low-voltage domain clock signal and the second low-voltage domain clock signal are two-phase non-overlapping clock signals.

[0050] In the above embodiment, the high-voltage differential signal is sampled by the capacitor, and the high-voltage DC common-mode signal is completely isolated by the capacitor.

[0051] When the first high-voltage differential signal V H is higher than the second high-voltage differential signal V L , the equivalent circuit of the differential signal processing circuit is as shown in Figure 3 . When the first low-voltage domain clock signal is at a high level and the second low-voltage domain clock signal is at a low level, the capacitors C1 and C3 are connected. One end of the capacitor C1 is connected to the first high-voltage differential signal V H , and the other end is connected to the midpoint signal V CM , one end of the capacitor C3 is connected to the common ground, and the other end is connected to the midpoint signal V CM ; when the second low-voltage domain clock signal is at a high level and the first low-voltage domain clock signal is at a low level, the capacitors C1 and C3 are connected. One end of the capacitor C1 is connected to the second high-voltage differential signal VL , the other end is connected to the midpoint signal V CM , one end of the capacitor C3 is connected to the reference voltage signal V REF , the other end is connected to the midpoint signal V CM .

[0052] The capacitances of the capacitors C1, C2, C3, and C4 are all C for example. Based on the above equivalent circuit, using the definition of charge conservation, we get:

[0053] (V CM -V H )C+(V CM -0)C=(V xp -V L )C+(V xp -V REF )C

[0054] Among them, V xp represents an output voltage of the level shift circuit.

[0055] Simplifying gives:

[0056]

[0057] Similarly, we can get:

[0058]

[0059] Among them, V xn represents another output voltage of the level shift circuit.

[0060] In summary, we can get:

[0061] V xp -V xn =V REF -(V H -V L )

[0062] The reference voltage signal V REF is 3.3V for example. From the above formula, it can be obtained that the voltages of the signals V xp and V xn are shifted to the signal V CM . And when the range of V H -V L is 0 to 6.6V, the voltage range of V xp -V xn is ±3.3V, meeting the quantization range of adc ±3.3V, thus isolating the influence of the DC common-mode voltage.

[0063] When the first high-voltage differential signal VH is lower than the second high-voltage differential signal VL, the first low-voltage domain clock signal in the level translation circuit and the second low-voltage domain clock signal are reversely connected. Similarly, according to the conservation of charge, we have:

[0064]

[0065] The reference voltage signal VREF is, for example, 3.3V. When V L = 0 to 6.6V and V H = 0, if V L = 0V, then V xp - V xn = 3.3V. If V L = 6.6V, then V xp - V xn = -3.3V.

[0066] Figure 4 FIG. 30 is a schematic structural diagram of the high-voltage cross-coupled switch circuit 10 in an embodiment provided by the present application. As Figure 4 shown, the high-voltage cross-coupled switch circuit 10 further includes: a first clock signal control circuit 101 and a second clock signal control circuit 102. The first clock signal control circuit 101 receives the low-voltage domain clock signal and controls the first switch unit S1 and the fourth switch unit S4. The second clock signal control circuit 102 receives the low-voltage domain clock signal and controls the second switch unit S2 and the third switch unit S3.

[0067] In some embodiments, the first switch unit S1 includes a PMOS transistor MP3 and an NMOS transistor MN5. The second switch unit S2 includes a PMOS transistor MP1 and an NMOS transistor MN1. The third switch unit S3 includes a PMOS transistor MP2 and an NMOS transistor MN2. The fourth switch unit S4 includes a PMOS transistor MP4 and an NMOS transistor MN6.

[0068] The gate of the PMOS transistor MP3 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN5, and its drain is connected to one of the first output terminals V OUT1 ; the gate of the NMOS transistor MN5 is connected to the first clock signal control circuit, its source is connected to the first high-voltage differential signal V H ; the gate of the NMOS transistor MN1 is connected to the second clock signal control circuit, its source is connected to the second high-voltage differential signal V L , and its drain is connected to the source of the PMOS transistor MP1; the gate of the PMOS transistor MP1 is connected to the second clock signal control circuit, and its drain is connected to one of the first output terminals VOUT1 ; The gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its source is connected to the second high-voltage differential signal V L , and its drain is connected to the source of the PMOS transistor MP2; the gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and its drain is connected to the other first output terminal V OUT2 ; the gate of the PMOS transistor MP4 is connected to the first clock signal control circuit, its source is connected to the drain of the NMOS transistor MN6, and its drain is connected to the other first output terminal V OUT2 ; the gate of the NMOS transistor MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal V H .

[0069] In some embodiments, the first clock signal control circuit 101 includes an NMOS transistor MN7, an NMOS transistor MN8, a PMOS transistor MP7, a PMOS transistor MP8, a capacitor Cp3, a capacitor Cp4, a capacitor Cp7, and a capacitor Cp8; the second clock signal control circuit includes an NMOS transistor MN3, an NMOS transistor MN4, a PMOS transistor MP5, a PMOS transistor MP6, a capacitor Cp1, a capacitor Cp2, a capacitor Cp5, and a capacitor Cp6.

[0070] The source of the NMOS transistor MN7 is connected to the first high-voltage differential signal V H , its gate is connected to the drain of the NMOS transistor MN8, its drain is connected to one end of the capacitor Cp3 and the gate of the NMOS transistor MN8, and the other end of the capacitor Cp3 is connected to the second low-voltage domain clock signal The source of the NMOS transistor MN8 is connected to the first high-voltage differential signal V H , its drain is connected to one end of the capacitor Cp4, and the other end of the capacitor Cp4 is connected to the first low-voltage domain clock signal

[0071] The source of the PMOS transistor MP7 is connected to the first high-voltage differential signal V H , its gate is connected to the drain of the PMOS transistor MP8, its drain is connected to one end of the capacitor Cp7 and the gate of the PMOS transistor MP8, and the other end of the capacitor Cp7 is connected to the fourth low-voltage domain clock signal The source of the PMOS transistor MP8 is connected to the first high-voltage differential signal V H , its drain is connected to one end of the capacitor Cp8, and the other end of the capacitor Cp8 is connected to the third low-voltage domain clock signal

[0072] The source of the NMOS transistor MN3 is connected to the second high-voltage differential signal VL , its gate is connected to the drain of the NMOS transistor MN4, its drain is connected to one end of the capacitor Cp1 and the gate of the NMOS transistor MN4, and the other end of the capacitor Cp1 is connected to the first low-voltage domain clock signal The source of the NMOS transistor MN4 is connected to the second high-voltage differential signal V L , its drain is connected to one end of the capacitor Cp2, and the other end of the capacitor Cp2 is connected to the second low-voltage domain clock signal

[0073] The source of the PMOS transistor MP5 is connected to the second high-voltage differential signal V L , its gate is connected to the drain of the PMOS transistor MP6, its drain is connected to one end of the capacitor Cp5 and the gate of the PMOS transistor MP6, and the other end of the capacitor Cp5 is connected to the third low-voltage domain clock signal The source of the PMOS transistor MP6 is connected to the second high-voltage differential signal V L , its drain is connected to one end of the capacitor Cp6, and the other end of the capacitor Cp6 is connected to the fourth low-voltage domain clock signal

[0074] In order to avoid using LDMOS, the above embodiment adopts a charge-pump-based switching structure, similar to the boosting part in the boost switch.

[0075] The gate-source voltage of the high-voltage device in the on state is determined by the charge distribution ratio between the coupling capacitor (Cpi) and the MOS parasitic capacitor. Taking the NMOS transistor MN3 as an example, the pulse signal on the first low-voltage domain clock signal of the capacitor bottom plate node will cause charge redistribution.

[0076] It should be noted that the third low-voltage domain clock signal is the delayed signal of the first low-voltage domain clock signal , and the fourth low-voltage domain clock signal is the delayed signal of the second low-voltage domain clock signal .

[0077] By setting the delayed signal, the NMOS transistors MN1, MN2, MN5, and MN6 can be turned on first, avoiding the vgs voltage of the PMOS transistors MP1, MP2, MP3, and MP4 from exceeding 5V.

[0078] In this embodiment, by setting the PMOS transistors MP1, MP2, MP3, and MP4, the first high-voltage differential signal V can be avoided Hmust be greater than the second high-voltage differential signal V L Under the condition limitation, so the first high-voltage differential signal V H can be greater than or equal to or less than the second high-voltage differential signal V L .

[0079] The control process of the high-voltage cross-coupled switch will be described below by taking the first switch unit S1 and the first clock signal control circuit as examples.

[0080] The first low-voltage domain clock signal and the second low-voltage domain clock signal are two-phase non-overlapping clock signals. When the first low-voltage domain clock signal is at a high level, the NMOS transistor MN7 is turned on, the NMOS transistor MN5 is turned on, and the third low-voltage domain clock signal is the opposite signal of the first low-voltage domain clock signal , so it is at a low level, the PMOS transistor MP7 is turned on, the PMOS transistor MP3 is turned on, and at this time the first switch unit S1 is turned on.

[0081] For the control processes of other switch units and clock signal control circuits, the same control principle is adopted, so it will not be elaborated here.

[0082] The embodiment of the present application also proposes a differential operational amplifier, including the differential signal processing circuit as described in the above embodiment.

[0083] It should be noted that the working principle and beneficial effects of the differential signal processing circuit have been elaborated in detail in the above embodiment, so they will not be elaborated in this embodiment.

[0084] The embodiment of the present application also proposes an operational amplifier chip, including the differential operational amplifier as described in the above embodiment.

[0085] It should be noted that the working principle and beneficial effects of the differential signal processing circuit have been elaborated in detail in the above embodiment, so they will not be elaborated in this embodiment.

[0086] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0087] The above embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A differential signal processing circuit, characterized in that: include: A high-voltage cross-coupling switch circuit, having two first input terminals and two first output terminals, wherein the high-voltage cross-coupling switch circuit is configured to receive high-voltage differential signals respectively through the two first input terminals, and select to output the high-voltage differential signals through the two first output terminals according to a low-voltage domain clock signal; The level shifting circuit has two second input terminals and two second output terminals, and is configured to receive the high-voltage differential signal through the two second input terminals, and according to the low-voltage domain clock signal, transfer the high-voltage differential signal to a low-voltage differential signal and output it through the two second output terminals.

2. The differential signal processing circuit according to claim 1, characterized in that: The high-voltage cross-coupled switch circuit includes: a first switch unit, a second switch unit, a third switch unit and a fourth switch unit, wherein one end of the first switch unit is connected to the first input end, and the other end is connected to the first output end, one end of the second switch unit is connected to the first input end, and the other end is connected to another first output end, one end of the third switch unit is connected to another first input end, and the other end is connected to the first output end, and one end of the fourth switch unit is connected to another first input end, and the other end is connected to another first output end.

3. The differential signal processing circuit according to claim 2, characterized in that: The high-voltage cross-coupled switch circuit also includes: a first clock signal control circuit and a second clock signal control circuit, the first clock signal control circuit receives the low-voltage domain clock signal to control the first switch unit and the fourth switch unit, and the second clock signal control circuit receives the low-voltage domain clock signal to control the second switch unit and the third switch unit.

4. The differential signal processing circuit according to claim 3, characterized in that: The first switch unit includes a PMOS tube MP3 and an NMOS tube MN5, the second switch unit includes a PMOS tube MP1 and an NMOS tube MN1, the third switch unit includes a PMOS tube MP2 and an NMOS tube MN2, and the fourth switch unit includes a PMOS tube MP4 and an NMOS tube MN6; The gate of the PMOS transistor MP3 is connected to the first clock signal control circuit, and the source thereof is connected to the drain of the NMOS transistor MN5, and the drain thereof is connected to the first output terminal; the gate of the NMOS transistor MN5 is connected to the first clock signal control circuit, and the source thereof is connected to the first high voltage differential signal; The gate of the NMOS transistor MN1 is connected to the second clock signal control circuit, the source thereof is connected to the second high voltage differential signal, and the drain thereof is connected to the source of the PMOS transistor MP1; the gate of the PMOS transistor MP1 is connected to the second clock signal control circuit, and the drain thereof is connected to the first output terminal; The gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, the source thereof is connected to the second high-voltage differential signal, and the drain thereof is connected to the source of the PMOS transistor MP2; the gate of the NMOS transistor MN2 is connected to the second clock signal control circuit, and the drain thereof is connected to another first output terminal; The gate of the PMOS tube MP4 is connected to the first clock signal control circuit, and its source is connected to the drain of the NMOS tube MN6, and its drain is connected to the other first output terminal; the gate of the NMOS tube MN6 is connected to the second clock signal control circuit, and its source is connected to the first high-voltage differential signal.

5. The differential signal processing circuit according to claim 4, characterized in that: The first clock signal control circuit includes NMOS transistor MN7, NMOS transistor MN8, PMOS transistor MP7, PMOS transistor MP8, capacitor Cp3, capacitor Cp4, capacitor Cp7, capacitor Cp8; the second clock signal control circuit includes NMOS transistor MN3, NMOS transistor MN4, PMOS transistor MP5, PMOS transistor MP6, capacitor Cp1, capacitor Cp2, capacitor Cp5, capacitor Cp6; The source of the NMOS transistor MN7 is connected to the first high-voltage differential signal, the gate thereof is connected to the drain of the NMOS transistor MN8, the drain thereof is connected to one end of the capacitor Cp3 and the gate of the NMOS transistor MN8, and the other end of the capacitor Cp3 is connected to the second low-voltage domain clock signal; the source of the NMOS transistor MN8 is connected to the first high-voltage differential signal, the drain thereof is connected to one end of the capacitor Cp4, and the other end of the capacitor Cp4 is connected to the first low-voltage domain clock signal; The source of the PMOS transistor MP7 is connected to the first high-voltage differential signal, the gate thereof is connected to the drain of the PMOS transistor MP8, the drain thereof is connected to one end of the capacitor Cp7 and the gate of the PMOS transistor MP8, and the other end of the capacitor Cp7 is connected to the fourth low-voltage domain clock signal; the source of the PMOS transistor MP8 is connected to the first high-voltage differential signal, the drain thereof is connected to one end of the capacitor Cp8, and the other end of the capacitor Cp8 is connected to the third low-voltage domain clock signal; The source of the NMOS transistor MN3 is connected to the second high-voltage differential signal, the gate thereof is connected to the drain of the NMOS transistor MN4, the drain thereof is connected to one end of the capacitor Cp1 and the gate of the NMOS transistor MN4, and the other end of the capacitor Cp1 is connected to the first low-voltage domain clock signal; the source of the NMOS transistor MN4 is connected to the second high-voltage differential signal, the drain thereof is connected to one end of the capacitor Cp2, and the other end of the capacitor Cp2 is connected to the second low-voltage domain clock signal; The source of the PMOS tube MP5 is connected to the second high-voltage differential signal, the gate thereof is connected to the drain of the PMOS tube MP6, the drain thereof is connected to one end of the capacitor Cp5 and the gate of the PMOS tube MP6, and the other end of the capacitor Cp5 is connected to the third low-voltage domain clock signal; the source of the PMOS tube MP6 is connected to the second high-voltage differential signal, the drain thereof is connected to one end of the capacitor Cp6, and the other end of the capacitor Cp6 is connected to the fourth low-voltage domain clock signal.

6. The differential signal processing circuit according to claim 5, characterized in that: The third low-voltage domain clock signal is a delayed signal of the first low-voltage domain clock signal; and the fourth low-voltage domain clock signal is a delayed signal of the second low-voltage domain clock signal.

7. The differential signal processing circuit according to any one of claims 4 to 6, characterized in that: The first high-voltage differential signal is greater than, equal to, or less than the second high-voltage differential signal.

8. The differential signal processing circuit according to claim 1, characterized in that: The level transfer circuit includes a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a ninth switch unit, a tenth switch unit, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4; One end of the fifth switch unit is connected to one end of the capacitor C3, and the other end is connected to the common ground, and the other end of the capacitor C3 is connected to the second output end; One end of the sixth switch unit is connected to one end of the capacitor C3, and the other end is connected to the reference voltage signal; One end of the seventh switch unit is connected to one end of the capacitor C4, the other end is connected to the reference voltage signal, and the other end of the capacitor C4 is connected to another second output end; One end of the eighth switch unit is connected to one end of the capacitor C4, and the other end is connected to the common ground; One end of the ninth switch unit is connected to one of the second output ends, and the other end is connected to one end of the tenth switch unit, and the other end of the tenth switch unit is connected to another of the second output ends; One end of the capacitor C1 is connected to the second input end, and the other end is connected to the second output end; one end of the capacitor C2 is connected to another second input end, and the other end is connected to another second output end.

9. A differential operational amplifier, characterized in that: The invention comprises a differential signal processing circuit as claimed in any one of claims 1 to 8.

10. An operational amplifier chip, characterized in that: Comprising the differential operational amplifier as claimed in claim 9.

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