Intermediate frequency chip and clock generation circuit thereof, intermediate frequency module and broadband terminal

Abstract

The invention provides an intermediate frequency chip and a clock generation circuit thereof, an intermediate frequency module and a broadband terminal, and the clock generation circuit comprises a phase-locked loop which is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal for controlling an analog-to-digital converter to sample in a process of converting an analog signal into a digital signal by the analog-to-digital converter in the intermediate frequency chip; the first frequency divider is used for carrying out frequency division on the first clock signal to generate a second clock signal, and the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to the baseband chip; and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. According to the clock generation circuit, a plurality of clock generation chips do not need to provide clock signals for the on-chip processor of the baseband chip, so that the cost and complexity of a clock scheme are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit communication technologies, and particularly to an intermediate frequency chip, its clock generation circuit, an intermediate frequency module, and a broadband terminal. Background Art

[0002] In related technologies, the intermediate frequency module of a satellite Internet broadband terminal includes a baseband chip. Among them, the baseband chip integrates multiple different types of IP (Intellectual Property) cores, such as a processor and communication interfaces like high-speed interfaces. However, it is difficult to achieve consistency in the working clocks required by different types of IP cores. Therefore, multiple additional clock generation chips are often needed to provide the clock signals required by the on-chip processor of the baseband chip. As a result, the overall clock scheme of the intermediate frequency module has a high cost and high complexity, which also affects the cost and performance of the intermediate frequency module. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in related technologies to some extent.

[0004] To this end, the first object of the present invention is to propose a clock generation circuit for an intermediate frequency chip. This clock generation circuit is a circuit designed in the intermediate frequency chip and can directly provide a sampling clock signal and / or a reference clock signal to the baseband chip. In this way, there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0005] The second object of the present invention is to propose an intermediate frequency chip.

[0006] The third object of the present invention is to propose an intermediate frequency module.

[0007] The fourth object of the present invention is to propose a broadband terminal.

[0008] To achieve the above object, an embodiment of the first aspect of the present invention proposes a clock generation circuit for an intermediate frequency chip, including: a phase-locked loop for generating a first clock signal based on a received reference clock signal, where the first clock signal is used to represent the clock signal for controlling the sampling of an analog-to-digital converter in the intermediate frequency chip during the conversion of an analog signal into a digital signal; a first frequency divider for dividing the first clock signal to generate a second clock signal, where the second clock signal is used to represent the sampling clock signal provided by the intermediate frequency chip to the baseband chip; a multiplexer for outputting a target clock signal based on the received reference clock signal and the second clock signal, where the target clock signal is at least one of the reference clock signal and the second clock signal.

[0009] The clock generation circuit of the intermediate frequency chip according to the embodiment of the present invention includes a phase-locked loop, a first frequency divider, and a multiplexer. Among them, the phase-locked loop is used to generate a first clock signal based on the received reference clock signal, where the first clock signal is used to characterize the clock signal that controls the sampling of the analog-to-digital converter in the intermediate frequency chip when converting an analog signal into a digital signal. The first frequency divider is used to divide the frequency of the first clock signal to generate a second clock signal, where the second clock signal is used to characterize the sampling clock signal provided by the intermediate frequency chip to the baseband chip. The multiplexer is used to output a target clock signal based on the received reference clock signal and the second clock signal, where the target clock signal is at least one of the reference clock signal and the second clock signal. Thus, the clock generation circuit of the present invention is a circuit designed in the intermediate frequency chip, which can directly provide the sampling clock signal and / or the reference clock signal to the baseband chip, so that there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme.

[0010] In addition, the clock generation circuit of the intermediate frequency chip proposed in the first aspect embodiment of the present invention may further have the following additional technical features:

[0011] According to an embodiment of the present invention, the phase-locked loop includes: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a second frequency divider, and a third frequency divider connected in sequence. Among them,

[0012] The first clock signal is a clock signal generated by the second frequency divider dividing the output signal of the voltage-controlled oscillator.

[0013] According to an embodiment of the present invention, in response to the communication interface of the baseband chip requiring a synchronous clock signal, the clock generation circuit of the intermediate frequency chip further includes:

[0014] A fourth frequency divider, which is used to divide the output signal of the voltage-controlled oscillator to generate a third clock signal, where the third clock signal is used to characterize the synchronous clock signal required by the communication interface of the baseband chip.

[0015] According to an embodiment of the present invention, the phase-locked loop further includes:

[0016] A buffer, which is used to buffer the output signal of the voltage-controlled oscillator.

[0017] According to an embodiment of the present invention, the division ratio of the first frequency divider is the oversampling rate or the decimation factor of the analog-to-digital converter.

[0018] According to an embodiment of the present invention, in response to different receiving data rates and transmitting data rates of the intermediate frequency chip, the frequency of the second clock signal is in a multiple relationship with the greatest common divisor of the receiving data rate and the transmitting data rate.

[0019] To achieve the above object, an embodiment of the second aspect of the present invention provides an intermediate frequency chip, including: the clock generation circuit of the intermediate frequency chip as described above.

[0020] The intermediate frequency chip according to the embodiment of the present invention includes the clock generation circuit of the intermediate frequency chip as described above. Through the clock generation circuit of the present invention, a sampling clock signal and / or a reference clock signal can be directly provided to the baseband chip, so that there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0021] To achieve the above object, an embodiment of the third aspect of the present invention provides an intermediate frequency module, including: an oscillator, a power splitter, a baseband chip, and the intermediate frequency chip as described above; wherein,

[0022] The power splitter is configured to divide the clock signal output by the oscillator into a reference clock signal and a working clock signal;

[0023] The intermediate frequency chip is configured to generate the target clock signal based on the reference clock signal;

[0024] The baseband chip is configured to receive the working clock signal and the target clock signal.

[0025] The intermediate frequency module according to the embodiment of the present invention includes an oscillator, a power splitter, a baseband chip, and the intermediate frequency chip as described above; wherein, the power splitter is configured to divide the clock signal output by the oscillator into a reference clock signal and a working clock signal; the intermediate frequency chip is configured to generate the target clock signal based on the reference clock signal; the baseband chip is configured to receive the working clock signal and the target clock signal. The clock generation circuit is designed in the intermediate frequency chip of the present invention, and through this clock generation circuit, a sampling clock signal and / or a reference clock signal can be directly provided to the baseband chip, so that there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0026] In addition, the intermediate frequency module proposed in the embodiment of the third aspect of the present invention may further have the following additional technical features:

[0027] According to an embodiment of the present invention, when the working clock signal and the target clock signal are not in an integer ratio and the baseband chip does not have a phase-locked loop, the intermediate frequency module further includes:

[0028] A clock generation chip is used to generate the working clock signal required by the baseband chip based on the working clock signal output by the power divider.

[0029] To achieve the above object, an embodiment of the fourth aspect of the present invention provides a broadband terminal, including: the intermediate frequency module as described above.

[0030] According to the broadband terminal of the embodiment of the present invention, by using the above intermediate frequency module, the sampling clock signal and / or reference clock signal can be directly provided to the baseband chip through the clock generation circuit on the clock chip. In this way, it is not necessary to use multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0033] Figure 1 is a schematic diagram of the clock scheme between the intermediate frequency chip and the baseband chip in the related art;

[0034] Figure 2 is a schematic diagram of the clock generation circuit of the intermediate frequency chip according to the embodiment of the present invention;

[0035] Figure 3 is a circuit diagram of the clock generation circuit of the intermediate frequency chip according to an embodiment of the invention;

[0036] Figure 4 is a schematic diagram of the clock scheme between the intermediate frequency chip and the baseband chip according to an embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of the clock scheme between the intermediate frequency chip and the baseband chip according to another embodiment of the present invention. Detailed Embodiments

[0038] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0039] The intermediate frequency chip, its clock generation circuit, the intermediate frequency module, and the broadband terminal according to the embodiments of the present invention will be described below with reference to the drawings.

[0040] Before introducing the clock generation circuit of the intermediate frequency chip according to the embodiments of the present invention, let's first introduce the clock scheme between the intermediate frequency chip and the baseband chip in the related art.

[0041] In the related art, the intermediate frequency module of a satellite Internet broadband terminal mainly includes an intermediate frequency chip and a baseband chip. Among them, the baseband chip often requires multiple clock generation chips, such as clock generation chip 1 and clock generation chip 2, to provide the clock signals required by the on-chip processor. As Figure 1 shown, in the related art, an OCXO (Oven-controlled Crystal Oscillator) with excellent phase noise performance is used to output a reference clock signal. After passing through a power divider, one path is given to clock generation chip 1 to generate the working clock signal CLK required by the on-chip processor of the baseband chip, and the other path is given to clock generation and distribution chip 2 to generate clock signals related to the interface waveform, such as the sampling clock signal Sampling rate and the synchronization clock signal SYSREF.

[0042] The clock scheme in the related art requires additional clock generation chips, and the clock scheme is relatively complex. Its disadvantages are as follows: First, the integration level is not high enough, and the clock generation chips with excellent phase noise performance are expensive, making it difficult to reduce the cost of the broadband terminal; second, the number of clock generation chips is large, which is likely to introduce spurs to the broadband terminal and affect the analog signal quality; third, if different models of baseband chips are used in the broadband terminal and there are differences in the operating frequencies, other clock schemes need to be adopted, increasing the difficulty of system debugging and standardization.

[0043] Therefore, the present invention proposes a clock generation circuit for an intermediate frequency chip. This clock generation circuit is a circuit designed in the intermediate frequency chip and can directly provide a sampling clock signal and / or a reference clock signal to the baseband chip. In this way, it is not necessary to use multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme.

[0044] Figure 2 is a schematic diagram of the clock generation circuit of the intermediate frequency chip according to the embodiments of the present invention.

[0045] As Figure 2 described, the clock generation circuit of the intermediate frequency chip according to the embodiments of the present invention includes: a phase-locked loop PLL, a first frequency divider / N3, and a multiplexer MUX.

[0046] Among them, a phase-locked loop (PLL) is used to generate a first clock signal Fs_AD based on a received reference clock signal fref. The first clock signal Fs_AD is used to represent the clock signal for controlling the sampling of an analog-to-digital converter in the intermediate frequency chip during the process of converting an analog signal into a digital signal. A first frequency divider ( / N3) is used to divide the frequency of the first clock signal Fs_AD to generate a second clock signal, where the second clock signal is used to represent the sampling clock signal provided by the intermediate frequency chip to the baseband chip. A multiplexer (MUX) is used to output a target clock signal Data CLK based on the received reference clock signal fref and the second clock signal, where the target clock signal Data CLK is at least one of the reference clock signal fref and the second clock signal.

[0047] Among them, the division ratio of the first frequency divider ( / N3) is the oversampling rate or decimation factor of the analog-to-digital converter. If the intermediate frequency chip is applied to satellite Internet and the received data rate and transmitted data rate of the intermediate frequency chip are different, then the frequency of the second clock signal is in a multiple relationship with the greatest common divisor of the received data rate and the transmitted data rate.

[0048] In the present invention, the multiplexer (MUX) can selectively output the reference clock signal fref and / or the second clock signal according to requirements. For example, the multiplexer (MUX) can be set to select and output the reference clock signal and / or the sampling clock signal according to a control signal. Among them, when the reference clock signal fref is needed, the control signal can be set to select the reference clock signal fref as the output; when the sampling clock signal is needed, the control signal can be set to select the sampling clock signal as the output; when it is necessary to output the reference clock signal fref and the sampling clock signal simultaneously, a multiplexer with multiple input terminals and multiple output terminals can be used. At this time, the reference clock signal fref and a replicated sampling clock signal are simultaneously connected to the input terminals of the multiplexer, and the control signal is set to select both of these input signals as the output simultaneously.

[0049] It should be noted that the selection of the multiplexer (MUX) depends on the specific application and system architecture. When designing and constructing an analog signal processing system, various factors need to be considered, such as the frequency, stability, and synchronization of the clock signal, etc., and a multiplexer (MUX) suitable for the system should be selected.

[0050] Thus, the clock generation circuit of the present invention is a circuit designed in the intermediate frequency chip, which can directly provide the sampling clock signal and / or the reference clock signal to the baseband chip. In this way, it is not necessary to use multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme.

[0051] The following combines Figure 3A detailed description is given of the clock generation circuit of the intermediate frequency chip of the present invention.

[0052] As Figure 3 shown, the phase-locked loop PLL in the embodiment of the present invention includes: a phase detector PDF, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO, a second frequency divider / N1, and a third frequency divider / N2 connected in sequence; wherein, the first clock signal is a clock signal generated by dividing the output signal fvco of the voltage-controlled oscillator VCO by the second frequency divider.

[0053] The first input terminal and the second input terminal of the phase detector PDF input the above-mentioned reference clock signal fref and the clock signal generated after being divided by the third frequency divider / N2. The phase detector PDF outputs a group of phase difference signals to the charge pump CP, and then the charge pump CP outputs a charging or discharging current to the loop filter LPF. After the low-pass filtering effect of the loop filter LPF, a control voltage is generated, and finally the output frequency of the voltage-controlled oscillator VCO is modulated by this control voltage to generate the final output signal fvco.

[0054] As Figure 3 shown, when the communication interface of the baseband chip, such as a high-speed interface, needs a synchronous clock signal (this synchronous clock signal is used for establishing a link and measuring the delay of the communication interface), the clock generation circuit of the intermediate frequency chip further includes: a fourth frequency divider / N4, which is used to divide the output signal fvco of the voltage-controlled oscillator VCO to generate a third clock signal SYSREF, wherein the third clock signal SYSREF is used to represent the synchronous clock signal SYSREF required by the communication interface of the baseband chip, and the synchronous clock signal SYSREF can be a periodic pulse signal, a single pulse signal or a multi-pulse signal.

[0055] It should be noted that the output frequency of the first frequency divider / N3 is the intermediate frequency signal data rate, and the output frequency of the fourth frequency divider / N4 is the parallel computing processing frequency of the intermediate frequency chip, and the two are usually also in an integer multiple relationship.

[0056] As Figure 3 shown, the phase-locked loop PLL further includes: a buffer Buffer, which is used to buffer the output signal of the voltage-controlled oscillator VCO.

[0057] In an embodiment of the present invention, corresponding clock generation circuits need to be added to both the analog circuit and the digital circuit inside the intermediate frequency chip. Among them: A phase-locked loop PLL (an integer phase-locked loop PLL) is composed of a phase detector PDF, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO, a buffer Buffer, a second frequency divider / N1, and a third frequency divider / N2. The first clock signal Fs_AD is the sampling clock signal of the analog-to-digital converter and is one of the loop clocks of the phase-locked loop PLL, and is phase-synchronized with the reference clock signal fref. The output frequency fvco of the voltage-controlled oscillator VCO can generate the sampling clock signal required by the baseband chip after passing through the second frequency divider / N1 and the first frequency divider / N3, where N3 is the oversampling rate of the analog-to-digital converter and is also equal to the decimation factor of the analog-to-digital converter. The first frequency divider / N3 and the reference clock signal fref can select and output the sampling clock signal or the reference clock signal fref through a multiplexer MUX to adapt to different baseband chips. On the other hand, the output frequency fvco of the voltage-controlled oscillator VCO generates the clock required for the interface only by the fourth frequency divider / N4. This clock frequency is the processing frequency of the parallel clock of the intermediate frequency chip signal, generally named pclk, and can be multiplied by 40 times to generate the interface rate. This clock frequency is supplied to the JESD204B PCS protocol layer to generate multi-frame clock signals, which are generally integer multiples of the synchronous clock signal SYSREF and are generated only after the high-speed serial port is synchronized. Therefore, the clock generation module of the synchronous clock signal SYSREF needs to have two characteristics: one is to divide the frequency to obtain a suitable frequency to be compatible with the baseband chip; the other is to have multiple functions, such as being able to output when powered on, being able to choose not to output, output one or more pulses, output periodically, and be triggered to output by other control signals, etc.

[0058] Figure 4 It is a schematic diagram of the clock scheme between the intermediate frequency chip and the baseband chip according to an embodiment of the present invention.

[0059] As Figure 4 shown, the intermediate frequency module of the present invention includes: an oscillator OCXO, a power splitter, a baseband chip, and the above-mentioned intermediate frequency chip; wherein, the power splitter is used to divide the clock signal output by the oscillator OCXO into a reference clock signal fref and a working clock signal CLK; the intermediate frequency chip is used to generate a target clock signal Data CLK based on the reference clock signal fref; the baseband chip is used to receive the working clock signal CLK and the target clock signal Data CLK.

[0060] Assume that the intermediate frequency chip is applied to satellite Internet. The baseband chip of satellite Internet requires a synchronous clock signal for communication interface link establishment and delay measurement. The clock generation circuit of the intermediate frequency chip will also generate a third clock signal SYSREF. Therefore, the clock signals that the baseband chip can receive at this time include: the working clock signal CLK, the target clock signal DataCLK, and the third clock signal SYSREF.

[0061] In an embodiment of the present invention, as Figure 5 shown, if the working clock signal CLK and the target clock signal DataCLK are not in an integer ratio and the baseband chip does not have a phase-locked loop, then the intermediate frequency module further includes: a clock generation chip, which is used to generate the working clock signal CLK required by the baseband chip based on the working clock signal output by the power divider.

[0062] Thus, the clock scheme between the intermediate frequency chip and the baseband chip of the present invention can save at least one clock generation chip, improve the system integration level, and make the design more convenient; the system reduces the clock sources that may introduce spurs, thereby improving the dynamic performance of the transceiver link.

[0063] The clock generation circuit of the intermediate frequency chip in the embodiment of the present invention includes a phase-locked loop, a first frequency divider, and a multiplexer; wherein, the phase-locked loop is used to generate a first clock signal based on the received reference clock signal, and the first clock signal is used to characterize the clock signal that controls the sampling of the analog-to-digital converter in the intermediate frequency chip when converting an analog signal into a digital signal; the first frequency divider is used to divide the first clock signal to generate a second clock signal, and the second clock signal is used to characterize the sampling clock signal provided by the intermediate frequency chip to the baseband chip; the multiplexer is used to output a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. Thus, the clock generation circuit of the present invention is a circuit designed in the intermediate frequency chip, which can directly provide the sampling clock signal and / or the reference clock signal to the baseband chip, so that it is not necessary to use multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0064] Based on the above embodiments, the present invention also proposes an intermediate frequency chip.

[0065] The intermediate frequency chip in the embodiment of the present invention includes: the clock generation circuit of the intermediate frequency chip as described above.

[0066] The intermediate frequency chip according to an embodiment of the present invention includes the clock generation circuit of the above-mentioned intermediate frequency chip. Through the clock generation circuit of the present invention, a sampling clock signal and / or a reference clock signal can be directly provided to the baseband chip. In this way, there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0067] Based on the above embodiments, the present invention also proposes an intermediate frequency module.

[0068] As Figure 4 shown, the intermediate frequency module according to an embodiment of the present invention includes: an oscillator OCXO, a power splitter, a baseband chip, and the above-mentioned intermediate frequency chip; wherein,

[0069] The power splitter is used to divide the clock signal output by the oscillator OCXO into a reference clock signal and a working clock signal;

[0070] The intermediate frequency chip is used to generate a target clock signal based on the reference clock signal;

[0071] The baseband chip is used to receive the working clock signal and the target clock signal.

[0072] According to an embodiment of the present invention, if the working clock signal and the target clock signal are not in an integer ratio and the baseband chip does not have a phase-locked loop, then the intermediate frequency module as Figure 5 shown further includes:

[0073] A clock generation chip, which is used to generate the working clock signal required by the baseband chip based on the working clock signal output by the power splitter.

[0074] It should be noted that for the details not disclosed in the intermediate frequency module according to the embodiment of the present invention, please refer to the details disclosed in the clock generation circuit of the intermediate frequency chip according to the embodiment of the present invention, and specific details will not be elaborated here.

[0075] The intermediate frequency module according to an embodiment of the present invention includes an oscillator, a power splitter, a baseband chip, and the above-mentioned intermediate frequency chip; wherein, the power splitter is used to divide the clock signal output by the oscillator into a reference clock signal and a working clock signal; the intermediate frequency chip is used to generate a target clock signal based on the reference clock signal; the baseband chip is used to receive the working clock signal and the target clock signal. The intermediate frequency chip of the present invention is designed with a clock generation circuit. Through this clock generation circuit, a sampling clock signal and / or a reference clock signal can be directly provided to the baseband chip. In this way, there is no need for multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0076] Based on the above embodiments, the present invention also proposes a broadband terminal.

[0077] The broadband terminal according to an embodiment of the present invention includes the intermediate frequency module as described above.

[0078] The broadband terminal according to an embodiment of the present invention can directly provide a sampling clock signal and / or a reference clock signal to the baseband chip through the clock generation circuit on the clock chip by using the above intermediate frequency module. In this way, it is not necessary to use multiple clock generation chips to provide clock signals to the on-chip processor of the baseband chip, thereby reducing the cost and complexity of the clock scheme and improving the performance of the intermediate frequency module.

[0079] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0080] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0081] In addition, each functional unit in various embodiments of the present invention can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

Claims

1. A clock generation circuit for an intermediate frequency chip, characterized in that, it includes: a phase-locked loop for generating a first clock signal based on a received reference clock signal, wherein the first clock signal is used to represent the clock signal for controlling the sampling of an analog-to-digital converter in the intermediate frequency chip during the conversion of an analog signal into a digital signal; a first frequency divider for dividing the first clock signal to generate a second clock signal, wherein the second clock signal is used to represent the sampling clock signal provided by the intermediate frequency chip to the baseband chip; a multiplexer for outputting a target clock signal based on the received reference clock signal and the second clock signal, wherein the target clock signal is at least one of the reference clock signal and the second clock signal.

2. The clock generation circuit for the intermediate frequency chip according to claim 1, characterized in that, the phase-locked loop includes: a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a second frequency divider, and a third frequency divider connected in sequence; wherein, the first clock signal is a clock signal generated by dividing the output signal of the voltage-controlled oscillator by the second frequency divider.

3. The clock generation circuit for the intermediate frequency chip according to claim 2, characterized in that, in response to the communication interface of the baseband chip requiring a synchronous clock signal, the clock generation circuit of the intermediate frequency chip further includes: a fourth frequency divider for dividing the output signal of the voltage-controlled oscillator to generate a third clock signal, wherein the third clock signal is used to represent the synchronous clock signal required by the communication interface of the baseband chip.

4. The clock generation circuit for the intermediate frequency chip according to claim 2, characterized in that, the phase-locked loop further includes: a buffer for buffering the output signal of the voltage-controlled oscillator.

5. The clock generation circuit for the intermediate frequency chip according to any one of claims 1-4, characterized in that, the division ratio of the first frequency divider is the oversampling rate or the decimation factor of the analog-to-digital converter.

6. The clock generation circuit for the intermediate frequency chip according to any one of claims 1-4, characterized in that, in response to different receive data rates and transmit data rates of the intermediate frequency chip, the frequency of the second clock signal is in a multiple relationship with the greatest common divisor of the receive data rate and the transmit data rate.

7. An intermediate frequency chip, characterized in that, it includes: the clock generation circuit for the intermediate frequency chip according to any one of claims 1-6.

8. An intermediate frequency module, characterized in that, it includes: an oscillator, a power splitter, a baseband chip, and the intermediate frequency chip according to claim 7; wherein, the power splitter is used to divide the clock signal output by the oscillator into a reference clock signal and a working clock signal; the intermediate frequency chip is used to generate the target clock signal based on the reference clock signal; the baseband chip is used to receive the working clock signal and the target clock signal.

9. The intermediate frequency module according to claim 8, characterized in that, The working clock signal and the target clock signal are not in an integer ratio, and the baseband chip does not have a phase-locked loop. The intermediate frequency module further includes: A clock generation chip for generating the working clock signal required by the baseband chip based on the working clock signal output by the power splitter.

10. A broadband terminal Characterized in that it includes: The intermediate frequency module according to claim 8 or 9.

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