Clock input buffer and electronic equipment

Abstract

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

Description

Technical Field

[0001] This application relates to the field of circuit technologies, and particularly to a clock input buffer and an electronic device. Background Art

[0002] With the development of high-speed applications such as 5G communication, artificial intelligence, and cellular facilities, the number of protocols that chips need to be compatible with is increasing, and the clock frequency is also getting higher. There is an increasingly wide demand for high-speed clock buffer circuits that can meet a wide operating voltage range.

[0003] However, in the design of high-speed modules, the intrinsic frequency and breakdown voltage of general MOS devices have an inverse relationship, that is, the higher the intrinsic frequency of the device, the lower the breakdown voltage. This is because to increase the intrinsic frequency, the gate capacitance and channel resistance need to be reduced. However, reducing the gate capacitance will reduce the gate area of the device, thereby reducing the breakdown voltage. Similarly, reducing the channel resistance will increase the channel doping concentration, thereby also reducing the breakdown voltage. And high-speed buffer modules with a wide operating voltage range usually need to have both a high intrinsic frequency and a high breakdown voltage at the same time. Due to this trade-off relationship, the design of high-speed buffer modules with a wide operating voltage range becomes very difficult. Summary of the Invention

[0004] The main purpose of this application is to provide a clock input buffer and an electronic device, which can at least solve the problem in related technologies that it is difficult to achieve high-speed clock transmission within a wide operating voltage range.

[0005] To achieve the above object, in the first aspect of this application, a clock input buffer is provided, including: a multi-protocol input circuit, a level conversion circuit, a step-down circuit, and a clock buffer circuit; the multi-protocol input circuit is electrically connected to the level conversion circuit and is used to be electrically connected to an external signal generator and a control unit, and the clock buffer circuit is electrically connected to the step-down circuit and the level conversion circuit respectively; the multi-protocol input circuit is configured to: switch to a target operating mode according to a control signal output by the control unit, and process an input signal based on the target operating mode; the level conversion circuit is configured to: perform level conversion on the output signal of the multi-protocol input circuit to obtain a low-voltage domain signal; the step-down circuit is configured to: convert a power supply voltage into a target power supply voltage and transmit it to the clock buffer circuit; the clock buffer circuit is configured to: buffer the low-voltage domain signal and then transmit it to an external load.

[0006] In the third aspect of this application, an electronic device is provided, including the clock input buffer as described in the first aspect of this application.

[0007] As can be seen from the above description, the present application adjusts the multi - protocol input circuit to different operating modes through the control signal transmitted by the control unit to be compatible with multiple input protocols. The multi - protocol input circuit processes input signals such as high - speed data or clock signals transmitted by the signal generator based on the target operating mode, and transmits the processed signals to the level - conversion circuit. The level - conversion circuit performs a level shift on the output signal of the multi - protocol input circuit to convert the output signal into a low - voltage domain signal, thereby meeting the working voltage requirements of the clock buffer circuit and realizing buffering of signals within a wide input voltage range. At the same time, the buck - down circuit performs a buck - down process on the power supply voltage to provide a low - voltage power supply voltage for the clock buffer circuit. Thus, the clock buffer circuit can use low - voltage domain devices to achieve high - speed signal buffering within a wide input voltage range, realizing high - speed signal matching and buffering within different input protocols and voltage ranges, and greatly expanding the application scenarios of the clock input buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0009] Figure 1 is a schematic structural diagram of a clock input buffer according to an embodiment of the present application;

[0010] Figure 2 is a circuit schematic diagram of a multi - protocol input circuit according to an embodiment of the present application;

[0011] Figure 3 is a circuit schematic diagram of a level - conversion circuit according to an embodiment of the present application;

[0012] Figure 4 is a circuit schematic diagram of a buck - down circuit according to an embodiment of the present application;

[0013] Figure 5 is a circuit schematic diagram of a clock buffer circuit according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] In order to make the invention objectives, features, and advantages of the present application more obvious and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0015] In the related art, due to the problem that it is difficult to achieve high-speed clock transmission within a wide operating voltage range, an embodiment of the present application provides a clock input buffer.

[0016] As Figure 1 shown is a schematic structural diagram of a clock input buffer provided by an embodiment of the present application. The clock input buffer includes: a multi-protocol input circuit 100, a level conversion circuit 200, a step-down circuit 300, and a clock buffer circuit 400; the multi-protocol input circuit 100 is electrically connected to the level conversion circuit 200 and is used to be electrically connected to an external signal generator 500 and a control unit 600, and the clock buffer circuit 400 is respectively electrically connected to the step-down circuit 300 and the level conversion circuit 200, wherein:

[0017] The multi-protocol input circuit 100 is configured to: switch to a target operating mode according to a control signal output by the control unit 600, and process an input signal based on the target operating mode; the level conversion circuit 200 is configured to: perform level conversion on the output signal of the multi-protocol input circuit 100 to obtain a low-voltage domain signal; the step-down circuit 300 is configured to: convert a power supply voltage into a target power supply voltage and transmit it to the clock buffer circuit 400; the clock buffer circuit 400 is configured to: buffer the low-voltage domain signal and then transmit it to an external load.

[0018] Specifically, in this embodiment, the multi-protocol input circuit 100 can be adjusted to different operating modes through a control signal transmitted by the control unit 600 to be compatible with multiple input protocols. The multi-protocol input circuit 100 processes input signals such as high-speed data or clock signals transmitted by the signal generator 500 based on the target operating mode, and transmits the processed signal to the level conversion circuit 200. The level conversion circuit 200 performs level transfer on the output signal of the multi-protocol input circuit 100 to convert the output signal into a low-voltage domain signal, so as to meet the working voltage requirement of the clock buffer circuit 400 and realize buffering of signals within a wide input voltage range; at the same time, the step-down circuit 300 provides a low-voltage power supply voltage for the clock buffer circuit 400 by performing step-down processing on the power supply voltage. Thus, the clock buffer circuit 400 can use low-voltage domain devices to realize buffering of high-speed signals within a wide input voltage range. The clock input buffer of this embodiment is integrated at the input stage of the clock chip to realize buffering and matching of high-speed input signals within a wide operating voltage range.

[0019] As Figure 2 shown is a circuit schematic diagram of a multi-protocol input circuit 100 provided by an embodiment of the present application. Please refer to Figure 2, the multi - protocol input circuit 100 includes a common - mode voltage selection unit 110, a pull - down resistor selection unit 120, and an impedance selection unit 130; the common - mode voltage selection unit 110 is electrically connected to the pull - down resistor selection unit 120 and is used to be electrically connected to a control unit 600 ( Figure 2 not shown in the figure), the impedance selection unit 130 is respectively electrically connected to the pull - down resistor selection unit 120 and a level - conversion circuit 200 and is used to be electrically connected to a signal generator 500 and the control unit 600, and the pull - down resistor selection unit 120 is also used to be electrically connected to the control unit 600; where:

[0020] The multi - protocol input circuit 100 is configured as follows: when receiving a first control signal output by the control unit 600, the common - mode voltage selection unit 110 enters the working state, and the multi - protocol input circuit 100 switches to the AC - coupling mode; when receiving a second control signal output by the control unit 600, the pull - down resistor selection unit 120 enters the working state, and the multi - protocol input circuit 100 switches to the LVPECL mode; and, the impedance selection unit 130 is adjusted according to a third control signal output by the control unit 600 to generate a target impedance.

[0021] Specifically, in this embodiment, the signal generator 500 transmits the generated high - speed signal or clock signal to the multi - protocol input circuit 100 through the non - inverting input terminal and the inverting input terminal. The multi - protocol input circuit 100 can be switched to different working modes through the control word transmitted by the control unit 600 to adapt to different external protocol inputs. For example, by accessing the common - mode voltage selection unit 110, the multi - protocol input circuit 100 can enter the AC - coupling mode, and when accessing the pull - down resistor selection unit 120, the multi - protocol input circuit 100 can enter the LVPECL mode. By adjusting the impedance selection unit 130, different input impedances can be provided for the clock input buffer to achieve impedance matching of the input port.

[0022] Furthermore, please refer to Figure 2 , the common - mode voltage selection unit 110 includes a first common - mode voltage supply unit, a first switching device S1, and a first capacitor C1; the first switching device S1 is respectively electrically connected to the first common - mode voltage supply unit, one end of the first capacitor C1, and the pull - down resistor selection unit 120 and is used to be electrically connected to the control unit 600, and the other end of the first capacitor C1 is grounded; the first switching device S1 is configured as follows: when receiving the first control signal, it enters the conducting state; where, when the first switching device S1 enters the conducting state, the first common - mode voltage supply unit provides a common - mode voltage for the input signal; the first capacitor C1 is configured as follows: filter the common - mode voltage.

[0023] Specifically, in this embodiment, the first switching device S1 is used to select the AC coupling mode. When the control unit 600 controls the first switching device S1 to close, the multi-protocol input circuit 100 enters the AC coupling input mode. In this mode, the DC component of the input signal is blocked, and only the AC signal is allowed to pass through, so as to eliminate the DC bias in the input signal and avoid affecting the circuit. In this mode, the first common-mode voltage supply unit provides the common-mode voltage VCM for the input signal and filters the common-mode voltage through the first capacitor C1. Here, the common-mode voltage refers to the average voltage on the two transmission lines of the differential signal; by providing the internal common-mode voltage through the first common-mode voltage supply unit, the common-mode point of the input signal is provided by the internal circuit at this time, which can adapt to the external AC coupling input. When the first switching device S1 is disconnected, the multi-protocol input circuit 100 enters the DC coupling input mode, and the DC operating point is provided by the external signal.

[0024] Furthermore, please refer to Figure 2 , the pull-down resistor selection unit 120 includes a first resistor R1 and a second switching device S2; one end of the first resistor R1 is electrically connected to the first end of the second switching device S2, the other end of the first resistor R1 is grounded, the second end of the second switching device S2 is respectively electrically connected to the common-mode voltage supply unit and the impedance selection unit 130, and the third end of the second switching device S2 is used to be electrically connected to the control unit 600; the second switching device S2 is configured to: when receiving the second control signal, enter the conducting state; wherein, when the second switching device S2 enters the conducting state, the first resistor R1 provides a pull-down resistor for the LVPECL mode.

[0025] Specifically, in this embodiment, the second switching device S2 is used to select the LVPECL mode. When the control unit 600 controls the second switching device S2 to close, the multi-protocol input circuit 100 enters the LVPECL mode, which is a differential signal transmission method and can be used for high-speed data transmission; in this mode, the internal first resistor R1 is connected into the circuit to provide a pull-down resistor for the LVPECL protocol.

[0026] Furthermore, please refer to Figure 2, the impedance selection unit 130 includes a first adjustable resistor R2 and a second adjustable resistor R3; the first end of the first adjustable resistor R2 is electrically connected to the level conversion circuit 200 and is used to be electrically connected to the signal generator 500, and the second end of the first adjustable resistor R2 is respectively electrically connected to the pull-down resistor selection unit 120 and the first end of the second adjustable resistor R3, and the second end of the second adjustable resistor R3 is electrically connected to the level conversion circuit 200 and is used to be electrically connected to the signal generator 500; the third ends of the first adjustable resistor R2 and the second adjustable resistor R3 are both used to be electrically connected to the control unit 600; the first adjustable resistor R2 and the second adjustable resistor R3 are both configured to: generate a target impedance according to the third control signal.

[0027] Specifically, in this embodiment, the multi-protocol input circuit 100 is further provided with adjustable resistors, and the control unit 600 can adjust the resistance values of the adjustable resistors to obtain different differential impedances. The first adjustable resistor R2 and the second adjustable resistor R3 in this embodiment are both provided with three gears of 50Ω, 100Ω, and 1KΩ, so as to realize the selection of three gears of differential 100Ω, differential 200Ω, and differential 2KΩ to meet the requirements of different input impedances. By adjusting the input impedance, the multi-protocol input circuit 100 can enter the high-impedance mode, at this time the input path is disconnected, and the input port presents a high-impedance state.

[0028] As Figure 3 shown is the circuit schematic diagram of a level conversion circuit 200 provided by an embodiment of the present application, please refer to Figure 3 , the level conversion circuit 200 includes a first AC coupling unit 210, a second AC coupling unit 220, and a second common-mode voltage supply unit; the first end of the first AC coupling unit 210 is electrically connected to the multi-protocol input circuit 100, the second end of the first AC coupling unit 210 is electrically connected to the clock buffer circuit 400, the third end of the first AC coupling unit 210 is respectively electrically connected to the second common-mode voltage supply unit and the first end of the second AC coupling unit 220, the second end of the second AC coupling unit 220 is electrically connected to the multi-protocol input circuit 100, and the third end of the second AC coupling unit 220 is electrically connected to the clock buffer circuit 400.

[0029] Further, please refer to Figure 3 , both the first AC coupling unit 210 and the second AC coupling unit 220 include a second capacitor C2 / C3 and a second resistor R4 / R5; one end of the second capacitor C2 / C3 is electrically connected to the multi-protocol input circuit 100, the other end of the second capacitor C2 / C3 is respectively electrically connected to one end of the second resistor R4 / R5 and the clock buffer circuit 400, and the other end of the second resistor R4 / R5 is electrically connected to the second common-mode voltage supply unit.

[0030] Specifically, in this embodiment, the level conversion circuit 200 includes a first AC coupling unit 210 and a second AC coupling unit 220, which respectively correspond to the non-inverting input terminal and the inverting input terminal. Through AC coupling, the level conversion circuit 200 can convert the common-mode level of an externally input signal into a common-mode voltage that meets the operating requirements of high-speed devices inside the clock buffer circuit 400. Among them, both the first AC coupling unit 210 and the second AC coupling unit 220 can achieve AC coupling through an RC high-pass filter. According to the calculation formula of the high-pass frequency: It can be known that the high-pass frequency can be adjusted by setting the magnitudes of the second capacitors and second resistors in the first AC coupling unit 210 and the second AC coupling unit 220 to meet the actual operating frequency. A second common-mode voltage supply unit established internally is provided between the first AC coupling unit 210 and the second AC coupling unit 220, which is used to provide a common-mode voltage point for the signal after AC coupling. This common-mode voltage meets the voltage requirements of the subsequent circuit, that is, the clock buffer circuit 400. Due to the effect of AC coupling, the level conversion circuit 200 transfers the common-mode point of the external operating voltage to the internally set common-mode voltage, thereby achieving level conversion. As long as the withstand voltage of the capacitors in the AC coupling unit meets the conditions, the safety of the operating voltage range of the devices in the clock buffer circuit 400 can be ensured.

[0031] As Figure 4 shown is the circuit schematic diagram of a buck circuit 300 provided by an embodiment of the present application. Please refer to Figure 4 , the buck circuit 300 includes a plurality of buck units 310 connected in series. The buck unit 310 includes a third switching device K1 / Km (m≥2) and a plurality of sub-buck units 311; the sub-buck units 311 are connected in parallel with the third switching device K1 / Km. One end of the third switching device K1 / Km in the first buck unit 310 is electrically connected to the power supply, and the other end of the third switching device K1 / Km in the first buck unit 310 is electrically connected to the third switching device K1 / Km in the next buck unit 310. One end of the third switching device K1 / Km in the last buck unit 310 is electrically connected to the third switching device K1 / Km in the previous buck unit 310, and the other end of the third switching device K1 / Km in the last buck unit 310 is electrically connected to the clock buffer circuit 400. The third terminal of the third switching device K1 / Km is used to be electrically connected to the control unit 600 ( Figure 4 not shown in the figure).

[0032] Further, please refer to Figure 4, the sub-step-down unit 311 further includes a fourth switching device and a MOS transistor; the first end of the fourth switching device is electrically connected to the first end of the third switching device K1 / Km, the second end of the fourth switching device is electrically connected to the source of the MOS transistor, the third end of the third switching device K1 / Km is used to be electrically connected to the control unit 600, and the gate and drain of the MOS transistor are both electrically connected to the second end of the third switching device K1 / Km.

[0033] Specifically, in this embodiment, the step-down circuit 300 is used to step down a relatively high power supply voltage to a voltage range that meets the requirements of the internal devices of the clock buffer circuit 400, and then supply the stepped-down power supply voltage to the clock buffer circuit 400. The step-down circuit 300 in this embodiment is configurable. The step-down circuit 300 includes an array of multiple step-down units 310. The step-down units 310 can be selected through the control word output by the control unit 600. When different step-down units 310 are connected to the circuit, the relatively high-voltage power supply voltage can be stepped down to different values. The multiple step-down units 310 in this embodiment are connected in series, and each step-down unit 310 includes a third switching device K1 / Km and multiple sub-step-down units 311. The third switching device is connected in parallel with the sub-step-down unit 311. Thus, the control unit 600 can roughly adjust the power supply voltage by controlling the number of step-down units 310 connected to the circuit, and then finely adjust the power supply voltage by adjusting the number of sub-step-down units 311 connected in each step-down unit 310. The sub-step-down unit 311 includes a fourth switching device and a MOS device such as Figure 4 the PMOS transistor in, and by adjusting the number of PMOS transistors connected, the voltage drop of the step-down unit 310 can be adjusted. The voltage drop of each step-down unit 310 is: where I is the current flowing through the step-down unit 310, N is the number of MOS transistors connected to the step-down unit 310, K is the coefficient for converting current into overdrive voltage, and Vth is the threshold voltage of the MOS transistor device. By adjusting the number of step-down units 310 connected, the voltage drop generated by the step-down circuit 300 is adjusted. The step-down value of the step-down circuit is:

[0035] where N 1 、N mrespectively represent the number of MOS transistors connected in the first and the m-th step-down units 310. K1 and Km respectively represent whether the third switching devices in the first and the m-th step-down units 310 are disconnected. When disconnected, their values are 1, and when closed, their values are 0 (when the third switching device is closed, the corresponding step-down unit 310 is bypassed). Thus, by adjusting the step-down circuit 300 through the array control word output by the control unit 600, the high-voltage power supply can be reduced to meet the safe operating voltage range of the high-speed low-voltage devices in the clock buffer circuit 400, so as to avoid the problem of overvoltage of the operating voltage of the high-speed devices.

[0036] As Figure 5 shown is the circuit schematic diagram of a clock buffer circuit 400 provided by an embodiment of the present application. Please refer to Figure 5 , the clock buffer circuit 400 includes a third resistor R6, a fourth resistor R7, a first driving transistor NM1, a second driving transistor NM2, and a tail current transistor Itail. One ends of the third resistor R6 and the fourth resistor R7 are both electrically connected to the step-down circuit 300. The other end of the third resistor R6 is electrically connected to the drain of the first driving transistor NM1 and is used for electrically connecting to an external load. The other end of the fourth resistor R7 is electrically connected to the drain of the second driving transistor NM2 and is used for electrically connecting to an external load. The gates of the first driving transistor NM1 and the second driving transistor NM2 are both electrically connected to the level conversion circuit 200. The sources of the first driving transistor NM1 and the second driving transistor NM2 are both electrically connected to one end of the tail current transistor Itail, and the other end of the tail current transistor Itail is grounded.

[0037] Specifically, in this embodiment, the clock buffer circuit 400 is used to buffer the input signal to provide appropriate drive, output level, and swing. The clock buffer circuit 400 in this embodiment is CML (Current Mode Logic), and its output swing is: Vout = R × I tail , where R is the resistance value of the load resistor, that is, the resistance value of the third resistor R6 or the fourth resistor R7, and I tail is the current of the tail current transistor Itail. Since high-speed data transmission needs to be satisfied, generally, it is required that: F work <1 / (2π×R×C load ), where C load is the output load capacitance, and F workis the operating frequency. According to the above formula, it can be known that the value of the load resistor R can be determined according to the operating frequency and the size of the load capacitance. Since the voltage of the input signal and the power supply voltage have been reduced to the safe operating area of the high-speed device through the AC-coupled level conversion circuit 200 and the configurable buck circuit 300. Therefore, in this embodiment, high-speed CMOS devices NM1 and NM2 in the low-voltage domain can be used as the input driving transistors. Generally, it is required that the cut-off frequency of the driving device be greater than 10 times the operating frequency, and the high-speed low-voltage devices can be selected and designed accordingly.

[0038] The clock input buffer circuit provided by the embodiment of the present application adjusts the multi-protocol input circuit to different operating modes through the control signal transmitted by the control unit to be compatible with multiple input protocols. The multi-protocol input circuit processes input signals such as high-speed data or clock signals transmitted by the signal generator based on the target operating mode, and transmits the processed signal to the level conversion circuit. The level conversion circuit performs a level shift on the output signal of the multi-protocol input circuit to convert the output signal into a low-voltage domain signal, so as to meet the working voltage requirements of the clock buffer circuit and realize buffering of signals in a wide input voltage range; at the same time, the buck circuit performs a buck processing on the power supply voltage to provide a low-voltage power supply voltage for the clock buffer circuit. Thus, the clock buffer circuit can use low-voltage domain devices to achieve high-speed signal buffering in a wide input voltage range, realizing high-speed signal matching and buffering in different input protocols and voltage ranges, and greatly expanding the application scenarios of the clock input buffer.

[0039] The embodiment of the present application also provides an electronic device, and the electronic device includes the above-mentioned clock input buffer.

[0040] It should be noted that the various embodiments in the content of the present application are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0041] It should also be noted that in the content of this application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of this application, the meaning of "a plurality" is two or more, unless otherwise specifically defined. The term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0042] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the content of this application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the content of this application can be implemented in other embodiments without departing from the spirit or scope of the content of this application. Therefore, the content of this application will not be limited to these embodiments shown in the content of this application, but rather will be accorded the widest scope consistent with the principles and novel features disclosed in the content of this application.

Claims

1. A clock input buffer, characterized in that: include: A multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit; the multi-protocol input circuit is electrically connected to the level conversion circuit and is used to be electrically connected to an external signal generator and a control unit, and the clock buffer circuit is electrically connected to the step-down circuit and the level conversion circuit respectively; The multi-protocol input circuit is configured to: switch to a target operating mode according to a control signal output by the control unit, and process an input signal based on the target operating mode; The level conversion circuit is configured to: perform level conversion on the output signal of the multi-protocol input circuit to obtain a low voltage domain signal; The step-down circuit is configured to: convert the power supply voltage into a target power supply voltage and transmit the target power supply voltage to the clock buffer circuit; The clock buffer circuit is configured to: buffer the low voltage domain signal and then transmit it to an external load.

2. The clock input buffer according to claim 1, wherein: The multi-protocol input circuit includes a common mode voltage selection unit, a pull-down resistor selection unit and an impedance selection unit; The common mode voltage selection unit is electrically connected to the pull-down resistor selection unit and is used to be electrically connected to the control unit, the impedance selection unit is electrically connected to the pull-down resistor selection unit and the level conversion circuit respectively and is used to be electrically connected to the signal generator and the control unit, and the pull-down resistor selection unit is also used to be electrically connected to the control unit; The multi-protocol input circuit is configured such that: when receiving the first control signal output by the control unit, the common mode voltage selection unit enters the working state, and the multi-protocol input circuit switches to the AC coupling mode; When receiving the second control signal output by the control unit, the pull-down resistor selection unit enters the working state, and the multi-protocol input circuit switches to the LVPECL mode; And, the impedance selection unit is adjusted according to the third control signal output by the control unit to generate a target impedance.

3. The clock input buffer according to claim 2, characterized in that: The common mode voltage selection unit includes a first common mode voltage supply unit, a first switch device and a first capacitor; The first switch device is electrically connected to the first common-mode voltage supply unit, one end of the first capacitor, and the pull-down resistor selection unit respectively and is used to be electrically connected to the control unit, and the other end of the first capacitor is grounded; The first switch device is configured to: enter a conducting state when receiving the first control signal; wherein when the first switch device enters the conducting state, the first common-mode voltage supply unit provides a common-mode voltage for the input signal; The first capacitor is configured to filter the common mode voltage.

4. The clock input buffer according to claim 2, characterized in that: The pull-down resistor selection unit includes a first resistor and a second switch device; One end of the first resistor is electrically connected to the first end of the second switch device, the other end of the first resistor is grounded, the second end of the second switch device is electrically connected to the common mode voltage supply unit and the impedance selection unit respectively, and the third end of the second switch device is used to be electrically connected to the control unit; The second switch device is configured to enter a conducting state when receiving the second control signal; wherein, when the second switch device enters the conducting state, the first resistor provides a pull-down resistor for the LVPECL mode.

5. The clock input buffer according to claim 2, characterized in that: The impedance selection unit includes a first adjustable resistor and a second adjustable resistor; The first end of the first adjustable resistor is electrically connected to the level conversion circuit and is used to be electrically connected to the signal generator, the second end of the first adjustable resistor is electrically connected to the pull-down resistor selection unit and the first end of the second adjustable resistor respectively, the second end of the second adjustable resistor is electrically connected to the level conversion circuit and is used to be electrically connected to the signal generator; the third ends of the first adjustable resistor and the second adjustable resistor are both used to be electrically connected to the control unit; The first adjustable resistor and the second adjustable resistor are both configured to generate a target impedance according to the third control signal.

6. The clock input buffer according to claim 1, wherein: The level conversion circuit includes a first AC coupling unit, a second AC coupling unit and a second common mode voltage supply unit; A first end of the first AC coupling unit is electrically connected to the multi-protocol input circuit, a second end of the first AC coupling unit is electrically connected to the clock buffer circuit, a third end of the first AC coupling unit is electrically connected to the second common-mode voltage supply unit and the first end of the second AC coupling unit respectively, a second end of the second AC coupling unit is electrically connected to the multi-protocol input circuit, and a third end of the second AC coupling unit is electrically connected to the clock buffer circuit.

7. The clock input buffer according to claim 6, characterized in that: The first AC coupling unit and the second AC coupling unit both include a second capacitor and a second resistor; One end of the second capacitor is electrically connected to the multi-protocol input circuit, the other end of the second capacitor is electrically connected to one end of the second resistor and the clock buffer circuit respectively, and the other end of the second resistor is electrically connected to the second common-mode voltage supply unit.

8. The clock input buffer according to claim 1, wherein: The buck circuit comprises a plurality of buck units connected in series, wherein the buck unit comprises a third switch device and a plurality of sub-buck units; The sub-buck unit is connected in parallel with the third switch device, one end of the third switch device in the first buck unit is electrically connected to the power supply, the other end of the third switch device in the first buck unit is electrically connected to the third switch device in the next buck unit, one end of the third switch device in the last buck unit is electrically connected to the third switch device in the previous buck unit, the other end of the third switch device in the last buck unit is electrically connected to the clock buffer circuit, and the third end of the third switch device is used to be electrically connected to the control unit.

9. The clock input buffer according to claim 8, characterized in that: The sub-step-down unit further includes a fourth switch device and a MOS tube; The first end of the fourth switch device is electrically connected to the first end of the third switch device, the second end of the fourth switch device is electrically connected to the source of the MOS tube, the third end of the third switch device is used to be electrically connected to the control unit, and the gate and drain of the MOS tube are both electrically connected to the second end of the third switch device.

10. The clock input buffer according to claim 1, wherein: The clock buffer circuit includes a third resistor, a fourth resistor, a first drive tube, a second drive tube and a tail current tube; One end of the third resistor and the fourth resistor are both electrically connected to the step-down circuit, the other end of the third resistor is electrically connected to the drain of the first drive tube and is used to be electrically connected to an external load, the other end of the fourth resistor is electrically connected to the drain of the second drive tube and is used to be electrically connected to an external load, the gates of the first drive tube and the second drive tube are both electrically connected to the level conversion circuit, the sources of the first drive tube and the second drive tube are both electrically connected to one end of the tail current tube, and the other end of the tail current tube is grounded.

11. The clock input buffer according to claim 10, characterized in that: The first driving transistor and the second driving transistor are low voltage domain CMOS devices.

12. An electronic device, characterized in that: Comprising a clock input buffer as claimed in any one of claims 1 to 11.

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