Anti-aliasing downsampling circuit, circuit module, chip and signal processing device

Abstract

The present application provides an anti-aliasing downsampling circuit, a circuit module, a chip and a signal processing device. The circuit includes a register, a module I Counter, multiplier, adder tree, multiplexer, adder, accumulator register and latch register; registers store different data in different clock cycles; module I The value of the counter variable increases with the change of the clock cycle. The filter coefficient selected according to the value of the count variable and the data stored in the preset register are input to the corresponding multiplier; the adder tree performs addition operation on the output result of the multiplier; under the control of the value of the count variable, the multiplexer selects to output 0 or the output result of the accumulator register, and the adder performs addition operation on the output result of the adder tree and the result selected by the multiplexer; the accumulator register stores the output result of the adder and uses the stored result as I The down-sampled result is fed into the adder via a multiplexer.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing, and in particular to an anti-aliasing downsampling circuit, circuit module, chip and signal processing device. Background Art

[0002] In the field of digital signal processing, downsampling, a common technique for reducing signal sampling rates, has significant application value. However, direct downsampling can easily cause high-frequency components in the signal spectrum to fold into the low-frequency portion, causing aliasing and severely impacting signal quality. To effectively address this issue, anti-aliasing filters are typically used before downsampling to remove high-frequency components above the Nyquist frequency. Currently, anti-aliasing filters are typically FIR filters. As non-recursive filters, their output depends solely on the input, offering advantages such as linear phase and stability.

[0003] However, existing downsampling technology has certain drawbacks. Implementing the anti-aliasing filter and the downsampling decimation circuit separately in the downsampling circuit generates a large number of redundant operations. These redundant operations not only increase processing complexity but also significantly increase the power consumption of the downsampling circuit. This is detrimental to the energy efficiency and efficient operation of digital signal processing equipment, limiting its application in power-demanding scenarios. Therefore, a new anti-aliasing downsampling circuit is urgently needed to reduce redundant operations. Summary of the Invention

[0004] Based on the above situation, the main purpose of this application is to provide an anti-aliasing downsampling circuit, circuit module, chip and signal processing device to reduce redundant operations.

[0005] To achieve the above objectives, the technical solutions adopted in this application are as follows:

[0006] The embodiment of the present application provides an anti-aliasing downsampling circuit, comprising: a register, a module I counters, multipliers, adder trees, multiplexers, adders, and accumulator registers;

[0007] The register stores different data at different clock cycles;

[0008] The mold I The value of the count variable of the counter increases as the clock cycle changes, and a filter coefficient is selected according to the value of the count variable. The filter coefficient and the data stored in the preset register are input into the corresponding multiplier for multiplication operation;

[0009] The adder tree performs an addition operation on the output results of all the multipliers;

[0010] The multiplexer is in the mode IUnder the numerical control of the counting variable of the counter, the output is selected to be 0 or the output result of the accumulator register, and the adder performs an addition operation on the output result of the adder tree and the result selected and output by the multiplexer;

[0011] The accumulator register stores the output result of the adder and uses the stored result as I The result is output by downsampling, or the stored result is input into the adder through the multiplexer.

[0012] As an option, the register is a shift register, and the shift register is set to M indivual.

[0013] As an option, M The shift register is divided into register groups, each of which includes I A shift register, I The data stored in one of the shift registers participates in the multiplication operation. I The data stored in -1 register is shifted to the next adjacent register according to the change of the clock cycle; wherein the register participating in the multiplication operation is the last register in the register group.

[0014] As an option, according to the number of the shift registers M and model I modulus of the counter I ,Will M +1 filter coefficient written coefficient tables, each of which has I filter coefficients.

[0015] As an option, the multiplier is provided with In one clock cycle, the adder tree The output results of the multipliers are added.

[0016] As an option, the value of the count variable ranges from 0 to I -1.

[0017] Optionally, when the value of the counting variable is 0, the multiplexer selects to output 0, the adder performs an addition operation on 0 and the output result of the 0th group of the adder tree, and the output result of the adder is stored in the accumulator register.

[0018] Optionally, the output result of group 0 of the adder tree is:

[0019] ,

[0020] Where, 、 、……、 They respectively represent the filter coefficients corresponding to when the value of the count variable is 0, Respectively represent the input data of the anti-aliasing downsampling circuit and the 1st, 2nd, ..., ( M +1) / I -1 The input data stored in the last register of the register group, r Indicates the index of the downsampled data.

[0021] As an option, when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

[0022] Alternatively, the value of the counter variable is greater than 0 and less than or equal to I -1, the multiplexer selects to output the data stored in the accumulator register, and the adder performs summation on the data stored in the accumulator register and the data from the first group to the first group of the adder tree. I -1 group of output results are iteratively added, and the output results of the adder are stored in the accumulator register.

[0023] Optionally, the value of the counter variable is I -1, the accumulator register stores the result as I The downsampling result is I The down-sampling result is input into the latch register for temporary storage.

[0024] An embodiment of the present application further provides a circuit module, comprising any of the above-mentioned anti-aliasing downsampling circuits.

[0025] An embodiment of the present application further provides a chip comprising any of the above-mentioned anti-aliasing downsampling circuits.

[0026] An embodiment of the present application also provides a signal processing device, including the above-mentioned circuit module or chip.

[0027] The anti-aliasing downsampling circuit provided in the embodiment of the present application is configured to set registers, I Counters, multipliers, adder trees, multiplexers, adders, and accumulator registers distribute multiplication and addition operations evenly across the I In one clock cycle, the multiplier and adder tree are IMultiplexing eliminates redundant operations, saving significant computation time. Calculations that would normally require multiple clock cycles can be completed in a shorter timeframe, thereby improving the overall computational speed of the circuit system. Redundant operations typically occupy logic resources such as multipliers and adders within a circuit. Eliminating these redundant operations frees up these resources, improving resource utilization. Intermediate results generated by redundant operations typically need to be stored in registers. Eliminating these redundant operations saves storage resources.

[0028] The circuit module provided in the embodiment of the present application has excellent anti-aliasing performance and flexible downsampling capability, while integrating other practical functions to meet the diverse signal processing requirements of different applications.

[0029] The chip provided in the embodiment of the present application integrates the above-mentioned anti-aliasing downsampling circuit, which can prevent spectrum aliasing and ensure the integrity of the sampled signal spectrum; improve signal quality and filter out high-frequency noise interference; reduce sampling rate requirements and reduce hardware costs and power consumption.

[0030] Other beneficial effects of the present application will be explained through the introduction of specific technical features and technical solutions in the specific implementation methods. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Preferred embodiments of the present application will be described below with reference to the accompanying drawings.

[0032] Figure 1 It is a structural block diagram of the anti-aliasing downsampling module in the prior art;

[0033] Figure 2 for Figure 1 The specific implementation structure block diagram of the anti-aliasing downsampling module;

[0034] Figure 3 This is a structural block diagram of an anti-aliasing downsampling circuit according to a preferred embodiment of the present application.

[0035] In the figure: 1. Register; 2. Module I Counter; 3. Multiplier; 4. Adder tree; 5. Multiplexer; 6. Accumulator register; 7. Adder; 8. Latch register. DETAILED DESCRIPTION

[0036] The present application is described below based on examples, but the present application is not limited to these examples. In the detailed description of the present application below, some specific details are described in detail. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, and components are not described in detail.

[0037] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0038] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include," "comprising," and similar words should be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to."

[0039] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0040] In digital signal processing systems, it's sometimes necessary to reduce the signal's sampling rate, known as downsampling. Before downsampling, the digital signal must be filtered using an anti-aliasing filter. This is because downsampling changes the signal's spectrum. If components with frequencies above half the new sampling rate (the Nyquist frequency) are not pre-filtered, aliasing will occur. For example, in video processing, when downsampling a high-frame-rate video to a lower frame rate, the video signal is first processed using a digital anti-aliasing filter to remove high-frequency components before downsampling to prevent aliasing distortion.

[0041] Since FIR (Finite Impulse Response) filters can accurately control the frequency response and achieve good low-pass characteristics by designing appropriate filter coefficients, FIR filters are often used as anti-aliasing filters.

[0042] like Figure 1 As shown, the anti-aliasing downsampling module in the prior art mainly includes an anti-aliasing filter and I The output of the downsampling decimator and the anti-aliasing filter are connected to I The input of the downsampling decimator is connected to I The downsampling decimator is used to output the downsampled result. Assume that the anti-aliasing filter adopts Figure 2 shown M The unit impulse response of the FIR filter is Indicates that the input of the FIR filter is , the output is .

[0043] in, M Unit impulse response of an FIR filter of order Expressed as:

[0044] (1)

[0045] It has the generalized linear phase characteristic condition, namely:

[0046] ,or .

[0047] Output of the FIR filter for:

[0048] (2)

[0049] In formula (2), h ( k ) represents the first k coefficients, x ( n − k ) indicates the input signal x ( n )Delay k signal after a clock cycle.

[0050] I Downsampling decimator every I Output 1 valid result per clock cycle :

[0051] (3)

[0052] In formula (3), x ( rI − k ) indicates the input signal x ( n ) at discrete moments rI − k The value of rI represents the current discrete moment, r Indicates the index of the downsampled data.

[0053] from Figure 2 and the output of the FIR filter From the expression of , we can see that in the anti-aliasing downsampling module of the prior art, when using FIR filter to remove high-frequency components, multiplication and addition operations are required for each sample of the input signal. M +1 multiplier and implementation M +1 adder tree for adding values. M Higher, or a multiple of the sampling rate reduction IWhen the number of samples is large, a large number of operations are generated. These operations actually have a certain degree of redundancy. For example, for some adjacent samples, their multiplication operations during the filtering process may have some common coefficients. However, because traditional implementations fail to effectively optimize these redundant operations, each sample requires a complete multiplication operation during the operation. This undoubtedly increases the number of multipliers used and, accordingly, the number of additions required by the adder tree during a single calculation.

[0054] The anti-aliasing downsampling circuit provided by the present application is implemented based on the circuit structure of a direct FIR filter. The anti-aliasing downsampling circuit obtained through theoretical analysis and circuit structure design can effectively eliminate redundant operations. By evenly distributing multiplication and addition operations and sharing multipliers, the problem of excessive local computation can be effectively avoided. At the same time, the present application reduces the number of multipliers by multiples and reduces the number of additions required to be processed in a single calculation of the adder tree. The present application can effectively solve the problem of redundant operations existing in the prior art, significantly reduce power consumption while reducing circuit scale, and effectively improve circuit performance.

[0055] Decompose and transform Equation (3), according to I times the sampling output requirement, The calculation is divided into I Group, calculate each group The sum of the results of the multiplication operations.

[0056] Specifically, formula (3) can be decomposed and transformed into:

[0057]

[0058] Based on the above decomposition and deformation process, the number of multiplication results can be obtained from M +1 is reduced to will need to be implemented M The adder tree for adding the results of +1 multiplications is simplified to The adder tree that adds the multiplication results is passed I Multiplexing multipliers and adder trees can be implemented M +1 addition of the multiplication results.

[0059] Based on the above theoretical analysis, multiplication and addition operations can be evenly distributed in I In one clock cycle, the multiplier and adder tree are I Multiplexing only requires multipliers and can achieve The adder tree for adding values ​​can be realized M+1 addition of the multiplication results.

[0060] Based on the above theoretical analysis results, the anti-aliasing downsampling circuit provided in the embodiment of the present application can be designed. The anti-aliasing downsampling circuit provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0061] Figure 3 This is a structural diagram of the anti-aliasing downsampling circuit provided in an embodiment of the present application, as shown in FIG. Figure 3 As shown, the anti-aliasing downsampling circuit includes: register 1, module I Counter 2, multiplier 3, adder tree 4, multiplexer 5, accumulation register 6, adder 7 and latch register 8.

[0062] Among them, register 1 stores different data in different clock cycles. I The value of the counter variable of counter 2 increases with the change of clock cycle. The filter coefficient is selected according to the value of the counter variable. The filter coefficient and the data stored in the preset register 1 are input into the corresponding multiplier 3 for multiplication operation. The adder tree 4 adds the output results of all multipliers 3. The multiplexer 5 is in the module. I Under the numerical control of the counting variable of counter 2, the output 0 or the output result of accumulator register 6 is selected, and adder 7 adds the output result of adder tree 4 and the output result selected by multiplexer 5. Accumulator register 6 stores the output result of adder 7 and uses the stored result as I The sampling result is doubled, or the stored result is input into the adder 7 through the multiplexer 5. Among them, the latch register 8 is outputted by the accumulation register 6. I The downsampling result is temporarily stored in the model. I Under the numerical control of the count variable of counter 2, latch register 8 outputs the value of the corresponding clock cycle. I Downsampling results.

[0063] It's important to note that register 1 can have more than one register. The data stored in register 1 is continuously updated with the clock signal. For example, during a processor operation, in the first clock cycle, register 1 stores the first operand obtained from one data source; in the second clock cycle, register 1 stores the second operand obtained from another data source. This dynamic storage feature enables register 1 to flexibly participate in various complex operations.

[0064] According to the model IThe value of the count variable of counter 2 is used to select the filter coefficients from the coefficient table corresponding to the preset register 1, and the data stored in the preset register 1 is multiplied by the filter coefficients in the corresponding coefficient table. The coefficient table can be a set of pre-set values, which are determined according to the specific operation requirements. The multiplication operation is to multiply the data stored in register 1 by the corresponding coefficients in the coefficient table. For example, in digital signal processing, in order to filter or transform a signal, it is necessary to multiply the input signal (stored in register 1) by the filter coefficients (stored in the coefficient table) to achieve a specific signal processing function.

[0065] The result of the multiplication operation is sent to the adder tree 4 for addition operation. The adder tree 4 can be a circuit module composed of multiple adders connected in a certain structure. Its function is to accumulate the results of multiple multiplication operations. The output of the adder tree 4 and the result selected by the multiplexer 5 are sent to the adder 7 for addition operation. The addition result is sent to the accumulation register 6 for storage. I Under the numerical control of the count variable of counter 2, multiplexer 5 selects to output 0 or the output result of accumulator register 6. I Under the numerical control of the count variable of counter 2, the accumulator register 6 stores the result as I The downsampling result is I The down-sampling result is input into the latch register 8 for temporary storage, or the stored result is output to the adder 7 through the multiplexer 5 for iterative addition calculation. In a specific embodiment, the register 1 can be a shift register, and the shift register can be set to M indivual. M The shift registers are connected in series. Each shift register can store different data in different clock cycles.

[0066] For example, assuming there are three or more shift registers, in the initial state, the first data is stored in the first shift register. When the first clock cycle arrives, the second data is input to the first shift register, and the first data is shifted to the second shift register for storage. When the second clock cycle arrives, the third data is input to the first shift register, and the second data is shifted to the second shift register for storage, and the first data is shifted to the third shift register for storage. And so on. As the clock cycles continue to arrive, the data input to each shift register continues to shift to the next adjacent shift register.

[0067] In the above embodiment, according to the number of shift registers M and model I Modulus value of counter 2 I , you canM The shift register is divided into register groups, each register group includes I A shift register, I The data stored in one of the shift registers participates in the multiplication operation. I The data stored in -1 register is shifted to the next adjacent register according to the change of the clock cycle; among them, the register where the data participating in the multiplication operation is located is the last register in the register group.

[0068] Based on the above theoretical analysis, since the register where the data involved in the multiplication operation is located is the last register in the register group, the final I -1 shift register is not actually needed, so you can set M - I +1 shift register can further save circuit overhead.

[0069] For example, when the filter order is 14 (that is, 14 shift registers are set), the module I Modulus value of counter 2 I When the value is 3 (i.e., the anti-aliasing downsampling circuit can achieve a 3x downsampling output), the 14 shift registers can be divided into four register groups, each with three shift registers, and two shift registers connected in series after the fourth register group. In actual use, since only the input data of the anti-aliasing downsampling circuit and the data stored in the third, sixth, ninth, and twelfth shift registers participate in the multiplication operation, the last two shift registers are not needed, so 12 shift registers can be set.

[0070] For each register group, assume that the three shift registers connected in sequence are the first shift register, the second shift register, and the third shift register. In the initial state, the first shift register in the current register group stores the first data. When the first clock cycle arrives, the second data is input to the first shift register, and the first data is shifted to the second shift register for storage. When the second clock cycle arrives, the third data is input to the first shift register, the second data is shifted to the second shift register for storage, and the first data is shifted to the third shift register for storage. When the third clock cycle arrives, the fourth data is input to the first shift register, the third data is shifted to the second shift register for storage, the second data is shifted to the third shift register for storage, and the first data is shifted to the first shift register in the next adjacent register group for storage, and so on.

[0071] For the current register group, according to the change of the clock cycle, the data stored in the first shift register and the second shift register are shifted to the next adjacent shift register, and the data stored in the third shift register participates in the multiplication operation. M and model I Modulus value of counter 2 I , you can M +1 filter coefficient written coefficient tables, each of which has I filter coefficients. It should be noted that when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

[0072] For example, when M is 14, I When is 3, there are 15 filter coefficients, which can be written into 5 coefficient tables, each with 3 filter coefficients. M is 13, I When is 3, there are 14 filter coefficients, which can be written into 5 coefficient tables. The first to fourth coefficient tables each contain 3 filter coefficients, and the fifth coefficient table contains 2 filter coefficients. The other filter coefficient in the fifth coefficient table can be padded with 0.

[0073] In the above embodiment, according to the number of shift registers M and model I Modulus value of counter 2 I , you can set multiplier 3 to In one clock cycle, the adder tree has 4 pairs of Specifically, a multiplier can be used to multiply the input data of the anti-aliasing downsampling circuit and the filter coefficients in the first coefficient table. The multipliers are respectively The data stored in the last register of each register group is multiplied by the filter coefficient in the corresponding coefficient table.

[0074] For example, when I is 3, M When the value is 12, 13, or 14, the number of multipliers can be set to 5. In one clock cycle, the adder tree 4 needs to perform an addition operation on the output results of the five multipliers 3.

[0075] The multiplier 3 is used to perform multiplication operation on the filter coefficient and the data stored in the preset register 1, wherein the filter coefficient can be calculated according to the modelI The value of the counting variable of counter 2 is selected. The range of the counting variable value is 0~ I -1, that is, the value of the counting variable can be 0, 1, 2, 3, ..., I -1. When I When is 3, the value of the count variable can be 0, 1, or 2. Each value of the count variable corresponds to a corresponding filter coefficient.

[0076] In the above embodiment, under the control of the numerical value of the counting variable, the multiplexer 5 can choose to output 0 or the data stored in the accumulation register 6.

[0077] Specifically, when the value of the counting variable is 0, the multiplexer 5 selects to output 0, the adder 7 adds 0 and the output result of the 0th group of the adder tree 4, and the output result of the adder 7 is stored in the accumulator register 6.

[0078] Among them, the output results of group 0 of adder tree 4 are:

[0079] (4)

[0080] In formula (4), 、 、……、 They represent the filter coefficients corresponding to when the value of the count variable is 0, Respectively represent the input data of the anti-aliasing downsampling circuit and the 1st, 2nd, ..., ( M +1) / I -1 The input data stored in the last register of the register group, r Indicates the index of the downsampled data.

[0081] When the value of the counting variable is greater than 0 and less than or equal to I When -1, the multiplexer 5 selects the data stored in the accumulator register 6 and outputs the data stored in the accumulator register 6. The adder 7 adds the data stored in the accumulator register 6 and the data from the first group to the first group of the adder tree 4. I -1 group of output results are iteratively added, and the output result of adder 7 is stored in accumulation register 6.

[0082] When the value of the counting variable is I -1, the result stored in register 6 is used as I The downsampling result is I The down-sampling result is input to latch register 8 for temporary storage. I Under the numerical control of the count variable of counter 2, latch register 8 outputs the value of the corresponding clock cycle. I Downsampling results.

[0083] It is understandable that in actual circuits, I -1 clock cycle calculation result, on the rising edge of the clock when the value of the count variable is 0, I The down-sampling result is latched by latch register 8 and output.

[0084] When the next clock cycle arrives, the value of the count variable is I -1 becomes 0 again.

[0085] Assume that the anti-aliasing downsampling circuit provided in the embodiment of the present application is n Clock cycle output ,The output results of the anti-aliasing downsampling circuit at each clock cycle are described below.

[0086] No. Clock cycle calculation and write the result into the accumulator register :

[0087] ,

[0088] .

[0089] No. Clock cycle calculation and accumulate the result into the accumulator register :

[0090] ,

[0091]

[0092] …

[0093] No. Clock cycle calculation and accumulate the result into the accumulator register :

[0094] ,

[0095] .

[0096] No. n Clock cycle calculation and accumulate the result into the accumulator register ,get And output:

[0097] ,

[0098] .

[0099] Every I The above operation is repeated for each input, and a downsampling result is output. The first calculation of each cycle is , not an accumulation operation; the final result is obtained and outputted in the last calculation.

[0100] The following example takes the filter order as 14 and the need to achieve 3 times downsampling output (i.e. M is 14, I 3), the structure and working principle of the anti-aliasing downsampling circuit provided in the embodiment of the present application are described.

[0101] Set up 14 shift registers, each of which is connected in series. Divide the 14 shift registers into 4 register groups, each of which has 3 shift registers. The last 2 shift registers are not actually needed.

[0102] The 15 filter coefficients are written as 5 coefficient tables, each with 3 filter coefficients.

[0103] Five multipliers 3 are provided, and in one clock cycle, the adder tree 4 can perform an addition operation on the output results of the five multipliers 3 .

[0104] mold I Counter 2 uses a modulo 3 counter, and the values ​​of its counting variable are 0, 1, and 2. When the value of the counting variable is 0, the corresponding filter coefficients in each coefficient table are h (2) h (5) h (8) h (11) and h (14). When the value of the count variable is 1, the corresponding filter coefficients in each coefficient table are h (1) h (4) h (7) h (10) and h (13). When the value of the counting variable is 2, the corresponding filter coefficients in each coefficient table are h (0), h (3) h (6) h (9) and h (12) The corresponding filter coefficients in different coefficient tables can be selected according to the value of the count variable.

[0105] Assume that the output is at the 9th clock cycle , then calculate in the 7th clock cycle and write the result into the accumulator register :

[0106] ,

[0107] .

[0108] 8th clock cycle calculation and accumulate the result into the accumulator register :

[0109] ,

[0110] .

[0111] Calculation of the 9th clock cycle and accumulate the result into the accumulator register ,get And output:

[0112] ,

[0113] .

[0114] Assuming that the 15 filter coefficients are as shown in Table 1, the coefficients in the 5 coefficient tables are as shown in Table 2.

[0115] Table 1 Filter coefficients

[0116]

[0117] Table 2 Coefficient table

[0118]

[0119] When input When the theoretical anti-aliasing filter output , the anti-aliasing downsampling circuit output As shown in Table 3. Compared with the anti-aliasing downsampling module in the prior art, the output end of the anti-aliasing downsampling circuit provided by the embodiment of the present application has an additional latch register 8, so Output later than One clock cycle.

[0120] Table 3 Anti-aliasing downsampling circuit output table

[0121]

[0122] The present application also provides a circuit module including the aforementioned anti-aliasing downsampling circuit. This circuit module integrates the anti-aliasing downsampling circuit provided in the present application. This circuit module can be expanded and optimized to provide efficient and reliable signal preprocessing solutions for a variety of digital signal processing scenarios. This circuit module offers excellent anti-aliasing performance and flexible downsampling capabilities, while also integrating other practical functions to meet the diverse signal processing requirements of different applications.

[0123] For example, in the field of audio processing, in audio recording, playback, and editing devices, the circuit module provided by the embodiments of the present application can be used to downsample high-sampling-rate audio signals while effectively suppressing ambient noise and noise generated by the device itself, ensuring high-quality audio signal output. Specifically, in a portable audio player, this circuit module can downsample high-sampling-rate audio files to a sampling rate suitable for device processing, while optimizing the quality of the audio signal and enhancing the user's listening experience.

[0124] In wireless and wired communication systems, the circuit modules provided by the embodiments of the present application can be used to preprocess received signals. Through functions such as anti-aliasing downsampling and noise suppression, signal reliability and transmission efficiency are improved, and bit error rates are reduced. Furthermore, the signal format conversion function enables compatibility with different communication protocols and devices, meeting the diverse needs of communication systems.

[0125] In industrial automation and sensor signal processing, the circuit module provided in the embodiment of the present application can perform operations such as anti-aliasing downsampling, gain adjustment, and noise suppression on sensor signals, converting the original signals into a format suitable for processing by industrial control systems, and providing reliable data support for monitoring and control of production processes.

[0126] In medical devices such as electrocardiographs and electroencephalographs, the circuit module provided in the embodiments of the present application can effectively remove noise interference in physiological signals, downsample the signals to reduce the amount of data, and at the same time ensure the integrity and accuracy of the signals, providing a reliable basis for medical diagnosis.

[0127] The present application also provides a chip including the aforementioned anti-aliasing downsampling circuit. The anti-aliasing downsampling circuit is configured to reduce the sampling rate of a signal while avoiding aliasing distortion, thereby reducing the amount of data. The anti-aliasing downsampling circuit eliminates redundant computations and has advantages such as small circuit size and low power consumption.

[0128] The chip provided in the embodiments of the present application can be used in consumer electronic products such as smartphones, tablet computers, and smart speakers to process audio and video signals. For example, during audio recording and playback on a smartphone, the chip can perform anti-aliasing downsampling on the audio signal collected by the microphone, while optimizing the audio quality and providing a clear and realistic sound quality experience. In terms of video capture and playback, the chip can efficiently process the video signal output by the camera, achieving video downsampling and format conversion to meet different storage and transmission requirements.

[0129] In industrial automation production lines, this chip can be used to process signals collected by various sensors, such as temperature sensors, pressure sensors, and accelerometers. By downsampling and optimizing sensor signals to prevent aliasing, it can accurately capture various parameters in the production process, providing reliable data support for industrial control systems. In the Internet of Things (IoT), this chip can be applied to various smart devices and sensor nodes, enabling efficient processing and transmission of massive amounts of data, improving the performance and reliability of IoT systems.

[0130] In medical devices such as electrocardiographs, electroencephalograms, and ultrasound machines, this chip effectively removes noise interference from biomedical signals and performs precise anti-aliasing and downsampling processing on the signals, ensuring that doctors receive accurate diagnostic information. Furthermore, the chip's multi-channel processing capabilities enable simultaneous processing of multiple biomedical signals, improving the efficiency of medical equipment.

[0131] In communications systems, this chip can be used to process both wireless and wired signals. For example, in base station equipment, it can perform anti-aliasing and downsampling on received RF signals, improving signal quality and transmission efficiency. In network equipment, the chip can process data signals, downsampling and format conversion to accommodate different network transmission protocols and bandwidth requirements.

[0132] The present application also provides a signal processing device comprising the aforementioned circuit module or chip. The signal processing device can be used in smart home systems, intelligent transportation systems, aerospace systems, and financial transaction systems, providing reliable solutions for various complex signal processing tasks.

[0133] It will be appreciated by those skilled in the art that, under the premise of no conflict, the above-mentioned preferred embodiments can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system according to the various embodiments disclosed in this application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for the convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0134] Those skilled in the art will appreciate that, provided there is no conflict, the above preferred solutions can be freely combined and superimposed.

[0135] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present application, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will be included in the scope of the claims of the present application.

Claims

1. An anti-aliasing downsampling circuit, characterized in that: include: Register, module I counters, multipliers, adder trees, multiplexers, adders, accumulator registers, and latch registers; The register stores different data at different clock cycles; The mold I The value of the count variable of the counter increases as the clock cycle changes, and a filter coefficient is selected according to the value of the count variable. The filter coefficient and the data stored in the preset register are input into the corresponding multiplier for multiplication operation; The adder tree performs an addition operation on the output results of all the multipliers; The multiplexer is in the mode I Under the numerical control of the counting variable of the counter, the output is selected to be 0 or the output result of the accumulator register, and the adder performs an addition operation on the output result of the adder tree and the result selected and output by the multiplexer; The accumulator register stores the output result of the adder and uses the stored result as I downsampling the result, or inputting the stored result into the adder through the multiplexer; The latch register outputs the accumulator register I The downsampling result is temporarily stored in the model I Under the numerical control of the counter's count variable, the latch register outputs the corresponding clock cycle. I Downsampling results; The register is a shift register, and the shift register is set to M indivual; M The shift register is divided into register groups, each of which includes I A shift register, I The data stored in one of the shift registers participates in the multiplication operation. I The data stored in -1 register is shifted to the next adjacent register according to the change of the clock cycle; wherein the register participating in the multiplication operation is the last register in the register group.

2. The anti-aliasing downsampling circuit according to claim 1, wherein: According to the number of shift registers M and model I modulus of the counter I ,Will M +1 filter coefficient written coefficient tables, each of which has I filter coefficients.

3. The anti-aliasing downsampling circuit according to claim 1, wherein: The multiplier is provided with In one clock cycle, the adder tree The output results of the multipliers are added.

4. The anti-aliasing downsampling circuit according to claim 1, wherein: The range of the value of the counting variable is 0~ I -1.

5. The anti-aliasing downsampling circuit according to claim 4, characterized in that: When the value of the counting variable is 0, the multiplexer selects to output 0, the adder performs an addition operation on 0 and the output result of the 0th group of the adder tree, and the output result of the adder is stored in the accumulator register.

6. The anti-aliasing downsampling circuit according to claim 5, characterized in that: The output results of group 0 of the adder tree are: ， Where, 、 、……、 They respectively represent the filter coefficients corresponding to when the value of the count variable is 0, Respectively represent the input data of the anti-aliasing downsampling circuit and the 1st, 2nd, ..., ( M +1) / I -1 The input data stored in the last register of the register group, r Indicates the index of the downsampled data.

7. The anti-aliasing downsampling circuit according to claim 6, characterized in that: when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

8. The anti-aliasing downsampling circuit according to claim 4, characterized in that: The value of the counter variable is greater than 0 and less than or equal to I -1, the multiplexer selects to output the data stored in the accumulator register, and the adder performs summation on the data stored in the accumulator register and the data from the first group to the first group of the adder tree. I -1 group of output results are iteratively added, and the output results of the adder are stored in the accumulator register.

9. The anti-aliasing downsampling circuit according to claim 8, characterized in that: The value of the count variable is I -1, the accumulator register stores the result as I The downsampling result is I The down-sampling result is input into the latch register for temporary storage.

10. A circuit module, characterized in that: The method comprises the anti-aliasing downsampling circuit according to any one of claims 1 to 9.

11. A chip, characterized in that: The method comprises the anti-aliasing downsampling circuit according to any one of claims 1 to 9.

12. A signal processing device, characterized in that: Comprising the circuit module according to claim 10 or the chip according to claim 11.

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