Disorder correction circuit, quantizer, disorder correction system and driving chip
By designing an offset correction circuit and using a control module and a correction module to sequentially correct multiple comparators, the problem of comparator offset error affecting accuracy in traditional quantizers is solved, and high precision and high performance of the quantizer are achieved under different conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU RUNXIN INFORMATION TECH CO LTD
- Filing Date
- 2025-01-22
- Publication Date
- 2026-07-10
AI Technical Summary
In traditional quantizers, the offset error of the comparator affects the accuracy and performance of the quantizer, especially in high-precision quantizers such as 12-bit successive approximation analog-to-digital converters, where effective offset correction methods are needed.
An offset correction circuit was designed, including a control module and a correction module. By transmitting a correction start signal when the circuit is powered on, multiple comparators are corrected sequentially to ensure that the comparators output low-level signals until the correction is completed. Combined with components such as a clock module, a judgment module, and a latch, efficient offset correction is achieved.
Under different process, voltage, and temperature conditions, the comparator's performance was ensured to meet system requirements, and the accuracy and performance of the quantizer were improved.
Smart Images
Figure CN120074517B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of comparator offset correction technology, and in particular to an offset correction circuit, a quantizer, an offset correction system, and a driver chip. Background Technology
[0002] In traditional quantizers, comparator offset is a critical issue as it directly impacts the quantizer's accuracy and performance. A comparator is a circuit that compares an analog voltage signal with a reference voltage; its offset error primarily stems from mismatches in circuit components (such as operational amplifiers and resistors). This mismatch leads to an equivalent input offset voltage for the comparator, thus affecting the quantizer's accuracy. For high-precision quantizers, such as 12-bit successive approximation analog-to-digital converters (ADCs), comparator offset errors must be carefully managed.
[0003] Traditional offset correction methods for comparators in quantizers include variable capacitor or capacitor array adjustment, automatic zeroing techniques, single-ended operational amplifier structures to avoid offset voltage, and redundant bit correction algorithms. Each method has its advantages and disadvantages, and the choice depends on the specific application scenario and requirements. With technological advancements, new offset correction methods are constantly emerging, providing more choices and possibilities for the development of quantizers.
[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention
[0005] The main objective of this invention is to provide an offset correction circuit, a quantizer, an offset correction system, and a driver chip, aiming to solve the technical problems affecting the accuracy and performance of the quantizer.
[0006] To achieve the above objectives, the present invention proposes an offset correction circuit, the offset correction circuit comprising:
[0007] Control module and calibration module;
[0008] The control module is connected to the correction module and a plurality of comparators respectively; the correction module is connected to a plurality of the comparators respectively;
[0009] The control module is used to transmit a correction start signal to the correction module when the circuit is detected to be powered on.
[0010] The calibration module is used to calibrate the plurality of comparators sequentially according to the calibration start signal, so that the plurality of comparators sequentially transmit low-level signals to the control module;
[0011] The control module is further configured to transmit a calibration end signal to the calibration module based on the low-level signal, so that the calibration module stops calibrating the plurality of comparators.
[0012] In one embodiment, the offset correction circuit further includes:
[0013] Clock module;
[0014] The clock module is connected to both the control module and the calibration module.
[0015] The clock module is used to transmit clock signals to the control module and the correction module.
[0016] In one embodiment, the clock module is also connected to each of the comparators;
[0017] The control module is also used to transmit a clock start signal to the clock module when the circuit is powered on;
[0018] The clock module is also configured to transmit the clock signal to the plurality of comparators when the clock start signal is received.
[0019] In one embodiment, the offset correction circuit further includes:
[0020] Judgment module;
[0021] The judgment module is connected to the correction module and the multiple comparators respectively;
[0022] The judgment module is used to transmit a continuous correction signal to the correction module when it does not receive the low-level signal transmitted by the comparator;
[0023] The correction module is further configured to correct the comparator based on the continuous correction signal.
[0024] In one embodiment, the correction module includes:
[0025] Start-up subunit and correction subunit;
[0026] The starting subunit is connected to the control module and the plurality of comparators respectively; the correction subunit is connected to the control module and the plurality of comparators respectively.
[0027] The start-up subunit is configured to transmit a level signal to a plurality of the comparators upon receiving the correction start-up signal;
[0028] The correction subunit is used to sequentially correct the plurality of comparators when the clock signal is received, so that the plurality of comparators sequentially transmit low-level signals to the control module.
[0029] In one embodiment, the offset correction circuit further includes:
[0030] latch;
[0031] The latches are connected to the control module and the multiple comparators respectively.
[0032] In one embodiment, the control module includes:
[0033] Registers and controllers;
[0034] The controller is connected to the register, the clock module, the correction module, and the multiple comparators, respectively.
[0035] The register is used to store relevant data of the comparator;
[0036] The controller is configured to extract the relevant data when the circuit is detected to be powered on, and execute the steps of transmitting the correction start signal to the correction module according to the relevant data, and receiving high-level signals transmitted by the multiple comparators.
[0037] In addition, to achieve the above objectives, the present invention also proposes a quantizer, which includes the aforementioned offset correction circuit.
[0038] Furthermore, to achieve the above objectives, the present invention also proposes an offset correction system, which includes the offset correction circuit described above.
[0039] In addition, to achieve the above objectives, the present invention also proposes a driver chip, which includes the aforementioned offset correction circuit.
[0040] One or more technical solutions proposed in this invention have at least the following technical effects:
[0041] The offset correction circuit of the present invention includes: a control module and a correction module; the control module is connected to the correction module and a plurality of comparators respectively; the correction module is connected to the plurality of comparators respectively; the control module is used to transmit a correction start signal to the correction module when the circuit is detected to be powered on; the correction module is used to sequentially correct the plurality of comparators according to the correction start signal, so that the plurality of comparators sequentially transmit low-level signals to the control module; the control module is also used to transmit a correction end signal to the correction module according to the low-level signal, so that the correction module stops correcting the plurality of comparators. By correcting the plurality of comparators sequentially according to the timing, it can be ensured that the performance of the comparators meets the system requirements under different PVT (Process, Voltage, Temperature) conditions, thereby ensuring the accuracy and performance of the quantizer. Attached Figure Description
[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 1 of the present invention;
[0045] Figure 2 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 2 of the present invention.
[0046] Explanation of icon numbers:
[0047] label name label name 1 Control module 2 Calibration module 3 Multiple comparators 4 Clock module 5 Judgment Module 6 latch 11 register 12 controller 21 Startup subunit 22 Correction subunit
[0048] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0050] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.
[0051] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0052] In traditional quantizers, comparator offset is a critical issue as it directly impacts the quantizer's accuracy and performance. A comparator is a circuit that compares an analog voltage signal with a reference voltage; its offset error primarily stems from mismatches in circuit components (such as operational amplifiers and resistors). This mismatch leads to an equivalent input offset voltage for the comparator, thus affecting the quantizer's accuracy. For high-precision quantizers, such as 12-bit successive approximation analog-to-digital converters (ADCs), comparator offset errors must be carefully managed.
[0053] Traditional offset correction methods for comparators in quantizers include variable capacitor or capacitor array adjustment, automatic zeroing techniques, single-ended operational amplifier structures to avoid offset voltage, and redundant bit correction algorithms. Each method has its advantages and disadvantages, and the choice depends on the specific application scenario and requirements. With technological advancements, new offset correction methods are constantly emerging, providing more choices and possibilities for the development of quantizers.
[0054] To address the above problems, this invention proposes an offset correction circuit, aiming to solve the technical problems affecting the accuracy and performance of the quantizer.
[0055] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the offset correction circuit of the present invention. The offset correction circuit includes:
[0056] Control module 1 and calibration module 2;
[0057] The control module 1 is connected to the correction module 2 and a plurality of comparators 3 respectively; the correction module 2 is connected to a plurality of the comparators 3 respectively;
[0058] The control module 1 is used to transmit a correction start signal to the correction module 2 when the circuit is detected to be powered on.
[0059] The correction module 2 is used to sequentially correct the plurality of comparators 3 according to the correction start signal, so that the plurality of comparators 3 sequentially transmit low-level signals to the control module 1;
[0060] The control module 1 is further configured to transmit a correction end signal to the correction module 2 based on the low-level signal, so that the correction module 2 stops correcting the plurality of comparators 3.
[0061] It should be noted that in this embodiment, the comparator 3 is a fully dynamic comparator. The fully dynamic comparator has high speed, but large offset and noise, which can easily affect the accuracy and performance of the quantizer. Therefore, the comparator 3 needs to be offset corrected.
[0062] Understandably, in order to improve the performance of continuous-time delta-sigma ADCs, the sampling clock rate is getting higher and higher, reaching GHz (gigahertz), and the requirements for quantizers are also getting higher and higher. Therefore, a fully dynamic comparator is used in the quantizer.
[0063] In a specific implementation, when the control module 1 detects that the circuit is powered on, it transmits the calibration start signal to the calibration module 2. Upon receiving the calibration start signal, the calibration module 2 transmits a low-level signal to the multiple comparators 3, so that all four input terminals of the multiple comparators 3 are low-level signals, and begins to calibrate the multiple comparators 3 sequentially. When the calibration module 2 completes the calibration of the first comparator 3, if the output of the first comparator 3 is a high-level signal, it determines that the calibration of the first comparator 3 has failed. At this time, the calibration module 2 will continue to calibrate the first comparator 3 until the output of the first comparator 3 is a low-level signal, and then begins to calibrate the next comparator 3. This process is repeated until the output of the last comparator 3 is a low-level signal, thus completing the calibration of the multiple comparators 3. That is, all the comparators 3 output low-level signals to the control module 1. After receiving the low-level signals output by all the comparators 3, the control module 1 transmits a calibration end signal to the calibration module 2, so that the calibration module 2 stops the calibration work of the multiple comparators 3.
[0064] To ensure that the above-mentioned correction module 2 is more accurate and efficient during the correction process, refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the offset correction circuit according to Embodiment 2 of the present invention.
[0065] In this embodiment, the offset correction circuit further includes:
[0066] Clock module 4;
[0067] The clock module 4 is connected to the control module 1 and the correction module 2 respectively;
[0068] The clock module 4 is used to transmit clock signals to the control module 1 and the correction module 2.
[0069] It should be noted that the clock signal mentioned above is a periodic signal, and the period can be set by the operator according to the actual situation.
[0070] In a specific implementation, the clock signal transmitted by the clock module 4 is mainly used to time the working state of the control module 1 and the correction module 2, improve the working synchronization between the control module 1 and the correction module 2, and improve the accuracy of the comparator 3 correction.
[0071] In this embodiment, the clock module 4 is also connected to each of the comparators 3;
[0072] The control module 1 is also used to transmit a clock start signal to the clock module 4 when the circuit is powered on;
[0073] The clock module 4 is also used to transmit the clock signal to the plurality of comparators 3 when the clock start signal is received.
[0074] It should be noted that the aforementioned clock start signal is used to activate the aforementioned clock module 4 to start timing the aforementioned comparator 3 when the aforementioned comparator 3 is being calibrated.
[0075] In a specific implementation, when the control module 1 is powered on, it transmits the clock start signal to the clock module 4. When the clock module 4 receives the clock start signal, it transmits the clock signal to multiple comparators 3. The purpose is to record the time consumed by each comparator 3 from the start of correction to the end of correction, so as to facilitate subsequent data analysis by the operator.
[0076] In this embodiment, the offset correction circuit further includes:
[0077] Judgment module 5;
[0078] The judgment module 5 is connected to the correction module 2 and the plurality of comparators 3 respectively;
[0079] The judgment module 5 is used to transmit a continuous correction signal to the correction module 2 when it does not receive the low-level signal transmitted by the comparator 3;
[0080] The correction module 2 is also used to correct the comparator according to the continuous correction signal.
[0081] It should be noted that the aforementioned continuous correction signal is the signal that the correction module 2 activates after the comparator fails to be corrected, and continues to correct the uncorrected comparator 3.
[0082] In its implementation, the judgment module 5 receives a level signal output by the comparator 3 when the correction module 2 completes the correction of one of the comparators 3. If the level signal received by the judgment module 5 is a high-level signal, it transmits the continuous correction signal to the correction module 2, so that the correction module 2 continues to correct the comparators 3 that have not met the correction requirements. If the level signal received by the judgment module 5 is a low-level signal, it is determined that the comparator 3 has met the correction requirements after correction, and the correction module 2 continues to correct the next comparator 3 that needs correction. When the correction module 2 receives the continuous correction signal, it continues to correct the comparator 3.
[0083] In this embodiment, the correction module 2 includes:
[0084] Start-up subunit 21 and correction subunit 22;
[0085] The starting subunit 21 is connected to the control module 1 and the plurality of comparators 3 respectively; the correction subunit 22 is connected to the control module 1 and the plurality of comparators 3 respectively.
[0086] The start-up subunit 21 is used to transmit a level signal to the plurality of comparators 3 when the correction start signal is received;
[0087] The correction subunit 22 is used to sequentially correct the plurality of comparators 3 when the clock signal is received, so that the plurality of comparators 3 sequentially transmit low-level signals to the control module 1.
[0088] In a specific implementation, when the startup subunit 21 receives the correction startup signal transmitted by the control module 1, it transmits a low-level signal to the multiple comparators 3 so that all four input terminals of the multiple comparators 3 are low-level signals. The correction subunit 22 is used to correct the multiple comparators 3 sequentially when it receives the clock signal so that the multiple comparators 3 sequentially transmit low-level signals to the control module 1.
[0089] In this embodiment, the offset correction circuit further includes:
[0090] Latch 6;
[0091] The latch 6 is connected to the control module 1 and the multiple comparators 3 respectively.
[0092] It should be noted that the latch 6 mentioned above can be a regenerative latch or a symmetrical latch, etc.
[0093] In its implementation, latch 6 primarily functions to maintain a constant output while the received input signal changes, until a new input signal is received. This helps ensure data stability and reliability. It also synchronously latches and releases data according to the aforementioned clock signal. This helps ensure correct data transmission and processing, especially in high-speed digital circuits.
[0094] In this embodiment, the control module 1 includes:
[0095] Register 11 and controller 12;
[0096] The controller 12 is connected to the register 11, the clock module 4, the correction module 2, and the multiple comparators 3 respectively;
[0097] The register is used to store the relevant data of the comparator 3;
[0098] The controller is configured to extract the relevant data when the circuit is detected to be powered on, and execute the steps of transmitting the correction start signal to the correction module 2 according to the relevant data, and receiving high-level signals transmitted by the multiple comparators 3.
[0099] It should be noted that the above-mentioned data refers to the data from the comparator 3 calibration process described above.
[0100] In a specific implementation, the register 11 pre-stores process data about the comparator 3 during calibration. The controller 12 is used to extract the relevant data when the circuit is detected to be powered on, and to execute the steps of transmitting the calibration start signal to the calibration module 2 and receiving multiple high-level signals transmitted by the comparator 3 according to the relevant data.
[0101] Furthermore, to achieve the above objectives, the present invention also proposes a quantizer, which includes the offset correction circuit as described above. Other embodiments or specific implementations of the quantizer of the present invention can be found in the embodiments of the offset correction circuit described above, and will not be repeated here.
[0102] Furthermore, to achieve the above objectives, the present invention also proposes an offset correction system, which includes the offset correction circuit as described above. Other embodiments or specific implementations of the offset correction system of the present invention can be found in the embodiments of the offset correction circuit described above, and will not be repeated here.
[0103] Furthermore, to achieve the above objectives, the present invention also proposes a driver chip, which includes an analog-to-digital converter as described above and an offset correction circuit. Other embodiments or specific implementations of the driver chip of the present invention can be found in the embodiments of the offset correction circuit described above, and will not be repeated here.
[0104] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. An offset correction circuit, characterized in that, The offset correction circuit includes: Control module and calibration module; The control module is connected to the correction module and a plurality of comparators respectively; the correction module is connected to a plurality of the comparators respectively; The control module is used to transmit a correction start signal to the correction module when the circuit is detected to be powered on. The calibration module is used to calibrate a plurality of comparators sequentially according to the calibration start signal, so that the plurality of comparators sequentially transmit low-level signals to the control module; The control module is further configured to transmit a calibration end signal to the calibration module based on the low-level signal, so that the calibration module stops calibrating the multiple comparators; The offset correction circuit also includes: Clock module; The clock module is connected to both the control module and the calibration module. The clock module is used to transmit clock signals to the control module and the correction module; The clock module is also connected to each of the comparators; The control module is also used to transmit a clock start signal to the clock module when the circuit is powered on; The clock module is also configured to transmit the clock signal to the plurality of comparators when the clock start signal is received; The offset correction circuit also includes: Judgment module; The judgment module is connected to the correction module and the multiple comparators respectively; The judgment module is used to transmit a continuous correction signal to the correction module when it does not receive the low-level signal transmitted by the comparator; The correction module is further configured to correct the comparator according to the continuous correction signal; The correction module includes: Start-up subunit and correction subunit; The startup subunit is connected to the control module and the plurality of comparators respectively; the correction subunit is connected to the control module and the plurality of comparators respectively. The start-up subunit is configured to transmit a level signal to a plurality of the comparators upon receiving the correction start-up signal; The correction subunit is used to sequentially correct the plurality of comparators when the clock signal is received, so that the plurality of comparators sequentially transmit low-level signals to the control module.
2. The offset correction circuit as described in claim 1, characterized in that, The offset correction circuit also includes: latch; The latches are connected to the control module and the multiple comparators, respectively.
3. The offset correction circuit as described in claim 2, characterized in that, The control module includes: Registers and controllers; The controller is connected to the register, the clock module, the correction module, and the multiple comparators, respectively. The register is used to store relevant data of the comparator; The controller is configured to extract the relevant data when the circuit is detected to be powered on, and execute the steps of transmitting the correction start signal to the correction module according to the relevant data, and receiving high-level signals transmitted by the comparators.
4. A quantizer, characterized in that, The offset correction system includes: the offset correction circuit according to any one of claims 1 to 3.
5. An offset correction system, characterized in that, The offset correction system includes: the offset correction circuit according to any one of claims 1 to 3.
6. A driver chip, characterized in that, The driver chip includes: the offset correction circuit according to any one of claims 1 to 3.