Signal measurement

Abstract

The invention relates to signal measurement. A signal measurement system, a controller and a method for digitally converting an input signal are provided. A signal measurement system includes an analog-to-digital converter (ADC) configured to receive an input signal and generate a plurality of digital samples of the input signal. The signal measurement system further includes a controller configured to control a number of digital conversions of the input signal performed by the ADC per unit time based on at least one of a characteristic of the input signal and / or a digitally determined characteristic of the input signal, wherein the digitally determined characteristic of the input signal is based on one or more previous digital samples of the input signal generated by the ADC.

Description

Technical Field

[0001] The present invention relates to a signal measurement system, method and controller for digitally converting an input signal. Background Art

[0002] For many different purposes, it may be useful to measure one or more characteristics of a device under test (DUT) at different test signal frequencies. For example, the impedance of a DUT can be measured by applying a test signal (such as a test current or a test voltage) to the DUT and measuring the current through the DUT or the voltage across the DUT. By determining the impedance of the test signal at various different frequencies, useful information related to the DUT can be determined. A specific example is electrochemical impedance spectroscopy (EIS), in which a test signal is applied to a battery (i.e., the DUT) and swept over a certain frequency range. The current or voltage signal generated by the battery is measured to determine the impedance of the battery at various different test signal frequencies. This EIS of the battery can extract different insights about the battery, such as its state of health (SoH), state of charge (SoC), and battery temperature.

[0003] In a system where the characteristics of a DUT are determined over a test signal frequency range, it is difficult to accurately determine the characteristics over the entire frequency range. For example, the determination of a characteristic may include some signal processing, such as discrete Fourier transform (DFT), fast Fourier transform (FFT), discrete cosine transform (DCT), wavelet processing, etc. This typically requires an analog-to-digital converter (ADC) to convert the DUT signal (e.g., a signal indicating the current through the DUT or the voltage across the DUT) into a series of digital samples. The digital samples can be built up over time and then analyzed by digital signal processing. Building up multiple digital samples over time means that the digital samples can represent multiple cycles of the measured signal, which is typically necessary for accurate digital signal processing. To accurately digitally convert a signal, the ADC conversion frequency is typically greater than the highest signal frequency expected to be measured, most commonly the ADC conversion frequency is at least twice the highest signal frequency (i.e., the ADC conversion frequency is typically equal to or greater than the Nyquist frequency). Therefore, the ADC conversion frequency is typically set based on the top of the spectral frequency range.

[0004] However, the bottom of the spectral frequency range may be much smaller than the top, for example, many orders of magnitude smaller. This means that in order to accommodate the highest frequency in the spectral range, when the signal is at the bottom of the spectral range, the ADC may generate a large number of samples per cycle of the signal. Such a large number of digital samples per cycle is typically not required, which represents low power efficiency of the ADC. In addition, it also imposes an additional burden on the memory and processing speed requirements for storing and analyzing the digital samples. Summary of the Invention

[0005] In a first aspect of the present disclosure, there is provided a signal measurement system for digitally converting an input signal, the system comprising: an analog-to-digital converter ADC configured to: receive the input signal; and generate a plurality of digital samples of the input signal; and a controller configured to control the number of digital conversions of the input signal performed by the ADC per unit time based on at least one of: the characteristics of the input signal; and / or the digitally determined characteristics of the input signal, wherein the digitally determined characteristics of the input signal are based on one or more previous digital samples of the input signal generated by the ADC.

[0006] In a second aspect of the present disclosure, there is provided a method for digitally converting an input signal, the method comprising: an analog-to-digital converter ADC that receives the input signal and generates a plurality of digital samples of the input signal; and a controller that controls the number of digital conversions of the input signal performed by the ADC per unit time based on at least one of: the characteristics of the input signal: the measured characteristics of the input signal, wherein the input signal measurement is based on one or more previous digital samples of the input signal generated by the ADC.

[0007] In a third aspect of the present disclosure, there is provided a controller for controlling the number of digital conversions of an input signal performed by an analog-to-digital converter ADC per unit time based on at least one of: the characteristics of the input signal, wherein the input signal is input to the ADC for digital conversion and / or the digitally determined characteristics of the input signal, wherein the digitally determined characteristics of the input signal are based on one or more previous digital samples of the input signal generated by the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] As an example only, aspects of the present disclosure are described with reference to the following drawings, in which:

[0009] Figure 1A Shows an example Nyquist plot of battery impedance;

[0010] Figure 1B Shows an example of an equivalent circuit model of a lithium-ion battery;

[0011] Figure 2 Shows a schematic diagram of an example signal measurement system according to one aspect of the present disclosure;

[0012] Figure 3 Shows a schematic diagram of an example signal measurement system according to another aspect of the present disclosure;

[0013] Figure 4 Shows an example flowchart representing Figure 2 or Figure 3 an example operation of the controller;

[0014] Figure 5 shows an example flow chart representing Figure 2 or Figure 3 another example operation of the controller of;

[0015] Figure 6 shows an example flow chart representing Figure 2 or Figure 3 another example operation of the controller of;

[0016] Figure 7 shows a schematic diagram representing Figure 2 or Figure 3 an example manner in which the controller of can control the number of digital conversions performed by the ADC;

[0017] Figure 8 shows representing Figure 2 or Figure 3 a schematic diagram of another example manner in which the controller of can control the number of digital conversions performed by the ADC;

[0018] Figure 9 shows a schematic diagram of an example signal measurement system according to another aspect of the present disclosure. Detailed Description

[0019] The present invention relates to a measurement system that can improve the power efficiency of an analog-to-digital converter (ADC) and reduce the processing requirements (e.g., memory size and / or processing speed) of a signal analyzer that analyzes digital samples of the ADC output, while still maintaining good conversion accuracy. It has many different uses / applications, and one particular application is for spectral measurements of a device under test (DUT), such as impedance spectroscopy of a battery.

[0020] Figure 1A shows an example Nyquist plot of the impedance of a battery (in this example, a lithium-ion battery).

[0021] Figure 1B shows an example equivalent circuit model of a lithium-ion battery (specifically, a double Randles model). The circuit model includes an electrolytic (ohmic) resistance (R S ), a double-layer capacitance (C DL ), a solid electrolyte interface resistance (R SEI ), a charge transfer resistance (R CT ), and a Warburg (diffusion) resistance (W).

[0022] Returning to Figure 1A, an example Nyquist plot is generated by applying a test signal (current or voltage) to the battery and measuring the voltage across the battery or the current through the battery as the test signal sweeps through a frequency range of approximately 1 mHz to 5 kHz (although any other suitable frequency range can be used). Based on the known amplitude of the test signal and the measured battery voltage or current, the battery impedance at each test signal frequency can be determined. The impedance of the battery in different sub-ranges or regions of the test signal frequency range represents a measure of different characteristics / information of the battery, such as corresponding to different chemical and physical processes.

[0023] For example, when the test signal is in the higher kHz sub-range 110, the impedance is dominated by R s and provides information related to the conductance and skin effect of the battery. When the test signal is in the lower kHz / higher Hz sub-range 120, the impedance is dominated by R SEI and provides information related to the solid electrolyte interface (SEI) of the battery. When the test signal is in the Hz sub-range 130, the impedance is dominated by C DL and R CL and provides information related to the charge transfer and electrochemical double layer of the battery. When the test signal is in the mHz sub-range 140, the impedance is dominated by W and provides information related to the mass transport of the battery.

[0024] It can be seen that the range of the test signal frequency is very wide, about six orders of magnitude in this example. In a system that measures the signal derived from the DUT (in this case, the battery voltage or current) through digital conversion by an ADC, the top of the frequency range is usually considered to set the ADC conversion frequency in order to achieve sufficient conversion accuracy for the entire test signal frequency range. For example, it can be set to at least the Nyquist frequency, which in this example is 2 x 5 kHz, i.e., 10 kHz. In order to perform digital signal analysis (such as any one or more of DFT, FFT, DCT, wavelet processing) on the digital samples output by the ADC, multiple samples are usually accumulated (e.g., stored or cached in memory) and then analyzed. For many types of signal analysis, in order to perform an analysis with sufficient accuracy, digital samples representing multiple cycles of the measured signal are required. In Figure 1A and 1B example, when the test signal is 5 kHz, the battery voltage will also be approximately 5 kHz, and digital samples representing multiple (e.g., ten, twenty, fifty, one hundred, etc.) cycles of the battery voltage can be accumulated and then analyzed. This requires sufficient digital memory storage to retain the required number of digital samples before analysis, which can then be discarded.

[0025] However, the inventors have recognized that problems can occur when the test signal frequency is low. In particular, when the test signal operates at the bottom of the frequency range, the ADC will generate a large number of digital samples per cycle of the signal. In the specific example given above, if the ADC conversion frequency is 10 kHz and the test signal frequency is 1 mHz, the period of the signal is approximately 1000 seconds, during which the ADC will generate over a million samples. Regardless of the specific numbers, it can be seen that if the frequency range of the test signal is large (e.g., spanning at least two orders of magnitude), when the test signal approaches the bottom of the range, the number of digital samples generated by the ADC per cycle of the signal will be large, meaning that a very large number of samples will be generated to span multiple cycles of the signal. Given this, it may be necessary to design a digital signal processor to have a large enough memory to store a large number of samples and a processing speed / capability to handle a large number of samples, even though the memory and processing capabilities will only be fully utilized when the test signal approaches the bottom of the frequency range. This represents additional cost and complexity. Alternatively, the digital signal processor can be designed to have more limited memory and processing capabilities (e.g., sufficient memory and processor capabilities to accurately process signals at mid to high test signal frequencies) and analyze digital samples that represent only a small number of cycles of the signal (e.g., one cycle or two cycles, etc.) when the test signal is at a relatively low frequency. Analyzing digital samples that represent only a very small number of signal cycles tends to reduce the accuracy of the analysis, such as resulting in a larger standard deviation of the measured signal and the characteristics determined by signal processing (e.g., a larger standard deviation of the determined battery impedance in the above example). Additionally, when the test signal is at a relatively low frequency, generating a large number of digital samples within each signal cycle also represents a significant and inefficient power consumption level of the ADC.

[0026] In view of these challenges, the inventors have developed a system in which the number of digital conversions performed by an ADC per unit time is controlled based on the reported characteristics of the signal input to the ADC and / or the characteristics of the measured signal derived from previous digital samples output from the ADC. For example, if the frequency of the signal reported as input to the ADC is relatively low, the ADC can be controlled such that the number of digital conversions performed per unit time is reduced compared to when the reported input signal has a higher frequency. In this example, whenever the frequency is low, the number of digital samples generated by the ADC per cycle of the measured signal may be reduced compared to the case where the ADC continues to convert at a fixed conversion frequency. Since the frequency of the measured signal is relatively low, fewer samples per unit time are required to accurately represent the signal compared to when the frequency is higher, and thus high-precision conversion can still be maintained. However, the digital signal processing requirements (e.g., memory size and / or processing power) can be reduced while still being able to store and process digital samples representing a sufficient number of signal cycles, because the ADC outputs fewer samples per cycle of the measured signal compared to the case where the ADC continues to convert at a fixed conversion frequency. Thus, accurate signal processing and analysis can be performed while keeping the memory and processing speed requirements at reasonable levels. In addition, since the ADC performs fewer conversions per unit time, its power consumption is also reduced.

[0027] Figure 2 An example signal measurement system 200 in accordance with one aspect of the present disclosure is shown. The system includes an ADC 210 configured to receive an input signal 205 and generate a plurality of digital samples 215 of the input signal 205 over time. The system 200 also includes a controller 220 configured to control the number of digital conversions of the input signal 205 performed by the ADC 210 per unit time (in other words, control the conversion frequency or rate of the ADC 210) based on at least one of: the characteristics of the input signal 205 (e.g., the frequency of the input signal 205) and / or digitally determined characteristics based on one or more previous digital samples 215 on the input signal 205 generated by the ADC 210. The controller 220 can be any suitable unit / device / circuit configured to perform the control functions described herein. For example, the controller 220 can include any one or more of a processor or microprocessor, a microcontroller, fixed or programmable logic (such as an FPGA), a dedicated hardware circuit, etc.

[0028] Figure 3FIG. 0 shows a specific example signal measurement system 300 according to another aspect of the present disclosure. The signal measurement system 300 is merely an example application of the principles disclosed herein to aid better understanding, but is not the only application, as will be described later. The system 300 is adapted to measure the characteristics of a DUT 320, where the input signal 205 is a signal derived from the DUT 320. In one specific example, the characteristic of the DUT 320 can be the impedance of the DUT (which is an example described in more detail above with reference to Figure 1A and 1B where the DUT is a battery). The system 300 includes the above-described ADC 210 and controller 220. It also includes a signal generator 310, which is configured to generate a test signal 312, such as a test signal 312 having one or more non-zero frequencies. The signal generator 310 is adapted to be coupled to the DUT 320 so as to apply the test signal 312 to the DUT 320 when measuring the characteristics of the DUT 320. If the system 300 is configured to perform spectral measurements, such as the impedance spectroscopy previously referenced Figure 1A and 1B then the signal generator 310 can be configured to vary the frequency of the test signal 312 over different frequency ranges. The test signal 312 can have any suitable waveform, such as a sine wave, square wave, triangular wave, etc., and can be of any type suitable for the measurement / test of the DUT, such as a current signal, voltage signal, etc. The amplitude / magnitude of the test signal 312 can be known, and thus can be used to determine the DUT characteristics. In the specific example of Figure 3 , the system 300 is configured to measure the impedance of the DUT 320, the test signal 312 is a current signal, and the input signal 205 is the voltage across the DUT 320.

[0029] The system 300 can optionally include a reference device 325 for system calibration. In Figure 3In a specific example, the reference device 325 is a reference resistor with a known high-precision impedance. The system 300 may also optionally have a multiplexer (MUX) / amplifier 330, which is configured to couple the ADC 210 to the DUT 320 or the reference device 325 and, optionally, also amplify the signal. For example, the MUX / amplifier 330 may first couple the ADC 210 to the reference device 325 such that the input signal 205 is a signal derived from the reference device 325 (e.g., the voltage across the reference device 325), and the system 300 may be calibrated for accurate measurement. After calibration, the MUX / amplifier 330 may then couple the ADC 330 to the DUT 320 such that the input signal 205 is a signal derived from the DUT 320 (e.g., the voltage across the DUT 320). It should be understood that in an alternative, the reference device 325 and the MUX / amplifier 330 may be omitted, and the system 300 is configured such that the ADC 210 input and the DUT 320 are directly coupled to each other (or indirectly coupled via an amplifier).

[0030] The system 300 also optionally includes a digital filter 340, which is coupled to the output of the ADC 340 to receive a plurality of digital samples 215, generate one or more filtered digital values based on the plurality of digital samplings 215, and output the one or more filtered digital values to the signal analyzer 350. By including the digital filter 340, the information received by the signal analyzer 350 can be improved, e.g., by filtering out or reducing unwanted / unnecessary information. In one example, the digital filter 340 may be a sinc filter, e.g., in the case of using a very high-frequency ADC 210, to reduce the number of samples received by the signal analyzer 350. However, it should be understood that the digital filter 340 may be completely omitted, in which case the digital samples 215 output by the ADC 210 may be directly received by the signal analyzer 350.

[0031] The signal analyzer 350 is configured to analyze a plurality of digital samples 215 to digitally determine at least one characteristic of the input signal 205 and / or the DUT 320 based on the received digital samples 215. For example, it can determine the amplitude / magnitude of the input signal 205 (e.g., the voltage or current amplitude / magnitude in the input signal 205). Additionally, or alternatively, it can determine the phase of the input signal 205 (e.g., the phase of the input signal relative to some other signal, such as the phase of the input signal relative to the test signal 312, or relative to some other reference signal). Additionally or alternatively, it can digitally determine any one or more of the following: the average (mode, median, and / or mean) of the amplitude / magnitude of the input signal 205; the variance of the amplitude / magnitude of the input signal 205 (including the standard deviation or sigma, since variance and standard deviation are inherently related); the entropy of the amplitude / magnitude of the input signal 205 (which is a measure of the lack of order or predictability of the signal); the average (mode, median, and / or mean) of the phase of the input signal 205 (e.g., the average phase of the input signal relative to a reference signal); the phase variance of the input signal 205; the phase entropy of the input signal 205. The input signal 205 can include a single frequency (e.g., if it is a single-tone signal) or multiple frequencies (e.g., a fundamental frequency and one or more harmonic frequencies, or in the case where the test signal 312 is a multi-tone signal, if the input signal 205 is a multi-tone signal, the input signal 205 can include multiple frequencies, or if the test signal 312 includes a continuous frequency band, the input signal 205 includes a continuous frequency band, etc.). For at least one of the signal frequencies of the input signal 205, at least one of the above-identified characteristics can be identified. Additionally, or alternatively, the signal analyzer 350 can digitally determine the frequency of the input signal 205 from the plurality of digital samples 215.

[0032] At least one of these digitally determined characteristics can be output as one or more digitally determined characteristics 355 to the controller 220. Additionally, or alternatively, the controller 220 can be configured to receive one or more reported characteristics 318 of the input signal 220, such as received from the signal generator 310 ( Figure 3It shows that the controller 220 receives the numerically determined feature 355 and the reported feature 318, but in another case, it can receive either the numerically determined feature 355 or the reported feature 318). Compared with one or more numerically determined features 355, one or more reported features 318 are not determined based on the digital samples 215 generated by the ADC 210, but are known by some other means. For example, one or more reported features 318 may include the frequency of the input signal 205. In this example, the signal generator 310 may know this frequency because it is generating a test signal 312 that will have substantially the same frequency as the input signal 205. As another example, one or more reported features 318 may include digital data indicating the frequency of the input signal 205, such as a register value received from the signal generator 310 or any other circuit / unit. Additionally, or alternatively, for each of at least one frequency of the input signal 205, the reported feature 355 may include the average value (mode, median, and / or mean) of the amplitude and / or phase of the input signal 205 (e.g., the phase of the input signal relative to a reference signal).

[0033] The controller 220 is configured to use the received numerically determined feature 335 and / or the reported feature 318 to control the number of digital conversions of the input signal 205 performed by the ADC 210 per unit time.

[0034] Figure 4Shows an example flow chart representing an example operation of the controller 220. Step S410 represents the start of a process, such as system startup or turn - on. In step S420, the controller 220 receives one or more reported characteristics 318, such as from the signal generator 310 or any other unit or circuit that can report at least one characteristic of the input signal 205. In a particular example, the reported characteristic 318 includes the frequency of the input signal 205, although it can alternatively or additionally be any of the other reported characteristics 318 described above. In a particular example, the reported characteristic received in step S420 can be the frequency, for example, if the input signal 205 includes a single tone (which may be the case if the signal generator 310 is configured to generate a single - tone test signal 312), or two or more frequencies, such as a fundamental frequency and one or more harmonic frequencies. In step S430, the controller 220 can determine the number of digital conversions per unit time that the ADC 210 should perform based on the reported characteristic 318, and then control the ADC 210 to perform that number of digital conversions per unit time. Different techniques for how the controller 220 controls the ADC 210 will be described later. In a particular example, the controller 220 can include (or have access to) a memory that stores a look - up table of digital conversion values per unit time according to the received reported characteristic 318. In another example, the controller 220 can be configured to include logic for executing an algorithm that uses the reported characteristic (e.g., the frequency of the input signal 205) as an input variable to the algorithm, and the algorithm outputs a value for the number of digital conversions per unit time.

[0035] In a particular example, the reported characteristic 318 may include the frequency of the input signal 205, and the controller 220 may be configured to set a relatively low number of digital conversions per unit time when the frequency of the input signal 205 is relatively low, and to set a relatively high number of digital conversions per unit time when the frequency of the input signal 205 is relatively high. For example, if the frequency of the input signal 205 is a first relatively low frequency (such as 1 Hz), the controller 220 may set the number of digital conversions per unit time to a relatively low first number of digital conversions per unit time. If the frequency of the input signal 205 is a second relatively high frequency (such as 1 kHz), the controller 220 may set the number of digital conversions per unit time to a relatively high second number of digital conversions per unit time, where the first number of digital conversions per unit time is less than the second number of digital conversions per unit time. By doing so, for a range of different input signal frequencies, the signal analyzer 350 can store and analyze a sufficient number of digital samples of input signal cycles to perform accurate signal analysis while minimizing the power consumption of the ADC 210 and the cost, complexity, and power consumption of the signal analyzer 350. The number of digital conversions per unit time may be proportional to the frequency of the input signal, or there may be predefined frequency bands of input signals, each having a corresponding predefined number of digital conversions per unit time.

[0036] In another example, the reported characteristic 318 may include an indication of the amplitude of the input signal 205. For example, if the amplitude of the input signal 205 is reported as being very small (e.g., less than a predefined amplitude threshold), it may be helpful to have digital samples corresponding to more cycles of the input signal 205. In this case, the controller 220 may be configured to reduce the number of digital samples per unit time compared to the number it would otherwise set, so that for a fixed number of digital samples (since typically the signal analyzer 350 is capable of storing and analyzing a fixed number of samples), more cycles of the input signal 205 can be represented.

[0037] In another example, the reported characteristic 318 may include an indication of the phase of the input signal 205 (e.g., its phase relative to the test signal 312). In the above example, it is desired to determine the impedance of the DUT 320, which consists of a real component and an imaginary component (or a phase component). If the DUT 320 introduces only a small phase difference between the test signal 312 and the input signal 205 (e.g., a phase less than a predetermined phase threshold), it may be more difficult to accurately measure the imaginary part (or phase) of the impedance. Similarly, if the DUT 320 introduces a relatively large phase difference between the test signal 312 and the input signal 205 (e.g., a phase greater than another predetermined phase threshold), it may be more difficult to accurately measure the real part of the impedance. In either case, a relatively high ADC sampling rate may be beneficial. As a result, the controller 220 may be configured to increase the number of digital samples per unit time compared to the number it was originally set to.

[0038] The controller 220 may be configured to repeatedly execute steps S420 and S430 until the systems 200, 300 stop operating (e.g., when it is turned off). In this way, whenever the reported characteristic 318 changes, e.g., because the frequency of the test signal 312 has changed, the controller 220 can become aware of it in step S420 and then adjust the number of digital conversions performed per unit time accordingly in step S430.

[0039] Figure 5 An example flowchart showing another example operation of the controller 220 is shown. Features similar to Figure 4 those are denoted by the same reference numerals and will not be described further for the sake of efficiency. In step S510, the controller 220 may set the number of digital samples performed per unit time to an initial default value and control the ADC 210 accordingly. In step S520, the controller 220 receives one or more digitally determined characteristics 355. In steps S530 and S550, the controller 220 determines whether the number of digital samples performed per unit time should be adjusted or kept the same. In Figure 5In a specific example, the received digital determination feature 355 includes any one or more of the following: the amplitude / magnitude of the input signal 205; the phase of the input signal 205; the average value of the amplitude / amplitude of the input signal 205; the variance of the amplitude / amplitude of the input signal 205; the entropy of the amplitude / amplitude of the input signal 205; the average value of the phase of the input signal 205; the phase variance of the input signal 205; and / or the entropy of the phase of the input signal 205. For each of these characteristics, the controller 220 may have a target value and / or a specific threshold and / or a value range. The controller 220 may be configured to compare each received characteristic with an appropriate target value and / or a specific threshold and / or a value range to determine whether to adjust the control of the ADC 210 and by how much. For example, the variance and / or entropy may depend on the accuracy with which a plurality of digital samples 215 represent the input signal 205. If the variance and / or entropy is relatively high, the plurality of digital samples 215 may not represent the input signal 205 with sufficient accuracy for the signal analyzer 360 to perform an accurate and reliable analysis. Thus, in such a case, step S530 may be configured to compare the received variance and / or entropy characteristic with a predetermined threshold. If it is greater than the threshold, the process may proceed to step S540, in which the controller 220 controls the ADC 210 to adjust the number of digital conversions performed per unit time (e.g., increase the number such that each cycle of the input signal 205 is more accurately represented by the digital samples 215, or decrease the number such that a fixed number of digital samples will represent more cycles of the input signal 205, which should improve the accuracy of the signal analysis performed on the digital samples 215. Whether the controller 220 is configured to increase or decrease the conversion rate of the ADC 210 may depend on the nature of the signal being measured and the type of signal analysis being performed on the digital samples, as well as implementation details). However, if it is less than the threshold, it is determined that the variance and / or entropy is at an acceptable level, and the method may proceed to step S550.

[0040] If the digital determination feature 355 includes the amplitude / magnitude of the input signal 205 and / or the average value of the amplitude / magnitude of the input signal 205, the controller 220 may have a target value or an expected value with which the digital determination characteristic may be compared, or may have a threshold below which the signal is considered relatively small (similar to that referred to above with reference to Figure 4The amplitude / magnitude example described above). For example, the system 300 may be calibrating using the reference device 325, in which case there will be a target or expected amplitude / magnitude (since the amplitude / magnitude of the test signal 312 is also known). If the magnitude of the difference between the received digitally determined characteristic and the target or expected value is greater than a predetermined tolerance threshold, the method can proceed to step S540 so that the input signal 205 can be more accurately represented by multiple digital samples 215 in the future. However, if the magnitude of the difference between the received digitally determined characteristic and the target or expected value is less than the predetermined tolerance threshold, the method can proceed to step S550. Similarly, if the digitally determined characteristic 355 includes the phase of the input signal 205 and / or the average value of the phase of the input signal 205, the controller 220 can have a target value or expected value with which the digitally determined characteristic can be compared, or can have a threshold below which the phase is considered relatively small and / or above which the phase is considered relatively large (similar to the amplitude / magnitude example described above with reference to Figure 4 The amplitude / magnitude example described above). Based on this comparison, the control of the ADC can be adjusted to make an appropriate change to the number of conversions per unit time.

[0041] In step S550, the controller 220 can determine whether to control the ADC 210 in a way that reduces the number of digital conversions performed per unit time. The aim is to try to achieve a conversion rate that satisfies step S530 but with the minimum number of conversions per unit time, thereby minimizing the power consumption of the ADC 210. If it is determined that the number of conversions per unit time should be reduced, the method proceeds to step S560, in which the controller 220 controls the ADC 210 in a way that reduces the number of conversions per unit time. However, if it is determined that the number of conversions per unit time should not be reduced, the method returns to step S520.

[0042] The determination in step S550 can be made in a number of different ways. In one example, step S550 can always determine that the number of digital conversions per unit time should be reduced, and the method always proceeds from step S550 to step S560. Based on this, the conversion rate can be continuously reduced until step S530 determines that the conversion rate is too low and the conversion rate is increased through step S540. This should result in the conversion rate being continuously adjusted up and down around the ideal conversion rate. In an alternative, step S550 can be determined at least in part based on the determination in step S530. For example, if the received digitally determined characteristic is just within the target / expected range, it can be determined in step S550 that the conversion rate should not be changed. However, if the received digitally determined characteristic is well within the target / expected range, it can be determined in step S550 that the conversion rate should be reduced based on the likelihood that subsequent digitally determined characteristics may still remain within the target / expected range.

[0043] Another advantage of this operating mode is that the conversion rate of ADC 210 is not rigidly tied to the frequency of the input signal 205. In this case, it is typically oversampled, and the ADC 210 conversion frequency is a multiple of the frequency of the input signal 205. Instead, the conversion rate of ADC 210 is associated with the result of the digital signal analysis, which means that the controller 220 can control the ADC 210 to convert at any rate, thereby potentially scanning the ADC 210 over a wide range of conversion frequencies including undersampling and oversampling frequencies. This means that if there is an interfering source or unwanted signal that aliases into the band of interest at a particular ADC 210 conversion rate, it should be reflected in the unwanted results in the digitally determined characteristic 355, thereby enabling the controller 220 to avoid these ADC conversion rates. Therefore, by finding the optimal ADC conversion rate, the overall accuracy of the multiple digital samples 215 and subsequent signal analysis should be improved.

[0044] The controller 220 can be configured to continuously loop back to step S520, as Figure 5 shown, until the systems 200, 300 stop operating (e.g., when it shuts down). In this way, after the initial step of S510, the conversion rate of the ADC 210 can be controlled in steps S520 to S560 based on one or more previous digital samples 215 generated by the ADC 210. Therefore, the control of the ADC 210 conversion rate can be continuously updated and fine-tuned to find the optimal conversion rate and react to any future changes (e.g., changes in the frequency of the input signal 205, thereby improving or deteriorating the digitally determined characteristic 355).

[0045] Figure 6 shows an example flow chart representing another example operation of the controller 220. Features similar to Figure 4 and Figure 5 are denoted by the same reference numerals and will not be further described for the sake of efficiency. As shown, Figure 6 the process of Figure 4 and Figure 5 is basically combined, so the controller 220 utilizes the reported characteristic 318 and the digitally determined characteristic 355. In this example, the loop returns to step S420. In this case, step S430 can be configured to adjust the ADC conversion rate only if the reported characteristic 318 changes compared to the previous iteration. In this way, any conversion rate changes made in step S540 or S560 should not be immediately undone by step S430. In an alternative, the loop can instead return to step S520, such that the reported characteristic 318 is basically only used at the beginning to set the initial ADC conversion rate.

[0046] Thus, it can be seen that by controlling the conversion rate of the ADC 210 in this way, the systems 200, 300 are made adaptive. In one exemplary benefit, the power efficiency of the systems 200, 300 can be increased because unnecessary high conversion rates can be avoided when the frequency of the input signal 205 is relatively low. Additionally, it can improve the overall accuracy across the frequency range without the need for any additional storage resources because at lower input signal 205 frequencies, more digital samples representing more cycles of the input signal 205 can be stored and processed for the same amount of memory. Signal analysis performed on data representing more cycles of the signal is generally more accurate and reliable. Alternatively, the overall accuracy level can be maintained while reducing the amount of memory resources, thereby saving cost and reducing complexity because fewer digital samples are needed to represent the same number of cycles of the input signal 205 when the input signal 205 is at a relatively low frequency.

[0047] Figure 7 A schematic diagram showing an example of a way in which the controller 220 can control the number of digital conversions performed by the ADC 210 per unit time is shown. In this example, the controller 220 is configured to receive a reference clock signal 705 having a reference frequency (e.g., a periodic signal such as a periodic square wave signal). The controller 220 includes a decimator or divider that is configured to divide the reference clock signal 705 by a variable N (where N≥1) to produce a clock signal 715 having a frequency less than or equal to the reference frequency. The ADC 210 is configured to receive the clock signal 715 for synchronizing its digital sample generation process, which is a process well understood by those skilled in the art. In this example, the number of digital conversions performed by the ADC 210 per unit time depends on the frequency of the received clock signal 715. As a result, by setting the value of N based on the reported characteristic 318 and / or the digitally determined characteristic 355, the controller 220 can control the number of digital conversions performed by the ADC 210 per unit time.

[0048] In an alternative, the controller 220 can be configured to generate the clock signal 715 in any other suitable way rather than by dividing the received reference clock signal 405 to generate the clock signal 715. For example, the controller 220 can include a reference clock generator to generate the reference clock signal 705 for itself, or it can include a variable frequency clock generator to directly generate the clock signal 715 at the desired frequency.

[0049] Figure 8A schematic diagram showing another example way in which the controller 220 can control the number of digital conversions that the ADC 210 performs per unit time is shown. In this example, the ADC 210 is configured to receive a reference clock signal 705 for synchronizing its digital sample generation process. The controller 220 is configured to control the state of an enable signal 815, which controls when the ADC 210 is enabled to perform a digital conversion. This technique can be referred to as "enable gating". For example, as will be understood by those skilled in the art, many ADCs have an enable pin / terminal, where the ADC 210 is configured to perform a digital conversion when the enable signal at the enable pin / terminal is high (or low), and not to perform a digital conversion when the enable signal at the enable pin or terminal is low (or high). Thus, regardless of the frequency of the reference clock signal 705, the controller 220 can control the conversion rate of the ADC 210 by controlling when the ADC 210 is enabled and not enabled to convert. For example, the controller 220 can set the enable signal 405 to a periodic signal having a specific duty cycle between high and low. When fewer conversions are needed per unit time, the controller 220 can lower the frequency of the enable signal 405 and / or can adjust the duty cycle such that the ADC 210 is enabled for a smaller proportion of the duration of the enable signal 815. In this way, the ADC 210 can be controlled to perform digital conversions at regular intervals such that the plurality of digital samples 215 should still accurately represent the input signal 205, but the number of digital samples produced per unit time can be adjusted. Based on the reference frequency of the reference clock signal 705, it can be determined how many digital conversions should be performed within each amount of time that the ADC 210 is enabled by the enable signal 815. As a result, setting the duty cycle and / or frequency of the enable signal 815 should result in the desired conversion rate of the ADC 210.

[0050] In another alternative, the controller 220 can be configured to control when the ADC 210 can perform digital conversion in some other way, rather than controlling the state of the enable signal 815. For example, it can control when the ADC 210 is powered on, such as by controlling the switch that connects the ADC 210 to the power supply, or by controlling when the power supply powers the larger circuit or device to which the ADC 210 belongs. This can be referred to as "power gating". In this way, when the ADC 210 is powered on, it can generate a plurality of digital samples 215 at a rate set by the reference clock signal 705. When the controller 220 powers off the ADC 210, it will stop generating digital samples 215 of the input signal 205. Therefore, by powering on and off the ADC 210 at a frequency and / or duty cycle controlled by the controller 220, the number of digital samples generated per unit time can be controlled in a similar way through power gating to achieve the above-mentioned gating. Power gating in this way can have the particular advantage of minimizing power consumption, because when the ADC 210 is powered off, it does not consume any power at all. In addition, in the power gating and enable gating examples, the need for additional hardware, such as Figure 7 the frequency divider 710, or additional system design, verification, and validation are not required (since the fixed reference clock signal 705 is used to synchronize the conversion process of the ADC 210).

[0051] Figure 9 FIG. shows a schematic diagram of an example signal measurement system 900 according to another aspect of the present disclosure. The system 900 is very similar to the above-described system, but also includes a variable gain amplifier (VGA) 910. In this example, the controller 220 is configured not only to control the conversion rate of the ADC 210, but also to control the gain of the VGA 910. The control of the VGA 910 gain can be performed based on the reported characteristic 318 and / or the digitally determined characteristic 355, and can help improve the signal-to-noise ratio (SNR) of the system. For example, if it is recognized from the reported characteristic 318 and / or the digitally determined characteristic 355 that the input signal 205 is relatively small (e.g., because the amplitude / amplitude or average amplitude / amplitude of the input signal 205 is less than a predetermined threshold), the VGA 910 can be controlled to increase its gain. The VGA 910 can be any suitable type known to those skilled in the art and can be controlled in any suitable way, such as by controlling a switched capacitor (SC) gain stage, a resistor gain state, a variable first-stage integrator, an integration time gain stage, etc.

[0052] Those skilled in the art will readily understand that various changes or modifications can be made to the above aspects of the present disclosure without departing from the scope of the present disclosure.

[0053] For example, the above description generally focuses on using system 200 as part of an impedance spectroscopy, particularly battery impedance spectroscopy performance. However, system 200 can be used to measure input signal 205 for any purpose. For example, DUT 320 can be any device having a resistive impedance (where a battery is an example), but it can also be any other type of device, such as a sensing or sensor device that can be an electrical, electrochemical, or bioimpedance device.

[0054] The functionality of controller 220 can be implemented by software, hardware, or a combination of software and hardware. For example, it can be implemented by software including computer-readable code that, when executed on a processor of an electronic device such as a microprocessor, performs the above functions. The software can be stored on any suitable computer-readable medium, such as a non-transitory computer-readable medium, like read-only memory, random access memory, CD-ROM, DVD, Blu-ray, magnetic tape, hard disk drive, solid-state drive, and optical disk drive. Alternatively, the functionality can be implemented by hardware, in which case controller 220 can include dedicated logic circuits, FPGAs, microcontrollers, etc., configured to perform the above functions.

[0055] The term "coupled" as used above includes a direct electrical connection between two components, as well as an indirect electrical connection where two components are electrically connected to each other through one or more intermediate components.

[0056] Aspects of the present invention

[0057] Non-limiting aspects of the present disclosure are listed in the following numbered clauses.

[0058] 1. A signal measurement system for digitally converting an input signal, the system comprising:

[0059] An analog-to-digital converter ADC configured to:

[0060] Receive the input signal; and

[0061] Generate a plurality of digital samples of the input signal; and

[0062] A controller configured to control the number of digital conversions of the input signal performed by the ADC per unit time based on at least one of:

[0063] A characteristic of the input signal;

[0064] A digitally determined characteristic of the input signal, where the digitally determined characteristic of the input signal is based on one or more previous digital samples of the input signal generated by the ADC.

[0065] 2. The signal measurement system of clause 1, wherein the characteristic of the input signal includes the frequency of the input signal.

[0066] The signal measurement system according to clause 2, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time such that:

[0067] when the frequency of the input signal is a first frequency, a first number of digital conversions of the input signal are performed by the ADC per unit time; and

[0068] when the frequency of the input signal is a second frequency, a second number of digital conversions of the input signal are performed by the ADC per unit time,

[0069] wherein the first number of digital conversions per unit time is less than the second number of digital samplings per unit time, and

[0070] wherein the first frequency is less than the second frequency.

[0071] 4. The signal measurement system according to any of the preceding clauses, wherein the characteristics of the input signal include any one or more of the following:

[0072] The amplitude of the input signal;

[0073] The phase of the input signal.

[0074] 5. The signal measurement system according to any of the preceding clauses, wherein the digitally determined characteristics of the input signal include any one or more of the following:

[0075] The amplitude of the input signal;

[0076] The average value of the amplitude of the input signal;

[0077] The variance of the amplitude of the input signal;

[0078] The entropy of the amplitude of the input signal;

[0079] The phase of the input signal;

[0080] The average value of the phase of the input signal;

[0081] The phase variance of the input signal;

[0082] The phase entropy of the input signal;

[0083] The frequency of the input signal.

[0084] 6. The signal measurement system according to any of the preceding clauses, wherein the ADC is configured to receive a clock signal for synchronizing the generation of digital samples.

[0085] 7. The signal measurement system according to clause 6, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the frequency of the clock signal received by the ADC.

[0086] 8. The signal measurement system according to clause 6 or clause 7, wherein the ADC is configured to receive an enable signal, the enable signal controlling when the ADC is enabled to perform digital conversion, and

[0087] wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the state of the enable signal.

[0088] 9. The signal measurement system according to any one of clauses 6 to 8, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the power supply to the ADC.

[0089] 10. The signal measurement system according to any of the preceding clauses, further comprising a signal analyzer configured to analyze the plurality of digital samples to determine any one or more of the following:

[0090] The amplitude of the input signal;

[0091] The average value of the amplitude of the input signal;

[0092] The variance of the amplitude of the input signal;

[0093] The entropy of the amplitude of the input signal;

[0094] The phase of the input signal;

[0095] The average value of the phase of the input signal;

[0096] The phase variance of the input signal;

[0097] The phase entropy of the input signal;

[0098] The frequency of the input signal.

[0099] 11. The signal measurement system according to any one of clauses 1 to 9, further comprising a digital filter configured to:

[0100] Receive the plurality of digital samples;

[0101] Generate one or more filtered digital values based on the plurality of digital samples; and

[0102] Output the one or more filtered digital values.

[0103] 12. The signal measurement system according to clause 11, wherein the digital filter includes a sinc filter.

[0104] 13. The signal measurement system according to clause 11 or clause 12, further comprising a signal analyzer configured to analyze the one or more filtered digital values to determine any one or more of the following:

[0105] The amplitude of the input signal;

[0106] The average value of the amplitude of the input signal;

[0107] The variance of the amplitude of the input signal;

[0108] The entropy of the amplitude of the input signal;

[0109] The phase of the input signal;

[0110] The average value of the phase of the input signal;

[0111] The phase variance of the input signal;

[0112] The phase entropy of the input signal;

[0113] The frequency of the input signal.

[0114] 14. The signal measurement system according to clause 10 or clause 13, wherein the signal analyzer is configured to perform the analysis using any one or more of the following: discrete Fourier transform (DFT); fast Fourier transform; discrete cosine transform; wavelet processing.

[0115] 15. The signal measurement system according to any of the preceding clauses, wherein the system is used to measure the characteristics of a device under test (DUT), and the input signal is a signal derived from the DUT, and the system is further configured to:

[0116] Measure the characteristics of the DUT using the plurality of digital samples.

[0117] 16. The signal measurement system according to clause 15, further comprising:

[0118] A signal generator for generating a test signal to be applied to the DUT when measuring the characteristics of the DUT, wherein the input signal depends on the test signal.

[0119] 17. The signal measurement system according to clause 16, wherein the signal generator is controllable to change the frequency of the test signal such that the characteristics of the DUT can be measured at a plurality of different test signal frequencies.

[0120] 18. The signal measurement system according to any one of clauses 15 to 17, wherein the characteristic of the DUT is the impedance of the DUT.

[0121] 19. A method for digitally converting an input signal, the method comprising:

[0122] An analog-to-digital converter ADC:

[0123] Receiving the input signal; and

[0124] Generating a plurality of digital samples of the input signal; and

[0125] A controller that controls the number of digital conversions of the input signal performed by the ADC per unit time based on at least one of:

[0126] The characteristic of the input signal;

[0127] The characteristic of the input signal measurement, wherein the input signal measurement is based on one or more previous digital samples of the input signal generated by the ADC.

[0128] 20. A controller configured to control the number of digital conversions of an input signal performed by an analog-to-digital converter ADC per unit time based on at least one of:

[0129] The characteristic of the input signal, wherein the input signal is input to the ADC for digital conversion;

[0130] The digitally determined characteristic of the input signal, wherein the digitally determined characteristic of the input signal is based on one or more previous digital samples of the input signal generated by the ADC.

[0131] 21. The controller according to clause 20, wherein the characteristic of the input signal includes the frequency of the input signal.

[0132] 22. The controller according to clause 21, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time such that:

[0133] When the frequency of the input signal is a first frequency, a first number of digital conversions of the input signal are performed by the ADC per unit time; and

[0134] When the frequency of the input signal is a second frequency, a second number of digital conversions of the input signal are performed by the ADC per unit time,

[0135] wherein the first number of digital conversions per unit time is less than the second number of digital samplings per unit time, and

[0136] Wherein the first frequency is less than the second frequency.

[0137] 23. The controller according to any one of clauses 20 to 22, wherein the characteristics of the input signal include any one or more of the following:

[0138] The amplitude of the input signal;

[0139] The phase of the input signal.

[0140] 24. The controller according to any one of clauses 20 to 23, wherein the digitally determined characteristics of the input signal include one or more of the following:

[0141] The amplitude of the input signal;

[0142] The average value of the amplitude of the input signal;

[0143] The variance of the amplitude of the input signal;

[0144] The entropy of the amplitude of the input signal;

[0145] The phase of the input signal;

[0146] The average value of the phase of the input signal;

[0147] The phase variance of the input signal;

[0148] The phase entropy of the input signal;

[0149] The frequency of the input signal.

[0150] 25. The controller according to any one of clauses 20 to 24, wherein the ADC is configured to receive a clock signal for synchronizing digital sample generation.

[0151] 26. The controller according to clause 25, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the frequency of the clock signal received by the ADC.

[0152] 27. The controller according to clause 25 or clause 26, wherein the ADC is configured to receive an enable signal, the enable signal controlling when to enable the ADC to perform digital conversion, and

[0153] wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the state of the enable signal.

[0154] 28. The controller according to any one of clauses 25 to 27, configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the power supply to the ADC.

Claims

1. A signal measurement system for digitally converting an input signal, the system comprising: The analog-to-digital converter ADC is configured as: receiving an input signal; and generating a plurality of digital samples of the input signal; and A controller configured to control the number of digital conversions of an input signal performed by the ADC per unit time based on at least one of: Characteristics of the input signal; A digitally determined characteristic of the input signal, wherein the digitally determined characteristic of the input signal is based on one or more previous digital samples of the input signal generated by the ADC. 2 . The signal measurement system of claim 1 , wherein the characteristic of the input signal comprises a frequency of the input signal.

3. The signal measurement system according to claim 2, wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time such that: When the frequency of the input signal is a first frequency, performing a first number of digital conversions of the input signal per unit time by the ADC; and When the frequency of the input signal is a second frequency, the ADC performs a digital conversion of a second quantity of the input signal per unit time, wherein the first number of digital conversions per unit time is less than the second number of digital samples per unit time, and The first frequency is smaller than the second frequency.

4. The signal measurement system according to claim 1, wherein the characteristics of the input signal include any one or more of the following: the amplitude of the input signal; The phase of the input signal.

5. The signal measurement system of claim 1 , wherein the digitally determined characteristics of the input signal include one or more of the following: the amplitude of the input signal; The average value of the input signal amplitude; The variance of the input signal amplitude; Entropy of the input signal amplitude; The phase of the input signal; The average value of the input signal phase; The phase variance of the input signal; Phase entropy of the input signal; The frequency of the input signal. The signal measurement system of claim 1 , wherein the ADC is configured to receive a clock signal for synchronizing digital sample generation. 7 . The signal measurement system of claim 6 , wherein the controller is configured to control the number of digital conversions of the input signal performed per unit time by the ADC by controlling a frequency of a clock signal received by the ADC.

8. The signal measurement system of claim 6, wherein the ADC is configured to receive an enable signal, the enable signal controlling when the ADC is enabled to perform digital conversion, and The controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling the state of the enable signal. 9 . The signal measurement system according to claim 6 , wherein the controller is configured to control the number of digital conversions of the input signal performed by the ADC per unit time by controlling power supply to the ADC.

10. The signal measurement system of claim 1, further comprising a signal analyzer configured to analyze the plurality of digital samples to determine any one or more of the following: the amplitude of the input signal; The average value of the input signal amplitude; The variance of the input signal amplitude; Entropy of the input signal amplitude; The phase of the input signal; The average value of the input signal phase; The phase variance of the input signal; Phase entropy of the input signal; The frequency of the input signal.

11. The signal measurement system according to claim 1 , further comprising a digital filter configured to: receiving the plurality of digital samples; generating one or more filtered digital values ​​based on the plurality of digital samples; and The one or more filtered digital values ​​are output.

12. The signal measurement system of claim 11, further comprising a signal analyzer configured to analyze the one or more filtered digital values ​​to determine any one or more of the following: the amplitude of the input signal; The average value of the input signal amplitude; The variance of the input signal amplitude; Entropy of the input signal amplitude; The phase of the input signal; The average value of the input signal phase; The phase variance of the input signal; Phase entropy of the input signal; The frequency of the input signal.

13. A signal measurement system according to any preceding claim, wherein the system is used to measure a characteristic of a device under test (DUT), and the input signal is a signal derived from the DUT, the system being further configured to: A characteristic of the DUT is measured using the plurality of digital samples.

14. The signal measurement system according to claim 13, further comprising: A signal generator is used to generate a test signal to be applied to the DUT when measuring the characteristics of the DUT, wherein the input signal depends on the test signal.

15. The signal measurement system of claim 14, wherein the signal generator is controllable to vary the frequency of the test signal so that the characteristics of the DUT can be measured at a plurality of different test signal frequencies.

16. The signal measurement system of claim 13, wherein the characteristic of the DUT is an impedance of the DUT.

17. A method for digitally converting an input signal, the method comprising: Analog-to-digital converter ADC: receiving the input signal; and generating a plurality of digital samples of the input signal; and A controller controls the number of digital conversions of an input signal performed per unit time by the ADC based on at least one of: Characteristics of the input signal; A characteristic of the input signal measurement, wherein the input signal measurement is based on one or more previous digital samples of the input signal generated by the ADC.

18. A controller configured to control the number of digital conversions of an input signal performed per unit time by an analog-to-digital converter (ADC) based on at least one of: characteristics of an input signal, wherein the input signal is input to the ADC for digital conversion; A digitally determined characteristic of the input signal, wherein the digitally determined characteristic of the input signal is based on one or more previous digital samples of the input signal generated by the ADC.

19. The controller of claim 18, wherein the characteristic of the input signal comprises a frequency of the input signal.

20. The controller of claim 18, wherein the digitally determined characteristics of the input signal include one or more of: the amplitude of the input signal; The average value of the input signal amplitude; The variance of the input signal amplitude; Entropy of the input signal amplitude; The phase of the input signal; The average value of the input signal phase; The phase variance of the input signal; Phase entropy of the input signal; The frequency of the input signal.

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