Chip delay error dynamic compensation method and system based on TDC

Abstract

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip delay error dynamic compensation scheme design, and particularly relates to a chip delay error dynamic compensation method and system based on a TDC. BACKGROUND

[0002] With the continuous advancement of semiconductor process nodes, the working frequency of chips is increasing, and the requirement for timing accuracy is becoming more and more stringent. In modern high-performance computing, communication and precision measurement fields, whether the chip can maintain timing stability under changing working conditions directly determines the reliability and performance of the system. However, in actual work, the transmission delay of the internal logic path of the chip will be significantly affected by process deviation, working voltage fluctuation and environmental temperature change (collectively referred to as PVT change). Such delay fluctuation may cause setup time or hold time violations, causing timing errors, and even causing system failure.

[0003] The traditional timing guarantee method mainly relies on static timing analysis in the design stage and pre-reserves a fixed timing margin in the chip. This method can still be used in the scene where the PVT condition is relatively stable, but its essence is a static and conservative strategy. In order to cover the worst case, a larger timing margin often needs to be reserved, which inevitably sacrifices the performance peak and energy efficiency of the chip. For high-frequency or precision measurement chips with complex and variable working conditions, this fixed margin method is increasingly insufficient. Dynamic voltage frequency scaling and other technologies can respond to system changes to some extent, but they are usually based on coarse-grained performance monitoring and are difficult to accurately compensate for subtle and rapid path delay changes.

[0004] In recent years, time-to-digital converter technology has attracted attention due to its high-precision time interval measurement capability. Some schemes attempt to use TDC to monitor the delay of the chip, but most applications still remain at the monitoring and diagnosis level and fail to form an efficient closed-loop control. How to combine the real-time accurate measurement capability of TDC with a low-overhead, adaptive control algorithm to build a complete scheme that can predict and actively compensate for delay errors in real time, thereby dynamically maintaining the chip timing closed loop, is a technical problem that needs to be solved in the current industry.

[0005] Therefore, the prior art still needs further development. SUMMARY

[0006] The present application aims to overcome the above technical deficiencies and provide a chip delay error dynamic compensation method and system based on a TDC to solve the problems existing in the prior art.

[0007] To achieve the above technical purpose, according to the first aspect of the present application, the present application provides a chip delay error dynamic compensation method based on a TDC, comprising: S1, measuring the delay of the critical path in real time by using a TDC core integrated inside the chip; S2, predicting the delay error by using an embedded algorithm based on the delay measurement value; S3, dynamically compensating the chip timing according to the predicted delay error.

[0008] Specifically, the step of measuring the delay of the critical path in real time by using the TDC core includes measuring the propagation time of a signal from a starting point to an ending point on the critical path by using the TDC core.

[0009] Specifically, the TDC core uses a Vernier method to measure time.

[0010] Specifically, the step of predicting the delay error by using the embedded algorithm includes predicting the delay trend by using a prediction model.

[0011] Specifically, the prediction model is a model based on machine learning.

[0012] Specifically, the dynamic compensation includes adjusting a clock signal or modifying the path delay.

[0013] Specifically, the step of adjusting the clock signal is implemented by dynamic frequency scaling.

[0014] Specifically, the method further includes the steps of verifying the effect of the dynamic compensation and adaptively adjusting the prediction algorithm.

[0015] Specifically, the verification is implemented by comparing the actual delay with the expected delay.

[0016] According to a second aspect of the present application, a TDC-based chip delay error dynamic compensation system is provided, comprising: a TDC core integrated inside the chip, configured to measure the delay of the critical path in real time; an embedded processing unit configured to predict the delay error by using an embedded algorithm based on the measurement value of the TDC core; a dynamic compensation unit configured to compensate the chip timing according to the predicted delay error.

[0017] Advantages: The TDC-based chip delay error dynamic compensation method and system provided by the present application can produce a series of significant advantages compared with the prior art.

[0018] Firstly, the application realizes active cancellation of delay fluctuation caused by process, voltage and temperature changes by using TDC core integrated inside the chip for real-time and high-precision critical path delay measurement, and combining embedded algorithms for dynamic prediction and compensation. This dynamic compensation mechanism changes the traditional static timing guarantee into adaptive timing management, fundamentally improving the timing stability and robustness of the chip under complex working environment, and significantly reducing the system failure risk caused by timing violations.

[0019] Secondly, the method of the application realizes complete closed-loop control from monitoring to compensation. By verifying the compensation effect in real time and adaptively adjusting the prediction algorithm, the system has the ability of continuous learning and self-optimization, can effectively track the long-term trend of delay change, and the compensation strategy is more forward-looking and accurate. This not only improves the response speed to rapidly changing factors, but also enhances the adaptability to slow drift (such as temperature change), ensuring the reliability of long-term work.

[0020] Finally, the system scheme of the application adopts a highly integrated design, integrating the TDC core, processing unit and compensation unit inside a single chip. This integrated design reduces the dependence on external test or calibration equipment, reduces system complexity and cost. At the same time, due to the precise dynamic compensation, the chip does not need to reserve a large static timing margin in the design stage, so the performance potential of the chip can be tapped, the operation speed can be improved or the power consumption can be reduced while ensuring reliability, which is particularly suitable for high-frequency chips and precision measurement chips with stringent requirements on timing and energy efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a flowchart of the TDC-based chip delay error dynamic compensation method provided in the embodiments of the application; Figure 2 is a system composition diagram of the TDC-based chip delay error dynamic compensation system provided in the embodiments of the application. DETAILED DESCRIPTION

[0022] In order for those skilled in the art to better understand the technical solutions of the application, the technical solutions of the application will be described clearly and completely below in combination with the drawings of the application. Based on the embodiments in the present application, other similar embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present application. In addition, the directional words mentioned in the following embodiments, such as "up", "down", "left", "right", etc. are only reference directions of the drawings, therefore, the directional words used are used for illustration and not for limiting the present application.

[0023] The application will be further described below in combination with the drawings and preferred embodiments.

[0024] Referring to Figure 1 The application provides a TDC-based chip delay error dynamic compensation method, comprising: S1, measuring the delay of a key path in real time by using a TDC core integrated in a chip.

[0025] It should be further explained that the TDC core is specifically integrated near a clock distribution network of the chip or at the start and end points of a key data path, for example, in a processor chip, the key path can be a key calculation path of an arithmetic logic unit (ALU), and the measurement frequency of the TDC core is set to 1000 Hz (i.e. 1000 measurements per second), the preferred value of the frequency is selected based on the working frequency of the chip and the power consumption balance, and the reason is as follows: the delay of a high-frequency chip (such as a working frequency above 1 GHz) changes rapidly, and the sampling frequency needs to be high enough to capture the change, but too high sampling (such as more than 10 kHz) will increase the power consumption and hardware overhead, therefore 1000 Hz is an empirical value, which can cover most application scenarios (such as high-frequency communication chips), and meanwhile keeps the power consumption within an acceptable range (for example, the TDC core power consumption is controlled within 5% of the total power consumption of the chip).

[0026] Further, during the measurement, the TDC core outputs the delay value in digital form, and the resolution is set to 10 ps (picoseconds), the preferred value of the resolution is selected based on the timing tolerance of the chip, and the reason is that the minimum delay change is usually several tens of picoseconds, and the 10 ps resolution can accurately detect the change, but too high resolution (such as 1 ps) will increase the circuit complexity, therefore 10 ps is a balance point of precision and cost.

[0027] S2, predicting the delay error by using an embedded algorithm based on the delay measurement value.

[0028] It needs to be further explained that the embedded algorithm runs on the microcontroller (such as ARM Cortex-M0 core) built in the chip, and the algorithm specifically adopts an exponential smoothing prediction model, which is simple and has small calculation amount, and is suitable for embedded environment. The model formula is: predicted error value = a x current measurement error + (1-a) x last time prediction error, wherein a is a smoothing coefficient, and the preferred value is 0.7. The reason for selecting this value is that a = 0.7 can quickly respond to new data (weight 70%) while retaining historical trends (weight 30%), which is suitable for scenarios where delay data usually has short-term correlation; if a is too small (such as 0.3), the response is lagging; if a is too large (such as 0.9), it is easily affected by noise. In the formula, the predicted error value represents the delay error prediction at the next time point (unit: ps), the current measurement error is the difference between the latest measurement value of the TDC core and the nominal delay (the nominal delay is determined when the chip is designed, for example, for a 1GHz chip, the nominal path delay is 1ns), and the last time prediction error is the prediction output of the last period. The algorithm performs prediction every 10 measurement points (i.e. every 10ms) to reduce processing load.

[0029] S3, dynamically compensating the chip timing according to the predicted delay error.

[0030] It needs to be further explained that the compensation is achieved by adjusting the phase of the internal clock generator (such as PLL) of the chip, and the specific compensation amount is: phase adjustment amount = Kp x predicted error value, wherein Kp is a proportional coefficient, and the preferred value is 1.5. The reason for selecting this value is that Kp = 1.5 provides moderate overcompensation, which can offset the system response delay, but not too large to avoid oscillation; the compensation action is completed within the clock period, for example, adjusted once every prediction, and the adjustment step is at least 5ps. The whole process is executed in a loop to form a closed loop control. It can be understood that this method can offset the delay fluctuation caused by process, voltage and temperature (PVT) changes in real time, reduce the timing error by more than 50%, and significantly improve the stability and yield of the chip under high frequency operation. Those skilled in the art can integrate TDC and algorithm logic through conventional EDA tools (such as Synopsys Prime Time).

[0031] Specifically, the real-time measurement of the delay of the critical path by the TDC core includes: measuring the propagation time of a signal from the starting point to the ending point on the critical path by the TDC core.

[0032] It needs to be further explained that in specific implementation, the critical path is determined by static timing analysis (STA) in the chip design stage, for example, in a CPU chip, the critical path can be the longest combinational logic path, starting from the output of register A and ending at the input of register B. The TDC core is physically arranged near the starting point and the ending point, and the propagation time is measured by detecting the time difference between the starting point signal (such as the rising edge of the clock) and the ending point signal (such as the data valid signal). The measurement circuit includes a start signal (starting trigger) and a stop signal (ending trigger), and the TDC core uses time-to-digital conversion technology, for example, based on the counter method, counting the number of clock cycles, and the clock frequency is preferably 100MHz (period 10ns), the measurement range covers 0-10ns, and the resolution is 10ps. The preferred value of the resolution is selected based on the typical value of the path delay (usually 1-5ns), and the reason is that a change as small as 10ps needs to be detected to avoid timing violations. In implementation, the measurement is performed periodically, and a continuous measurement is performed every 1ms, and the average value is taken as the output to reduce noise.

[0033] It can be understood that the above scheme ensures that the measurement target is clear, improves the specificity of the method, enables the person skilled in the art to directly locate the critical path, reduces measurement errors, and improves compensation accuracy.

[0034] Specifically, the TDC core uses vernier method for time measurement.

[0035] It needs to be further explained that the TDC core uses vernier method for time measurement. Vernier method is a high-precision time measurement technology, and in specific implementation, the TDC core includes two ring oscillators: a fast oscillator and a slow oscillator, and the frequency of the fast oscillator is preferably 1.1GHz, and the frequency of the slow oscillator is preferably 1.0GHz. The preferred value of the frequency ratio 1.1:1 is selected based on the trade-off between measurement accuracy and circuit complexity, and the reason is that this ratio can achieve high resolution (theoretical resolution = 1 / (fast frequency-slow frequency) = 1 / 0.1GHz = 10ps), and at the same time, the frequency difference of the oscillators is not too large, avoiding difficulty in phase locking. The measurement process is as follows: when the starting point signal arrives, the fast oscillator starts counting; when the ending point signal arrives, the slow oscillator starts counting. The time calculation formula is: propagation time = (fast count-slow count) x T_base, where T_base is the basic time unit, which is preferably the inverse of the slow oscillator period, i.e. 1ns (corresponding to 1GHz). In the formula, fast count is the number of pulses (integer) of the fast oscillator from start to stop, slow count is the number of pulses (integer) of the slow oscillator from start to stop, and T_base is the time reference (unit: second).

[0036] Further, the Vernier method further comprises a calibration circuit, which performs calibration once every 1000 measurements, and the calibration method is to correct the counting error by measuring a known delay (such as an internal reference delay of 100 ps), and the calibration threshold is set to 5 ps, that is, when the error exceeds 5 ps, the frequency of the oscillator is adjusted.

[0037] It can be understood that the Vernier method provides an accuracy of up to 10 ps and low power consumption (oscillator power of about 1 mW), and is particularly suitable for integration in a chip, can accurately capture delay changes, and enhances the reliability of the method.

[0038] Specifically, the prediction of the delay error by the embedded algorithm comprises: using a prediction model to predict the delay trend.

[0039] It needs to be further explained that the prediction of the delay trend by the prediction model. In specific implementation, the prediction model uses an autoregressive (AR) model, which is simple and suitable for embedded processing. The model order p is preferably 2, and the reason for selecting this value is that p=2 can capture the short-term trend (such as first-order difference) and inertia (second-order difference) of the delay data, while the calculation amount is small (only the last 2 points need to be stored); higher order (such as p=3) will increase the complexity but the accuracy will be improved limitedly. The model formula is: error prediction value = a1 x E_{t-1} + a2 x E_{t-2}, wherein a1 and a2 are model coefficients, and the preferred values are a1=0.6 and a2=0.4, which are obtained by training historical data, and the training uses the least square method, and the training data are the last 100 measurement error values (acquisition frequency of 1000 Hz, i.e. 0.1 second data), and the training period is performed once every 100 measurements (i.e. every 0.1 second) to adapt to changes. In the formula, the error prediction value is the predicted error at time t (unit: ps), E_{t-1} is the actual measurement error at time t-1, and E_{t-2} is the actual measurement error at time t-2. The model also includes noise processing, and if the measurement error changes more than the threshold value of 50 ps, the point is ignored to avoid abnormal influence.

[0040] It can be understood that the AR model can effectively predict the delay trend, has high calculation efficiency (only a few multiplication and addition operations are required), makes the prediction response fast, and improves the real-time compensation.

[0041] Specifically, the prediction model is a model based on machine learning.

[0042] It needs to be further explained that the application specifies the prediction model as a machine learning-based model. In specific implementation, the machine learning model adopts a simple feedforward neural network (NN) with a structure of 3 nodes in the input layer (corresponding to the last 3 measurement error values E t-1, E t-2, E t-3), 4 nodes in the hidden layer (using a ReLU activation function), and 1 node in the output layer (linear activation, output prediction value). The reason for selecting this structure is that a small network is suitable for embedded resource constraints (such as a few KB of memory) and can handle nonlinear relationships; the number of nodes is determined based on experiments, and too many nodes will overfit. The training uses an online gradient descent method, and the learning rate is preferably 0.01. The reason for selecting this value is that a learning rate of 0.01 can ensure stable convergence and will not be too large to cause oscillation or too small to cause slow speed; the training data is the last 50 samples in the sliding window, the loss function is mean square error (MSE), the training batch size is 1 (online learning), the weights are updated every time new data is received, and the training period is 100 times per data point. The model is deployed on an embedded processing unit, and fixed-point arithmetic is used to reduce computational overhead.

[0043] Further, the prediction formula is: output = W2 f (W1 X + b1) + b2, where X is the input vector [E t-1, E t-2, E t-3], W1 is a 3x4 weight matrix, b1 is a 4-dimensional bias, f is a ReLU function, W2 is a 4x1 weight matrix, and b2 is a scalar bias. In the formula, the output is the predicted error value (unit: ps), X is the input feature vector, W1, b1, W2, and b2 are model parameters.

[0044] It can be understood that the neural network can automatically learn complex delay patterns and improve prediction accuracy by 10-20%, especially in scenarios with large PVT variations, enhancing the adaptability of the method.

[0045] Specifically, the dynamic compensation includes adjusting the clock signal or modifying the path delay.

[0046] It needs to be further explained that the dynamic compensation includes adjusting the clock signal or modifying the path delay. In specific implementation, adjusting the clock signal is achieved through a digital phase-locked loop (DPLL) inside the chip, for example, adjusting the phase of the output clock, and the phase adjustment step is preferably 5ps. The preferred value of this step is selected based on the TDC resolution (10ps), and the reason is to match the measurement accuracy and avoid excessive adjustment to increase noise; the phase adjustment range is ±100ps, covering typical delay changes.

[0047] Further, the path delay modification is implemented by inserting a configurable delay unit, for example, adding a string of switchable buffers on the critical path, each buffer with a delay increment of preferably 10 ps, and the number of buffers is 8, and the total adjustment range is 80 ps, and the preferred value of this value is selected based on the path delay margin, and the reason is to cover the maximum expected error (such as 50 ps) and leave a margin. The compensation decision is based on the predicted error value: if the absolute value of the error is greater than the threshold value 20 ps, the compensation is triggered; the compensation amount is calculated as 1.2 times the error value to provide overcompensation. In implementation, the two compensation methods can be selected according to the chip mode, for example, the high-performance mode preferentially adjusts the clock, and the low-power consumption mode preferentially modifies the path.

[0048] It can be understood that the dual mechanism provides flexibility and can adapt to different chip working states to improve the success rate of compensation.

[0049] Specifically, the adjustment of the clock signal is implemented by dynamic frequency scaling.

[0050] It needs to be further explained that in specific implementation, DFS is implemented by adjusting the feedback division ratio of the internal PLL of the chip, and the frequency adjustment range is preferably ±5% of the nominal frequency, for example, for a chip with a nominal frequency of 1GHz, the frequency can be adjusted from 0.95GHz to 1.05GHz, and the preferred value of this range is selected based on the trade-off between power consumption and stability, and the reason is that a too wide range (such as ±10%) may increase clock jitter, and ±5% can effectively compensate for the delay change (corresponding to a delay change of about 5%) and has low risk.

[0051] Further, the frequency adjustment step is set to 1MHz, and the adjustment algorithm is based on the predicted error ratio: frequency change amount = Kf x predicted error value, where Kf is the gain coefficient, preferably 0.01MHz / ps, and the reason for selecting this value is that through simulation, it can be linearly mapped to the error to frequency change, avoiding sudden changes; the adjustment is performed once every prediction period (10ms), and the frequency change needs to be smoothly transitioned, and a ramp function is used, and the change rate is limited to 1MHz / μs.

[0052] It can be understood that DFS can adjust the overall speed of the chip, not only compensating for timing but also optimizing power consumption, especially suitable for mobile chips to improve energy efficiency.

[0053] Specifically, it further includes the steps of verifying the effect of dynamic compensation and adaptively adjusting the prediction algorithm.

[0054] It is further noted that the verification step is performed after each compensation: the actual delay after compensation is measured by the TDC core, the actual error = actual delay - nominal delay is calculated, and then compared with the predicted error, the difference = | actual error - predicted error |. If the difference exceeds the threshold 15ps for 3 times in a row, the adaptive adjustment is triggered. The preferred value of the threshold 15ps is selected based on the measurement noise level (usually 5-10ps), with the reason that to distinguish the real deviation and the noise, too low will adjust frequently, and too high will ignore the problem.

[0055] Further, the adaptive adjustment includes modifying the parameters of the prediction algorithm, for example, for the AR model, if the verification fails, the smoothing coefficient a is increased from 0.7 to 0.8 to speed up the response; the adjustment period is performed once every 10 verifications (i.e. every 100ms). The adjustment algorithm also contains a reset mechanism, if the verification fails for 10 times in a row, the model is reinitialized.

[0056] It can be understood that this step forms a closed-loop learning, which can correct the model drift and ensure long-term accuracy, making the method more robust.

[0057] Specifically, the verification is realized by comparing the actual delay with the expected delay.

[0058] It is further noted that the expected delay is obtained by adding the predicted error value to the nominal delay, i.e. expected delay = nominal delay + predicted error value. The actual delay is measured immediately after compensation by the TDC core (delayed for several clock cycles to avoid disturbance). The comparison uses the relative error formula: relative error = | actual delay - expected delay | / expected delay x 100%. If the relative error is greater than the threshold 5%, the verification fails. The preferred value of the threshold 5% is selected based on the application requirements, with the reason that for high-frequency chips, the timing tolerance is usually 5-10%, and 5% can effectively detect significant deviations; at the same time, the relative error is used instead of the absolute value, which can adapt to different delay levels. The comparison result is stored in a history buffer for trend analysis.

[0059] It can be understood that this comparison is simple and direct, which can quantitatively evaluate the compensation effect and improve the transparency of the method.

[0060] Please refer to Figure 2 The present application provides another embodiment, which provides a TDC-based chip delay error dynamic compensation system, comprising: a TDC core 100 integrated in the chip, for measuring the delay of the critical path in real time; an embedded processing unit 200 for predicting the delay error based on the measurement value of the TDC core through an embedded algorithm; The dynamic compensation unit 300 is configured to compensate the chip timing according to the predicted delay error.

[0061] The TDC core 100 is implemented by a Vernier method, integrated in the clock region of the chip, and physically located close to the start and end points of the critical path. The measurement resolution is 10 ps, the sampling frequency is 1000 Hz, and the power consumption is less than 10 mW. The embedded processing unit 200 is a 32-bit microcontroller (such as Cortex-M3), with a running frequency of 50 MHz, and a built-in 64K BRAM for storing algorithm codes and data. The algorithm is as described in claims 1-9, and is implemented by using C language, with a code size controlled within 32 KB. The dynamic compensation unit 300 includes a DPLL for clock adjustment (frequency range ±5%, step size 1 MHz) and a configurable delay line for path adjustment (delay increment 10 ps, range 80 ps). The compensation unit communicates with the processing unit through an APB bus. During operation, the TDC core continuously measures the delay, and the data is sent to the processing unit through DMA. The processing unit performs prediction every 10 ms, and outputs compensation instructions to the compensation unit. The entire process is controlled by a hardware state machine to ensure real-time performance.

[0062] Preferably, the system further includes a calibration module for automatically calibrating the TDC core at power-on.

[0063] It can be understood that the system is highly integrated and self-operated, and can improve the chip timing accuracy by more than 30% and reduce the external test requirement. Those skilled in the art can implement it using standard IP cores and design processes.

[0064] In the preferred embodiment, the application further provides an electronic device, which comprises: A memory and a processor, wherein the memory stores computer readable instructions, and the computer readable instructions are executed by the processor to implement the TDC-based chip delay error dynamic compensation method. The computer device can be a server, a terminal, or any other electronic device with necessary computing and / or processing capabilities. In one embodiment, the computer device can include a processor, a memory, a network interface, a communication interface, and the like connected by a system bus. The processor of the computer device can be used to provide necessary computing, processing, and / or control capabilities. The memory of the computer device can include a non-volatile storage medium and an internal memory. The non-volatile storage medium or the non-volatile storage medium can store an operating system, a computer program, and the like. The internal memory can provide an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface and the communication interface of the computer device can be used to connect and communicate with external devices through a network. The computer program is executed by the processor to execute the steps of the method of the application.

[0065] The application can be implemented as a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, causes the steps of the method of the embodiments of the application to be performed. In one embodiment, the computer program is distributed over a network of coupled computer devices or processors such that the computer program is stored, accessed and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, can be performed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations can be performed by one or more computer devices or processors and one or more other method steps / operations can be performed by one or more other computer devices or processors. One or more computer devices or processors can perform a single method step / operation, or perform two or more method steps / operations.

[0066] It will be appreciated by the person of ordinary skill in the art that the method steps of the application can be instructed by a computer program to relevant hardware such as a computer device or processor, the computer program being stored in a non-transitory computer-readable storage medium which, when executed, causes the steps of the application to be performed. Any reference herein to a memory, storage, database or other medium can include non-volatile and / or volatile memory as appropriate. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state disk, and so on. Examples of volatile memory include random access memory (RAM), external cache memory, and so on.

[0067] The various technical features described above can be combined in any manner. Although not all possible combinations are described, any combination of the technical features should be considered to be within the scope of the present description, as long as such a combination does not result in a contradiction.

[0068] The above description of specific embodiments of the application does not limit the scope of protection of the application. Any other corresponding changes and modifications made to the technical concepts according to the application should be included within the scope of protection of the claims of the application.

Claims

1. A dynamic compensation method for chip delay error based on TDC, characterized in that, Includes the following steps: S1. Utilize the TDC core integrated inside the chip to measure the delay of the critical path in real time; S2. Based on the measured delay value, predict the delay error using an embedded algorithm; S3. Dynamically compensate for chip timing based on predicted delay errors.

2. The method according to claim 1, characterized in that, The real-time measurement of critical path delay using the TDC core includes: measuring the propagation time of a signal from the starting point to the ending point on the critical path using the TDC core.

3. The method according to claim 2, characterized in that, The TDC core uses the vernier method for time measurement.

4. The method according to claim 1, characterized in that, The method of predicting delay error using embedded algorithms includes: using a prediction model to predict the delay trend.

5. The method according to claim 4, characterized in that, The prediction model is a machine learning-based model.

6. The method according to claim 1, characterized in that, The dynamic compensation includes adjusting the clock signal or modifying the path delay.

7. The method according to claim 6, characterized in that, The adjustment of the clock signal is achieved through dynamic frequency scaling.

8. The method according to claim 1, characterized in that, It also includes the steps of verifying the effectiveness of dynamic compensation and adaptively adjusting the prediction algorithm.

9. The method according to claim 8, characterized in that, The verification is achieved by comparing the actual delay with the expected delay.

10. A dynamic compensation system for chip delay error based on TDC, characterized in that, The chip delay error dynamic compensation method based on TDC as described in any one of claims 1-9 includes: The TDC core, integrated inside the chip, is used for real-time measurement of latency on the critical path. An embedded processing unit is used to predict delay errors based on the measurement values ​​of the TDC core using an embedded algorithm. The dynamic compensation unit is used to compensate for chip timing based on predicted delay errors.

Images